1 /* $OpenBSD: if_run.c,v 1.137 2022/05/10 08:20:36 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2013-2014 Kevin Lo 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2700U/RT2800U/RT3000U/RT3900E chipset driver. 22 * http://www.ralinktech.com/ 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/timeout.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 #include <sys/endian.h> 37 38 #include <machine/intr.h> 39 40 #if NBPFILTER > 0 41 #include <net/bpf.h> 42 #endif 43 #include <net/if.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <netinet/in.h> 48 #include <netinet/if_ether.h> 49 50 #include <net80211/ieee80211_var.h> 51 #include <net80211/ieee80211_amrr.h> 52 #include <net80211/ieee80211_radiotap.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include <dev/usb/usbdevs.h> 58 59 #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ 60 #include <dev/usb/if_runvar.h> 61 62 #ifdef RUN_DEBUG 63 #define DPRINTF(x) do { if (run_debug) printf x; } while (0) 64 #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) 65 int run_debug = 0; 66 #else 67 #define DPRINTF(x) 68 #define DPRINTFN(n, x) 69 #endif 70 71 #define USB_ID(v, p) { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } 72 static const struct usb_devno run_devs[] = { 73 USB_ID(ABOCOM, RT2770), 74 USB_ID(ABOCOM, RT2870), 75 USB_ID(ABOCOM, RT3070), 76 USB_ID(ABOCOM, RT3071), 77 USB_ID(ABOCOM, RT3072), 78 USB_ID(ABOCOM2, RT2870_1), 79 USB_ID(ACCTON, RT2770), 80 USB_ID(ACCTON, RT2870_1), 81 USB_ID(ACCTON, RT2870_2), 82 USB_ID(ACCTON, RT2870_3), 83 USB_ID(ACCTON, RT2870_4), 84 USB_ID(ACCTON, RT2870_5), 85 USB_ID(ACCTON, RT3070), 86 USB_ID(ACCTON, RT3070_1), 87 USB_ID(ACCTON, RT3070_2), 88 USB_ID(ACCTON, RT3070_3), 89 USB_ID(ACCTON, RT3070_4), 90 USB_ID(ACCTON, RT3070_5), 91 USB_ID(ACCTON, RT3070_6), 92 USB_ID(AIRTIES, RT3070), 93 USB_ID(AIRTIES, RT3070_2), 94 USB_ID(ALLWIN, RT2070), 95 USB_ID(ALLWIN, RT2770), 96 USB_ID(ALLWIN, RT2870), 97 USB_ID(ALLWIN, RT3070), 98 USB_ID(ALLWIN, RT3071), 99 USB_ID(ALLWIN, RT3072), 100 USB_ID(ALLWIN, RT3572), 101 USB_ID(AMIGO, RT2870_1), 102 USB_ID(AMIGO, RT2870_2), 103 USB_ID(AMIT, CGWLUSB2GNR), 104 USB_ID(AMIT, RT2870_1), 105 USB_ID(AMIT2, RT2870), 106 USB_ID(ASUS, RT2870_1), 107 USB_ID(ASUS, RT2870_2), 108 USB_ID(ASUS, RT2870_3), 109 USB_ID(ASUS, RT2870_4), 110 USB_ID(ASUS, RT2870_5), 111 USB_ID(ASUS, RT3070_1), 112 USB_ID(ASUS, USBN13), 113 USB_ID(ASUS, USBN53), 114 USB_ID(ASUS, USBN66), 115 USB_ID(ASUS2, USBN11), 116 USB_ID(AZUREWAVE, RT2870_1), 117 USB_ID(AZUREWAVE, RT2870_2), 118 USB_ID(AZUREWAVE, RT3070_1), 119 USB_ID(AZUREWAVE, RT3070_2), 120 USB_ID(AZUREWAVE, RT3070_3), 121 USB_ID(AZUREWAVE, RT3070_4), 122 USB_ID(AZUREWAVE, RT3070_5), 123 USB_ID(BELKIN, F9L1103), 124 USB_ID(BELKIN, F5D8053V3), 125 USB_ID(BELKIN, F5D8055), 126 USB_ID(BELKIN, F5D8055V2), 127 USB_ID(BELKIN, F6D4050V1), 128 USB_ID(BELKIN, F6D4050V2), 129 USB_ID(BELKIN, F7D1101V2), 130 USB_ID(BELKIN, RT2870_1), 131 USB_ID(BELKIN, RT2870_2), 132 USB_ID(BEWAN, RT3070), 133 USB_ID(CISCOLINKSYS, AE1000), 134 USB_ID(CISCOLINKSYS, AM10), 135 USB_ID(CISCOLINKSYS2, RT3070), 136 USB_ID(CISCOLINKSYS3, RT3070), 137 USB_ID(CONCEPTRONIC2, RT2870_1), 138 USB_ID(CONCEPTRONIC2, RT2870_2), 139 USB_ID(CONCEPTRONIC2, RT2870_3), 140 USB_ID(CONCEPTRONIC2, RT2870_5), 141 USB_ID(CONCEPTRONIC2, RT2870_6), 142 USB_ID(CONCEPTRONIC2, RT2870_7), 143 USB_ID(CONCEPTRONIC2, RT2870_8), 144 USB_ID(CONCEPTRONIC2, RT3070_1), 145 USB_ID(CONCEPTRONIC2, RT3070_2), 146 USB_ID(CONCEPTRONIC2, RT3070_3), 147 USB_ID(CONCEPTRONIC2, VIGORN61), 148 USB_ID(COREGA, CGWLUSB300GNM), 149 USB_ID(COREGA, RT2870_1), 150 USB_ID(COREGA, RT2870_2), 151 USB_ID(COREGA, RT2870_3), 152 USB_ID(COREGA, RT3070), 153 USB_ID(CYBERTAN, RT2870), 154 USB_ID(DLINK, DWA125B2), 155 USB_ID(DLINK, DWA127), 156 USB_ID(DLINK, DWA130F1), 157 USB_ID(DLINK, DWA137A1), 158 USB_ID(DLINK, DWA140B3), 159 USB_ID(DLINK, DWA140D1), 160 USB_ID(DLINK, DWA160B2), 161 USB_ID(DLINK, DWA162), 162 USB_ID(DLINK, RT2870), 163 USB_ID(DLINK, RT3072), 164 USB_ID(DLINK2, DWA130), 165 USB_ID(DLINK2, RT2870_1), 166 USB_ID(DLINK2, RT2870_2), 167 USB_ID(DLINK2, RT3070_1), 168 USB_ID(DLINK2, RT3070_2), 169 USB_ID(DLINK2, RT3070_3), 170 USB_ID(DLINK2, RT3070_4), 171 USB_ID(DLINK2, RT3070_5), 172 USB_ID(DLINK2, RT3072), 173 USB_ID(DLINK2, RT3072_1), 174 USB_ID(DVICO, RT3070), 175 USB_ID(EDIMAX, EW7717), 176 USB_ID(EDIMAX, EW7718), 177 USB_ID(EDIMAX, EW7722UTN), 178 USB_ID(EDIMAX, RT2870_1), 179 USB_ID(ENCORE, RT3070_1), 180 USB_ID(ENCORE, RT3070_2), 181 USB_ID(ENCORE, RT3070_3), 182 USB_ID(GIGABYTE, GNWB31N), 183 USB_ID(GIGABYTE, GNWB32L), 184 USB_ID(GIGABYTE, RT2870_1), 185 USB_ID(GIGASET, RT3070_1), 186 USB_ID(GIGASET, RT3070_2), 187 USB_ID(GUILLEMOT, HWNU300), 188 USB_ID(HAWKING, HWDN2), 189 USB_ID(HAWKING, HWUN2), 190 USB_ID(HAWKING, RT2870_1), 191 USB_ID(HAWKING, RT2870_2), 192 USB_ID(HAWKING, RT2870_3), 193 USB_ID(HAWKING, RT2870_4), 194 USB_ID(HAWKING, RT2870_5), 195 USB_ID(IODATA, RT3072_1), 196 USB_ID(IODATA, RT3072_2), 197 USB_ID(IODATA, RT3072_3), 198 USB_ID(IODATA, RT3072_4), 199 USB_ID(LINKSYS4, RT3070), 200 USB_ID(LINKSYS4, WUSB100), 201 USB_ID(LINKSYS4, WUSB54GCV3), 202 USB_ID(LINKSYS4, WUSB600N), 203 USB_ID(LINKSYS4, WUSB600NV2), 204 USB_ID(LOGITEC, LANW150NU2), 205 USB_ID(LOGITEC, LANW300NU2), 206 USB_ID(LOGITEC, LANW300NU2S), 207 USB_ID(LOGITEC, RT2870_1), 208 USB_ID(LOGITEC, RT2870_2), 209 USB_ID(LOGITEC, RT2870_3), 210 USB_ID(MELCO, RT2870_1), 211 USB_ID(MELCO, RT2870_2), 212 USB_ID(MELCO, WLIUCAG300N), 213 USB_ID(MELCO, WLIUCG300N), 214 USB_ID(MELCO, WLIUCG301N), 215 USB_ID(MELCO, WLIUCGN), 216 USB_ID(MELCO, WLIUCGNHP), 217 USB_ID(MELCO, WLIUCGNM), 218 USB_ID(MELCO, WLIUCGNM2), 219 USB_ID(MOTOROLA4, RT2770), 220 USB_ID(MOTOROLA4, RT3070), 221 USB_ID(MSI, RT3070_1), 222 USB_ID(MSI, RT3070_2), 223 USB_ID(MSI, RT3070_3), 224 USB_ID(MSI, RT3070_4), 225 USB_ID(MSI, RT3070_5), 226 USB_ID(MSI, RT3070_6), 227 USB_ID(MSI, RT3070_7), 228 USB_ID(MSI, RT3070_8), 229 USB_ID(MSI, RT3070_9), 230 USB_ID(MSI, RT3070_10), 231 USB_ID(MSI, RT3070_11), 232 USB_ID(MSI, RT3070_12), 233 USB_ID(MSI, RT3070_13), 234 USB_ID(MSI, RT3070_14), 235 USB_ID(MSI, RT3070_15), 236 USB_ID(OVISLINK, RT3071), 237 USB_ID(OVISLINK, RT3072), 238 USB_ID(PARA, RT3070), 239 USB_ID(PEGATRON, RT2870), 240 USB_ID(PEGATRON, RT3070), 241 USB_ID(PEGATRON, RT3070_2), 242 USB_ID(PEGATRON, RT3070_3), 243 USB_ID(PEGATRON, RT3072), 244 USB_ID(PHILIPS, RT2870), 245 USB_ID(PLANEX2, GWUS300MINIS), 246 USB_ID(PLANEX2, GWUSMICRO300), 247 USB_ID(PLANEX2, GWUSMICRON), 248 USB_ID(PLANEX2, RT2870), 249 USB_ID(PLANEX2, RT3070), 250 USB_ID(QCOM, RT2870), 251 USB_ID(QUANTA, RT3070), 252 USB_ID(RALINK, RT2070), 253 USB_ID(RALINK, RT2770), 254 USB_ID(RALINK, RT2870), 255 USB_ID(RALINK, RT3070), 256 USB_ID(RALINK, RT3071), 257 USB_ID(RALINK, RT3072), 258 USB_ID(RALINK, RT3370), 259 USB_ID(RALINK, RT3572), 260 USB_ID(RALINK, RT3573), 261 USB_ID(RALINK, RT5370), 262 USB_ID(RALINK, RT5372), 263 USB_ID(RALINK, RT5572), 264 USB_ID(RALINK, RT8070), 265 USB_ID(SAMSUNG, WIS09ABGN), 266 USB_ID(SAMSUNG2, RT2870_1), 267 USB_ID(SENAO, RT2870_1), 268 USB_ID(SENAO, RT2870_2), 269 USB_ID(SENAO, RT2870_3), 270 USB_ID(SENAO, RT2870_4), 271 USB_ID(SENAO, RT3070), 272 USB_ID(SENAO, RT3071), 273 USB_ID(SENAO, RT3072_1), 274 USB_ID(SENAO, RT3072_2), 275 USB_ID(SENAO, RT3072_3), 276 USB_ID(SENAO, RT3072_4), 277 USB_ID(SENAO, RT3072_5), 278 USB_ID(SITECOMEU, WL302), 279 USB_ID(SITECOMEU, WL315), 280 USB_ID(SITECOMEU, WL321), 281 USB_ID(SITECOMEU, RT3070_3), 282 USB_ID(SITECOMEU, WL302), 283 USB_ID(SITECOMEU, WL344), 284 USB_ID(SITECOMEU, WL329), 285 USB_ID(SITECOMEU, WL345), 286 USB_ID(SITECOMEU, RT2870_1), 287 USB_ID(SITECOMEU, RT2870_2), 288 USB_ID(SITECOMEU, RT2870_3), 289 USB_ID(SITECOMEU, RT3070_1), 290 USB_ID(SITECOMEU, RT3072_3), 291 USB_ID(SITECOMEU, RT3072_4), 292 USB_ID(SITECOMEU, RT3072_5), 293 USB_ID(SITECOMEU, RT3072_6), 294 USB_ID(SITECOMEU, WL302), 295 USB_ID(SITECOMEU, WL315), 296 USB_ID(SITECOMEU, WL321), 297 USB_ID(SITECOMEU, WL324), 298 USB_ID(SITECOMEU, WL329), 299 USB_ID(SITECOMEU, WL343), 300 USB_ID(SITECOMEU, WL344), 301 USB_ID(SITECOMEU, WL345), 302 USB_ID(SITECOMEU, WL349V4), 303 USB_ID(SITECOMEU, WL608), 304 USB_ID(SITECOMEU, WLA4000), 305 USB_ID(SITECOMEU, WLA5000), 306 USB_ID(SPARKLAN, RT2870_1), 307 USB_ID(SPARKLAN, RT2870_2), 308 USB_ID(SPARKLAN, RT3070), 309 USB_ID(SWEEX2, LW153), 310 USB_ID(SWEEX2, LW303), 311 USB_ID(SWEEX2, LW313), 312 USB_ID(TOSHIBA, RT3070), 313 USB_ID(UMEDIA, RT2870_1), 314 USB_ID(UMEDIA, TEW645UB), 315 USB_ID(ZCOM, RT2870_1), 316 USB_ID(ZCOM, RT2870_2), 317 USB_ID(ZINWELL, RT2870_1), 318 USB_ID(ZINWELL, RT2870_2), 319 USB_ID(ZINWELL, RT3070), 320 USB_ID(ZINWELL, RT3072_1), 321 USB_ID(ZINWELL, RT3072_2), 322 USB_ID(ZYXEL, NWD2105), 323 USB_ID(ZYXEL, NWD211AN), 324 USB_ID(ZYXEL, RT2870_1), 325 USB_ID(ZYXEL, RT2870_2), 326 USB_ID(ZYXEL, RT3070) 327 }; 328 329 int run_match(struct device *, void *, void *); 330 void run_attach(struct device *, struct device *, void *); 331 int run_detach(struct device *, int); 332 int run_alloc_rx_ring(struct run_softc *); 333 void run_free_rx_ring(struct run_softc *); 334 int run_alloc_tx_ring(struct run_softc *, int); 335 void run_free_tx_ring(struct run_softc *, int); 336 int run_load_microcode(struct run_softc *); 337 int run_reset(struct run_softc *); 338 int run_read(struct run_softc *, uint16_t, uint32_t *); 339 int run_read_region_1(struct run_softc *, uint16_t, uint8_t *, 340 int); 341 int run_write_2(struct run_softc *, uint16_t, uint16_t); 342 int run_write(struct run_softc *, uint16_t, uint32_t); 343 int run_write_region_1(struct run_softc *, uint16_t, 344 const uint8_t *, int); 345 int run_set_region_4(struct run_softc *, uint16_t, uint32_t, int); 346 int run_efuse_read(struct run_softc *, uint16_t, uint16_t *); 347 int run_efuse_read_2(struct run_softc *, uint16_t, uint16_t *); 348 int run_eeprom_read_2(struct run_softc *, uint16_t, uint16_t *); 349 int run_rt2870_rf_write(struct run_softc *, uint8_t, uint32_t); 350 int run_rt3070_rf_read(struct run_softc *, uint8_t, uint8_t *); 351 int run_rt3070_rf_write(struct run_softc *, uint8_t, uint8_t); 352 int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); 353 int run_bbp_write(struct run_softc *, uint8_t, uint8_t); 354 int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); 355 const char * run_get_rf(int); 356 void run_get_txpower(struct run_softc *); 357 void run_rt3593_get_txpower(struct run_softc *); 358 int run_read_eeprom(struct run_softc *); 359 struct ieee80211_node *run_node_alloc(struct ieee80211com *); 360 int run_media_change(struct ifnet *); 361 void run_next_scan(void *); 362 void run_task(void *); 363 void run_do_async(struct run_softc *, void (*)(struct run_softc *, 364 void *), void *, int); 365 int run_newstate(struct ieee80211com *, enum ieee80211_state, int); 366 void run_newstate_cb(struct run_softc *, void *); 367 void run_updateedca(struct ieee80211com *); 368 void run_updateedca_cb(struct run_softc *, void *); 369 int run_set_key(struct ieee80211com *, struct ieee80211_node *, 370 struct ieee80211_key *); 371 void run_set_key_cb(struct run_softc *, void *); 372 void run_delete_key(struct ieee80211com *, struct ieee80211_node *, 373 struct ieee80211_key *); 374 void run_delete_key_cb(struct run_softc *, void *); 375 void run_calibrate_to(void *); 376 void run_calibrate_cb(struct run_softc *, void *); 377 void run_newassoc(struct ieee80211com *, struct ieee80211_node *, 378 int); 379 void run_rx_frame(struct run_softc *, uint8_t *, int, 380 struct mbuf_list *); 381 void run_rxeof(struct usbd_xfer *, void *, usbd_status); 382 void run_txeof(struct usbd_xfer *, void *, usbd_status); 383 int run_tx(struct run_softc *, struct mbuf *, 384 struct ieee80211_node *); 385 void run_start(struct ifnet *); 386 void run_watchdog(struct ifnet *); 387 int run_ioctl(struct ifnet *, u_long, caddr_t); 388 void run_iq_calib(struct run_softc *, u_int); 389 void run_select_chan_group(struct run_softc *, int); 390 void run_set_agc(struct run_softc *, uint8_t); 391 void run_set_rx_antenna(struct run_softc *, int); 392 void run_rt2870_set_chan(struct run_softc *, u_int); 393 void run_rt3070_set_chan(struct run_softc *, u_int); 394 void run_rt3572_set_chan(struct run_softc *, u_int); 395 void run_rt3593_set_chan(struct run_softc *, u_int); 396 void run_rt5390_set_chan(struct run_softc *, u_int); 397 void run_rt5592_set_chan(struct run_softc *, u_int); 398 int run_set_chan(struct run_softc *, struct ieee80211_channel *); 399 void run_enable_tsf_sync(struct run_softc *); 400 void run_enable_mrr(struct run_softc *); 401 void run_set_txpreamble(struct run_softc *); 402 void run_set_basicrates(struct run_softc *); 403 void run_set_leds(struct run_softc *, uint16_t); 404 void run_set_bssid(struct run_softc *, const uint8_t *); 405 void run_set_macaddr(struct run_softc *, const uint8_t *); 406 void run_updateslot(struct ieee80211com *); 407 void run_updateslot_cb(struct run_softc *, void *); 408 #if NBPFILTER > 0 409 int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); 410 #endif 411 void run_rt5390_bbp_init(struct run_softc *); 412 int run_bbp_init(struct run_softc *); 413 int run_rt3070_rf_init(struct run_softc *); 414 void run_rt3593_rf_init(struct run_softc *); 415 void run_rt5390_rf_init(struct run_softc *); 416 int run_rt3070_filter_calib(struct run_softc *, uint8_t, uint8_t, 417 uint8_t *); 418 void run_rt3070_rf_setup(struct run_softc *); 419 void run_rt3593_rf_setup(struct run_softc *); 420 void run_rt5390_rf_setup(struct run_softc *); 421 int run_txrx_enable(struct run_softc *); 422 void run_adjust_freq_offset(struct run_softc *); 423 int run_init(struct ifnet *); 424 void run_stop(struct ifnet *, int); 425 426 struct cfdriver run_cd = { 427 NULL, "run", DV_IFNET 428 }; 429 430 const struct cfattach run_ca = { 431 sizeof (struct run_softc), run_match, run_attach, run_detach 432 }; 433 434 static const struct { 435 uint32_t reg; 436 uint32_t val; 437 } rt2870_def_mac[] = { 438 RT2870_DEF_MAC 439 }; 440 441 static const struct { 442 uint8_t reg; 443 uint8_t val; 444 } rt2860_def_bbp[] = { 445 RT2860_DEF_BBP 446 },rt5390_def_bbp[] = { 447 RT5390_DEF_BBP 448 },rt5592_def_bbp[] = { 449 RT5592_DEF_BBP 450 }; 451 452 /* 453 * Default values for BBP register R196 for RT5592. 454 */ 455 static const uint8_t rt5592_bbp_r196[] = { 456 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, 457 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, 458 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, 459 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, 460 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, 461 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 462 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 463 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, 464 0x2e, 0x36, 0x30, 0x6e 465 }; 466 467 static const struct rfprog { 468 uint8_t chan; 469 uint32_t r1, r2, r3, r4; 470 } rt2860_rf2850[] = { 471 RT2860_RF2850 472 }; 473 474 struct { 475 uint8_t n, r, k; 476 } rt3070_freqs[] = { 477 RT3070_RF3052 478 }; 479 480 static const struct rt5592_freqs { 481 uint16_t n; 482 uint8_t k, m, r; 483 } rt5592_freqs_20mhz[] = { 484 RT5592_RF5592_20MHZ 485 },rt5592_freqs_40mhz[] = { 486 RT5592_RF5592_40MHZ 487 }; 488 489 static const struct { 490 uint8_t reg; 491 uint8_t val; 492 } rt3070_def_rf[] = { 493 RT3070_DEF_RF 494 },rt3572_def_rf[] = { 495 RT3572_DEF_RF 496 },rt3593_def_rf[] = { 497 RT3593_DEF_RF 498 },rt5390_def_rf[] = { 499 RT5390_DEF_RF 500 },rt5392_def_rf[] = { 501 RT5392_DEF_RF 502 },rt5592_def_rf[] = { 503 RT5592_DEF_RF 504 },rt5592_2ghz_def_rf[] = { 505 RT5592_2GHZ_DEF_RF 506 },rt5592_5ghz_def_rf[] = { 507 RT5592_5GHZ_DEF_RF 508 }; 509 510 static const struct { 511 u_int firstchan; 512 u_int lastchan; 513 uint8_t reg; 514 uint8_t val; 515 } rt5592_chan_5ghz[] = { 516 RT5592_CHAN_5GHZ 517 }; 518 519 int 520 run_match(struct device *parent, void *match, void *aux) 521 { 522 struct usb_attach_arg *uaa = aux; 523 524 if (uaa->iface == NULL || uaa->configno != 1) 525 return UMATCH_NONE; 526 527 return (usb_lookup(run_devs, uaa->vendor, uaa->product) != NULL) ? 528 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE; 529 } 530 531 void 532 run_attach(struct device *parent, struct device *self, void *aux) 533 { 534 struct run_softc *sc = (struct run_softc *)self; 535 struct usb_attach_arg *uaa = aux; 536 struct ieee80211com *ic = &sc->sc_ic; 537 struct ifnet *ifp = &ic->ic_if; 538 usb_interface_descriptor_t *id; 539 usb_endpoint_descriptor_t *ed; 540 int i, nrx, ntx, ntries; 541 uint32_t ver; 542 543 sc->sc_udev = uaa->device; 544 sc->sc_iface = uaa->iface; 545 546 /* 547 * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX 548 * and 6 for TX (4 EDCAs + HCCA + Prio). 549 * Update 03-14-2009: some devices like the Planex GW-US300MiniS 550 * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). 551 */ 552 nrx = ntx = 0; 553 id = usbd_get_interface_descriptor(sc->sc_iface); 554 for (i = 0; i < id->bNumEndpoints; i++) { 555 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 556 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 557 continue; 558 559 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 560 sc->rxq.pipe_no = ed->bEndpointAddress; 561 nrx++; 562 } else if (ntx < 4) { 563 sc->txq[ntx].pipe_no = ed->bEndpointAddress; 564 ntx++; 565 } 566 } 567 /* make sure we've got them all */ 568 if (nrx < 1 || ntx < 4) { 569 printf("%s: missing endpoint\n", sc->sc_dev.dv_xname); 570 return; 571 } 572 573 usb_init_task(&sc->sc_task, run_task, sc, USB_TASK_TYPE_GENERIC); 574 timeout_set(&sc->scan_to, run_next_scan, sc); 575 timeout_set(&sc->calib_to, run_calibrate_to, sc); 576 577 sc->amrr.amrr_min_success_threshold = 1; 578 sc->amrr.amrr_max_success_threshold = 10; 579 580 /* wait for the chip to settle */ 581 for (ntries = 0; ntries < 100; ntries++) { 582 if (run_read(sc, RT2860_ASIC_VER_ID, &ver) != 0) 583 return; 584 if (ver != 0 && ver != 0xffffffff) 585 break; 586 DELAY(10); 587 } 588 if (ntries == 100) { 589 printf("%s: timeout waiting for NIC to initialize\n", 590 sc->sc_dev.dv_xname); 591 return; 592 } 593 sc->mac_ver = ver >> 16; 594 sc->mac_rev = ver & 0xffff; 595 596 /* retrieve RF rev. no and various other things from EEPROM */ 597 run_read_eeprom(sc); 598 599 printf("%s: MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), " 600 "address %s\n", sc->sc_dev.dv_xname, sc->mac_ver, 601 sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, 602 sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 603 604 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 605 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 606 ic->ic_state = IEEE80211_S_INIT; 607 608 /* set device capabilities */ 609 ic->ic_caps = 610 IEEE80211_C_MONITOR | /* monitor mode supported */ 611 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 612 IEEE80211_C_SHSLOT | /* short slot time supported */ 613 IEEE80211_C_WEP | /* WEP */ 614 IEEE80211_C_RSN; /* WPA/RSN */ 615 616 if (sc->rf_rev == RT2860_RF_2750 || 617 sc->rf_rev == RT2860_RF_2850 || 618 sc->rf_rev == RT3070_RF_3052 || 619 sc->rf_rev == RT3070_RF_3053 || 620 sc->rf_rev == RT5592_RF_5592) { 621 /* set supported .11a rates */ 622 ic->ic_sup_rates[IEEE80211_MODE_11A] = 623 ieee80211_std_rateset_11a; 624 625 /* set supported .11a channels */ 626 for (i = 14; i < nitems(rt2860_rf2850); i++) { 627 uint8_t chan = rt2860_rf2850[i].chan; 628 ic->ic_channels[chan].ic_freq = 629 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 630 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 631 } 632 } 633 634 /* set supported .11b and .11g rates */ 635 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 636 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 637 638 /* set supported .11b and .11g channels (1 through 14) */ 639 for (i = 1; i <= 14; i++) { 640 ic->ic_channels[i].ic_freq = 641 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 642 ic->ic_channels[i].ic_flags = 643 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 644 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 645 } 646 647 ifp->if_softc = sc; 648 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 649 ifp->if_ioctl = run_ioctl; 650 ifp->if_start = run_start; 651 ifp->if_watchdog = run_watchdog; 652 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 653 654 if_attach(ifp); 655 ieee80211_ifattach(ifp); 656 ic->ic_node_alloc = run_node_alloc; 657 ic->ic_newassoc = run_newassoc; 658 ic->ic_updateslot = run_updateslot; 659 ic->ic_updateedca = run_updateedca; 660 ic->ic_set_key = run_set_key; 661 ic->ic_delete_key = run_delete_key; 662 /* override state transition machine */ 663 sc->sc_newstate = ic->ic_newstate; 664 ic->ic_newstate = run_newstate; 665 ieee80211_media_init(ifp, run_media_change, ieee80211_media_status); 666 667 #if NBPFILTER > 0 668 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 669 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 670 671 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 672 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 673 sc->sc_rxtap.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT); 674 675 sc->sc_txtap_len = sizeof sc->sc_txtapu; 676 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 677 sc->sc_txtap.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT); 678 #endif 679 } 680 681 int 682 run_detach(struct device *self, int flags) 683 { 684 struct run_softc *sc = (struct run_softc *)self; 685 struct ifnet *ifp = &sc->sc_ic.ic_if; 686 int qid, s; 687 688 s = splusb(); 689 690 if (timeout_initialized(&sc->scan_to)) 691 timeout_del(&sc->scan_to); 692 if (timeout_initialized(&sc->calib_to)) 693 timeout_del(&sc->calib_to); 694 695 /* wait for all queued asynchronous commands to complete */ 696 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 697 698 usbd_ref_wait(sc->sc_udev); 699 700 if (ifp->if_softc != NULL) { 701 ifp->if_flags &= ~IFF_RUNNING; 702 ifq_clr_oactive(&ifp->if_snd); 703 ieee80211_ifdetach(ifp); 704 if_detach(ifp); 705 } 706 707 for (qid = 0; qid < 4; qid++) 708 run_free_tx_ring(sc, qid); 709 run_free_rx_ring(sc); 710 711 splx(s); 712 713 return 0; 714 } 715 716 int 717 run_alloc_rx_ring(struct run_softc *sc) 718 { 719 struct run_rx_ring *rxq = &sc->rxq; 720 int i, error; 721 722 error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); 723 if (error != 0) 724 goto fail; 725 726 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 727 struct run_rx_data *data = &rxq->data[i]; 728 729 data->sc = sc; /* backpointer for callbacks */ 730 731 data->xfer = usbd_alloc_xfer(sc->sc_udev); 732 if (data->xfer == NULL) { 733 error = ENOMEM; 734 goto fail; 735 } 736 data->buf = usbd_alloc_buffer(data->xfer, RUN_MAX_RXSZ); 737 if (data->buf == NULL) { 738 error = ENOMEM; 739 goto fail; 740 } 741 } 742 if (error != 0) 743 fail: run_free_rx_ring(sc); 744 return error; 745 } 746 747 void 748 run_free_rx_ring(struct run_softc *sc) 749 { 750 struct run_rx_ring *rxq = &sc->rxq; 751 int i; 752 753 if (rxq->pipeh != NULL) { 754 usbd_close_pipe(rxq->pipeh); 755 rxq->pipeh = NULL; 756 } 757 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 758 if (rxq->data[i].xfer != NULL) 759 usbd_free_xfer(rxq->data[i].xfer); 760 rxq->data[i].xfer = NULL; 761 } 762 } 763 764 int 765 run_alloc_tx_ring(struct run_softc *sc, int qid) 766 { 767 struct run_tx_ring *txq = &sc->txq[qid]; 768 int i, error; 769 uint16_t txwisize; 770 771 txwisize = sizeof(struct rt2860_txwi); 772 if (sc->mac_ver == 0x5592) 773 txwisize += sizeof(uint32_t); 774 775 txq->cur = txq->queued = 0; 776 777 error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); 778 if (error != 0) 779 goto fail; 780 781 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 782 struct run_tx_data *data = &txq->data[i]; 783 784 data->sc = sc; /* backpointer for callbacks */ 785 data->qid = qid; 786 787 data->xfer = usbd_alloc_xfer(sc->sc_udev); 788 if (data->xfer == NULL) { 789 error = ENOMEM; 790 goto fail; 791 } 792 data->buf = usbd_alloc_buffer(data->xfer, RUN_MAX_TXSZ); 793 if (data->buf == NULL) { 794 error = ENOMEM; 795 goto fail; 796 } 797 /* zeroize the TXD + TXWI part */ 798 memset(data->buf, 0, sizeof(struct rt2870_txd) + txwisize); 799 } 800 if (error != 0) 801 fail: run_free_tx_ring(sc, qid); 802 return error; 803 } 804 805 void 806 run_free_tx_ring(struct run_softc *sc, int qid) 807 { 808 struct run_tx_ring *txq = &sc->txq[qid]; 809 int i; 810 811 if (txq->pipeh != NULL) { 812 usbd_close_pipe(txq->pipeh); 813 txq->pipeh = NULL; 814 } 815 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 816 if (txq->data[i].xfer != NULL) 817 usbd_free_xfer(txq->data[i].xfer); 818 txq->data[i].xfer = NULL; 819 } 820 } 821 822 int 823 run_load_microcode(struct run_softc *sc) 824 { 825 usb_device_request_t req; 826 const char *fwname; 827 u_char *ucode; 828 size_t size; 829 uint32_t tmp; 830 int ntries, error; 831 832 /* RT3071/RT3072 use a different firmware */ 833 if (sc->mac_ver != 0x2860 && 834 sc->mac_ver != 0x2872 && 835 sc->mac_ver != 0x3070) 836 fwname = "run-rt3071"; 837 else 838 fwname = "run-rt2870"; 839 840 if ((error = loadfirmware(fwname, &ucode, &size)) != 0) { 841 printf("%s: failed loadfirmware of file %s (error %d)\n", 842 sc->sc_dev.dv_xname, fwname, error); 843 return error; 844 } 845 if (size != 4096) { 846 printf("%s: invalid firmware size (should be 4KB)\n", 847 sc->sc_dev.dv_xname); 848 free(ucode, M_DEVBUF, size); 849 return EINVAL; 850 } 851 852 /* write microcode image */ 853 run_write_region_1(sc, RT2870_FW_BASE, ucode, size); 854 free(ucode, M_DEVBUF, size); 855 run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 856 run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 857 858 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 859 req.bRequest = RT2870_RESET; 860 USETW(req.wValue, 8); 861 USETW(req.wIndex, 0); 862 USETW(req.wLength, 0); 863 if ((error = usbd_do_request(sc->sc_udev, &req, NULL)) != 0) 864 return error; 865 866 usbd_delay_ms(sc->sc_udev, 10); 867 run_write(sc, RT2860_H2M_BBPAGENT, 0); 868 run_write(sc, RT2860_H2M_MAILBOX, 0); 869 run_write(sc, RT2860_H2M_INTSRC, 0); 870 if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) 871 return error; 872 873 /* wait until microcontroller is ready */ 874 for (ntries = 0; ntries < 1000; ntries++) { 875 if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) 876 return error; 877 if (tmp & RT2860_MCU_READY) 878 break; 879 DELAY(1000); 880 } 881 if (ntries == 1000) { 882 printf("%s: timeout waiting for MCU to initialize\n", 883 sc->sc_dev.dv_xname); 884 return ETIMEDOUT; 885 } 886 DPRINTF(("microcode successfully loaded after %d tries\n", ntries)); 887 return 0; 888 } 889 890 int 891 run_reset(struct run_softc *sc) 892 { 893 usb_device_request_t req; 894 895 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 896 req.bRequest = RT2870_RESET; 897 USETW(req.wValue, 1); 898 USETW(req.wIndex, 0); 899 USETW(req.wLength, 0); 900 return usbd_do_request(sc->sc_udev, &req, NULL); 901 } 902 903 int 904 run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) 905 { 906 uint32_t tmp; 907 int error; 908 909 error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp); 910 if (error == 0) 911 *val = letoh32(tmp); 912 else 913 *val = 0xffffffff; 914 return error; 915 } 916 917 int 918 run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) 919 { 920 usb_device_request_t req; 921 922 req.bmRequestType = UT_READ_VENDOR_DEVICE; 923 req.bRequest = RT2870_READ_REGION_1; 924 USETW(req.wValue, 0); 925 USETW(req.wIndex, reg); 926 USETW(req.wLength, len); 927 return usbd_do_request(sc->sc_udev, &req, buf); 928 } 929 930 int 931 run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) 932 { 933 usb_device_request_t req; 934 935 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 936 req.bRequest = RT2870_WRITE_2; 937 USETW(req.wValue, val); 938 USETW(req.wIndex, reg); 939 USETW(req.wLength, 0); 940 return usbd_do_request(sc->sc_udev, &req, NULL); 941 } 942 943 int 944 run_write(struct run_softc *sc, uint16_t reg, uint32_t val) 945 { 946 int error; 947 948 if ((error = run_write_2(sc, reg, val & 0xffff)) == 0) 949 error = run_write_2(sc, reg + 2, val >> 16); 950 return error; 951 } 952 953 int 954 run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, 955 int len) 956 { 957 #if 1 958 int i, error = 0; 959 /* 960 * NB: the WRITE_REGION_1 command is not stable on RT2860. 961 * We thus issue multiple WRITE_2 commands instead. 962 */ 963 KASSERT((len & 1) == 0); 964 for (i = 0; i < len && error == 0; i += 2) 965 error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); 966 return error; 967 #else 968 usb_device_request_t req; 969 970 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 971 req.bRequest = RT2870_WRITE_REGION_1; 972 USETW(req.wValue, 0); 973 USETW(req.wIndex, reg); 974 USETW(req.wLength, len); 975 return usbd_do_request(sc->sc_udev, &req, buf); 976 #endif 977 } 978 979 int 980 run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) 981 { 982 int error = 0; 983 984 for (; count > 0 && error == 0; count--, reg += 4) 985 error = run_write(sc, reg, val); 986 return error; 987 } 988 989 /* Read 16-bit from eFUSE ROM. */ 990 int 991 run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 992 { 993 uint32_t tmp; 994 uint16_t reg; 995 int error, ntries; 996 997 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 998 return error; 999 1000 /*- 1001 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1002 * DATA0: F E D C 1003 * DATA1: B A 9 8 1004 * DATA2: 7 6 5 4 1005 * DATA3: 3 2 1 0 1006 */ 1007 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1008 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1009 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1010 for (ntries = 0; ntries < 100; ntries++) { 1011 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1012 return error; 1013 if (!(tmp & RT3070_EFSROM_KICK)) 1014 break; 1015 DELAY(2); 1016 } 1017 if (ntries == 100) 1018 return ETIMEDOUT; 1019 1020 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1021 *val = 0xffff; /* address not found */ 1022 return 0; 1023 } 1024 /* determine to which 32-bit register our 16-bit word belongs */ 1025 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1026 if ((error = run_read(sc, reg, &tmp)) != 0) 1027 return error; 1028 1029 tmp >>= (8 * (addr & 0x3)); 1030 *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; 1031 return 0; 1032 } 1033 1034 /* Read 16-bit from eFUSE ROM for RT3xxx. */ 1035 int 1036 run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1037 { 1038 uint32_t tmp; 1039 uint16_t reg; 1040 int error, ntries; 1041 1042 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1043 return error; 1044 1045 addr *= 2; 1046 /*- 1047 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1048 * DATA0: F E D C 1049 * DATA1: B A 9 8 1050 * DATA2: 7 6 5 4 1051 * DATA3: 3 2 1 0 1052 */ 1053 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1054 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1055 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1056 for (ntries = 0; ntries < 100; ntries++) { 1057 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1058 return error; 1059 if (!(tmp & RT3070_EFSROM_KICK)) 1060 break; 1061 DELAY(2); 1062 } 1063 if (ntries == 100) 1064 return ETIMEDOUT; 1065 1066 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1067 *val = 0xffff; /* address not found */ 1068 return 0; 1069 } 1070 /* determine to which 32-bit register our 16-bit word belongs */ 1071 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1072 if ((error = run_read(sc, reg, &tmp)) != 0) 1073 return error; 1074 1075 *val = (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1076 return 0; 1077 } 1078 1079 int 1080 run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1081 { 1082 usb_device_request_t req; 1083 uint16_t tmp; 1084 int error; 1085 1086 addr *= 2; 1087 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1088 req.bRequest = RT2870_EEPROM_READ; 1089 USETW(req.wValue, 0); 1090 USETW(req.wIndex, addr); 1091 USETW(req.wLength, sizeof tmp); 1092 error = usbd_do_request(sc->sc_udev, &req, &tmp); 1093 if (error == 0) 1094 *val = letoh16(tmp); 1095 else 1096 *val = 0xffff; 1097 return error; 1098 } 1099 1100 static __inline int 1101 run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 1102 { 1103 /* either eFUSE ROM or EEPROM */ 1104 return sc->sc_srom_read(sc, addr, val); 1105 } 1106 1107 int 1108 run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) 1109 { 1110 uint32_t tmp; 1111 int error, ntries; 1112 1113 for (ntries = 0; ntries < 10; ntries++) { 1114 if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0) 1115 return error; 1116 if (!(tmp & RT2860_RF_REG_CTRL)) 1117 break; 1118 } 1119 if (ntries == 10) 1120 return ETIMEDOUT; 1121 1122 /* RF registers are 24-bit on the RT2860 */ 1123 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1124 (val & 0x3fffff) << 2 | (reg & 3); 1125 return run_write(sc, RT2860_RF_CSR_CFG0, tmp); 1126 } 1127 1128 int 1129 run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1130 { 1131 uint32_t tmp; 1132 int error, ntries; 1133 1134 for (ntries = 0; ntries < 100; ntries++) { 1135 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1136 return error; 1137 if (!(tmp & RT3070_RF_KICK)) 1138 break; 1139 } 1140 if (ntries == 100) 1141 return ETIMEDOUT; 1142 1143 tmp = RT3070_RF_KICK | reg << 8; 1144 if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0) 1145 return error; 1146 1147 for (ntries = 0; ntries < 100; ntries++) { 1148 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1149 return error; 1150 if (!(tmp & RT3070_RF_KICK)) 1151 break; 1152 } 1153 if (ntries == 100) 1154 return ETIMEDOUT; 1155 1156 *val = tmp & 0xff; 1157 return 0; 1158 } 1159 1160 int 1161 run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1162 { 1163 uint32_t tmp; 1164 int error, ntries; 1165 1166 for (ntries = 0; ntries < 10; ntries++) { 1167 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1168 return error; 1169 if (!(tmp & RT3070_RF_KICK)) 1170 break; 1171 } 1172 if (ntries == 10) 1173 return ETIMEDOUT; 1174 1175 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 1176 return run_write(sc, RT3070_RF_CSR_CFG, tmp); 1177 } 1178 1179 int 1180 run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1181 { 1182 uint32_t tmp; 1183 int ntries, error; 1184 1185 for (ntries = 0; ntries < 10; ntries++) { 1186 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1187 return error; 1188 if (!(tmp & RT2860_BBP_CSR_KICK)) 1189 break; 1190 } 1191 if (ntries == 10) 1192 return ETIMEDOUT; 1193 1194 tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8; 1195 if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0) 1196 return error; 1197 1198 for (ntries = 0; ntries < 10; ntries++) { 1199 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1200 return error; 1201 if (!(tmp & RT2860_BBP_CSR_KICK)) 1202 break; 1203 } 1204 if (ntries == 10) 1205 return ETIMEDOUT; 1206 1207 *val = tmp & 0xff; 1208 return 0; 1209 } 1210 1211 int 1212 run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1213 { 1214 uint32_t tmp; 1215 int ntries, error; 1216 1217 for (ntries = 0; ntries < 10; ntries++) { 1218 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1219 return error; 1220 if (!(tmp & RT2860_BBP_CSR_KICK)) 1221 break; 1222 } 1223 if (ntries == 10) 1224 return ETIMEDOUT; 1225 1226 tmp = RT2860_BBP_CSR_KICK | reg << 8 | val; 1227 return run_write(sc, RT2860_BBP_CSR_CFG, tmp); 1228 } 1229 1230 /* 1231 * Send a command to the 8051 microcontroller unit. 1232 */ 1233 int 1234 run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) 1235 { 1236 uint32_t tmp; 1237 int error, ntries; 1238 1239 for (ntries = 0; ntries < 100; ntries++) { 1240 if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0) 1241 return error; 1242 if (!(tmp & RT2860_H2M_BUSY)) 1243 break; 1244 } 1245 if (ntries == 100) 1246 return ETIMEDOUT; 1247 1248 tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg; 1249 if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0) 1250 error = run_write(sc, RT2860_HOST_CMD, cmd); 1251 return error; 1252 } 1253 1254 /* 1255 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 1256 * Used to adjust per-rate Tx power registers. 1257 */ 1258 static __inline uint32_t 1259 b4inc(uint32_t b32, int8_t delta) 1260 { 1261 int8_t i, b4; 1262 1263 for (i = 0; i < 8; i++) { 1264 b4 = b32 & 0xf; 1265 b4 += delta; 1266 if (b4 < 0) 1267 b4 = 0; 1268 else if (b4 > 0xf) 1269 b4 = 0xf; 1270 b32 = b32 >> 4 | b4 << 28; 1271 } 1272 return b32; 1273 } 1274 1275 const char * 1276 run_get_rf(int rev) 1277 { 1278 switch (rev) { 1279 case RT2860_RF_2820: return "RT2820"; 1280 case RT2860_RF_2850: return "RT2850"; 1281 case RT2860_RF_2720: return "RT2720"; 1282 case RT2860_RF_2750: return "RT2750"; 1283 case RT3070_RF_3020: return "RT3020"; 1284 case RT3070_RF_2020: return "RT2020"; 1285 case RT3070_RF_3021: return "RT3021"; 1286 case RT3070_RF_3022: return "RT3022"; 1287 case RT3070_RF_3052: return "RT3052"; 1288 case RT3070_RF_3053: return "RT3053"; 1289 case RT5592_RF_5592: return "RT5592"; 1290 case RT5390_RF_5370: return "RT5370"; 1291 case RT5390_RF_5372: return "RT5372"; 1292 } 1293 return "unknown"; 1294 } 1295 1296 void 1297 run_rt3593_get_txpower(struct run_softc *sc) 1298 { 1299 uint16_t addr, val; 1300 int i; 1301 1302 /* Read power settings for 2GHz channels. */ 1303 for (i = 0; i < 14; i += 2) { 1304 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : 1305 RT2860_EEPROM_PWR2GHZ_BASE1; 1306 run_srom_read(sc, addr + i / 2, &val); 1307 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1308 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1309 1310 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : 1311 RT2860_EEPROM_PWR2GHZ_BASE2; 1312 run_srom_read(sc, addr + i / 2, &val); 1313 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1314 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1315 1316 if (sc->ntxchains == 3) { 1317 run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, 1318 &val); 1319 sc->txpow3[i + 0] = (int8_t)(val & 0xff); 1320 sc->txpow3[i + 1] = (int8_t)(val >> 8); 1321 } 1322 } 1323 /* Fix broken Tx power entries. */ 1324 for (i = 0; i < 14; i++) { 1325 if (sc->txpow1[i] > 31) 1326 sc->txpow1[i] = 5; 1327 if (sc->txpow2[i] > 31) 1328 sc->txpow2[i] = 5; 1329 if (sc->ntxchains == 3) { 1330 if (sc->txpow3[i] > 31) 1331 sc->txpow3[i] = 5; 1332 } 1333 } 1334 /* Read power settings for 5GHz channels. */ 1335 for (i = 0; i < 40; i += 2) { 1336 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1337 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1338 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1339 1340 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1341 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1342 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1343 1344 if (sc->ntxchains == 3) { 1345 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, 1346 &val); 1347 sc->txpow3[i + 14] = (int8_t)(val & 0xff); 1348 sc->txpow3[i + 15] = (int8_t)(val >> 8); 1349 } 1350 } 1351 } 1352 1353 void 1354 run_get_txpower(struct run_softc *sc) 1355 { 1356 uint16_t val; 1357 int i; 1358 1359 /* Read power settings for 2GHz channels. */ 1360 for (i = 0; i < 14; i += 2) { 1361 run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); 1362 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1363 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1364 1365 if (sc->mac_ver != 0x5390) { 1366 run_srom_read(sc, 1367 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); 1368 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1369 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1370 } 1371 } 1372 /* Fix broken Tx power entries. */ 1373 for (i = 0; i < 14; i++) { 1374 if (sc->mac_ver >= 0x5390) { 1375 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 27) 1376 sc->txpow1[i] = 5; 1377 } else { 1378 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 1379 sc->txpow1[i] = 5; 1380 } 1381 if (sc->mac_ver > 0x5390) { 1382 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 27) 1383 sc->txpow2[i] = 5; 1384 } else if (sc->mac_ver < 0x5390) { 1385 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 1386 sc->txpow2[i] = 5; 1387 } 1388 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1389 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 1390 } 1391 /* Read power settings for 5GHz channels. */ 1392 for (i = 0; i < 40; i += 2) { 1393 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1394 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1395 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1396 1397 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1398 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1399 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1400 } 1401 /* Fix broken Tx power entries. */ 1402 for (i = 0; i < 40; i++ ) { 1403 if (sc->mac_ver != 0x5592) { 1404 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 1405 sc->txpow1[14 + i] = 5; 1406 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 1407 sc->txpow2[14 + i] = 5; 1408 } 1409 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1410 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 1411 sc->txpow2[14 + i])); 1412 } 1413 } 1414 1415 int 1416 run_read_eeprom(struct run_softc *sc) 1417 { 1418 struct ieee80211com *ic = &sc->sc_ic; 1419 int8_t delta_2ghz, delta_5ghz; 1420 uint32_t tmp; 1421 uint16_t val; 1422 int ridx, ant, i; 1423 1424 /* check whether the ROM is eFUSE ROM or EEPROM */ 1425 sc->sc_srom_read = run_eeprom_read_2; 1426 if (sc->mac_ver >= 0x3070) { 1427 run_read(sc, RT3070_EFUSE_CTRL, &tmp); 1428 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 1429 if (tmp & RT3070_SEL_EFUSE || sc->mac_ver == 0x3593) 1430 sc->sc_srom_read = run_efuse_read_2; 1431 } 1432 1433 /* read ROM version */ 1434 run_srom_read(sc, RT2860_EEPROM_VERSION, &val); 1435 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 1436 1437 /* read MAC address */ 1438 run_srom_read(sc, RT2860_EEPROM_MAC01, &val); 1439 ic->ic_myaddr[0] = val & 0xff; 1440 ic->ic_myaddr[1] = val >> 8; 1441 run_srom_read(sc, RT2860_EEPROM_MAC23, &val); 1442 ic->ic_myaddr[2] = val & 0xff; 1443 ic->ic_myaddr[3] = val >> 8; 1444 run_srom_read(sc, RT2860_EEPROM_MAC45, &val); 1445 ic->ic_myaddr[4] = val & 0xff; 1446 ic->ic_myaddr[5] = val >> 8; 1447 1448 if (sc->mac_ver < 0x3593) { 1449 /* read vendor BBP settings */ 1450 for (i = 0; i < 10; i++) { 1451 run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); 1452 sc->bbp[i].val = val & 0xff; 1453 sc->bbp[i].reg = val >> 8; 1454 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, 1455 sc->bbp[i].val)); 1456 } 1457 if (sc->mac_ver >= 0x3071) { 1458 /* read vendor RF settings */ 1459 for (i = 0; i < 10; i++) { 1460 run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, 1461 &val); 1462 sc->rf[i].val = val & 0xff; 1463 sc->rf[i].reg = val >> 8; 1464 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 1465 sc->rf[i].val)); 1466 } 1467 } 1468 } 1469 1470 /* read RF frequency offset from EEPROM */ 1471 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1472 RT3593_EEPROM_FREQ, &val); 1473 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 1474 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 1475 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1476 RT3593_EEPROM_FREQ_LEDS, &val); 1477 if ((val >> 8) != 0xff) { 1478 /* read LEDs operating mode */ 1479 sc->leds = val >> 8; 1480 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED1 : 1481 RT3593_EEPROM_LED1, &sc->led[0]); 1482 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED2 : 1483 RT3593_EEPROM_LED2, &sc->led[1]); 1484 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED3 : 1485 RT3593_EEPROM_LED3, &sc->led[2]); 1486 } else { 1487 /* broken EEPROM, use default settings */ 1488 sc->leds = 0x01; 1489 sc->led[0] = 0x5555; 1490 sc->led[1] = 0x2221; 1491 sc->led[2] = 0x5627; /* differs from RT2860 */ 1492 } 1493 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 1494 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 1495 1496 /* read RF information */ 1497 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) 1498 run_srom_read(sc, 0x00, &val); 1499 else 1500 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1501 if (val == 0xffff) { 1502 DPRINTF(("invalid EEPROM antenna info, using default\n")); 1503 if (sc->mac_ver == 0x3572) { 1504 /* default to RF3052 2T2R */ 1505 sc->rf_rev = RT3070_RF_3052; 1506 sc->ntxchains = 2; 1507 sc->nrxchains = 2; 1508 } else if (sc->mac_ver >= 0x3070) { 1509 /* default to RF3020 1T1R */ 1510 sc->rf_rev = RT3070_RF_3020; 1511 sc->ntxchains = 1; 1512 sc->nrxchains = 1; 1513 } else { 1514 /* default to RF2820 1T2R */ 1515 sc->rf_rev = RT2860_RF_2820; 1516 sc->ntxchains = 1; 1517 sc->nrxchains = 2; 1518 } 1519 } else { 1520 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) { 1521 sc->rf_rev = val; 1522 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1523 } else 1524 sc->rf_rev = (val >> 8) & 0xf; 1525 sc->ntxchains = (val >> 4) & 0xf; 1526 sc->nrxchains = val & 0xf; 1527 } 1528 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 1529 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 1530 1531 /* check if RF supports automatic Tx access gain control */ 1532 run_srom_read(sc, RT2860_EEPROM_CONFIG, &val); 1533 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 1534 /* check if driver should patch the DAC issue */ 1535 if ((val >> 8) != 0xff) 1536 sc->patch_dac = (val >> 15) & 1; 1537 if ((val & 0xff) != 0xff) { 1538 sc->ext_5ghz_lna = (val >> 3) & 1; 1539 sc->ext_2ghz_lna = (val >> 2) & 1; 1540 /* check if RF supports automatic Tx access gain control */ 1541 sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; 1542 /* check if we have a hardware radio switch */ 1543 sc->rfswitch = val & 1; 1544 } 1545 1546 /* Read Tx power settings. */ 1547 if (sc->mac_ver == 0x3593) 1548 run_rt3593_get_txpower(sc); 1549 else 1550 run_get_txpower(sc); 1551 1552 /* read Tx power compensation for each Tx rate */ 1553 run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); 1554 delta_2ghz = delta_5ghz = 0; 1555 if ((val & 0xff) != 0xff && (val & 0x80)) { 1556 delta_2ghz = val & 0xf; 1557 if (!(val & 0x40)) /* negative number */ 1558 delta_2ghz = -delta_2ghz; 1559 } 1560 val >>= 8; 1561 if ((val & 0xff) != 0xff && (val & 0x80)) { 1562 delta_5ghz = val & 0xf; 1563 if (!(val & 0x40)) /* negative number */ 1564 delta_5ghz = -delta_5ghz; 1565 } 1566 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 1567 delta_2ghz, delta_5ghz)); 1568 1569 for (ridx = 0; ridx < 5; ridx++) { 1570 uint32_t reg; 1571 1572 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val); 1573 reg = val; 1574 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val); 1575 reg |= (uint32_t)val << 16; 1576 1577 sc->txpow20mhz[ridx] = reg; 1578 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 1579 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 1580 1581 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 1582 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 1583 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 1584 } 1585 1586 /* read RSSI offsets and LNA gains from EEPROM */ 1587 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_2GHZ : 1588 RT3593_EEPROM_RSSI1_2GHZ, &val); 1589 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 1590 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 1591 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_2GHZ : 1592 RT3593_EEPROM_RSSI2_2GHZ, &val); 1593 if (sc->mac_ver >= 0x3070) { 1594 if (sc->mac_ver == 0x3593) { 1595 sc->txmixgain_2ghz = 0; 1596 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1597 } else { 1598 /* 1599 * On RT3070 chips (limited to 2 Rx chains), this ROM 1600 * field contains the Tx mixer gain for the 2GHz band. 1601 */ 1602 if ((val & 0xff) != 0xff) 1603 sc->txmixgain_2ghz = val & 0x7; 1604 } 1605 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 1606 } else 1607 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1608 if (sc->mac_ver == 0x3593) 1609 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1610 sc->lna[2] = val >> 8; /* channel group 2 */ 1611 1612 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : 1613 RT3593_EEPROM_RSSI1_5GHZ, &val); 1614 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 1615 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 1616 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : 1617 RT3593_EEPROM_RSSI2_5GHZ, &val); 1618 if (sc->mac_ver == 0x3572) { 1619 /* 1620 * On RT3572 chips (limited to 2 Rx chains), this ROM 1621 * field contains the Tx mixer gain for the 5GHz band. 1622 */ 1623 if ((val & 0xff) != 0xff) 1624 sc->txmixgain_5ghz = val & 0x7; 1625 DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz)); 1626 } else 1627 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 1628 if (sc->mac_ver == 0x3593) { 1629 sc->txmixgain_5ghz = 0; 1630 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1631 } 1632 sc->lna[3] = val >> 8; /* channel group 3 */ 1633 1634 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : 1635 RT3593_EEPROM_LNA, &val); 1636 sc->lna[0] = val & 0xff; /* channel group 0 */ 1637 sc->lna[1] = val >> 8; /* channel group 1 */ 1638 1639 /* fix broken 5GHz LNA entries */ 1640 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 1641 DPRINTF(("invalid LNA for channel group %d\n", 2)); 1642 sc->lna[2] = sc->lna[1]; 1643 } 1644 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 1645 DPRINTF(("invalid LNA for channel group %d\n", 3)); 1646 sc->lna[3] = sc->lna[1]; 1647 } 1648 1649 /* fix broken RSSI offset entries */ 1650 for (ant = 0; ant < 3; ant++) { 1651 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 1652 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 1653 ant + 1, sc->rssi_2ghz[ant])); 1654 sc->rssi_2ghz[ant] = 0; 1655 } 1656 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 1657 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 1658 ant + 1, sc->rssi_5ghz[ant])); 1659 sc->rssi_5ghz[ant] = 0; 1660 } 1661 } 1662 return 0; 1663 } 1664 1665 struct ieee80211_node * 1666 run_node_alloc(struct ieee80211com *ic) 1667 { 1668 return malloc(sizeof (struct run_node), M_USBDEV, M_NOWAIT | M_ZERO); 1669 } 1670 1671 int 1672 run_media_change(struct ifnet *ifp) 1673 { 1674 struct run_softc *sc = ifp->if_softc; 1675 struct ieee80211com *ic = &sc->sc_ic; 1676 uint8_t rate, ridx; 1677 int error; 1678 1679 error = ieee80211_media_change(ifp); 1680 if (error != ENETRESET) 1681 return error; 1682 1683 if (ic->ic_fixed_rate != -1) { 1684 rate = ic->ic_sup_rates[ic->ic_curmode]. 1685 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1686 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 1687 if (rt2860_rates[ridx].rate == rate) 1688 break; 1689 sc->fixed_ridx = ridx; 1690 } 1691 1692 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1693 (IFF_UP | IFF_RUNNING)) { 1694 run_stop(ifp, 0); 1695 error = run_init(ifp); 1696 } 1697 1698 return error; 1699 } 1700 1701 void 1702 run_next_scan(void *arg) 1703 { 1704 struct run_softc *sc = arg; 1705 int s; 1706 1707 if (usbd_is_dying(sc->sc_udev)) 1708 return; 1709 1710 usbd_ref_incr(sc->sc_udev); 1711 1712 s = splnet(); 1713 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1714 ieee80211_next_scan(&sc->sc_ic.ic_if); 1715 splx(s); 1716 1717 usbd_ref_decr(sc->sc_udev); 1718 } 1719 1720 void 1721 run_task(void *arg) 1722 { 1723 struct run_softc *sc = arg; 1724 struct run_host_cmd_ring *ring = &sc->cmdq; 1725 struct run_host_cmd *cmd; 1726 int s; 1727 1728 if (usbd_is_dying(sc->sc_udev)) 1729 return; 1730 1731 /* process host commands */ 1732 s = splusb(); 1733 while (ring->next != ring->cur) { 1734 cmd = &ring->cmd[ring->next]; 1735 splx(s); 1736 /* callback */ 1737 cmd->cb(sc, cmd->data); 1738 s = splusb(); 1739 ring->queued--; 1740 ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT; 1741 } 1742 splx(s); 1743 } 1744 1745 void 1746 run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), 1747 void *arg, int len) 1748 { 1749 struct run_host_cmd_ring *ring = &sc->cmdq; 1750 struct run_host_cmd *cmd; 1751 int s; 1752 1753 if (usbd_is_dying(sc->sc_udev)) 1754 return; 1755 1756 s = splusb(); 1757 cmd = &ring->cmd[ring->cur]; 1758 cmd->cb = cb; 1759 KASSERT(len <= sizeof (cmd->data)); 1760 memcpy(cmd->data, arg, len); 1761 ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT; 1762 1763 /* if there is no pending command already, schedule a task */ 1764 if (++ring->queued == 1) 1765 usb_add_task(sc->sc_udev, &sc->sc_task); 1766 splx(s); 1767 } 1768 1769 int 1770 run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1771 { 1772 struct run_softc *sc = ic->ic_softc; 1773 struct run_cmd_newstate cmd; 1774 1775 /* do it in a process context */ 1776 cmd.state = nstate; 1777 cmd.arg = arg; 1778 run_do_async(sc, run_newstate_cb, &cmd, sizeof cmd); 1779 return 0; 1780 } 1781 1782 void 1783 run_newstate_cb(struct run_softc *sc, void *arg) 1784 { 1785 struct run_cmd_newstate *cmd = arg; 1786 struct ieee80211com *ic = &sc->sc_ic; 1787 enum ieee80211_state ostate; 1788 struct ieee80211_node *ni; 1789 uint32_t tmp, sta[3]; 1790 uint8_t wcid; 1791 int s; 1792 1793 s = splnet(); 1794 ostate = ic->ic_state; 1795 1796 if (ostate == IEEE80211_S_RUN) { 1797 /* turn link LED off */ 1798 run_set_leds(sc, RT2860_LED_RADIO); 1799 } 1800 1801 switch (cmd->state) { 1802 case IEEE80211_S_INIT: 1803 if (ostate == IEEE80211_S_RUN) { 1804 /* abort TSF synchronization */ 1805 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 1806 run_write(sc, RT2860_BCN_TIME_CFG, 1807 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1808 RT2860_TBTT_TIMER_EN)); 1809 } 1810 break; 1811 1812 case IEEE80211_S_SCAN: 1813 run_set_chan(sc, ic->ic_bss->ni_chan); 1814 if (!usbd_is_dying(sc->sc_udev)) 1815 timeout_add_msec(&sc->scan_to, 200); 1816 break; 1817 1818 case IEEE80211_S_AUTH: 1819 case IEEE80211_S_ASSOC: 1820 run_set_chan(sc, ic->ic_bss->ni_chan); 1821 break; 1822 1823 case IEEE80211_S_RUN: 1824 run_set_chan(sc, ic->ic_bss->ni_chan); 1825 1826 ni = ic->ic_bss; 1827 1828 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1829 run_updateslot(ic); 1830 run_enable_mrr(sc); 1831 run_set_txpreamble(sc); 1832 run_set_basicrates(sc); 1833 run_set_bssid(sc, ni->ni_bssid); 1834 } 1835 if (ic->ic_opmode == IEEE80211_M_STA) { 1836 /* add BSS entry to the WCID table */ 1837 wcid = RUN_AID2WCID(ni->ni_associd); 1838 run_write_region_1(sc, RT2860_WCID_ENTRY(wcid), 1839 ni->ni_macaddr, IEEE80211_ADDR_LEN); 1840 1841 /* fake a join to init the tx rate */ 1842 run_newassoc(ic, ni, 1); 1843 } 1844 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1845 run_enable_tsf_sync(sc); 1846 1847 /* clear statistic registers used by AMRR */ 1848 run_read_region_1(sc, RT2860_TX_STA_CNT0, 1849 (uint8_t *)sta, sizeof sta); 1850 /* start calibration timer */ 1851 if (!usbd_is_dying(sc->sc_udev)) 1852 timeout_add_sec(&sc->calib_to, 1); 1853 } 1854 1855 /* turn link LED on */ 1856 run_set_leds(sc, RT2860_LED_RADIO | 1857 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ? 1858 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1859 break; 1860 } 1861 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 1862 splx(s); 1863 } 1864 1865 void 1866 run_updateedca(struct ieee80211com *ic) 1867 { 1868 /* do it in a process context */ 1869 run_do_async(ic->ic_softc, run_updateedca_cb, NULL, 0); 1870 } 1871 1872 /* ARGSUSED */ 1873 void 1874 run_updateedca_cb(struct run_softc *sc, void *arg) 1875 { 1876 struct ieee80211com *ic = &sc->sc_ic; 1877 int s, aci; 1878 1879 s = splnet(); 1880 /* update MAC TX configuration registers */ 1881 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 1882 run_write(sc, RT2860_EDCA_AC_CFG(aci), 1883 ic->ic_edca_ac[aci].ac_ecwmax << 16 | 1884 ic->ic_edca_ac[aci].ac_ecwmin << 12 | 1885 ic->ic_edca_ac[aci].ac_aifsn << 8 | 1886 ic->ic_edca_ac[aci].ac_txoplimit); 1887 } 1888 1889 /* update SCH/DMA registers too */ 1890 run_write(sc, RT2860_WMM_AIFSN_CFG, 1891 ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | 1892 ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | 1893 ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 | 1894 ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn); 1895 run_write(sc, RT2860_WMM_CWMIN_CFG, 1896 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | 1897 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | 1898 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 | 1899 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin); 1900 run_write(sc, RT2860_WMM_CWMAX_CFG, 1901 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | 1902 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | 1903 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 | 1904 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax); 1905 run_write(sc, RT2860_WMM_TXOP0_CFG, 1906 ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | 1907 ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit); 1908 run_write(sc, RT2860_WMM_TXOP1_CFG, 1909 ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | 1910 ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit); 1911 splx(s); 1912 } 1913 1914 int 1915 run_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1916 struct ieee80211_key *k) 1917 { 1918 struct run_softc *sc = ic->ic_softc; 1919 struct run_cmd_key cmd; 1920 1921 /* defer setting of WEP keys until interface is brought up */ 1922 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1923 (IFF_UP | IFF_RUNNING)) 1924 return 0; 1925 1926 /* do it in a process context */ 1927 cmd.key = *k; 1928 cmd.ni = ni; 1929 run_do_async(sc, run_set_key_cb, &cmd, sizeof cmd); 1930 sc->sc_key_tasks++; 1931 1932 return EBUSY; 1933 } 1934 1935 void 1936 run_set_key_cb(struct run_softc *sc, void *arg) 1937 { 1938 struct ieee80211com *ic = &sc->sc_ic; 1939 struct run_cmd_key *cmd = arg; 1940 struct ieee80211_key *k = &cmd->key; 1941 uint32_t attr; 1942 uint16_t base; 1943 uint8_t mode, wcid, iv[8]; 1944 1945 sc->sc_key_tasks--; 1946 1947 /* map net80211 cipher to RT2860 security mode */ 1948 switch (k->k_cipher) { 1949 case IEEE80211_CIPHER_WEP40: 1950 mode = RT2860_MODE_WEP40; 1951 break; 1952 case IEEE80211_CIPHER_WEP104: 1953 mode = RT2860_MODE_WEP104; 1954 break; 1955 case IEEE80211_CIPHER_TKIP: 1956 mode = RT2860_MODE_TKIP; 1957 break; 1958 case IEEE80211_CIPHER_CCMP: 1959 mode = RT2860_MODE_AES_CCMP; 1960 break; 1961 default: 1962 IEEE80211_SEND_MGMT(ic, cmd->ni, IEEE80211_FC0_SUBTYPE_DEAUTH, 1963 IEEE80211_REASON_AUTH_LEAVE); 1964 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1965 return; 1966 } 1967 1968 if (k->k_flags & IEEE80211_KEY_GROUP) { 1969 wcid = 0; /* NB: update WCID0 for group keys */ 1970 base = RT2860_SKEY(0, k->k_id); 1971 } else { 1972 wcid = (cmd->ni != NULL) ? RUN_AID2WCID(cmd->ni->ni_associd) : 0; 1973 base = RT2860_PKEY(wcid); 1974 } 1975 1976 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 1977 run_write_region_1(sc, base, k->k_key, 16); 1978 run_write_region_1(sc, base + 16, &k->k_key[24], 8); 1979 run_write_region_1(sc, base + 24, &k->k_key[16], 8); 1980 } else { 1981 /* roundup len to 16-bit: XXX fix write_region_1() instead */ 1982 run_write_region_1(sc, base, k->k_key, (k->k_len + 1) & ~1); 1983 } 1984 1985 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 1986 (k->k_flags & IEEE80211_KEY_TX)) { 1987 /* set initial packet number in IV+EIV */ 1988 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 1989 k->k_cipher == IEEE80211_CIPHER_WEP104) { 1990 memset(iv, 0, sizeof iv); 1991 iv[3] = sc->sc_ic.ic_def_txkey << 6; 1992 } else { 1993 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 1994 iv[0] = k->k_tsc >> 8; 1995 iv[1] = (iv[0] | 0x20) & 0x7f; 1996 iv[2] = k->k_tsc; 1997 } else /* CCMP */ { 1998 iv[0] = k->k_tsc; 1999 iv[1] = k->k_tsc >> 8; 2000 iv[2] = 0; 2001 } 2002 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 2003 iv[4] = k->k_tsc >> 16; 2004 iv[5] = k->k_tsc >> 24; 2005 iv[6] = k->k_tsc >> 32; 2006 iv[7] = k->k_tsc >> 40; 2007 } 2008 run_write_region_1(sc, RT2860_IVEIV(wcid), iv, 8); 2009 } 2010 2011 if (k->k_flags & IEEE80211_KEY_GROUP) { 2012 /* install group key */ 2013 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2014 attr &= ~(0xf << (k->k_id * 4)); 2015 attr |= mode << (k->k_id * 4); 2016 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2017 } else { 2018 /* install pairwise key */ 2019 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2020 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2021 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2022 } 2023 2024 if (sc->sc_key_tasks == 0) { 2025 if (cmd->ni != NULL) 2026 cmd->ni->ni_port_valid = 1; 2027 ieee80211_set_link_state(ic, LINK_STATE_UP); 2028 } 2029 } 2030 2031 void 2032 run_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2033 struct ieee80211_key *k) 2034 { 2035 struct run_softc *sc = ic->ic_softc; 2036 struct run_cmd_key cmd; 2037 2038 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 2039 ic->ic_state != IEEE80211_S_RUN) 2040 return; /* nothing to do */ 2041 2042 /* do it in a process context */ 2043 cmd.key = *k; 2044 cmd.ni = ni; 2045 run_do_async(sc, run_delete_key_cb, &cmd, sizeof cmd); 2046 } 2047 2048 void 2049 run_delete_key_cb(struct run_softc *sc, void *arg) 2050 { 2051 struct run_cmd_key *cmd = arg; 2052 struct ieee80211_key *k = &cmd->key; 2053 uint32_t attr; 2054 uint8_t wcid; 2055 2056 if (k->k_flags & IEEE80211_KEY_GROUP) { 2057 /* remove group key */ 2058 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2059 attr &= ~(0xf << (k->k_id * 4)); 2060 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2061 2062 } else { 2063 /* remove pairwise key */ 2064 wcid = (cmd->ni != NULL) ? RUN_AID2WCID(cmd->ni->ni_associd) : 0; 2065 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2066 attr &= ~0xf; 2067 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2068 } 2069 } 2070 2071 void 2072 run_calibrate_to(void *arg) 2073 { 2074 /* do it in a process context */ 2075 run_do_async(arg, run_calibrate_cb, NULL, 0); 2076 /* next timeout will be rescheduled in the calibration task */ 2077 } 2078 2079 /* ARGSUSED */ 2080 void 2081 run_calibrate_cb(struct run_softc *sc, void *arg) 2082 { 2083 struct ifnet *ifp = &sc->sc_ic.ic_if; 2084 uint32_t sta[3]; 2085 int s, error; 2086 2087 /* read statistic counters (clear on read) and update AMRR state */ 2088 error = run_read_region_1(sc, RT2860_TX_STA_CNT0, (uint8_t *)sta, 2089 sizeof sta); 2090 if (error != 0) 2091 goto skip; 2092 2093 DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n", 2094 letoh32(sta[1]) >> 16, letoh32(sta[1]) & 0xffff, 2095 letoh32(sta[0]) & 0xffff)); 2096 2097 s = splnet(); 2098 /* count failed TX as errors */ 2099 ifp->if_oerrors += letoh32(sta[0]) & 0xffff; 2100 2101 sc->amn.amn_retrycnt = 2102 (letoh32(sta[0]) & 0xffff) + /* failed TX count */ 2103 (letoh32(sta[1]) >> 16); /* TX retransmission count */ 2104 2105 sc->amn.amn_txcnt = 2106 sc->amn.amn_retrycnt + 2107 (letoh32(sta[1]) & 0xffff); /* successful TX count */ 2108 2109 ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); 2110 splx(s); 2111 2112 skip: 2113 if (!usbd_is_dying(sc->sc_udev)) 2114 timeout_add_sec(&sc->calib_to, 1); 2115 } 2116 2117 void 2118 run_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 2119 { 2120 struct run_softc *sc = ic->ic_softc; 2121 struct run_node *rn = (void *)ni; 2122 struct ieee80211_rateset *rs = &ni->ni_rates; 2123 uint8_t rate; 2124 int ridx, i, j; 2125 2126 DPRINTF(("new assoc isnew=%d addr=%s\n", 2127 isnew, ether_sprintf(ni->ni_macaddr))); 2128 2129 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2130 /* start at lowest available bit-rate, AMRR will raise */ 2131 ni->ni_txrate = 0; 2132 2133 for (i = 0; i < rs->rs_nrates; i++) { 2134 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2135 /* convert 802.11 rate to hardware rate index */ 2136 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 2137 if (rt2860_rates[ridx].rate == rate) 2138 break; 2139 rn->ridx[i] = ridx; 2140 /* determine rate of control response frames */ 2141 for (j = i; j >= 0; j--) { 2142 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 2143 rt2860_rates[rn->ridx[i]].phy == 2144 rt2860_rates[rn->ridx[j]].phy) 2145 break; 2146 } 2147 if (j >= 0) { 2148 rn->ctl_ridx[i] = rn->ridx[j]; 2149 } else { 2150 /* no basic rate found, use mandatory one */ 2151 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 2152 } 2153 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 2154 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 2155 } 2156 } 2157 2158 /* 2159 * Return the Rx chain with the highest RSSI for a given frame. 2160 */ 2161 static __inline uint8_t 2162 run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi) 2163 { 2164 uint8_t rxchain = 0; 2165 2166 if (sc->nrxchains > 1) { 2167 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 2168 rxchain = 1; 2169 if (sc->nrxchains > 2) 2170 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 2171 rxchain = 2; 2172 } 2173 return rxchain; 2174 } 2175 2176 void 2177 run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen, 2178 struct mbuf_list *ml) 2179 { 2180 struct ieee80211com *ic = &sc->sc_ic; 2181 struct ifnet *ifp = &ic->ic_if; 2182 struct ieee80211_frame *wh; 2183 struct ieee80211_rxinfo rxi; 2184 struct ieee80211_node *ni; 2185 struct rt2870_rxd *rxd; 2186 struct rt2860_rxwi *rxwi; 2187 struct mbuf *m; 2188 uint32_t flags; 2189 uint16_t len; 2190 #if NBPFILTER > 0 2191 uint16_t phy; 2192 #endif 2193 uint16_t rxwisize; 2194 uint8_t ant, rssi; 2195 int s; 2196 2197 rxwi = (struct rt2860_rxwi *)buf; 2198 rxwisize = sizeof(struct rt2860_rxwi); 2199 if (sc->mac_ver == 0x5592) 2200 rxwisize += sizeof(uint64_t); 2201 else if (sc->mac_ver == 0x3593) 2202 rxwisize += sizeof(uint32_t); 2203 len = letoh16(rxwi->len) & 0xfff; 2204 if (__predict_false(len > dmalen)) { 2205 DPRINTF(("bad RXWI length %u > %u\n", len, dmalen)); 2206 return; 2207 } 2208 if (len > MCLBYTES) { 2209 DPRINTF(("frame too large (length=%d)\n", len)); 2210 ifp->if_ierrors++; 2211 return; 2212 } 2213 /* Rx descriptor is located at the end */ 2214 rxd = (struct rt2870_rxd *)(buf + dmalen); 2215 flags = letoh32(rxd->flags); 2216 2217 if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 2218 ifp->if_ierrors++; 2219 return; 2220 } 2221 2222 if (__predict_false((flags & RT2860_RX_MICERR))) { 2223 /* report MIC failures to net80211 for TKIP */ 2224 ic->ic_stats.is_rx_locmicfail++; 2225 ieee80211_michael_mic_failure(ic, 0/* XXX */); 2226 ifp->if_ierrors++; 2227 return; 2228 } 2229 2230 wh = (struct ieee80211_frame *)(buf + rxwisize); 2231 memset(&rxi, 0, sizeof(rxi)); 2232 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2233 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 2234 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 2235 } 2236 2237 if (flags & RT2860_RX_L2PAD) { 2238 u_int hdrlen = ieee80211_get_hdrlen(wh); 2239 memmove((caddr_t)wh + 2, wh, hdrlen); 2240 wh = (struct ieee80211_frame *)((caddr_t)wh + 2); 2241 } 2242 2243 /* could use m_devget but net80211 wants contig mgmt frames */ 2244 MGETHDR(m, M_DONTWAIT, MT_DATA); 2245 if (__predict_false(m == NULL)) { 2246 ifp->if_ierrors++; 2247 return; 2248 } 2249 if (len > MHLEN) { 2250 MCLGET(m, M_DONTWAIT); 2251 if (__predict_false(!(m->m_flags & M_EXT))) { 2252 ifp->if_ierrors++; 2253 m_freem(m); 2254 return; 2255 } 2256 } 2257 /* finalize mbuf */ 2258 memcpy(mtod(m, caddr_t), wh, len); 2259 m->m_pkthdr.len = m->m_len = len; 2260 2261 ant = run_maxrssi_chain(sc, rxwi); 2262 rssi = rxwi->rssi[ant]; 2263 2264 #if NBPFILTER > 0 2265 if (__predict_false(sc->sc_drvbpf != NULL)) { 2266 struct run_rx_radiotap_header *tap = &sc->sc_rxtap; 2267 struct mbuf mb; 2268 2269 tap->wr_flags = 0; 2270 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 2271 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 2272 tap->wr_antsignal = rssi; 2273 tap->wr_antenna = ant; 2274 tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); 2275 tap->wr_rate = 2; /* in case it can't be found below */ 2276 phy = letoh16(rxwi->phy); 2277 switch (phy & RT2860_PHY_MODE) { 2278 case RT2860_PHY_CCK: 2279 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 2280 case 0: tap->wr_rate = 2; break; 2281 case 1: tap->wr_rate = 4; break; 2282 case 2: tap->wr_rate = 11; break; 2283 case 3: tap->wr_rate = 22; break; 2284 } 2285 if (phy & RT2860_PHY_SHPRE) 2286 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2287 break; 2288 case RT2860_PHY_OFDM: 2289 switch (phy & RT2860_PHY_MCS) { 2290 case 0: tap->wr_rate = 12; break; 2291 case 1: tap->wr_rate = 18; break; 2292 case 2: tap->wr_rate = 24; break; 2293 case 3: tap->wr_rate = 36; break; 2294 case 4: tap->wr_rate = 48; break; 2295 case 5: tap->wr_rate = 72; break; 2296 case 6: tap->wr_rate = 96; break; 2297 case 7: tap->wr_rate = 108; break; 2298 } 2299 break; 2300 } 2301 mb.m_data = (caddr_t)tap; 2302 mb.m_len = sc->sc_rxtap_len; 2303 mb.m_next = m; 2304 mb.m_nextpkt = NULL; 2305 mb.m_type = 0; 2306 mb.m_flags = 0; 2307 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 2308 } 2309 #endif 2310 2311 s = splnet(); 2312 ni = ieee80211_find_rxnode(ic, wh); 2313 rxi.rxi_rssi = rssi; 2314 ieee80211_inputm(ifp, m, ni, &rxi, ml); 2315 2316 /* node is no longer needed */ 2317 ieee80211_release_node(ic, ni); 2318 splx(s); 2319 } 2320 2321 void 2322 run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2323 { 2324 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2325 struct run_rx_data *data = priv; 2326 struct run_softc *sc = data->sc; 2327 uint8_t *buf; 2328 uint32_t dmalen; 2329 int xferlen; 2330 uint16_t rxwisize; 2331 2332 rxwisize = sizeof(struct rt2860_rxwi); 2333 if (sc->mac_ver == 0x5592) 2334 rxwisize += sizeof(uint64_t); 2335 else if (sc->mac_ver == 0x3593) 2336 rxwisize += sizeof(uint32_t); 2337 2338 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2339 DPRINTF(("RX status=%d\n", status)); 2340 if (status == USBD_STALLED) 2341 usbd_clear_endpoint_stall_async(sc->rxq.pipeh); 2342 if (status != USBD_CANCELLED) 2343 goto skip; 2344 return; 2345 } 2346 usbd_get_xfer_status(xfer, NULL, NULL, &xferlen, NULL); 2347 2348 if (__predict_false(xferlen < sizeof (uint32_t) + rxwisize + 2349 sizeof(struct rt2870_rxd))) { 2350 DPRINTF(("xfer too short %d\n", xferlen)); 2351 goto skip; 2352 } 2353 2354 /* HW can aggregate multiple 802.11 frames in a single USB xfer */ 2355 buf = data->buf; 2356 while (xferlen > 8) { 2357 dmalen = letoh32(*(uint32_t *)buf) & 0xffff; 2358 2359 if (__predict_false(dmalen == 0 || (dmalen & 3) != 0)) { 2360 DPRINTF(("bad DMA length %u\n", dmalen)); 2361 break; 2362 } 2363 if (__predict_false(dmalen + 8 > xferlen)) { 2364 DPRINTF(("bad DMA length %u > %d\n", 2365 dmalen + 8, xferlen)); 2366 break; 2367 } 2368 run_rx_frame(sc, buf + sizeof (uint32_t), dmalen, &ml); 2369 buf += dmalen + 8; 2370 xferlen -= dmalen + 8; 2371 } 2372 if_input(&sc->sc_ic.ic_if, &ml); 2373 2374 skip: /* setup a new transfer */ 2375 usbd_setup_xfer(xfer, sc->rxq.pipeh, data, data->buf, RUN_MAX_RXSZ, 2376 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, run_rxeof); 2377 (void)usbd_transfer(data->xfer); 2378 } 2379 2380 void 2381 run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2382 { 2383 struct run_tx_data *data = priv; 2384 struct run_softc *sc = data->sc; 2385 struct run_tx_ring *txq = &sc->txq[data->qid]; 2386 struct ifnet *ifp = &sc->sc_ic.ic_if; 2387 int s; 2388 2389 s = splnet(); 2390 txq->queued--; 2391 sc->qfullmsk &= ~(1 << data->qid); 2392 2393 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2394 DPRINTF(("TX status=%d\n", status)); 2395 if (status == USBD_STALLED) 2396 usbd_clear_endpoint_stall_async(txq->pipeh); 2397 ifp->if_oerrors++; 2398 splx(s); 2399 return; 2400 } 2401 2402 sc->sc_tx_timer = 0; 2403 ifq_clr_oactive(&ifp->if_snd); 2404 run_start(ifp); 2405 splx(s); 2406 } 2407 2408 int 2409 run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2410 { 2411 struct ieee80211com *ic = &sc->sc_ic; 2412 struct run_node *rn = (void *)ni; 2413 struct ieee80211_frame *wh; 2414 struct run_tx_ring *ring; 2415 struct run_tx_data *data; 2416 struct rt2870_txd *txd; 2417 struct rt2860_txwi *txwi; 2418 uint16_t qos, dur; 2419 uint16_t txwisize; 2420 uint8_t type, mcs, tid, qid; 2421 int error, hasqos, ridx, ctl_ridx, xferlen; 2422 2423 wh = mtod(m, struct ieee80211_frame *); 2424 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2425 2426 if ((hasqos = ieee80211_has_qos(wh))) { 2427 qos = ieee80211_get_qos(wh); 2428 tid = qos & IEEE80211_QOS_TID; 2429 qid = ieee80211_up_to_ac(ic, tid); 2430 } else { 2431 qos = 0; 2432 tid = 0; 2433 qid = EDCA_AC_BE; 2434 } 2435 ring = &sc->txq[qid]; 2436 data = &ring->data[ring->cur]; 2437 2438 /* pickup a rate index */ 2439 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2440 type != IEEE80211_FC0_TYPE_DATA) { 2441 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2442 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 2443 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2444 } else if (ic->ic_fixed_rate != -1) { 2445 ridx = sc->fixed_ridx; 2446 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2447 } else { 2448 ridx = rn->ridx[ni->ni_txrate]; 2449 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 2450 } 2451 2452 /* get MCS code from rate index */ 2453 mcs = rt2860_rates[ridx].mcs; 2454 2455 txwisize = sizeof(struct rt2860_txwi); 2456 if (sc->mac_ver == 0x5592) 2457 txwisize += sizeof(uint32_t); 2458 xferlen = txwisize + m->m_pkthdr.len; 2459 2460 /* roundup to 32-bit alignment */ 2461 xferlen = (xferlen + 3) & ~3; 2462 2463 txd = (struct rt2870_txd *)data->buf; 2464 txd->flags = RT2860_TX_QSEL_EDCA; 2465 txd->len = htole16(xferlen); 2466 2467 /* setup TX Wireless Information */ 2468 txwi = (struct rt2860_txwi *)(txd + 1); 2469 txwi->flags = 0; 2470 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 2471 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? 2472 RUN_AID2WCID(ni->ni_associd) : 0xff; 2473 txwi->len = htole16(m->m_pkthdr.len); 2474 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 2475 txwi->phy = htole16(RT2860_PHY_CCK); 2476 if (ridx != RT2860_RIDX_CCK1 && 2477 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 2478 mcs |= RT2860_PHY_SHPRE; 2479 } else 2480 txwi->phy = htole16(RT2860_PHY_OFDM); 2481 txwi->phy |= htole16(mcs); 2482 2483 txwi->txop = RT2860_TX_TXOP_BACKOFF; 2484 2485 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2486 (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 2487 IEEE80211_QOS_ACK_POLICY_NOACK)) { 2488 txwi->xflags |= RT2860_TX_ACK; 2489 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2490 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 2491 else 2492 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 2493 *(uint16_t *)wh->i_dur = htole16(dur); 2494 } 2495 2496 #if NBPFILTER > 0 2497 if (__predict_false(sc->sc_drvbpf != NULL)) { 2498 struct run_tx_radiotap_header *tap = &sc->sc_txtap; 2499 struct mbuf mb; 2500 2501 tap->wt_flags = 0; 2502 tap->wt_rate = rt2860_rates[ridx].rate; 2503 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2504 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2505 if (mcs & RT2860_PHY_SHPRE) 2506 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2507 2508 mb.m_data = (caddr_t)tap; 2509 mb.m_len = sc->sc_txtap_len; 2510 mb.m_next = m; 2511 mb.m_nextpkt = NULL; 2512 mb.m_type = 0; 2513 mb.m_flags = 0; 2514 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 2515 } 2516 #endif 2517 2518 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)txwi + txwisize); 2519 m_freem(m); 2520 2521 xferlen += sizeof (*txd) + 4; 2522 2523 usbd_setup_xfer(data->xfer, ring->pipeh, data, data->buf, xferlen, 2524 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, RUN_TX_TIMEOUT, run_txeof); 2525 error = usbd_transfer(data->xfer); 2526 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) 2527 return error; 2528 2529 ieee80211_release_node(ic, ni); 2530 2531 ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT; 2532 if (++ring->queued >= RUN_TX_RING_COUNT) 2533 sc->qfullmsk |= 1 << qid; 2534 2535 return 0; 2536 } 2537 2538 void 2539 run_start(struct ifnet *ifp) 2540 { 2541 struct run_softc *sc = ifp->if_softc; 2542 struct ieee80211com *ic = &sc->sc_ic; 2543 struct ieee80211_node *ni; 2544 struct mbuf *m; 2545 2546 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 2547 return; 2548 2549 for (;;) { 2550 if (sc->qfullmsk != 0) { 2551 ifq_set_oactive(&ifp->if_snd); 2552 break; 2553 } 2554 /* send pending management frames first */ 2555 m = mq_dequeue(&ic->ic_mgtq); 2556 if (m != NULL) { 2557 ni = m->m_pkthdr.ph_cookie; 2558 goto sendit; 2559 } 2560 if (ic->ic_state != IEEE80211_S_RUN) 2561 break; 2562 2563 /* encapsulate and send data frames */ 2564 m = ifq_dequeue(&ifp->if_snd); 2565 if (m == NULL) 2566 break; 2567 #if NBPFILTER > 0 2568 if (ifp->if_bpf != NULL) 2569 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 2570 #endif 2571 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 2572 continue; 2573 sendit: 2574 #if NBPFILTER > 0 2575 if (ic->ic_rawbpf != NULL) 2576 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 2577 #endif 2578 if (run_tx(sc, m, ni) != 0) { 2579 ieee80211_release_node(ic, ni); 2580 ifp->if_oerrors++; 2581 continue; 2582 } 2583 2584 sc->sc_tx_timer = 5; 2585 ifp->if_timer = 1; 2586 } 2587 } 2588 2589 void 2590 run_watchdog(struct ifnet *ifp) 2591 { 2592 struct run_softc *sc = ifp->if_softc; 2593 2594 ifp->if_timer = 0; 2595 2596 if (sc->sc_tx_timer > 0) { 2597 if (--sc->sc_tx_timer == 0) { 2598 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2599 /* run_init(ifp); XXX needs a process context! */ 2600 ifp->if_oerrors++; 2601 return; 2602 } 2603 ifp->if_timer = 1; 2604 } 2605 2606 ieee80211_watchdog(ifp); 2607 } 2608 2609 int 2610 run_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2611 { 2612 struct run_softc *sc = ifp->if_softc; 2613 struct ieee80211com *ic = &sc->sc_ic; 2614 int s, error = 0; 2615 2616 if (usbd_is_dying(sc->sc_udev)) 2617 return ENXIO; 2618 2619 usbd_ref_incr(sc->sc_udev); 2620 2621 s = splnet(); 2622 2623 switch (cmd) { 2624 case SIOCSIFADDR: 2625 ifp->if_flags |= IFF_UP; 2626 /* FALLTHROUGH */ 2627 case SIOCSIFFLAGS: 2628 if (ifp->if_flags & IFF_UP) { 2629 if (!(ifp->if_flags & IFF_RUNNING)) 2630 run_init(ifp); 2631 } else { 2632 if (ifp->if_flags & IFF_RUNNING) 2633 run_stop(ifp, 1); 2634 } 2635 break; 2636 2637 case SIOCS80211CHANNEL: 2638 /* 2639 * This allows for fast channel switching in monitor mode 2640 * (used by kismet). 2641 */ 2642 error = ieee80211_ioctl(ifp, cmd, data); 2643 if (error == ENETRESET && 2644 ic->ic_opmode == IEEE80211_M_MONITOR) { 2645 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2646 (IFF_UP | IFF_RUNNING)) 2647 run_set_chan(sc, ic->ic_ibss_chan); 2648 error = 0; 2649 } 2650 break; 2651 2652 default: 2653 error = ieee80211_ioctl(ifp, cmd, data); 2654 } 2655 2656 if (error == ENETRESET) { 2657 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2658 (IFF_UP | IFF_RUNNING)) { 2659 run_stop(ifp, 0); 2660 run_init(ifp); 2661 } 2662 error = 0; 2663 } 2664 2665 splx(s); 2666 2667 usbd_ref_decr(sc->sc_udev); 2668 2669 return error; 2670 } 2671 2672 void 2673 run_iq_calib(struct run_softc *sc, u_int chan) 2674 { 2675 uint16_t val; 2676 2677 /* Tx0 IQ gain. */ 2678 run_bbp_write(sc, 158, 0x2c); 2679 if (chan <= 14) 2680 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val); 2681 else if (chan <= 64) { 2682 run_efuse_read(sc, 2683 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, &val); 2684 } else if (chan <= 138) { 2685 run_efuse_read(sc, 2686 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, &val); 2687 } else if (chan <= 165) { 2688 run_efuse_read(sc, 2689 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, 2690 &val); 2691 } else 2692 val = 0; 2693 run_bbp_write(sc, 159, val); 2694 2695 /* Tx0 IQ phase. */ 2696 run_bbp_write(sc, 158, 0x2d); 2697 if (chan <= 14) { 2698 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, &val); 2699 } else if (chan <= 64) { 2700 run_efuse_read(sc, 2701 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, &val); 2702 } else if (chan <= 138) { 2703 run_efuse_read(sc, 2704 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, &val); 2705 } else if (chan <= 165) { 2706 run_efuse_read(sc, 2707 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, &val); 2708 } else 2709 val = 0; 2710 run_bbp_write(sc, 159, val); 2711 2712 /* Tx1 IQ gain. */ 2713 run_bbp_write(sc, 158, 0x4a); 2714 if (chan <= 14) { 2715 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, &val); 2716 } else if (chan <= 64) { 2717 run_efuse_read(sc, 2718 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, &val); 2719 } else if (chan <= 138) { 2720 run_efuse_read(sc, 2721 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, &val); 2722 } else if (chan <= 165) { 2723 run_efuse_read(sc, 2724 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, &val); 2725 } else 2726 val = 0; 2727 run_bbp_write(sc, 159, val); 2728 2729 /* Tx1 IQ phase. */ 2730 run_bbp_write(sc, 158, 0x4b); 2731 if (chan <= 14) { 2732 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, &val); 2733 } else if (chan <= 64) { 2734 run_efuse_read(sc, 2735 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, &val); 2736 } else if (chan <= 138) { 2737 run_efuse_read(sc, 2738 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, &val); 2739 } else if (chan <= 165) { 2740 run_efuse_read(sc, 2741 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, &val); 2742 } else 2743 val = 0; 2744 run_bbp_write(sc, 159, val); 2745 2746 /* RF IQ compensation control. */ 2747 run_bbp_write(sc, 158, 0x04); 2748 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, &val); 2749 run_bbp_write(sc, 159, val); 2750 2751 /* RF IQ imbalance compensation control. */ 2752 run_bbp_write(sc, 158, 0x03); 2753 run_efuse_read(sc, 2754 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val); 2755 run_bbp_write(sc, 159, val); 2756 } 2757 2758 void 2759 run_select_chan_group(struct run_softc *sc, int group) 2760 { 2761 uint32_t tmp; 2762 uint8_t agc; 2763 2764 run_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2765 run_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2766 run_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2767 if (sc->mac_ver < 0x3572) 2768 run_bbp_write(sc, 86, 0x00); 2769 2770 if (sc->mac_ver == 0x3593) { 2771 run_bbp_write(sc, 77, 0x98); 2772 run_bbp_write(sc, 83, (group == 0) ? 0x8a : 0x9a); 2773 } 2774 2775 if (group == 0) { 2776 if (sc->ext_2ghz_lna) { 2777 if (sc->mac_ver >= 0x5390) 2778 run_bbp_write(sc, 75, 0x52); 2779 else { 2780 run_bbp_write(sc, 82, 0x62); 2781 run_bbp_write(sc, 75, 0x46); 2782 } 2783 } else { 2784 if (sc->mac_ver == 0x5592) { 2785 run_bbp_write(sc, 79, 0x1c); 2786 run_bbp_write(sc, 80, 0x0e); 2787 run_bbp_write(sc, 81, 0x3a); 2788 run_bbp_write(sc, 82, 0x62); 2789 2790 run_bbp_write(sc, 195, 0x80); 2791 run_bbp_write(sc, 196, 0xe0); 2792 run_bbp_write(sc, 195, 0x81); 2793 run_bbp_write(sc, 196, 0x1f); 2794 run_bbp_write(sc, 195, 0x82); 2795 run_bbp_write(sc, 196, 0x38); 2796 run_bbp_write(sc, 195, 0x83); 2797 run_bbp_write(sc, 196, 0x32); 2798 run_bbp_write(sc, 195, 0x85); 2799 run_bbp_write(sc, 196, 0x28); 2800 run_bbp_write(sc, 195, 0x86); 2801 run_bbp_write(sc, 196, 0x19); 2802 } else if (sc->mac_ver >= 0x5390) 2803 run_bbp_write(sc, 75, 0x50); 2804 else { 2805 run_bbp_write(sc, 82, 2806 (sc->mac_ver == 0x3593) ? 0x62 : 0x84); 2807 run_bbp_write(sc, 75, 0x50); 2808 } 2809 } 2810 } else { 2811 if (sc->mac_ver == 0x5592) { 2812 run_bbp_write(sc, 79, 0x18); 2813 run_bbp_write(sc, 80, 0x08); 2814 run_bbp_write(sc, 81, 0x38); 2815 run_bbp_write(sc, 82, 0x92); 2816 2817 run_bbp_write(sc, 195, 0x80); 2818 run_bbp_write(sc, 196, 0xf0); 2819 run_bbp_write(sc, 195, 0x81); 2820 run_bbp_write(sc, 196, 0x1e); 2821 run_bbp_write(sc, 195, 0x82); 2822 run_bbp_write(sc, 196, 0x28); 2823 run_bbp_write(sc, 195, 0x83); 2824 run_bbp_write(sc, 196, 0x20); 2825 run_bbp_write(sc, 195, 0x85); 2826 run_bbp_write(sc, 196, 0x7f); 2827 run_bbp_write(sc, 195, 0x86); 2828 run_bbp_write(sc, 196, 0x7f); 2829 } else if (sc->mac_ver == 0x3572) 2830 run_bbp_write(sc, 82, 0x94); 2831 else 2832 run_bbp_write(sc, 82, 2833 (sc->mac_ver == 0x3593) ? 0x82 : 0xf2); 2834 if (sc->ext_5ghz_lna) 2835 run_bbp_write(sc, 75, 0x46); 2836 else 2837 run_bbp_write(sc, 75, 0x50); 2838 } 2839 2840 run_read(sc, RT2860_TX_BAND_CFG, &tmp); 2841 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2842 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2843 run_write(sc, RT2860_TX_BAND_CFG, tmp); 2844 2845 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2846 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2847 if (sc->mac_ver == 0x3593) 2848 tmp |= 1 << 29 | 1 << 28; 2849 if (sc->nrxchains > 1) 2850 tmp |= RT2860_LNA_PE1_EN; 2851 if (group == 0) { /* 2GHz */ 2852 tmp |= RT2860_PA_PE_G0_EN; 2853 if (sc->ntxchains > 1) 2854 tmp |= RT2860_PA_PE_G1_EN; 2855 if (sc->mac_ver == 0x3593) { 2856 if (sc->ntxchains > 2) 2857 tmp |= 1 << 25; 2858 } 2859 } else { /* 5GHz */ 2860 tmp |= RT2860_PA_PE_A0_EN; 2861 if (sc->ntxchains > 1) 2862 tmp |= RT2860_PA_PE_A1_EN; 2863 } 2864 if (sc->mac_ver == 0x3572) { 2865 run_rt3070_rf_write(sc, 8, 0x00); 2866 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2867 run_rt3070_rf_write(sc, 8, 0x80); 2868 } else 2869 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2870 2871 if (sc->mac_ver == 0x5592) { 2872 run_bbp_write(sc, 195, 0x8d); 2873 run_bbp_write(sc, 196, 0x1a); 2874 } 2875 2876 if (sc->mac_ver == 0x3593) { 2877 run_read(sc, RT2860_GPIO_CTRL, &tmp); 2878 tmp &= ~0x01010000; 2879 if (group == 0) 2880 tmp |= 0x00010000; 2881 tmp = (tmp & ~0x00009090) | 0x00000090; 2882 run_write(sc, RT2860_GPIO_CTRL, tmp); 2883 } 2884 2885 /* set initial AGC value */ 2886 if (group == 0) { /* 2GHz band */ 2887 if (sc->mac_ver >= 0x3070) 2888 agc = 0x1c + sc->lna[0] * 2; 2889 else 2890 agc = 0x2e + sc->lna[0]; 2891 } else { /* 5GHz band */ 2892 if (sc->mac_ver == 0x5592) 2893 agc = 0x24 + sc->lna[group] * 2; 2894 else if (sc->mac_ver == 0x3572 || sc->mac_ver == 0x3593) 2895 agc = 0x22 + (sc->lna[group] * 5) / 3; 2896 else 2897 agc = 0x32 + (sc->lna[group] * 5) / 3; 2898 } 2899 run_set_agc(sc, agc); 2900 } 2901 2902 void 2903 run_rt2870_set_chan(struct run_softc *sc, u_int chan) 2904 { 2905 const struct rfprog *rfprog = rt2860_rf2850; 2906 uint32_t r2, r3, r4; 2907 int8_t txpow1, txpow2; 2908 int i; 2909 2910 /* find the settings for this channel (we know it exists) */ 2911 for (i = 0; rfprog[i].chan != chan; i++); 2912 2913 r2 = rfprog[i].r2; 2914 if (sc->ntxchains == 1) 2915 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2916 if (sc->nrxchains == 1) 2917 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2918 else if (sc->nrxchains == 2) 2919 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2920 2921 /* use Tx power values from EEPROM */ 2922 txpow1 = sc->txpow1[i]; 2923 txpow2 = sc->txpow2[i]; 2924 if (chan > 14) { 2925 if (txpow1 >= 0) 2926 txpow1 = txpow1 << 1 | 1; 2927 else 2928 txpow1 = (7 + txpow1) << 1; 2929 if (txpow2 >= 0) 2930 txpow2 = txpow2 << 1 | 1; 2931 else 2932 txpow2 = (7 + txpow2) << 1; 2933 } 2934 r3 = rfprog[i].r3 | txpow1 << 7; 2935 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2936 2937 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2938 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2939 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2940 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2941 2942 DELAY(200); 2943 2944 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2945 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2946 run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1); 2947 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2948 2949 DELAY(200); 2950 2951 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2952 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2953 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2954 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2955 } 2956 2957 void 2958 run_rt3070_set_chan(struct run_softc *sc, u_int chan) 2959 { 2960 int8_t txpow1, txpow2; 2961 uint8_t rf; 2962 int i; 2963 2964 /* find the settings for this channel (we know it exists) */ 2965 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2966 2967 /* use Tx power values from EEPROM */ 2968 txpow1 = sc->txpow1[i]; 2969 txpow2 = sc->txpow2[i]; 2970 2971 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2972 2973 /* RT3370/RT3390: RF R3 [7:4] is not reserved bits. */ 2974 run_rt3070_rf_read(sc, 3, &rf); 2975 rf = (rf & ~0x0f) | rt3070_freqs[i].k; 2976 run_rt3070_rf_write(sc, 3, rf); 2977 2978 run_rt3070_rf_read(sc, 6, &rf); 2979 rf = (rf & ~0x03) | rt3070_freqs[i].r; 2980 run_rt3070_rf_write(sc, 6, rf); 2981 2982 /* set Tx0 power */ 2983 run_rt3070_rf_read(sc, 12, &rf); 2984 rf = (rf & ~0x1f) | txpow1; 2985 run_rt3070_rf_write(sc, 12, rf); 2986 2987 /* set Tx1 power */ 2988 run_rt3070_rf_read(sc, 13, &rf); 2989 rf = (rf & ~0x1f) | txpow2; 2990 run_rt3070_rf_write(sc, 13, rf); 2991 2992 run_rt3070_rf_read(sc, 1, &rf); 2993 rf &= ~0xfc; 2994 if (sc->ntxchains == 1) 2995 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 2996 else if (sc->ntxchains == 2) 2997 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 2998 if (sc->nrxchains == 1) 2999 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 3000 else if (sc->nrxchains == 2) 3001 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 3002 run_rt3070_rf_write(sc, 1, rf); 3003 3004 /* set RF offset */ 3005 run_rt3070_rf_read(sc, 23, &rf); 3006 rf = (rf & ~0x7f) | sc->freq; 3007 run_rt3070_rf_write(sc, 23, rf); 3008 3009 /* program RF filter */ 3010 run_rt3070_rf_read(sc, 24, &rf); /* Tx */ 3011 rf = (rf & ~0x3f) | sc->rf24_20mhz; 3012 run_rt3070_rf_write(sc, 24, rf); 3013 run_rt3070_rf_read(sc, 31, &rf); /* Rx */ 3014 rf = (rf & ~0x3f) | sc->rf24_20mhz; 3015 run_rt3070_rf_write(sc, 31, rf); 3016 3017 /* enable RF tuning */ 3018 run_rt3070_rf_read(sc, 7, &rf); 3019 run_rt3070_rf_write(sc, 7, rf | 0x01); 3020 } 3021 3022 void 3023 run_rt3572_set_chan(struct run_softc *sc, u_int chan) 3024 { 3025 int8_t txpow1, txpow2; 3026 uint32_t tmp; 3027 uint8_t rf; 3028 int i; 3029 3030 /* find the settings for this channel (we know it exists) */ 3031 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3032 3033 /* use Tx power values from EEPROM */ 3034 txpow1 = sc->txpow1[i]; 3035 txpow2 = sc->txpow2[i]; 3036 3037 if (chan <= 14) { 3038 run_bbp_write(sc, 25, sc->bbp25); 3039 run_bbp_write(sc, 26, sc->bbp26); 3040 } else { 3041 /* enable IQ phase correction */ 3042 run_bbp_write(sc, 25, 0x09); 3043 run_bbp_write(sc, 26, 0xff); 3044 } 3045 3046 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 3047 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 3048 run_rt3070_rf_read(sc, 6, &rf); 3049 rf = (rf & ~0x0f) | rt3070_freqs[i].r; 3050 rf |= (chan <= 14) ? 0x08 : 0x04; 3051 run_rt3070_rf_write(sc, 6, rf); 3052 3053 /* set PLL mode */ 3054 run_rt3070_rf_read(sc, 5, &rf); 3055 rf &= ~(0x08 | 0x04); 3056 rf |= (chan <= 14) ? 0x04 : 0x08; 3057 run_rt3070_rf_write(sc, 5, rf); 3058 3059 /* set Tx power for chain 0 */ 3060 if (chan <= 14) 3061 rf = 0x60 | txpow1; 3062 else 3063 rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); 3064 run_rt3070_rf_write(sc, 12, rf); 3065 3066 /* set Tx power for chain 1 */ 3067 if (chan <= 14) 3068 rf = 0x60 | txpow2; 3069 else 3070 rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); 3071 run_rt3070_rf_write(sc, 13, rf); 3072 3073 /* set Tx/Rx streams */ 3074 run_rt3070_rf_read(sc, 1, &rf); 3075 rf &= ~0xfc; 3076 if (sc->ntxchains == 1) 3077 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 3078 else if (sc->ntxchains == 2) 3079 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 3080 if (sc->nrxchains == 1) 3081 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 3082 else if (sc->nrxchains == 2) 3083 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 3084 run_rt3070_rf_write(sc, 1, rf); 3085 3086 /* set RF offset */ 3087 run_rt3070_rf_read(sc, 23, &rf); 3088 rf = (rf & ~0x7f) | sc->freq; 3089 run_rt3070_rf_write(sc, 23, rf); 3090 3091 /* program RF filter */ 3092 rf = sc->rf24_20mhz; 3093 run_rt3070_rf_write(sc, 24, rf); /* Tx */ 3094 run_rt3070_rf_write(sc, 31, rf); /* Rx */ 3095 3096 /* enable RF tuning */ 3097 run_rt3070_rf_read(sc, 7, &rf); 3098 rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); 3099 run_rt3070_rf_write(sc, 7, rf); 3100 3101 /* TSSI */ 3102 rf = (chan <= 14) ? 0xc3 : 0xc0; 3103 run_rt3070_rf_write(sc, 9, rf); 3104 3105 /* set loop filter 1 */ 3106 run_rt3070_rf_write(sc, 10, 0xf1); 3107 /* set loop filter 2 */ 3108 run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); 3109 3110 /* set tx_mx2_ic */ 3111 run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); 3112 /* set tx_mx1_ic */ 3113 if (chan <= 14) 3114 rf = 0x48 | sc->txmixgain_2ghz; 3115 else 3116 rf = 0x78 | sc->txmixgain_5ghz; 3117 run_rt3070_rf_write(sc, 16, rf); 3118 3119 /* set tx_lo1 */ 3120 run_rt3070_rf_write(sc, 17, 0x23); 3121 /* set tx_lo2 */ 3122 if (chan <= 14) 3123 rf = 0x93; 3124 else if (chan <= 64) 3125 rf = 0xb7; 3126 else if (chan <= 128) 3127 rf = 0x74; 3128 else 3129 rf = 0x72; 3130 run_rt3070_rf_write(sc, 19, rf); 3131 3132 /* set rx_lo1 */ 3133 if (chan <= 14) 3134 rf = 0xb3; 3135 else if (chan <= 64) 3136 rf = 0xf6; 3137 else if (chan <= 128) 3138 rf = 0xf4; 3139 else 3140 rf = 0xf3; 3141 run_rt3070_rf_write(sc, 20, rf); 3142 3143 /* set pfd_delay */ 3144 if (chan <= 14) 3145 rf = 0x15; 3146 else if (chan <= 64) 3147 rf = 0x3d; 3148 else 3149 rf = 0x01; 3150 run_rt3070_rf_write(sc, 25, rf); 3151 3152 /* set rx_lo2 */ 3153 run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); 3154 /* set ldo_rf_vc */ 3155 run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); 3156 /* set drv_cc */ 3157 run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); 3158 3159 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3160 tmp &= ~0x8080; 3161 if (chan <= 14) 3162 tmp |= 0x80; 3163 run_write(sc, RT2860_GPIO_CTRL, tmp); 3164 3165 /* enable RF tuning */ 3166 run_rt3070_rf_read(sc, 7, &rf); 3167 run_rt3070_rf_write(sc, 7, rf | 0x01); 3168 3169 DELAY(2000); 3170 } 3171 3172 void 3173 run_rt3593_set_chan(struct run_softc *sc, u_int chan) 3174 { 3175 int8_t txpow1, txpow2, txpow3; 3176 uint8_t h20mhz, rf; 3177 int i; 3178 3179 /* find the settings for this channel (we know it exists) */ 3180 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3181 3182 /* use Tx power values from EEPROM */ 3183 txpow1 = sc->txpow1[i]; 3184 txpow2 = sc->txpow2[i]; 3185 txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; 3186 3187 if (chan <= 14) { 3188 run_bbp_write(sc, 25, sc->bbp25); 3189 run_bbp_write(sc, 26, sc->bbp26); 3190 } else { 3191 /* Enable IQ phase correction. */ 3192 run_bbp_write(sc, 25, 0x09); 3193 run_bbp_write(sc, 26, 0xff); 3194 } 3195 3196 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3197 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3198 run_rt3070_rf_read(sc, 11, &rf); 3199 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3200 run_rt3070_rf_write(sc, 11, rf); 3201 3202 /* Set pll_idoh. */ 3203 run_rt3070_rf_read(sc, 11, &rf); 3204 rf &= ~0x4c; 3205 rf |= (chan <= 14) ? 0x44 : 0x48; 3206 run_rt3070_rf_write(sc, 11, rf); 3207 3208 if (chan <= 14) 3209 rf = txpow1 & 0x1f; 3210 else 3211 rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); 3212 run_rt3070_rf_write(sc, 53, rf); 3213 3214 if (chan <= 14) 3215 rf = txpow2 & 0x1f; 3216 else 3217 rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); 3218 run_rt3070_rf_write(sc, 55, rf); 3219 3220 if (chan <= 14) 3221 rf = txpow3 & 0x1f; 3222 else 3223 rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); 3224 run_rt3070_rf_write(sc, 54, rf); 3225 3226 rf = RT3070_RF_BLOCK | RT3070_PLL_PD; 3227 if (sc->ntxchains == 3) 3228 rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; 3229 else 3230 rf |= RT3070_TX0_PD | RT3070_TX1_PD; 3231 rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; 3232 run_rt3070_rf_write(sc, 1, rf); 3233 3234 run_adjust_freq_offset(sc); 3235 3236 run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); 3237 3238 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 3239 run_rt3070_rf_read(sc, 30, &rf); 3240 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 3241 run_rt3070_rf_write(sc, 30, rf); 3242 3243 run_rt3070_rf_read(sc, 36, &rf); 3244 if (chan <= 14) 3245 rf |= 0x80; 3246 else 3247 rf &= ~0x80; 3248 run_rt3070_rf_write(sc, 36, rf); 3249 3250 /* Set vcolo_bs. */ 3251 run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); 3252 /* Set pfd_delay. */ 3253 run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); 3254 3255 /* Set vco bias current control. */ 3256 run_rt3070_rf_read(sc, 6, &rf); 3257 rf &= ~0xc0; 3258 if (chan <= 14) 3259 rf |= 0x40; 3260 else if (chan <= 128) 3261 rf |= 0x80; 3262 else 3263 rf |= 0x40; 3264 run_rt3070_rf_write(sc, 6, rf); 3265 3266 run_rt3070_rf_read(sc, 30, &rf); 3267 rf = (rf & ~0x18) | 0x10; 3268 run_rt3070_rf_write(sc, 30, rf); 3269 3270 run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); 3271 run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); 3272 3273 run_rt3070_rf_read(sc, 51, &rf); 3274 rf = (rf & ~0x03) | 0x01; 3275 run_rt3070_rf_write(sc, 51, rf); 3276 /* Set tx_mx1_cc. */ 3277 run_rt3070_rf_read(sc, 51, &rf); 3278 rf &= ~0x1c; 3279 rf |= (chan <= 14) ? 0x14 : 0x10; 3280 run_rt3070_rf_write(sc, 51, rf); 3281 /* Set tx_mx1_ic. */ 3282 run_rt3070_rf_read(sc, 51, &rf); 3283 rf &= ~0xe0; 3284 rf |= (chan <= 14) ? 0x60 : 0x40; 3285 run_rt3070_rf_write(sc, 51, rf); 3286 /* Set tx_lo1_ic. */ 3287 run_rt3070_rf_read(sc, 49, &rf); 3288 rf &= ~0x1c; 3289 rf |= (chan <= 14) ? 0x0c : 0x08; 3290 run_rt3070_rf_write(sc, 49, rf); 3291 /* Set tx_lo1_en. */ 3292 run_rt3070_rf_read(sc, 50, &rf); 3293 run_rt3070_rf_write(sc, 50, rf & ~0x20); 3294 /* Set drv_cc. */ 3295 run_rt3070_rf_read(sc, 57, &rf); 3296 rf &= ~0xfc; 3297 rf |= (chan <= 14) ? 0x6c : 0x3c; 3298 run_rt3070_rf_write(sc, 57, rf); 3299 /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ 3300 run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); 3301 /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ 3302 run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); 3303 /* Enable VCO calibration. */ 3304 run_rt3070_rf_read(sc, 3, &rf); 3305 rf &= ~RT3593_VCOCAL; 3306 rf |= (chan <= 14) ? RT3593_VCOCAL : 0xbe; 3307 run_rt3070_rf_write(sc, 3, rf); 3308 3309 if (chan <= 14) 3310 rf = 0x23; 3311 else if (chan <= 64) 3312 rf = 0x36; 3313 else if (chan <= 128) 3314 rf = 0x32; 3315 else 3316 rf = 0x30; 3317 run_rt3070_rf_write(sc, 39, rf); 3318 if (chan <= 14) 3319 rf = 0xbb; 3320 else if (chan <= 64) 3321 rf = 0xeb; 3322 else if (chan <= 128) 3323 rf = 0xb3; 3324 else 3325 rf = 0x9b; 3326 run_rt3070_rf_write(sc, 45, rf); 3327 3328 /* Set FEQ/AEQ control. */ 3329 run_bbp_write(sc, 105, 0x34); 3330 } 3331 3332 void 3333 run_rt5390_set_chan(struct run_softc *sc, u_int chan) 3334 { 3335 int8_t txpow1, txpow2; 3336 uint8_t rf; 3337 int i; 3338 3339 /* find the settings for this channel (we know it exists) */ 3340 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3341 3342 /* use Tx power values from EEPROM */ 3343 txpow1 = sc->txpow1[i]; 3344 txpow2 = sc->txpow2[i]; 3345 3346 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3347 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3348 run_rt3070_rf_read(sc, 11, &rf); 3349 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3350 run_rt3070_rf_write(sc, 11, rf); 3351 3352 run_rt3070_rf_read(sc, 49, &rf); 3353 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3354 /* The valid range of the RF R49 is 0x00 to 0x27. */ 3355 if ((rf & 0x3f) > 0x27) 3356 rf = (rf & ~0x3f) | 0x27; 3357 run_rt3070_rf_write(sc, 49, rf); 3358 3359 if (sc->mac_ver == 0x5392) { 3360 run_rt3070_rf_read(sc, 50, &rf); 3361 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3362 /* The valid range of the RF R50 is 0x00 to 0x27. */ 3363 if ((rf & 0x3f) > 0x27) 3364 rf = (rf & ~0x3f) | 0x27; 3365 run_rt3070_rf_write(sc, 50, rf); 3366 } 3367 3368 run_rt3070_rf_read(sc, 1, &rf); 3369 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 3370 if (sc->mac_ver == 0x5392) 3371 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 3372 run_rt3070_rf_write(sc, 1, rf); 3373 3374 if (sc->mac_ver != 0x5392) { 3375 run_rt3070_rf_read(sc, 2, &rf); 3376 rf |= 0x80; 3377 run_rt3070_rf_write(sc, 2, rf); 3378 DELAY(10); 3379 rf &= 0x7f; 3380 run_rt3070_rf_write(sc, 2, rf); 3381 } 3382 3383 run_adjust_freq_offset(sc); 3384 3385 if (sc->mac_ver == 0x5392) { 3386 /* Fix for RT5392C. */ 3387 if (sc->mac_rev >= 0x0223) { 3388 if (chan <= 4) 3389 rf = 0x0f; 3390 else if (chan >= 5 && chan <= 7) 3391 rf = 0x0e; 3392 else 3393 rf = 0x0d; 3394 run_rt3070_rf_write(sc, 23, rf); 3395 3396 if (chan <= 4) 3397 rf = 0x0c; 3398 else if (chan == 5) 3399 rf = 0x0b; 3400 else if (chan >= 6 && chan <= 7) 3401 rf = 0x0a; 3402 else if (chan >= 8 && chan <= 10) 3403 rf = 0x09; 3404 else 3405 rf = 0x08; 3406 run_rt3070_rf_write(sc, 59, rf); 3407 } else { 3408 if (chan <= 11) 3409 rf = 0x0f; 3410 else 3411 rf = 0x0b; 3412 run_rt3070_rf_write(sc, 59, rf); 3413 } 3414 } else { 3415 /* Fix for RT5390F. */ 3416 if (sc->mac_rev >= 0x0502) { 3417 if (chan <= 11) 3418 rf = 0x43; 3419 else 3420 rf = 0x23; 3421 run_rt3070_rf_write(sc, 55, rf); 3422 3423 if (chan <= 11) 3424 rf = 0x0f; 3425 else if (chan == 12) 3426 rf = 0x0d; 3427 else 3428 rf = 0x0b; 3429 run_rt3070_rf_write(sc, 59, rf); 3430 } else { 3431 run_rt3070_rf_write(sc, 55, 0x44); 3432 run_rt3070_rf_write(sc, 59, 0x8f); 3433 } 3434 } 3435 3436 /* Enable VCO calibration. */ 3437 run_rt3070_rf_read(sc, 3, &rf); 3438 rf |= RT3593_VCOCAL; 3439 run_rt3070_rf_write(sc, 3, rf); 3440 } 3441 3442 void 3443 run_rt5592_set_chan(struct run_softc *sc, u_int chan) 3444 { 3445 const struct rt5592_freqs *freqs; 3446 uint32_t tmp; 3447 uint8_t reg, rf, txpow_bound; 3448 int8_t txpow1, txpow2; 3449 int i; 3450 3451 run_read(sc, RT5592_DEBUG_INDEX, &tmp); 3452 freqs = (tmp & RT5592_SEL_XTAL) ? 3453 rt5592_freqs_40mhz : rt5592_freqs_20mhz; 3454 3455 /* find the settings for this channel (we know it exists) */ 3456 for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); 3457 3458 /* use Tx power values from EEPROM */ 3459 txpow1 = sc->txpow1[i]; 3460 txpow2 = sc->txpow2[i]; 3461 3462 run_read(sc, RT3070_LDO_CFG0, &tmp); 3463 tmp &= ~0x1c000000; 3464 if (chan > 14) 3465 tmp |= 0x14000000; 3466 run_write(sc, RT3070_LDO_CFG0, tmp); 3467 3468 /* N setting. */ 3469 run_rt3070_rf_write(sc, 8, freqs->n & 0xff); 3470 run_rt3070_rf_read(sc, 9, &rf); 3471 rf &= ~(1 << 4); 3472 rf |= ((freqs->n & 0x0100) >> 8) << 4; 3473 run_rt3070_rf_write(sc, 9, rf); 3474 3475 /* K setting. */ 3476 run_rt3070_rf_read(sc, 9, &rf); 3477 rf &= ~0x0f; 3478 rf |= (freqs->k & 0x0f); 3479 run_rt3070_rf_write(sc, 9, rf); 3480 3481 /* Mode setting. */ 3482 run_rt3070_rf_read(sc, 11, &rf); 3483 rf &= ~0x0c; 3484 rf |= ((freqs->m - 0x8) & 0x3) << 2; 3485 run_rt3070_rf_write(sc, 11, rf); 3486 run_rt3070_rf_read(sc, 9, &rf); 3487 rf &= ~(1 << 7); 3488 rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; 3489 run_rt3070_rf_write(sc, 9, rf); 3490 3491 /* R setting. */ 3492 run_rt3070_rf_read(sc, 11, &rf); 3493 rf &= ~0x03; 3494 rf |= (freqs->r - 0x1); 3495 run_rt3070_rf_write(sc, 11, rf); 3496 3497 if (chan <= 14) { 3498 /* Initialize RF registers for 2GHZ. */ 3499 for (i = 0; i < nitems(rt5592_2ghz_def_rf); i++) { 3500 run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, 3501 rt5592_2ghz_def_rf[i].val); 3502 } 3503 3504 rf = (chan <= 10) ? 0x07 : 0x06; 3505 run_rt3070_rf_write(sc, 23, rf); 3506 run_rt3070_rf_write(sc, 59, rf); 3507 3508 run_rt3070_rf_write(sc, 55, 0x43); 3509 3510 /* 3511 * RF R49/R50 Tx power ALC code. 3512 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. 3513 */ 3514 reg = 2; 3515 txpow_bound = 0x27; 3516 } else { 3517 /* Initialize RF registers for 5GHZ. */ 3518 for (i = 0; i < nitems(rt5592_5ghz_def_rf); i++) { 3519 run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, 3520 rt5592_5ghz_def_rf[i].val); 3521 } 3522 for (i = 0; i < nitems(rt5592_chan_5ghz); i++) { 3523 if (chan >= rt5592_chan_5ghz[i].firstchan && 3524 chan <= rt5592_chan_5ghz[i].lastchan) { 3525 run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, 3526 rt5592_chan_5ghz[i].val); 3527 } 3528 } 3529 3530 /* 3531 * RF R49/R50 Tx power ALC code. 3532 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. 3533 */ 3534 reg = 3; 3535 txpow_bound = 0x2b; 3536 } 3537 3538 /* RF R49 ch0 Tx power ALC code. */ 3539 run_rt3070_rf_read(sc, 49, &rf); 3540 rf &= ~0xc0; 3541 rf |= (reg << 6); 3542 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3543 if ((rf & 0x3f) > txpow_bound) 3544 rf = (rf & ~0x3f) | txpow_bound; 3545 run_rt3070_rf_write(sc, 49, rf); 3546 3547 /* RF R50 ch1 Tx power ALC code. */ 3548 run_rt3070_rf_read(sc, 50, &rf); 3549 rf &= ~(1 << 7 | 1 << 6); 3550 rf |= (reg << 6); 3551 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3552 if ((rf & 0x3f) > txpow_bound) 3553 rf = (rf & ~0x3f) | txpow_bound; 3554 run_rt3070_rf_write(sc, 50, rf); 3555 3556 /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ 3557 run_rt3070_rf_read(sc, 1, &rf); 3558 rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD); 3559 if (sc->ntxchains > 1) 3560 rf |= RT3070_TX1_PD; 3561 if (sc->nrxchains > 1) 3562 rf |= RT3070_RX1_PD; 3563 run_rt3070_rf_write(sc, 1, rf); 3564 3565 run_rt3070_rf_write(sc, 6, 0xe4); 3566 3567 run_rt3070_rf_write(sc, 30, 0x10); 3568 run_rt3070_rf_write(sc, 31, 0x80); 3569 run_rt3070_rf_write(sc, 32, 0x80); 3570 3571 run_adjust_freq_offset(sc); 3572 3573 /* Enable VCO calibration. */ 3574 run_rt3070_rf_read(sc, 3, &rf); 3575 rf |= RT3593_VCOCAL; 3576 run_rt3070_rf_write(sc, 3, rf); 3577 } 3578 3579 void 3580 run_set_agc(struct run_softc *sc, uint8_t agc) 3581 { 3582 uint8_t bbp; 3583 3584 if (sc->mac_ver == 0x3572) { 3585 run_bbp_read(sc, 27, &bbp); 3586 bbp &= ~(0x3 << 5); 3587 run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ 3588 run_bbp_write(sc, 66, agc); 3589 run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ 3590 run_bbp_write(sc, 66, agc); 3591 } else 3592 run_bbp_write(sc, 66, agc); 3593 } 3594 3595 void 3596 run_set_rx_antenna(struct run_softc *sc, int aux) 3597 { 3598 uint32_t tmp; 3599 uint8_t bbp152; 3600 3601 if (aux) { 3602 if (sc->rf_rev == RT5390_RF_5370) { 3603 run_bbp_read(sc, 152, &bbp152); 3604 run_bbp_write(sc, 152, bbp152 & ~0x80); 3605 } else { 3606 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 0); 3607 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3608 run_write(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 3609 } 3610 } else { 3611 if (sc->rf_rev == RT5390_RF_5370) { 3612 run_bbp_read(sc, 152, &bbp152); 3613 run_bbp_write(sc, 152, bbp152 | 0x80); 3614 } else { 3615 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 1); 3616 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3617 run_write(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 3618 } 3619 } 3620 } 3621 3622 int 3623 run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) 3624 { 3625 struct ieee80211com *ic = &sc->sc_ic; 3626 u_int chan, group; 3627 3628 chan = ieee80211_chan2ieee(ic, c); 3629 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3630 return EINVAL; 3631 3632 if (sc->mac_ver == 0x5592) 3633 run_rt5592_set_chan(sc, chan); 3634 else if (sc->mac_ver >= 0x5390) 3635 run_rt5390_set_chan(sc, chan); 3636 else if (sc->mac_ver == 0x3593) 3637 run_rt3593_set_chan(sc, chan); 3638 else if (sc->mac_ver == 0x3572) 3639 run_rt3572_set_chan(sc, chan); 3640 else if (sc->mac_ver >= 0x3070) 3641 run_rt3070_set_chan(sc, chan); 3642 else 3643 run_rt2870_set_chan(sc, chan); 3644 3645 /* determine channel group */ 3646 if (chan <= 14) 3647 group = 0; 3648 else if (chan <= 64) 3649 group = 1; 3650 else if (chan <= 128) 3651 group = 2; 3652 else 3653 group = 3; 3654 3655 /* XXX necessary only when group has changed! */ 3656 run_select_chan_group(sc, group); 3657 3658 DELAY(1000); 3659 3660 /* Perform IQ calibration. */ 3661 if (sc->mac_ver >= 0x5392) 3662 run_iq_calib(sc, chan); 3663 3664 return 0; 3665 } 3666 3667 void 3668 run_enable_tsf_sync(struct run_softc *sc) 3669 { 3670 struct ieee80211com *ic = &sc->sc_ic; 3671 uint32_t tmp; 3672 3673 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 3674 tmp &= ~0x1fffff; 3675 tmp |= ic->ic_bss->ni_intval * 16; 3676 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3677 /* local TSF is always updated with remote TSF on beacon reception */ 3678 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3679 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 3680 } 3681 3682 void 3683 run_enable_mrr(struct run_softc *sc) 3684 { 3685 #define CCK(mcs) (mcs) 3686 #define OFDM(mcs) (1 << 3 | (mcs)) 3687 run_write(sc, RT2860_LG_FBK_CFG0, 3688 OFDM(6) << 28 | /* 54->48 */ 3689 OFDM(5) << 24 | /* 48->36 */ 3690 OFDM(4) << 20 | /* 36->24 */ 3691 OFDM(3) << 16 | /* 24->18 */ 3692 OFDM(2) << 12 | /* 18->12 */ 3693 OFDM(1) << 8 | /* 12-> 9 */ 3694 OFDM(0) << 4 | /* 9-> 6 */ 3695 OFDM(0)); /* 6-> 6 */ 3696 3697 run_write(sc, RT2860_LG_FBK_CFG1, 3698 CCK(2) << 12 | /* 11->5.5 */ 3699 CCK(1) << 8 | /* 5.5-> 2 */ 3700 CCK(0) << 4 | /* 2-> 1 */ 3701 CCK(0)); /* 1-> 1 */ 3702 #undef OFDM 3703 #undef CCK 3704 } 3705 3706 void 3707 run_set_txpreamble(struct run_softc *sc) 3708 { 3709 uint32_t tmp; 3710 3711 run_read(sc, RT2860_AUTO_RSP_CFG, &tmp); 3712 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 3713 tmp |= RT2860_CCK_SHORT_EN; 3714 else 3715 tmp &= ~RT2860_CCK_SHORT_EN; 3716 run_write(sc, RT2860_AUTO_RSP_CFG, tmp); 3717 } 3718 3719 void 3720 run_set_basicrates(struct run_softc *sc) 3721 { 3722 struct ieee80211com *ic = &sc->sc_ic; 3723 3724 /* set basic rates mask */ 3725 if (ic->ic_curmode == IEEE80211_MODE_11B) 3726 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 3727 else if (ic->ic_curmode == IEEE80211_MODE_11A) 3728 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 3729 else /* 11g */ 3730 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 3731 } 3732 3733 void 3734 run_set_leds(struct run_softc *sc, uint16_t which) 3735 { 3736 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3737 which | (sc->leds & 0x7f)); 3738 } 3739 3740 void 3741 run_set_bssid(struct run_softc *sc, const uint8_t *bssid) 3742 { 3743 run_write(sc, RT2860_MAC_BSSID_DW0, 3744 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3745 run_write(sc, RT2860_MAC_BSSID_DW1, 3746 bssid[4] | bssid[5] << 8); 3747 } 3748 3749 void 3750 run_set_macaddr(struct run_softc *sc, const uint8_t *addr) 3751 { 3752 run_write(sc, RT2860_MAC_ADDR_DW0, 3753 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3754 run_write(sc, RT2860_MAC_ADDR_DW1, 3755 addr[4] | addr[5] << 8 | 0xff << 16); 3756 } 3757 3758 void 3759 run_updateslot(struct ieee80211com *ic) 3760 { 3761 /* do it in a process context */ 3762 run_do_async(ic->ic_softc, run_updateslot_cb, NULL, 0); 3763 } 3764 3765 /* ARGSUSED */ 3766 void 3767 run_updateslot_cb(struct run_softc *sc, void *arg) 3768 { 3769 uint32_t tmp; 3770 3771 run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp); 3772 tmp &= ~0xff; 3773 tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 3774 IEEE80211_DUR_DS_SHSLOT : IEEE80211_DUR_DS_SLOT; 3775 run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3776 } 3777 3778 #if NBPFILTER > 0 3779 int8_t 3780 run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain) 3781 { 3782 struct ieee80211com *ic = &sc->sc_ic; 3783 struct ieee80211_channel *c = ic->ic_ibss_chan; 3784 int delta; 3785 3786 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3787 u_int chan = ieee80211_chan2ieee(ic, c); 3788 delta = sc->rssi_5ghz[rxchain]; 3789 3790 /* determine channel group */ 3791 if (chan <= 64) 3792 delta -= sc->lna[1]; 3793 else if (chan <= 128) 3794 delta -= sc->lna[2]; 3795 else 3796 delta -= sc->lna[3]; 3797 } else 3798 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3799 3800 return -12 - delta - rssi; 3801 } 3802 #endif 3803 3804 void 3805 run_rt5390_bbp_init(struct run_softc *sc) 3806 { 3807 int i; 3808 uint8_t bbp; 3809 3810 /* Apply maximum likelihood detection for 2 stream case. */ 3811 run_bbp_read(sc, 105, &bbp); 3812 if (sc->nrxchains > 1) 3813 run_bbp_write(sc, 105, bbp | RT5390_MLD); 3814 3815 /* Avoid data lost and CRC error. */ 3816 run_bbp_read(sc, 4, &bbp); 3817 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3818 3819 if (sc->mac_ver == 0x5592) { 3820 for (i = 0; i < nitems(rt5592_def_bbp); i++) { 3821 run_bbp_write(sc, rt5592_def_bbp[i].reg, 3822 rt5592_def_bbp[i].val); 3823 } 3824 for (i = 0; i < nitems(rt5592_bbp_r196); i++) { 3825 run_bbp_write(sc, 195, i + 0x80); 3826 run_bbp_write(sc, 196, rt5592_bbp_r196[i]); 3827 } 3828 } else { 3829 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3830 run_bbp_write(sc, rt5390_def_bbp[i].reg, 3831 rt5390_def_bbp[i].val); 3832 } 3833 } 3834 if (sc->mac_ver == 0x5392) { 3835 run_bbp_write(sc, 88, 0x90); 3836 run_bbp_write(sc, 95, 0x9a); 3837 run_bbp_write(sc, 98, 0x12); 3838 run_bbp_write(sc, 106, 0x12); 3839 run_bbp_write(sc, 134, 0xd0); 3840 run_bbp_write(sc, 135, 0xf6); 3841 run_bbp_write(sc, 148, 0x84); 3842 } 3843 3844 run_bbp_read(sc, 152, &bbp); 3845 run_bbp_write(sc, 152, bbp | 0x80); 3846 3847 /* Fix BBP254 for RT5592C. */ 3848 if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { 3849 run_bbp_read(sc, 254, &bbp); 3850 run_bbp_write(sc, 254, bbp | 0x80); 3851 } 3852 3853 /* Disable hardware antenna diversity. */ 3854 if (sc->mac_ver == 0x5390) 3855 run_bbp_write(sc, 154, 0); 3856 3857 /* Initialize Rx CCK/OFDM frequency offset report. */ 3858 run_bbp_write(sc, 142, 1); 3859 run_bbp_write(sc, 143, 57); 3860 } 3861 3862 int 3863 run_bbp_init(struct run_softc *sc) 3864 { 3865 int i, error, ntries; 3866 uint8_t bbp0; 3867 3868 /* wait for BBP to wake up */ 3869 for (ntries = 0; ntries < 20; ntries++) { 3870 if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) 3871 return error; 3872 if (bbp0 != 0 && bbp0 != 0xff) 3873 break; 3874 } 3875 if (ntries == 20) 3876 return ETIMEDOUT; 3877 3878 /* initialize BBP registers to default values */ 3879 if (sc->mac_ver >= 0x5390) 3880 run_rt5390_bbp_init(sc); 3881 else { 3882 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3883 run_bbp_write(sc, rt2860_def_bbp[i].reg, 3884 rt2860_def_bbp[i].val); 3885 } 3886 } 3887 3888 if (sc->mac_ver == 0x3593) { 3889 run_bbp_write(sc, 79, 0x13); 3890 run_bbp_write(sc, 80, 0x05); 3891 run_bbp_write(sc, 81, 0x33); 3892 run_bbp_write(sc, 86, 0x46); 3893 run_bbp_write(sc, 137, 0x0f); 3894 } 3895 3896 /* fix BBP84 for RT2860E */ 3897 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3898 run_bbp_write(sc, 84, 0x19); 3899 3900 if (sc->mac_ver >= 0x3070 && (sc->mac_ver != 0x3593 && 3901 sc->mac_ver != 0x5592)) { 3902 run_bbp_write(sc, 79, 0x13); 3903 run_bbp_write(sc, 80, 0x05); 3904 run_bbp_write(sc, 81, 0x33); 3905 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3906 run_bbp_write(sc, 69, 0x16); 3907 run_bbp_write(sc, 73, 0x12); 3908 } 3909 return 0; 3910 } 3911 3912 int 3913 run_rt3070_rf_init(struct run_softc *sc) 3914 { 3915 uint32_t tmp; 3916 uint8_t bbp4, mingain, rf, target; 3917 int i; 3918 3919 run_rt3070_rf_read(sc, 30, &rf); 3920 /* toggle RF R30 bit 7 */ 3921 run_rt3070_rf_write(sc, 30, rf | 0x80); 3922 DELAY(1000); 3923 run_rt3070_rf_write(sc, 30, rf & ~0x80); 3924 3925 /* initialize RF registers to default value */ 3926 if (sc->mac_ver == 0x3572) { 3927 for (i = 0; i < nitems(rt3572_def_rf); i++) { 3928 run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, 3929 rt3572_def_rf[i].val); 3930 } 3931 } else { 3932 for (i = 0; i < nitems(rt3070_def_rf); i++) { 3933 run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, 3934 rt3070_def_rf[i].val); 3935 } 3936 } 3937 if (sc->mac_ver == 0x3070 && sc->mac_rev < 0x0201) { 3938 /* 3939 * Change voltage from 1.2V to 1.35V for RT3070. 3940 * The DAC issue (RT3070_LDO_CFG0) has been fixed 3941 * in RT3070(F). 3942 */ 3943 run_read(sc, RT3070_LDO_CFG0, &tmp); 3944 tmp = (tmp & ~0x0f000000) | 0x0d000000; 3945 run_write(sc, RT3070_LDO_CFG0, tmp); 3946 3947 } else if (sc->mac_ver == 0x3071) { 3948 run_rt3070_rf_read(sc, 6, &rf); 3949 run_rt3070_rf_write(sc, 6, rf | 0x40); 3950 run_rt3070_rf_write(sc, 31, 0x14); 3951 3952 run_read(sc, RT3070_LDO_CFG0, &tmp); 3953 tmp &= ~0x1f000000; 3954 if (sc->mac_rev < 0x0211) 3955 tmp |= 0x0d000000; /* 1.35V */ 3956 else 3957 tmp |= 0x01000000; /* 1.2V */ 3958 run_write(sc, RT3070_LDO_CFG0, tmp); 3959 3960 /* patch LNA_PE_G1 */ 3961 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 3962 run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 3963 3964 } else if (sc->mac_ver == 0x3572) { 3965 run_rt3070_rf_read(sc, 6, &rf); 3966 run_rt3070_rf_write(sc, 6, rf | 0x40); 3967 /* increase voltage from 1.2V to 1.35V */ 3968 run_read(sc, RT3070_LDO_CFG0, &tmp); 3969 tmp = (tmp & ~0x1f000000) | 0x0d000000; 3970 run_write(sc, RT3070_LDO_CFG0, tmp); 3971 3972 if (sc->mac_rev < 0x0211 || !sc->patch_dac) { 3973 DELAY(1); /* wait for 1msec */ 3974 /* decrease voltage back to 1.2V */ 3975 tmp = (tmp & ~0x1f000000) | 0x01000000; 3976 run_write(sc, RT3070_LDO_CFG0, tmp); 3977 } 3978 } 3979 3980 /* select 20MHz bandwidth */ 3981 run_rt3070_rf_read(sc, 31, &rf); 3982 run_rt3070_rf_write(sc, 31, rf & ~0x20); 3983 3984 /* calibrate filter for 20MHz bandwidth */ 3985 sc->rf24_20mhz = 0x1f; /* default value */ 3986 target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; 3987 run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); 3988 3989 /* select 40MHz bandwidth */ 3990 run_bbp_read(sc, 4, &bbp4); 3991 run_bbp_write(sc, 4, (bbp4 & ~0x18) | 0x10); 3992 run_rt3070_rf_read(sc, 31, &rf); 3993 run_rt3070_rf_write(sc, 31, rf | 0x20); 3994 3995 /* calibrate filter for 40MHz bandwidth */ 3996 sc->rf24_40mhz = 0x2f; /* default value */ 3997 target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; 3998 run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); 3999 4000 /* go back to 20MHz bandwidth */ 4001 run_bbp_read(sc, 4, &bbp4); 4002 run_bbp_write(sc, 4, bbp4 & ~0x18); 4003 4004 if (sc->mac_ver == 0x3572) { 4005 /* save default BBP registers 25 and 26 values */ 4006 run_bbp_read(sc, 25, &sc->bbp25); 4007 run_bbp_read(sc, 26, &sc->bbp26); 4008 4009 } else if (sc->mac_rev < 0x0201 || sc->mac_rev < 0x0211) 4010 run_rt3070_rf_write(sc, 27, 0x03); 4011 4012 run_read(sc, RT3070_OPT_14, &tmp); 4013 run_write(sc, RT3070_OPT_14, tmp | 1); 4014 4015 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4016 run_rt3070_rf_read(sc, 17, &rf); 4017 rf &= ~RT3070_TX_LO1; 4018 if ((sc->mac_ver == 0x3070 || 4019 (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && 4020 !sc->ext_2ghz_lna) 4021 rf |= 0x20; /* fix for long range Rx issue */ 4022 mingain = (sc->mac_ver == 0x3070) ? 1 : 2; 4023 if (sc->txmixgain_2ghz >= mingain) 4024 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 4025 run_rt3070_rf_write(sc, 17, rf); 4026 } 4027 if (sc->mac_ver == 0x3071) { 4028 run_rt3070_rf_read(sc, 1, &rf); 4029 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 4030 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 4031 run_rt3070_rf_write(sc, 1, rf); 4032 4033 run_rt3070_rf_read(sc, 15, &rf); 4034 run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 4035 4036 run_rt3070_rf_read(sc, 20, &rf); 4037 run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 4038 4039 run_rt3070_rf_read(sc, 21, &rf); 4040 run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 4041 } 4042 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4043 /* fix Tx to Rx IQ glitch by raising RF voltage */ 4044 run_rt3070_rf_read(sc, 27, &rf); 4045 rf &= ~0x77; 4046 if (sc->mac_rev < 0x0211) 4047 rf |= 0x03; 4048 run_rt3070_rf_write(sc, 27, rf); 4049 } 4050 return 0; 4051 } 4052 4053 void 4054 run_rt3593_rf_init(struct run_softc *sc) 4055 { 4056 uint32_t tmp; 4057 uint8_t rf; 4058 int i; 4059 4060 /* Disable the GPIO bits 4 and 7 for LNA PE control. */ 4061 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4062 tmp &= ~(1 << 4 | 1 << 7); 4063 run_write(sc, RT3070_GPIO_SWITCH, tmp); 4064 4065 /* Initialize RF registers to default value. */ 4066 for (i = 0; i < nitems(rt3593_def_rf); i++) { 4067 run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, 4068 rt3593_def_rf[i].val); 4069 } 4070 4071 /* Toggle RF R2 to initiate calibration. */ 4072 run_rt3070_rf_write(sc, 2, RT3593_RESCAL); 4073 4074 /* Initialize RF frequency offset. */ 4075 run_adjust_freq_offset(sc); 4076 4077 run_rt3070_rf_read(sc, 18, &rf); 4078 run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); 4079 4080 /* 4081 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to 4082 * decrease voltage back to 1.2V. 4083 */ 4084 run_read(sc, RT3070_LDO_CFG0, &tmp); 4085 tmp = (tmp & ~0x1f000000) | 0x0d000000; 4086 run_write(sc, RT3070_LDO_CFG0, tmp); 4087 DELAY(1); 4088 tmp = (tmp & ~0x1f000000) | 0x01000000; 4089 run_write(sc, RT3070_LDO_CFG0, tmp); 4090 4091 sc->rf24_20mhz = 0x1f; 4092 sc->rf24_40mhz = 0x2f; 4093 4094 /* Save default BBP registers 25 and 26 values. */ 4095 run_bbp_read(sc, 25, &sc->bbp25); 4096 run_bbp_read(sc, 26, &sc->bbp26); 4097 4098 run_read(sc, RT3070_OPT_14, &tmp); 4099 run_write(sc, RT3070_OPT_14, tmp | 1); 4100 } 4101 4102 void 4103 run_rt5390_rf_init(struct run_softc *sc) 4104 { 4105 uint32_t tmp; 4106 uint8_t rf; 4107 int i; 4108 4109 /* Toggle RF R2 to initiate calibration. */ 4110 if (sc->mac_ver == 0x5390) { 4111 run_rt3070_rf_read(sc, 2, &rf); 4112 run_rt3070_rf_write(sc, 2, rf | RT3593_RESCAL); 4113 DELAY(10); 4114 run_rt3070_rf_write(sc, 2, rf & ~RT3593_RESCAL); 4115 } else { 4116 run_rt3070_rf_write(sc, 2, RT3593_RESCAL); 4117 DELAY(10); 4118 } 4119 4120 /* Initialize RF registers to default value. */ 4121 if (sc->mac_ver == 0x5592) { 4122 for (i = 0; i < nitems(rt5592_def_rf); i++) { 4123 run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, 4124 rt5592_def_rf[i].val); 4125 } 4126 /* Initialize RF frequency offset. */ 4127 run_adjust_freq_offset(sc); 4128 } else if (sc->mac_ver == 0x5392) { 4129 for (i = 0; i < nitems(rt5392_def_rf); i++) { 4130 run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, 4131 rt5392_def_rf[i].val); 4132 } 4133 if (sc->mac_rev >= 0x0223) { 4134 run_rt3070_rf_write(sc, 23, 0x0f); 4135 run_rt3070_rf_write(sc, 24, 0x3e); 4136 run_rt3070_rf_write(sc, 51, 0x32); 4137 run_rt3070_rf_write(sc, 53, 0x22); 4138 run_rt3070_rf_write(sc, 56, 0xc1); 4139 run_rt3070_rf_write(sc, 59, 0x0f); 4140 } 4141 } else { 4142 for (i = 0; i < nitems(rt5390_def_rf); i++) { 4143 run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, 4144 rt5390_def_rf[i].val); 4145 } 4146 if (sc->mac_rev >= 0x0502) { 4147 run_rt3070_rf_write(sc, 6, 0xe0); 4148 run_rt3070_rf_write(sc, 25, 0x80); 4149 run_rt3070_rf_write(sc, 46, 0x73); 4150 run_rt3070_rf_write(sc, 53, 0x00); 4151 run_rt3070_rf_write(sc, 56, 0x42); 4152 run_rt3070_rf_write(sc, 61, 0xd1); 4153 } 4154 } 4155 4156 sc->rf24_20mhz = 0x1f; /* default value */ 4157 sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; 4158 4159 if (sc->mac_rev < 0x0211) 4160 run_rt3070_rf_write(sc, 27, 0x3); 4161 4162 run_read(sc, RT3070_OPT_14, &tmp); 4163 run_write(sc, RT3070_OPT_14, tmp | 1); 4164 } 4165 4166 int 4167 run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, 4168 uint8_t *val) 4169 { 4170 uint8_t rf22, rf24; 4171 uint8_t bbp55_pb, bbp55_sb, delta; 4172 int ntries; 4173 4174 /* program filter */ 4175 run_rt3070_rf_read(sc, 24, &rf24); 4176 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 4177 run_rt3070_rf_write(sc, 24, rf24); 4178 4179 /* enable baseband loopback mode */ 4180 run_rt3070_rf_read(sc, 22, &rf22); 4181 run_rt3070_rf_write(sc, 22, rf22 | 0x01); 4182 4183 /* set power and frequency of passband test tone */ 4184 run_bbp_write(sc, 24, 0x00); 4185 for (ntries = 0; ntries < 100; ntries++) { 4186 /* transmit test tone */ 4187 run_bbp_write(sc, 25, 0x90); 4188 DELAY(1000); 4189 /* read received power */ 4190 run_bbp_read(sc, 55, &bbp55_pb); 4191 if (bbp55_pb != 0) 4192 break; 4193 } 4194 if (ntries == 100) 4195 return ETIMEDOUT; 4196 4197 /* set power and frequency of stopband test tone */ 4198 run_bbp_write(sc, 24, 0x06); 4199 for (ntries = 0; ntries < 100; ntries++) { 4200 /* transmit test tone */ 4201 run_bbp_write(sc, 25, 0x90); 4202 DELAY(1000); 4203 /* read received power */ 4204 run_bbp_read(sc, 55, &bbp55_sb); 4205 4206 delta = bbp55_pb - bbp55_sb; 4207 if (delta > target) 4208 break; 4209 4210 /* reprogram filter */ 4211 rf24++; 4212 run_rt3070_rf_write(sc, 24, rf24); 4213 } 4214 if (ntries < 100) { 4215 if (rf24 != init) 4216 rf24--; /* backtrack */ 4217 *val = rf24; 4218 run_rt3070_rf_write(sc, 24, rf24); 4219 } 4220 4221 /* restore initial state */ 4222 run_bbp_write(sc, 24, 0x00); 4223 4224 /* disable baseband loopback mode */ 4225 run_rt3070_rf_read(sc, 22, &rf22); 4226 run_rt3070_rf_write(sc, 22, rf22 & ~0x01); 4227 4228 return 0; 4229 } 4230 4231 void 4232 run_rt3070_rf_setup(struct run_softc *sc) 4233 { 4234 uint8_t bbp, rf; 4235 int i; 4236 4237 if (sc->mac_ver == 0x3572) { 4238 /* enable DC filter */ 4239 if (sc->mac_rev >= 0x0201) 4240 run_bbp_write(sc, 103, 0xc0); 4241 4242 run_bbp_read(sc, 138, &bbp); 4243 if (sc->ntxchains == 1) 4244 bbp |= 0x20; /* turn off DAC1 */ 4245 if (sc->nrxchains == 1) 4246 bbp &= ~0x02; /* turn off ADC1 */ 4247 run_bbp_write(sc, 138, bbp); 4248 4249 if (sc->mac_rev >= 0x0211) { 4250 /* improve power consumption */ 4251 run_bbp_read(sc, 31, &bbp); 4252 run_bbp_write(sc, 31, bbp & ~0x03); 4253 } 4254 4255 run_rt3070_rf_read(sc, 16, &rf); 4256 rf = (rf & ~0x07) | sc->txmixgain_2ghz; 4257 run_rt3070_rf_write(sc, 16, rf); 4258 4259 } else if (sc->mac_ver == 0x3071) { 4260 /* enable DC filter */ 4261 if (sc->mac_rev >= 0x0211) { 4262 run_bbp_write(sc, 103, 0xc0); 4263 4264 /* improve power consumption */ 4265 run_bbp_read(sc, 31, &bbp); 4266 run_bbp_write(sc, 31, bbp & ~0x03); 4267 } 4268 4269 run_bbp_read(sc, 138, &bbp); 4270 if (sc->ntxchains == 1) 4271 bbp |= 0x20; /* turn off DAC1 */ 4272 if (sc->nrxchains == 1) 4273 bbp &= ~0x02; /* turn off ADC1 */ 4274 run_bbp_write(sc, 138, bbp); 4275 4276 run_write(sc, RT2860_TX_SW_CFG1, 0); 4277 if (sc->mac_rev < 0x0211) { 4278 run_write(sc, RT2860_TX_SW_CFG2, 4279 sc->patch_dac ? 0x2c : 0x0f); 4280 } else 4281 run_write(sc, RT2860_TX_SW_CFG2, 0); 4282 4283 } else if (sc->mac_ver == 0x3070) { 4284 if (sc->mac_rev >= 0x0201) { 4285 /* enable DC filter */ 4286 run_bbp_write(sc, 103, 0xc0); 4287 4288 /* improve power consumption */ 4289 run_bbp_read(sc, 31, &bbp); 4290 run_bbp_write(sc, 31, bbp & ~0x03); 4291 } 4292 4293 if (sc->mac_rev < 0x0201) { 4294 run_write(sc, RT2860_TX_SW_CFG1, 0); 4295 run_write(sc, RT2860_TX_SW_CFG2, 0x2c); 4296 } else 4297 run_write(sc, RT2860_TX_SW_CFG2, 0); 4298 } 4299 4300 /* initialize RF registers from ROM for >=RT3071*/ 4301 if (sc->mac_ver >= 0x3071) { 4302 for (i = 0; i < 10; i++) { 4303 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 4304 continue; 4305 run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 4306 } 4307 } 4308 } 4309 4310 void 4311 run_rt3593_rf_setup(struct run_softc *sc) 4312 { 4313 uint8_t bbp, rf; 4314 4315 if (sc->mac_rev >= 0x0211) { 4316 /* Enable DC filter. */ 4317 run_bbp_write(sc, 103, 0xc0); 4318 } 4319 run_write(sc, RT2860_TX_SW_CFG1, 0); 4320 if (sc->mac_rev < 0x0211) { 4321 run_write(sc, RT2860_TX_SW_CFG2, 4322 sc->patch_dac ? 0x2c : 0x0f); 4323 } else 4324 run_write(sc, RT2860_TX_SW_CFG2, 0); 4325 4326 run_rt3070_rf_read(sc, 50, &rf); 4327 run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); 4328 4329 run_rt3070_rf_read(sc, 51, &rf); 4330 rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | 4331 ((sc->txmixgain_2ghz & 0x07) << 2); 4332 run_rt3070_rf_write(sc, 51, rf); 4333 4334 run_rt3070_rf_read(sc, 38, &rf); 4335 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4336 4337 run_rt3070_rf_read(sc, 39, &rf); 4338 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4339 4340 run_rt3070_rf_read(sc, 1, &rf); 4341 run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); 4342 4343 run_rt3070_rf_read(sc, 30, &rf); 4344 rf = (rf & ~0x18) | 0x10; 4345 run_rt3070_rf_write(sc, 30, rf); 4346 4347 /* Apply maximum likelihood detection for 2 stream case. */ 4348 run_bbp_read(sc, 105, &bbp); 4349 if (sc->nrxchains > 1) 4350 run_bbp_write(sc, 105, bbp | RT5390_MLD); 4351 4352 /* Avoid data lost and CRC error. */ 4353 run_bbp_read(sc, 4, &bbp); 4354 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4355 4356 run_bbp_write(sc, 92, 0x02); 4357 run_bbp_write(sc, 82, 0x82); 4358 run_bbp_write(sc, 106, 0x05); 4359 run_bbp_write(sc, 104, 0x92); 4360 run_bbp_write(sc, 88, 0x90); 4361 run_bbp_write(sc, 148, 0xc8); 4362 run_bbp_write(sc, 47, 0x48); 4363 run_bbp_write(sc, 120, 0x50); 4364 4365 run_bbp_write(sc, 163, 0x9d); 4366 4367 /* SNR mapping. */ 4368 run_bbp_write(sc, 142, 0x06); 4369 run_bbp_write(sc, 143, 0xa0); 4370 run_bbp_write(sc, 142, 0x07); 4371 run_bbp_write(sc, 143, 0xa1); 4372 run_bbp_write(sc, 142, 0x08); 4373 run_bbp_write(sc, 143, 0xa2); 4374 4375 run_bbp_write(sc, 31, 0x08); 4376 run_bbp_write(sc, 68, 0x0b); 4377 run_bbp_write(sc, 105, 0x04); 4378 } 4379 4380 void 4381 run_rt5390_rf_setup(struct run_softc *sc) 4382 { 4383 uint8_t bbp, rf; 4384 4385 if (sc->mac_rev >= 0x0211) { 4386 /* Enable DC filter. */ 4387 run_bbp_write(sc, 103, 0xc0); 4388 4389 if (sc->mac_ver != 0x5592) { 4390 /* Improve power consumption. */ 4391 run_bbp_read(sc, 31, &bbp); 4392 run_bbp_write(sc, 31, bbp & ~0x03); 4393 } 4394 } 4395 4396 run_bbp_read(sc, 138, &bbp); 4397 if (sc->ntxchains == 1) 4398 bbp |= 0x20; /* turn off DAC1 */ 4399 if (sc->nrxchains == 1) 4400 bbp &= ~0x02; /* turn off ADC1 */ 4401 run_bbp_write(sc, 138, bbp); 4402 4403 run_rt3070_rf_read(sc, 38, &rf); 4404 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4405 4406 run_rt3070_rf_read(sc, 39, &rf); 4407 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4408 4409 /* Avoid data lost and CRC error. */ 4410 run_bbp_read(sc, 4, &bbp); 4411 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4412 4413 run_rt3070_rf_read(sc, 30, &rf); 4414 rf = (rf & ~0x18) | 0x10; 4415 run_rt3070_rf_write(sc, 30, rf); 4416 4417 if (sc->mac_ver != 0x5592) { 4418 run_write(sc, RT2860_TX_SW_CFG1, 0); 4419 if (sc->mac_rev < 0x0211) { 4420 run_write(sc, RT2860_TX_SW_CFG2, 4421 sc->patch_dac ? 0x2c : 0x0f); 4422 } else 4423 run_write(sc, RT2860_TX_SW_CFG2, 0); 4424 } 4425 } 4426 4427 int 4428 run_txrx_enable(struct run_softc *sc) 4429 { 4430 uint32_t tmp; 4431 int error, ntries; 4432 4433 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 4434 for (ntries = 0; ntries < 200; ntries++) { 4435 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4436 return error; 4437 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4438 break; 4439 DELAY(1000); 4440 } 4441 if (ntries == 200) 4442 return ETIMEDOUT; 4443 4444 DELAY(50); 4445 4446 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE; 4447 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4448 4449 /* enable Rx bulk aggregation (set timeout and limit) */ 4450 tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN | 4451 RT2860_USB_RX_AGG_TO(128) | RT2860_USB_RX_AGG_LMT(2); 4452 run_write(sc, RT2860_USB_DMA_CFG, tmp); 4453 4454 /* set Rx filter */ 4455 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 4456 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 4457 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 4458 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 4459 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 4460 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 4461 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 4462 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 4463 } 4464 run_write(sc, RT2860_RX_FILTR_CFG, tmp); 4465 4466 run_write(sc, RT2860_MAC_SYS_CTRL, 4467 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4468 4469 return 0; 4470 } 4471 4472 void 4473 run_adjust_freq_offset(struct run_softc *sc) 4474 { 4475 uint8_t rf, tmp; 4476 4477 run_rt3070_rf_read(sc, 17, &rf); 4478 tmp = rf; 4479 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 4480 rf = MIN(rf, 0x5f); 4481 4482 if (tmp != rf) 4483 run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); 4484 } 4485 4486 int 4487 run_init(struct ifnet *ifp) 4488 { 4489 struct run_softc *sc = ifp->if_softc; 4490 struct ieee80211com *ic = &sc->sc_ic; 4491 uint32_t tmp; 4492 uint8_t bbp1, bbp3; 4493 int i, error, qid, ridx, ntries; 4494 4495 if (usbd_is_dying(sc->sc_udev)) 4496 return ENXIO; 4497 4498 for (ntries = 0; ntries < 100; ntries++) { 4499 if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0) 4500 goto fail; 4501 if (tmp != 0 && tmp != 0xffffffff) 4502 break; 4503 DELAY(10); 4504 } 4505 if (ntries == 100) { 4506 error = ETIMEDOUT; 4507 goto fail; 4508 } 4509 4510 if ((error = run_load_microcode(sc)) != 0) { 4511 printf("%s: could not load 8051 microcode\n", 4512 sc->sc_dev.dv_xname); 4513 goto fail; 4514 } 4515 4516 /* init host command ring */ 4517 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4518 4519 /* init Tx rings (4 EDCAs) */ 4520 for (qid = 0; qid < 4; qid++) { 4521 if ((error = run_alloc_tx_ring(sc, qid)) != 0) 4522 goto fail; 4523 } 4524 /* init Rx ring */ 4525 if ((error = run_alloc_rx_ring(sc)) != 0) 4526 goto fail; 4527 4528 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 4529 run_set_macaddr(sc, ic->ic_myaddr); 4530 4531 for (ntries = 0; ntries < 100; ntries++) { 4532 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4533 goto fail; 4534 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4535 break; 4536 DELAY(1000); 4537 } 4538 if (ntries == 100) { 4539 printf("%s: timeout waiting for DMA engine\n", 4540 sc->sc_dev.dv_xname); 4541 error = ETIMEDOUT; 4542 goto fail; 4543 } 4544 tmp &= 0xff0; 4545 tmp |= RT2860_TX_WB_DDONE; 4546 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4547 4548 /* turn off PME_OEN to solve high-current issue */ 4549 run_read(sc, RT2860_SYS_CTRL, &tmp); 4550 run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN); 4551 4552 run_write(sc, RT2860_MAC_SYS_CTRL, 4553 RT2860_BBP_HRST | RT2860_MAC_SRST); 4554 run_write(sc, RT2860_USB_DMA_CFG, 0); 4555 4556 if ((error = run_reset(sc)) != 0) { 4557 printf("%s: could not reset chipset\n", sc->sc_dev.dv_xname); 4558 goto fail; 4559 } 4560 4561 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4562 4563 /* init Tx power for all Tx rates (from EEPROM) */ 4564 for (ridx = 0; ridx < 5; ridx++) { 4565 if (sc->txpow20mhz[ridx] == 0xffffffff) 4566 continue; 4567 run_write(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 4568 } 4569 4570 for (i = 0; i < nitems(rt2870_def_mac); i++) 4571 run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); 4572 run_write(sc, RT2860_WMM_AIFSN_CFG, 0x00002273); 4573 run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344); 4574 run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa); 4575 4576 if (sc->mac_ver >= 0x5390) { 4577 run_write(sc, RT2860_TX_SW_CFG0, 4578 4 << RT2860_DLY_PAPE_EN_SHIFT | 4); 4579 if (sc->mac_ver >= 0x5392) { 4580 run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff); 4581 if (sc->mac_ver == 0x5592) { 4582 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980); 4583 run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082); 4584 } else { 4585 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980); 4586 run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); 4587 } 4588 } 4589 } else if (sc->mac_ver == 0x3593) { 4590 run_write(sc, RT2860_TX_SW_CFG0, 4591 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); 4592 } else if (sc->mac_ver >= 0x3070) { 4593 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 4594 run_write(sc, RT2860_TX_SW_CFG0, 4595 4 << RT2860_DLY_PAPE_EN_SHIFT); 4596 } 4597 4598 /* wait while MAC is busy */ 4599 for (ntries = 0; ntries < 100; ntries++) { 4600 if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0) 4601 goto fail; 4602 if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 4603 break; 4604 DELAY(1000); 4605 } 4606 if (ntries == 100) { 4607 error = ETIMEDOUT; 4608 goto fail; 4609 } 4610 4611 /* clear Host to MCU mailbox */ 4612 run_write(sc, RT2860_H2M_BBPAGENT, 0); 4613 run_write(sc, RT2860_H2M_MAILBOX, 0); 4614 DELAY(1000); 4615 4616 if ((error = run_bbp_init(sc)) != 0) { 4617 printf("%s: could not initialize BBP\n", sc->sc_dev.dv_xname); 4618 goto fail; 4619 } 4620 4621 /* abort TSF synchronization */ 4622 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 4623 tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 4624 RT2860_TBTT_TIMER_EN); 4625 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 4626 4627 /* clear RX WCID search table */ 4628 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4629 /* clear WCID attribute table */ 4630 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4631 /* clear shared key table */ 4632 run_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 4633 /* clear shared key mode */ 4634 run_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 4635 4636 run_read(sc, RT2860_US_CYC_CNT, &tmp); 4637 tmp = (tmp & ~0xff) | 0x1e; 4638 run_write(sc, RT2860_US_CYC_CNT, tmp); 4639 4640 if (sc->mac_rev != 0x0101) 4641 run_write(sc, RT2860_TXOP_CTRL_CFG, 0x0000583f); 4642 4643 run_write(sc, RT2860_WMM_TXOP0_CFG, 0); 4644 run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); 4645 4646 /* write vendor-specific BBP values (from EEPROM) */ 4647 if (sc->mac_ver < 0x3593) { 4648 for (i = 0; i < 8; i++) { 4649 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4650 continue; 4651 run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4652 } 4653 } 4654 4655 /* select Main antenna for 1T1R devices */ 4656 if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370) 4657 run_set_rx_antenna(sc, 0); 4658 4659 /* send LEDs operating mode to microcontroller */ 4660 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); 4661 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); 4662 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); 4663 4664 if (sc->mac_ver >= 0x5390) 4665 run_rt5390_rf_init(sc); 4666 else if (sc->mac_ver == 0x3593) 4667 run_rt3593_rf_init(sc); 4668 else if (sc->mac_ver >= 0x3070) 4669 run_rt3070_rf_init(sc); 4670 4671 /* disable non-existing Rx chains */ 4672 run_bbp_read(sc, 3, &bbp3); 4673 bbp3 &= ~(1 << 3 | 1 << 4); 4674 if (sc->nrxchains == 2) 4675 bbp3 |= 1 << 3; 4676 else if (sc->nrxchains == 3) 4677 bbp3 |= 1 << 4; 4678 run_bbp_write(sc, 3, bbp3); 4679 4680 /* disable non-existing Tx chains */ 4681 run_bbp_read(sc, 1, &bbp1); 4682 if (sc->ntxchains == 1) 4683 bbp1 &= ~(1 << 3 | 1 << 4); 4684 run_bbp_write(sc, 1, bbp1); 4685 4686 if (sc->mac_ver >= 0x5390) 4687 run_rt5390_rf_setup(sc); 4688 else if (sc->mac_ver == 0x3593) 4689 run_rt3593_rf_setup(sc); 4690 else if (sc->mac_ver >= 0x3070) 4691 run_rt3070_rf_setup(sc); 4692 4693 /* select default channel */ 4694 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 4695 run_set_chan(sc, ic->ic_ibss_chan); 4696 4697 /* turn radio LED on */ 4698 run_set_leds(sc, RT2860_LED_RADIO); 4699 4700 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 4701 struct run_rx_data *data = &sc->rxq.data[i]; 4702 4703 usbd_setup_xfer(data->xfer, sc->rxq.pipeh, data, data->buf, 4704 RUN_MAX_RXSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 4705 USBD_NO_TIMEOUT, run_rxeof); 4706 error = usbd_transfer(data->xfer); 4707 if (error != 0 && error != USBD_IN_PROGRESS) 4708 goto fail; 4709 } 4710 4711 if ((error = run_txrx_enable(sc)) != 0) 4712 goto fail; 4713 4714 ifp->if_flags |= IFF_RUNNING; 4715 ifq_clr_oactive(&ifp->if_snd); 4716 4717 if (ic->ic_flags & IEEE80211_F_WEPON) { 4718 /* install WEP keys */ 4719 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 4720 if (ic->ic_nw_keys[i].k_cipher != IEEE80211_CIPHER_NONE) 4721 (void)run_set_key(ic, NULL, &ic->ic_nw_keys[i]); 4722 } 4723 } 4724 4725 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4726 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4727 else 4728 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4729 4730 if (error != 0) 4731 fail: run_stop(ifp, 1); 4732 return error; 4733 } 4734 4735 void 4736 run_stop(struct ifnet *ifp, int disable) 4737 { 4738 struct run_softc *sc = ifp->if_softc; 4739 struct ieee80211com *ic = &sc->sc_ic; 4740 uint32_t tmp; 4741 int s, ntries, qid; 4742 4743 if (ifp->if_flags & IFF_RUNNING) 4744 run_set_leds(sc, 0); /* turn all LEDs off */ 4745 4746 sc->sc_tx_timer = 0; 4747 ifp->if_timer = 0; 4748 ifp->if_flags &= ~IFF_RUNNING; 4749 ifq_clr_oactive(&ifp->if_snd); 4750 4751 timeout_del(&sc->scan_to); 4752 timeout_del(&sc->calib_to); 4753 4754 s = splusb(); 4755 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4756 /* wait for all queued asynchronous commands to complete */ 4757 usb_wait_task(sc->sc_udev, &sc->sc_task); 4758 splx(s); 4759 4760 /* Disable Tx/Rx DMA. */ 4761 run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp); 4762 tmp &= ~(RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 4763 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4764 4765 for (ntries = 0; ntries < 100; ntries++) { 4766 if (run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp) != 0) 4767 break; 4768 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4769 break; 4770 DELAY(10); 4771 } 4772 if (ntries == 100) { 4773 printf("%s: timeout waiting for DMA engine\n", 4774 sc->sc_dev.dv_xname); 4775 } 4776 4777 /* disable Tx/Rx */ 4778 run_read(sc, RT2860_MAC_SYS_CTRL, &tmp); 4779 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4780 run_write(sc, RT2860_MAC_SYS_CTRL, tmp); 4781 4782 /* wait for pending Tx to complete */ 4783 for (ntries = 0; ntries < 100; ntries++) { 4784 if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) 4785 break; 4786 if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) 4787 break; 4788 } 4789 DELAY(1000); 4790 run_write(sc, RT2860_USB_DMA_CFG, 0); 4791 4792 /* reset adapter */ 4793 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4794 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4795 4796 /* reset Tx and Rx rings */ 4797 sc->qfullmsk = 0; 4798 for (qid = 0; qid < 4; qid++) 4799 run_free_tx_ring(sc, qid); 4800 run_free_rx_ring(sc); 4801 } 4802