1 /* $OpenBSD: if_run.c,v 1.126 2019/04/25 01:52:14 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2013-2014 Kevin Lo 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2700U/RT2800U/RT3000U/RT3900E chipset driver. 22 * http://www.ralinktech.com/ 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/timeout.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 #include <sys/endian.h> 37 38 #include <machine/intr.h> 39 40 #if NBPFILTER > 0 41 #include <net/bpf.h> 42 #endif 43 #include <net/if.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <netinet/in.h> 48 #include <netinet/if_ether.h> 49 50 #include <net80211/ieee80211_var.h> 51 #include <net80211/ieee80211_amrr.h> 52 #include <net80211/ieee80211_radiotap.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include <dev/usb/usbdevs.h> 58 59 #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ 60 #include <dev/usb/if_runvar.h> 61 62 #ifdef RUN_DEBUG 63 #define DPRINTF(x) do { if (run_debug) printf x; } while (0) 64 #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) 65 int run_debug = 0; 66 #else 67 #define DPRINTF(x) 68 #define DPRINTFN(n, x) 69 #endif 70 71 #define USB_ID(v, p) { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } 72 static const struct usb_devno run_devs[] = { 73 USB_ID(ABOCOM, RT2770), 74 USB_ID(ABOCOM, RT2870), 75 USB_ID(ABOCOM, RT3070), 76 USB_ID(ABOCOM, RT3071), 77 USB_ID(ABOCOM, RT3072), 78 USB_ID(ABOCOM2, RT2870_1), 79 USB_ID(ACCTON, RT2770), 80 USB_ID(ACCTON, RT2870_1), 81 USB_ID(ACCTON, RT2870_2), 82 USB_ID(ACCTON, RT2870_3), 83 USB_ID(ACCTON, RT2870_4), 84 USB_ID(ACCTON, RT2870_5), 85 USB_ID(ACCTON, RT3070), 86 USB_ID(ACCTON, RT3070_1), 87 USB_ID(ACCTON, RT3070_2), 88 USB_ID(ACCTON, RT3070_3), 89 USB_ID(ACCTON, RT3070_4), 90 USB_ID(ACCTON, RT3070_5), 91 USB_ID(ACCTON, RT3070_6), 92 USB_ID(AIRTIES, RT3070), 93 USB_ID(AIRTIES, RT3070_2), 94 USB_ID(ALLWIN, RT2070), 95 USB_ID(ALLWIN, RT2770), 96 USB_ID(ALLWIN, RT2870), 97 USB_ID(ALLWIN, RT3070), 98 USB_ID(ALLWIN, RT3071), 99 USB_ID(ALLWIN, RT3072), 100 USB_ID(ALLWIN, RT3572), 101 USB_ID(AMIGO, RT2870_1), 102 USB_ID(AMIGO, RT2870_2), 103 USB_ID(AMIT, CGWLUSB2GNR), 104 USB_ID(AMIT, RT2870_1), 105 USB_ID(AMIT2, RT2870), 106 USB_ID(ASUS, RT2870_1), 107 USB_ID(ASUS, RT2870_2), 108 USB_ID(ASUS, RT2870_3), 109 USB_ID(ASUS, RT2870_4), 110 USB_ID(ASUS, RT2870_5), 111 USB_ID(ASUS, RT3070_1), 112 USB_ID(ASUS, USBN13), 113 USB_ID(ASUS, USBN53), 114 USB_ID(ASUS, USBN66), 115 USB_ID(ASUS2, USBN11), 116 USB_ID(AZUREWAVE, RT2870_1), 117 USB_ID(AZUREWAVE, RT2870_2), 118 USB_ID(AZUREWAVE, RT3070_1), 119 USB_ID(AZUREWAVE, RT3070_2), 120 USB_ID(AZUREWAVE, RT3070_3), 121 USB_ID(AZUREWAVE, RT3070_4), 122 USB_ID(AZUREWAVE, RT3070_5), 123 USB_ID(BELKIN, F9L1103), 124 USB_ID(BELKIN, F5D8053V3), 125 USB_ID(BELKIN, F5D8055), 126 USB_ID(BELKIN, F5D8055V2), 127 USB_ID(BELKIN, F6D4050V1), 128 USB_ID(BELKIN, F6D4050V2), 129 USB_ID(BELKIN, F7D1101V2), 130 USB_ID(BELKIN, RT2870_1), 131 USB_ID(BELKIN, RT2870_2), 132 USB_ID(BEWAN, RT3070), 133 USB_ID(CISCOLINKSYS, AE1000), 134 USB_ID(CISCOLINKSYS, AM10), 135 USB_ID(CISCOLINKSYS2, RT3070), 136 USB_ID(CISCOLINKSYS3, RT3070), 137 USB_ID(CONCEPTRONIC2, RT2870_1), 138 USB_ID(CONCEPTRONIC2, RT2870_2), 139 USB_ID(CONCEPTRONIC2, RT2870_3), 140 USB_ID(CONCEPTRONIC2, RT2870_4), 141 USB_ID(CONCEPTRONIC2, RT2870_5), 142 USB_ID(CONCEPTRONIC2, RT2870_6), 143 USB_ID(CONCEPTRONIC2, RT2870_7), 144 USB_ID(CONCEPTRONIC2, RT2870_8), 145 USB_ID(CONCEPTRONIC2, RT3070_1), 146 USB_ID(CONCEPTRONIC2, RT3070_2), 147 USB_ID(CONCEPTRONIC2, RT3070_3), 148 USB_ID(CONCEPTRONIC2, VIGORN61), 149 USB_ID(COREGA, CGWLUSB300GNM), 150 USB_ID(COREGA, RT2870_1), 151 USB_ID(COREGA, RT2870_2), 152 USB_ID(COREGA, RT2870_3), 153 USB_ID(COREGA, RT3070), 154 USB_ID(CYBERTAN, RT2870), 155 USB_ID(DLINK, DWA125B2), 156 USB_ID(DLINK, DWA127), 157 USB_ID(DLINK, DWA130F1), 158 USB_ID(DLINK, DWA137A1), 159 USB_ID(DLINK, DWA140B3), 160 USB_ID(DLINK, DWA140D1), 161 USB_ID(DLINK, DWA160B2), 162 USB_ID(DLINK, DWA162), 163 USB_ID(DLINK, RT2870), 164 USB_ID(DLINK, RT3072), 165 USB_ID(DLINK2, DWA130), 166 USB_ID(DLINK2, RT2870_1), 167 USB_ID(DLINK2, RT2870_2), 168 USB_ID(DLINK2, RT3070_1), 169 USB_ID(DLINK2, RT3070_2), 170 USB_ID(DLINK2, RT3070_3), 171 USB_ID(DLINK2, RT3070_4), 172 USB_ID(DLINK2, RT3070_5), 173 USB_ID(DLINK2, RT3072), 174 USB_ID(DLINK2, RT3072_1), 175 USB_ID(DVICO, RT3070), 176 USB_ID(EDIMAX, EW7717), 177 USB_ID(EDIMAX, EW7718), 178 USB_ID(EDIMAX, EW7722UTN), 179 USB_ID(EDIMAX, RT2870_1), 180 USB_ID(ENCORE, RT3070_1), 181 USB_ID(ENCORE, RT3070_2), 182 USB_ID(ENCORE, RT3070_3), 183 USB_ID(GIGABYTE, GNWB31N), 184 USB_ID(GIGABYTE, GNWB32L), 185 USB_ID(GIGABYTE, RT2870_1), 186 USB_ID(GIGASET, RT3070_1), 187 USB_ID(GIGASET, RT3070_2), 188 USB_ID(GUILLEMOT, HWNU300), 189 USB_ID(HAWKING, HWDN2), 190 USB_ID(HAWKING, HWUN2), 191 USB_ID(HAWKING, RT2870_1), 192 USB_ID(HAWKING, RT2870_2), 193 USB_ID(HAWKING, RT2870_3), 194 USB_ID(HAWKING, RT2870_4), 195 USB_ID(HAWKING, RT2870_5), 196 USB_ID(IODATA, RT3072_1), 197 USB_ID(IODATA, RT3072_2), 198 USB_ID(IODATA, RT3072_3), 199 USB_ID(IODATA, RT3072_4), 200 USB_ID(LINKSYS4, RT3070), 201 USB_ID(LINKSYS4, WUSB100), 202 USB_ID(LINKSYS4, WUSB54GCV3), 203 USB_ID(LINKSYS4, WUSB600N), 204 USB_ID(LINKSYS4, WUSB600NV2), 205 USB_ID(LOGITEC, LANW150NU2), 206 USB_ID(LOGITEC, LANW300NU2), 207 USB_ID(LOGITEC, LANW300NU2S), 208 USB_ID(LOGITEC, RT2870_1), 209 USB_ID(LOGITEC, RT2870_2), 210 USB_ID(LOGITEC, RT2870_3), 211 USB_ID(MELCO, RT2870_1), 212 USB_ID(MELCO, RT2870_2), 213 USB_ID(MELCO, WLIUCAG300N), 214 USB_ID(MELCO, WLIUCG300N), 215 USB_ID(MELCO, WLIUCG301N), 216 USB_ID(MELCO, WLIUCGN), 217 USB_ID(MELCO, WLIUCGNHP), 218 USB_ID(MELCO, WLIUCGNM), 219 USB_ID(MELCO, WLIUCGNM2), 220 USB_ID(MOTOROLA4, RT2770), 221 USB_ID(MOTOROLA4, RT3070), 222 USB_ID(MSI, RT3070_1), 223 USB_ID(MSI, RT3070_2), 224 USB_ID(MSI, RT3070_3), 225 USB_ID(MSI, RT3070_4), 226 USB_ID(MSI, RT3070_5), 227 USB_ID(MSI, RT3070_6), 228 USB_ID(MSI, RT3070_7), 229 USB_ID(MSI, RT3070_8), 230 USB_ID(MSI, RT3070_9), 231 USB_ID(MSI, RT3070_10), 232 USB_ID(MSI, RT3070_11), 233 USB_ID(MSI, RT3070_12), 234 USB_ID(MSI, RT3070_13), 235 USB_ID(MSI, RT3070_14), 236 USB_ID(MSI, RT3070_15), 237 USB_ID(OVISLINK, RT3071), 238 USB_ID(OVISLINK, RT3072), 239 USB_ID(PARA, RT3070), 240 USB_ID(PEGATRON, RT2870), 241 USB_ID(PEGATRON, RT3070), 242 USB_ID(PEGATRON, RT3070_2), 243 USB_ID(PEGATRON, RT3070_3), 244 USB_ID(PEGATRON, RT3072), 245 USB_ID(PHILIPS, RT2870), 246 USB_ID(PLANEX2, GWUS300MINIS), 247 USB_ID(PLANEX2, GWUSMICRO300), 248 USB_ID(PLANEX2, GWUSMICRON), 249 USB_ID(PLANEX2, RT2870), 250 USB_ID(PLANEX2, RT3070), 251 USB_ID(QCOM, RT2870), 252 USB_ID(QUANTA, RT3070), 253 USB_ID(RALINK, RT2070), 254 USB_ID(RALINK, RT2770), 255 USB_ID(RALINK, RT2870), 256 USB_ID(RALINK, RT3070), 257 USB_ID(RALINK, RT3071), 258 USB_ID(RALINK, RT3072), 259 USB_ID(RALINK, RT3370), 260 USB_ID(RALINK, RT3572), 261 USB_ID(RALINK, RT3573), 262 USB_ID(RALINK, RT5370), 263 USB_ID(RALINK, RT5572), 264 USB_ID(RALINK, RT8070), 265 USB_ID(SAMSUNG, WIS09ABGN), 266 USB_ID(SAMSUNG2, RT2870_1), 267 USB_ID(SENAO, RT2870_1), 268 USB_ID(SENAO, RT2870_2), 269 USB_ID(SENAO, RT2870_3), 270 USB_ID(SENAO, RT2870_4), 271 USB_ID(SENAO, RT3070), 272 USB_ID(SENAO, RT3071), 273 USB_ID(SENAO, RT3072_1), 274 USB_ID(SENAO, RT3072_2), 275 USB_ID(SENAO, RT3072_3), 276 USB_ID(SENAO, RT3072_4), 277 USB_ID(SENAO, RT3072_5), 278 USB_ID(SITECOMEU, WL302), 279 USB_ID(SITECOMEU, WL315), 280 USB_ID(SITECOMEU, WL321), 281 USB_ID(SITECOMEU, RT3070_3), 282 USB_ID(SITECOMEU, WL302), 283 USB_ID(SITECOMEU, WL344), 284 USB_ID(SITECOMEU, WL329), 285 USB_ID(SITECOMEU, WL345), 286 USB_ID(SITECOMEU, RT2870_1), 287 USB_ID(SITECOMEU, RT2870_2), 288 USB_ID(SITECOMEU, RT2870_3), 289 USB_ID(SITECOMEU, RT3070_1), 290 USB_ID(SITECOMEU, RT3072_3), 291 USB_ID(SITECOMEU, RT3072_4), 292 USB_ID(SITECOMEU, RT3072_5), 293 USB_ID(SITECOMEU, RT3072_6), 294 USB_ID(SITECOMEU, WL302), 295 USB_ID(SITECOMEU, WL315), 296 USB_ID(SITECOMEU, WL321), 297 USB_ID(SITECOMEU, WL324), 298 USB_ID(SITECOMEU, WL329), 299 USB_ID(SITECOMEU, WL343), 300 USB_ID(SITECOMEU, WL344), 301 USB_ID(SITECOMEU, WL345), 302 USB_ID(SITECOMEU, WL349V4), 303 USB_ID(SITECOMEU, WL608), 304 USB_ID(SITECOMEU, WLA4000), 305 USB_ID(SITECOMEU, WLA5000), 306 USB_ID(SPARKLAN, RT2870_1), 307 USB_ID(SPARKLAN, RT2870_2), 308 USB_ID(SPARKLAN, RT3070), 309 USB_ID(SWEEX2, LW153), 310 USB_ID(SWEEX2, LW303), 311 USB_ID(SWEEX2, LW313), 312 USB_ID(TOSHIBA, RT3070), 313 USB_ID(UMEDIA, RT2870_1), 314 USB_ID(UMEDIA, TEW645UB), 315 USB_ID(ZCOM, RT2870_1), 316 USB_ID(ZCOM, RT2870_2), 317 USB_ID(ZINWELL, RT2870_1), 318 USB_ID(ZINWELL, RT2870_2), 319 USB_ID(ZINWELL, RT3070), 320 USB_ID(ZINWELL, RT3072_1), 321 USB_ID(ZINWELL, RT3072_2), 322 USB_ID(ZYXEL, NWD2105), 323 USB_ID(ZYXEL, NWD211AN), 324 USB_ID(ZYXEL, RT2870_1), 325 USB_ID(ZYXEL, RT2870_2), 326 USB_ID(ZYXEL, RT3070) 327 }; 328 329 int run_match(struct device *, void *, void *); 330 void run_attach(struct device *, struct device *, void *); 331 int run_detach(struct device *, int); 332 int run_alloc_rx_ring(struct run_softc *); 333 void run_free_rx_ring(struct run_softc *); 334 int run_alloc_tx_ring(struct run_softc *, int); 335 void run_free_tx_ring(struct run_softc *, int); 336 int run_load_microcode(struct run_softc *); 337 int run_reset(struct run_softc *); 338 int run_read(struct run_softc *, uint16_t, uint32_t *); 339 int run_read_region_1(struct run_softc *, uint16_t, uint8_t *, 340 int); 341 int run_write_2(struct run_softc *, uint16_t, uint16_t); 342 int run_write(struct run_softc *, uint16_t, uint32_t); 343 int run_write_region_1(struct run_softc *, uint16_t, 344 const uint8_t *, int); 345 int run_set_region_4(struct run_softc *, uint16_t, uint32_t, int); 346 int run_efuse_read(struct run_softc *, uint16_t, uint16_t *); 347 int run_efuse_read_2(struct run_softc *, uint16_t, uint16_t *); 348 int run_eeprom_read_2(struct run_softc *, uint16_t, uint16_t *); 349 int run_rt2870_rf_write(struct run_softc *, uint8_t, uint32_t); 350 int run_rt3070_rf_read(struct run_softc *, uint8_t, uint8_t *); 351 int run_rt3070_rf_write(struct run_softc *, uint8_t, uint8_t); 352 int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); 353 int run_bbp_write(struct run_softc *, uint8_t, uint8_t); 354 int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); 355 const char * run_get_rf(int); 356 void run_get_txpower(struct run_softc *); 357 void run_rt3593_get_txpower(struct run_softc *); 358 int run_read_eeprom(struct run_softc *); 359 struct ieee80211_node *run_node_alloc(struct ieee80211com *); 360 int run_media_change(struct ifnet *); 361 void run_next_scan(void *); 362 void run_task(void *); 363 void run_do_async(struct run_softc *, void (*)(struct run_softc *, 364 void *), void *, int); 365 int run_newstate(struct ieee80211com *, enum ieee80211_state, int); 366 void run_newstate_cb(struct run_softc *, void *); 367 void run_updateedca(struct ieee80211com *); 368 void run_updateedca_cb(struct run_softc *, void *); 369 int run_set_key(struct ieee80211com *, struct ieee80211_node *, 370 struct ieee80211_key *); 371 void run_set_key_cb(struct run_softc *, void *); 372 void run_delete_key(struct ieee80211com *, struct ieee80211_node *, 373 struct ieee80211_key *); 374 void run_delete_key_cb(struct run_softc *, void *); 375 void run_calibrate_to(void *); 376 void run_calibrate_cb(struct run_softc *, void *); 377 void run_newassoc(struct ieee80211com *, struct ieee80211_node *, 378 int); 379 void run_rx_frame(struct run_softc *, uint8_t *, int); 380 void run_rxeof(struct usbd_xfer *, void *, usbd_status); 381 void run_txeof(struct usbd_xfer *, void *, usbd_status); 382 int run_tx(struct run_softc *, struct mbuf *, 383 struct ieee80211_node *); 384 void run_start(struct ifnet *); 385 void run_watchdog(struct ifnet *); 386 int run_ioctl(struct ifnet *, u_long, caddr_t); 387 void run_iq_calib(struct run_softc *, u_int); 388 void run_select_chan_group(struct run_softc *, int); 389 void run_set_agc(struct run_softc *, uint8_t); 390 void run_set_rx_antenna(struct run_softc *, int); 391 void run_rt2870_set_chan(struct run_softc *, u_int); 392 void run_rt3070_set_chan(struct run_softc *, u_int); 393 void run_rt3572_set_chan(struct run_softc *, u_int); 394 void run_rt3593_set_chan(struct run_softc *, u_int); 395 void run_rt5390_set_chan(struct run_softc *, u_int); 396 void run_rt5592_set_chan(struct run_softc *, u_int); 397 int run_set_chan(struct run_softc *, struct ieee80211_channel *); 398 void run_enable_tsf_sync(struct run_softc *); 399 void run_enable_mrr(struct run_softc *); 400 void run_set_txpreamble(struct run_softc *); 401 void run_set_basicrates(struct run_softc *); 402 void run_set_leds(struct run_softc *, uint16_t); 403 void run_set_bssid(struct run_softc *, const uint8_t *); 404 void run_set_macaddr(struct run_softc *, const uint8_t *); 405 void run_updateslot(struct ieee80211com *); 406 void run_updateslot_cb(struct run_softc *, void *); 407 #if NBPFILTER > 0 408 int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); 409 #endif 410 void run_rt5390_bbp_init(struct run_softc *); 411 int run_bbp_init(struct run_softc *); 412 int run_rt3070_rf_init(struct run_softc *); 413 void run_rt3593_rf_init(struct run_softc *); 414 void run_rt5390_rf_init(struct run_softc *); 415 int run_rt3070_filter_calib(struct run_softc *, uint8_t, uint8_t, 416 uint8_t *); 417 void run_rt3070_rf_setup(struct run_softc *); 418 void run_rt3593_rf_setup(struct run_softc *); 419 void run_rt5390_rf_setup(struct run_softc *); 420 int run_txrx_enable(struct run_softc *); 421 void run_adjust_freq_offset(struct run_softc *); 422 int run_init(struct ifnet *); 423 void run_stop(struct ifnet *, int); 424 425 struct cfdriver run_cd = { 426 NULL, "run", DV_IFNET 427 }; 428 429 const struct cfattach run_ca = { 430 sizeof (struct run_softc), run_match, run_attach, run_detach 431 }; 432 433 static const struct { 434 uint32_t reg; 435 uint32_t val; 436 } rt2870_def_mac[] = { 437 RT2870_DEF_MAC 438 }; 439 440 static const struct { 441 uint8_t reg; 442 uint8_t val; 443 } rt2860_def_bbp[] = { 444 RT2860_DEF_BBP 445 },rt5390_def_bbp[] = { 446 RT5390_DEF_BBP 447 },rt5592_def_bbp[] = { 448 RT5592_DEF_BBP 449 }; 450 451 /* 452 * Default values for BBP register R196 for RT5592. 453 */ 454 static const uint8_t rt5592_bbp_r196[] = { 455 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, 456 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, 457 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, 458 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, 459 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, 460 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 461 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 462 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, 463 0x2e, 0x36, 0x30, 0x6e 464 }; 465 466 static const struct rfprog { 467 uint8_t chan; 468 uint32_t r1, r2, r3, r4; 469 } rt2860_rf2850[] = { 470 RT2860_RF2850 471 }; 472 473 struct { 474 uint8_t n, r, k; 475 } rt3070_freqs[] = { 476 RT3070_RF3052 477 }; 478 479 static const struct rt5592_freqs { 480 uint16_t n; 481 uint8_t k, m, r; 482 } rt5592_freqs_20mhz[] = { 483 RT5592_RF5592_20MHZ 484 },rt5592_freqs_40mhz[] = { 485 RT5592_RF5592_40MHZ 486 }; 487 488 static const struct { 489 uint8_t reg; 490 uint8_t val; 491 } rt3070_def_rf[] = { 492 RT3070_DEF_RF 493 },rt3572_def_rf[] = { 494 RT3572_DEF_RF 495 },rt3593_def_rf[] = { 496 RT3593_DEF_RF 497 },rt5390_def_rf[] = { 498 RT5390_DEF_RF 499 },rt5392_def_rf[] = { 500 RT5392_DEF_RF 501 },rt5592_def_rf[] = { 502 RT5592_DEF_RF 503 },rt5592_2ghz_def_rf[] = { 504 RT5592_2GHZ_DEF_RF 505 },rt5592_5ghz_def_rf[] = { 506 RT5592_5GHZ_DEF_RF 507 }; 508 509 static const struct { 510 u_int firstchan; 511 u_int lastchan; 512 uint8_t reg; 513 uint8_t val; 514 } rt5592_chan_5ghz[] = { 515 RT5592_CHAN_5GHZ 516 }; 517 518 int 519 run_match(struct device *parent, void *match, void *aux) 520 { 521 struct usb_attach_arg *uaa = aux; 522 523 if (uaa->iface == NULL || uaa->configno != 1) 524 return UMATCH_NONE; 525 526 return (usb_lookup(run_devs, uaa->vendor, uaa->product) != NULL) ? 527 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE; 528 } 529 530 void 531 run_attach(struct device *parent, struct device *self, void *aux) 532 { 533 struct run_softc *sc = (struct run_softc *)self; 534 struct usb_attach_arg *uaa = aux; 535 struct ieee80211com *ic = &sc->sc_ic; 536 struct ifnet *ifp = &ic->ic_if; 537 usb_interface_descriptor_t *id; 538 usb_endpoint_descriptor_t *ed; 539 int i, nrx, ntx, ntries; 540 uint32_t ver; 541 542 sc->sc_udev = uaa->device; 543 sc->sc_iface = uaa->iface; 544 545 /* 546 * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX 547 * and 6 for TX (4 EDCAs + HCCA + Prio). 548 * Update 03-14-2009: some devices like the Planex GW-US300MiniS 549 * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). 550 */ 551 nrx = ntx = 0; 552 id = usbd_get_interface_descriptor(sc->sc_iface); 553 for (i = 0; i < id->bNumEndpoints; i++) { 554 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 555 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 556 continue; 557 558 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 559 sc->rxq.pipe_no = ed->bEndpointAddress; 560 nrx++; 561 } else if (ntx < 4) { 562 sc->txq[ntx].pipe_no = ed->bEndpointAddress; 563 ntx++; 564 } 565 } 566 /* make sure we've got them all */ 567 if (nrx < 1 || ntx < 4) { 568 printf("%s: missing endpoint\n", sc->sc_dev.dv_xname); 569 return; 570 } 571 572 usb_init_task(&sc->sc_task, run_task, sc, USB_TASK_TYPE_GENERIC); 573 timeout_set(&sc->scan_to, run_next_scan, sc); 574 timeout_set(&sc->calib_to, run_calibrate_to, sc); 575 576 sc->amrr.amrr_min_success_threshold = 1; 577 sc->amrr.amrr_max_success_threshold = 10; 578 579 /* wait for the chip to settle */ 580 for (ntries = 0; ntries < 100; ntries++) { 581 if (run_read(sc, RT2860_ASIC_VER_ID, &ver) != 0) 582 return; 583 if (ver != 0 && ver != 0xffffffff) 584 break; 585 DELAY(10); 586 } 587 if (ntries == 100) { 588 printf("%s: timeout waiting for NIC to initialize\n", 589 sc->sc_dev.dv_xname); 590 return; 591 } 592 sc->mac_ver = ver >> 16; 593 sc->mac_rev = ver & 0xffff; 594 595 /* retrieve RF rev. no and various other things from EEPROM */ 596 run_read_eeprom(sc); 597 598 printf("%s: MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), " 599 "address %s\n", sc->sc_dev.dv_xname, sc->mac_ver, 600 sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, 601 sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 602 603 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 604 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 605 ic->ic_state = IEEE80211_S_INIT; 606 607 /* set device capabilities */ 608 ic->ic_caps = 609 IEEE80211_C_MONITOR | /* monitor mode supported */ 610 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 611 IEEE80211_C_SHSLOT | /* short slot time supported */ 612 IEEE80211_C_WEP | /* WEP */ 613 IEEE80211_C_RSN; /* WPA/RSN */ 614 615 if (sc->rf_rev == RT2860_RF_2750 || 616 sc->rf_rev == RT2860_RF_2850 || 617 sc->rf_rev == RT3070_RF_3052 || 618 sc->rf_rev == RT3070_RF_3053 || 619 sc->rf_rev == RT5592_RF_5592) { 620 /* set supported .11a rates */ 621 ic->ic_sup_rates[IEEE80211_MODE_11A] = 622 ieee80211_std_rateset_11a; 623 624 /* set supported .11a channels */ 625 for (i = 14; i < nitems(rt2860_rf2850); i++) { 626 uint8_t chan = rt2860_rf2850[i].chan; 627 ic->ic_channels[chan].ic_freq = 628 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 629 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 630 } 631 } 632 633 /* set supported .11b and .11g rates */ 634 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 635 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 636 637 /* set supported .11b and .11g channels (1 through 14) */ 638 for (i = 1; i <= 14; i++) { 639 ic->ic_channels[i].ic_freq = 640 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 641 ic->ic_channels[i].ic_flags = 642 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 643 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 644 } 645 646 ifp->if_softc = sc; 647 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 648 ifp->if_ioctl = run_ioctl; 649 ifp->if_start = run_start; 650 ifp->if_watchdog = run_watchdog; 651 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 652 653 if_attach(ifp); 654 ieee80211_ifattach(ifp); 655 ic->ic_node_alloc = run_node_alloc; 656 ic->ic_newassoc = run_newassoc; 657 ic->ic_updateslot = run_updateslot; 658 ic->ic_updateedca = run_updateedca; 659 ic->ic_set_key = run_set_key; 660 ic->ic_delete_key = run_delete_key; 661 /* override state transition machine */ 662 sc->sc_newstate = ic->ic_newstate; 663 ic->ic_newstate = run_newstate; 664 ieee80211_media_init(ifp, run_media_change, ieee80211_media_status); 665 666 #if NBPFILTER > 0 667 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 668 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 669 670 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 671 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 672 sc->sc_rxtap.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT); 673 674 sc->sc_txtap_len = sizeof sc->sc_txtapu; 675 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 676 sc->sc_txtap.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT); 677 #endif 678 } 679 680 int 681 run_detach(struct device *self, int flags) 682 { 683 struct run_softc *sc = (struct run_softc *)self; 684 struct ifnet *ifp = &sc->sc_ic.ic_if; 685 int qid, s; 686 687 s = splusb(); 688 689 if (timeout_initialized(&sc->scan_to)) 690 timeout_del(&sc->scan_to); 691 if (timeout_initialized(&sc->calib_to)) 692 timeout_del(&sc->calib_to); 693 694 /* wait for all queued asynchronous commands to complete */ 695 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 696 697 usbd_ref_wait(sc->sc_udev); 698 699 if (ifp->if_softc != NULL) { 700 ifp->if_flags &= ~IFF_RUNNING; 701 ifq_clr_oactive(&ifp->if_snd); 702 ieee80211_ifdetach(ifp); 703 if_detach(ifp); 704 } 705 706 for (qid = 0; qid < 4; qid++) 707 run_free_tx_ring(sc, qid); 708 run_free_rx_ring(sc); 709 710 splx(s); 711 712 return 0; 713 } 714 715 int 716 run_alloc_rx_ring(struct run_softc *sc) 717 { 718 struct run_rx_ring *rxq = &sc->rxq; 719 int i, error; 720 721 error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); 722 if (error != 0) 723 goto fail; 724 725 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 726 struct run_rx_data *data = &rxq->data[i]; 727 728 data->sc = sc; /* backpointer for callbacks */ 729 730 data->xfer = usbd_alloc_xfer(sc->sc_udev); 731 if (data->xfer == NULL) { 732 error = ENOMEM; 733 goto fail; 734 } 735 data->buf = usbd_alloc_buffer(data->xfer, RUN_MAX_RXSZ); 736 if (data->buf == NULL) { 737 error = ENOMEM; 738 goto fail; 739 } 740 } 741 if (error != 0) 742 fail: run_free_rx_ring(sc); 743 return error; 744 } 745 746 void 747 run_free_rx_ring(struct run_softc *sc) 748 { 749 struct run_rx_ring *rxq = &sc->rxq; 750 int i; 751 752 if (rxq->pipeh != NULL) { 753 usbd_abort_pipe(rxq->pipeh); 754 usbd_close_pipe(rxq->pipeh); 755 rxq->pipeh = NULL; 756 } 757 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 758 if (rxq->data[i].xfer != NULL) 759 usbd_free_xfer(rxq->data[i].xfer); 760 rxq->data[i].xfer = NULL; 761 } 762 } 763 764 int 765 run_alloc_tx_ring(struct run_softc *sc, int qid) 766 { 767 struct run_tx_ring *txq = &sc->txq[qid]; 768 int i, error; 769 uint16_t txwisize; 770 771 txwisize = sizeof(struct rt2860_txwi); 772 if (sc->mac_ver == 0x5592) 773 txwisize += sizeof(uint32_t); 774 775 txq->cur = txq->queued = 0; 776 777 error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); 778 if (error != 0) 779 goto fail; 780 781 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 782 struct run_tx_data *data = &txq->data[i]; 783 784 data->sc = sc; /* backpointer for callbacks */ 785 data->qid = qid; 786 787 data->xfer = usbd_alloc_xfer(sc->sc_udev); 788 if (data->xfer == NULL) { 789 error = ENOMEM; 790 goto fail; 791 } 792 data->buf = usbd_alloc_buffer(data->xfer, RUN_MAX_TXSZ); 793 if (data->buf == NULL) { 794 error = ENOMEM; 795 goto fail; 796 } 797 /* zeroize the TXD + TXWI part */ 798 memset(data->buf, 0, sizeof(struct rt2870_txd) + txwisize); 799 } 800 if (error != 0) 801 fail: run_free_tx_ring(sc, qid); 802 return error; 803 } 804 805 void 806 run_free_tx_ring(struct run_softc *sc, int qid) 807 { 808 struct run_tx_ring *txq = &sc->txq[qid]; 809 int i; 810 811 if (txq->pipeh != NULL) { 812 usbd_abort_pipe(txq->pipeh); 813 usbd_close_pipe(txq->pipeh); 814 txq->pipeh = NULL; 815 } 816 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 817 if (txq->data[i].xfer != NULL) 818 usbd_free_xfer(txq->data[i].xfer); 819 txq->data[i].xfer = NULL; 820 } 821 } 822 823 int 824 run_load_microcode(struct run_softc *sc) 825 { 826 usb_device_request_t req; 827 const char *fwname; 828 u_char *ucode; 829 size_t size; 830 uint32_t tmp; 831 int ntries, error; 832 833 /* RT3071/RT3072 use a different firmware */ 834 if (sc->mac_ver != 0x2860 && 835 sc->mac_ver != 0x2872 && 836 sc->mac_ver != 0x3070) 837 fwname = "run-rt3071"; 838 else 839 fwname = "run-rt2870"; 840 841 if ((error = loadfirmware(fwname, &ucode, &size)) != 0) { 842 printf("%s: failed loadfirmware of file %s (error %d)\n", 843 sc->sc_dev.dv_xname, fwname, error); 844 return error; 845 } 846 if (size != 4096) { 847 printf("%s: invalid firmware size (should be 4KB)\n", 848 sc->sc_dev.dv_xname); 849 free(ucode, M_DEVBUF, size); 850 return EINVAL; 851 } 852 853 /* write microcode image */ 854 run_write_region_1(sc, RT2870_FW_BASE, ucode, size); 855 free(ucode, M_DEVBUF, size); 856 run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 857 run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 858 859 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 860 req.bRequest = RT2870_RESET; 861 USETW(req.wValue, 8); 862 USETW(req.wIndex, 0); 863 USETW(req.wLength, 0); 864 if ((error = usbd_do_request(sc->sc_udev, &req, NULL)) != 0) 865 return error; 866 867 usbd_delay_ms(sc->sc_udev, 10); 868 run_write(sc, RT2860_H2M_BBPAGENT, 0); 869 run_write(sc, RT2860_H2M_MAILBOX, 0); 870 run_write(sc, RT2860_H2M_INTSRC, 0); 871 if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) 872 return error; 873 874 /* wait until microcontroller is ready */ 875 for (ntries = 0; ntries < 1000; ntries++) { 876 if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) 877 return error; 878 if (tmp & RT2860_MCU_READY) 879 break; 880 DELAY(1000); 881 } 882 if (ntries == 1000) { 883 printf("%s: timeout waiting for MCU to initialize\n", 884 sc->sc_dev.dv_xname); 885 return ETIMEDOUT; 886 } 887 DPRINTF(("microcode successfully loaded after %d tries\n", ntries)); 888 return 0; 889 } 890 891 int 892 run_reset(struct run_softc *sc) 893 { 894 usb_device_request_t req; 895 896 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 897 req.bRequest = RT2870_RESET; 898 USETW(req.wValue, 1); 899 USETW(req.wIndex, 0); 900 USETW(req.wLength, 0); 901 return usbd_do_request(sc->sc_udev, &req, NULL); 902 } 903 904 int 905 run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) 906 { 907 uint32_t tmp; 908 int error; 909 910 error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp); 911 if (error == 0) 912 *val = letoh32(tmp); 913 else 914 *val = 0xffffffff; 915 return error; 916 } 917 918 int 919 run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) 920 { 921 usb_device_request_t req; 922 923 req.bmRequestType = UT_READ_VENDOR_DEVICE; 924 req.bRequest = RT2870_READ_REGION_1; 925 USETW(req.wValue, 0); 926 USETW(req.wIndex, reg); 927 USETW(req.wLength, len); 928 return usbd_do_request(sc->sc_udev, &req, buf); 929 } 930 931 int 932 run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) 933 { 934 usb_device_request_t req; 935 936 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 937 req.bRequest = RT2870_WRITE_2; 938 USETW(req.wValue, val); 939 USETW(req.wIndex, reg); 940 USETW(req.wLength, 0); 941 return usbd_do_request(sc->sc_udev, &req, NULL); 942 } 943 944 int 945 run_write(struct run_softc *sc, uint16_t reg, uint32_t val) 946 { 947 int error; 948 949 if ((error = run_write_2(sc, reg, val & 0xffff)) == 0) 950 error = run_write_2(sc, reg + 2, val >> 16); 951 return error; 952 } 953 954 int 955 run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, 956 int len) 957 { 958 #if 1 959 int i, error = 0; 960 /* 961 * NB: the WRITE_REGION_1 command is not stable on RT2860. 962 * We thus issue multiple WRITE_2 commands instead. 963 */ 964 KASSERT((len & 1) == 0); 965 for (i = 0; i < len && error == 0; i += 2) 966 error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); 967 return error; 968 #else 969 usb_device_request_t req; 970 971 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 972 req.bRequest = RT2870_WRITE_REGION_1; 973 USETW(req.wValue, 0); 974 USETW(req.wIndex, reg); 975 USETW(req.wLength, len); 976 return usbd_do_request(sc->sc_udev, &req, buf); 977 #endif 978 } 979 980 int 981 run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) 982 { 983 int error = 0; 984 985 for (; count > 0 && error == 0; count--, reg += 4) 986 error = run_write(sc, reg, val); 987 return error; 988 } 989 990 /* Read 16-bit from eFUSE ROM. */ 991 int 992 run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 993 { 994 uint32_t tmp; 995 uint16_t reg; 996 int error, ntries; 997 998 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 999 return error; 1000 1001 /*- 1002 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1003 * DATA0: F E D C 1004 * DATA1: B A 9 8 1005 * DATA2: 7 6 5 4 1006 * DATA3: 3 2 1 0 1007 */ 1008 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1009 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1010 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1011 for (ntries = 0; ntries < 100; ntries++) { 1012 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1013 return error; 1014 if (!(tmp & RT3070_EFSROM_KICK)) 1015 break; 1016 DELAY(2); 1017 } 1018 if (ntries == 100) 1019 return ETIMEDOUT; 1020 1021 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1022 *val = 0xffff; /* address not found */ 1023 return 0; 1024 } 1025 /* determine to which 32-bit register our 16-bit word belongs */ 1026 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1027 if ((error = run_read(sc, reg, &tmp)) != 0) 1028 return error; 1029 1030 tmp >>= (8 * (addr & 0x3)); 1031 *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; 1032 return 0; 1033 } 1034 1035 /* Read 16-bit from eFUSE ROM for RT3xxx. */ 1036 int 1037 run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1038 { 1039 uint32_t tmp; 1040 uint16_t reg; 1041 int error, ntries; 1042 1043 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1044 return error; 1045 1046 addr *= 2; 1047 /*- 1048 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1049 * DATA0: F E D C 1050 * DATA1: B A 9 8 1051 * DATA2: 7 6 5 4 1052 * DATA3: 3 2 1 0 1053 */ 1054 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1055 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1056 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1057 for (ntries = 0; ntries < 100; ntries++) { 1058 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1059 return error; 1060 if (!(tmp & RT3070_EFSROM_KICK)) 1061 break; 1062 DELAY(2); 1063 } 1064 if (ntries == 100) 1065 return ETIMEDOUT; 1066 1067 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1068 *val = 0xffff; /* address not found */ 1069 return 0; 1070 } 1071 /* determine to which 32-bit register our 16-bit word belongs */ 1072 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1073 if ((error = run_read(sc, reg, &tmp)) != 0) 1074 return error; 1075 1076 *val = (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1077 return 0; 1078 } 1079 1080 int 1081 run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1082 { 1083 usb_device_request_t req; 1084 uint16_t tmp; 1085 int error; 1086 1087 addr *= 2; 1088 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1089 req.bRequest = RT2870_EEPROM_READ; 1090 USETW(req.wValue, 0); 1091 USETW(req.wIndex, addr); 1092 USETW(req.wLength, sizeof tmp); 1093 error = usbd_do_request(sc->sc_udev, &req, &tmp); 1094 if (error == 0) 1095 *val = letoh16(tmp); 1096 else 1097 *val = 0xffff; 1098 return error; 1099 } 1100 1101 static __inline int 1102 run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 1103 { 1104 /* either eFUSE ROM or EEPROM */ 1105 return sc->sc_srom_read(sc, addr, val); 1106 } 1107 1108 int 1109 run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) 1110 { 1111 uint32_t tmp; 1112 int error, ntries; 1113 1114 for (ntries = 0; ntries < 10; ntries++) { 1115 if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0) 1116 return error; 1117 if (!(tmp & RT2860_RF_REG_CTRL)) 1118 break; 1119 } 1120 if (ntries == 10) 1121 return ETIMEDOUT; 1122 1123 /* RF registers are 24-bit on the RT2860 */ 1124 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1125 (val & 0x3fffff) << 2 | (reg & 3); 1126 return run_write(sc, RT2860_RF_CSR_CFG0, tmp); 1127 } 1128 1129 int 1130 run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1131 { 1132 uint32_t tmp; 1133 int error, ntries; 1134 1135 for (ntries = 0; ntries < 100; ntries++) { 1136 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1137 return error; 1138 if (!(tmp & RT3070_RF_KICK)) 1139 break; 1140 } 1141 if (ntries == 100) 1142 return ETIMEDOUT; 1143 1144 tmp = RT3070_RF_KICK | reg << 8; 1145 if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0) 1146 return error; 1147 1148 for (ntries = 0; ntries < 100; ntries++) { 1149 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1150 return error; 1151 if (!(tmp & RT3070_RF_KICK)) 1152 break; 1153 } 1154 if (ntries == 100) 1155 return ETIMEDOUT; 1156 1157 *val = tmp & 0xff; 1158 return 0; 1159 } 1160 1161 int 1162 run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1163 { 1164 uint32_t tmp; 1165 int error, ntries; 1166 1167 for (ntries = 0; ntries < 10; ntries++) { 1168 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1169 return error; 1170 if (!(tmp & RT3070_RF_KICK)) 1171 break; 1172 } 1173 if (ntries == 10) 1174 return ETIMEDOUT; 1175 1176 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 1177 return run_write(sc, RT3070_RF_CSR_CFG, tmp); 1178 } 1179 1180 int 1181 run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1182 { 1183 uint32_t tmp; 1184 int ntries, error; 1185 1186 for (ntries = 0; ntries < 10; ntries++) { 1187 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1188 return error; 1189 if (!(tmp & RT2860_BBP_CSR_KICK)) 1190 break; 1191 } 1192 if (ntries == 10) 1193 return ETIMEDOUT; 1194 1195 tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8; 1196 if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0) 1197 return error; 1198 1199 for (ntries = 0; ntries < 10; ntries++) { 1200 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1201 return error; 1202 if (!(tmp & RT2860_BBP_CSR_KICK)) 1203 break; 1204 } 1205 if (ntries == 10) 1206 return ETIMEDOUT; 1207 1208 *val = tmp & 0xff; 1209 return 0; 1210 } 1211 1212 int 1213 run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1214 { 1215 uint32_t tmp; 1216 int ntries, error; 1217 1218 for (ntries = 0; ntries < 10; ntries++) { 1219 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1220 return error; 1221 if (!(tmp & RT2860_BBP_CSR_KICK)) 1222 break; 1223 } 1224 if (ntries == 10) 1225 return ETIMEDOUT; 1226 1227 tmp = RT2860_BBP_CSR_KICK | reg << 8 | val; 1228 return run_write(sc, RT2860_BBP_CSR_CFG, tmp); 1229 } 1230 1231 /* 1232 * Send a command to the 8051 microcontroller unit. 1233 */ 1234 int 1235 run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) 1236 { 1237 uint32_t tmp; 1238 int error, ntries; 1239 1240 for (ntries = 0; ntries < 100; ntries++) { 1241 if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0) 1242 return error; 1243 if (!(tmp & RT2860_H2M_BUSY)) 1244 break; 1245 } 1246 if (ntries == 100) 1247 return ETIMEDOUT; 1248 1249 tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg; 1250 if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0) 1251 error = run_write(sc, RT2860_HOST_CMD, cmd); 1252 return error; 1253 } 1254 1255 /* 1256 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 1257 * Used to adjust per-rate Tx power registers. 1258 */ 1259 static __inline uint32_t 1260 b4inc(uint32_t b32, int8_t delta) 1261 { 1262 int8_t i, b4; 1263 1264 for (i = 0; i < 8; i++) { 1265 b4 = b32 & 0xf; 1266 b4 += delta; 1267 if (b4 < 0) 1268 b4 = 0; 1269 else if (b4 > 0xf) 1270 b4 = 0xf; 1271 b32 = b32 >> 4 | b4 << 28; 1272 } 1273 return b32; 1274 } 1275 1276 const char * 1277 run_get_rf(int rev) 1278 { 1279 switch (rev) { 1280 case RT2860_RF_2820: return "RT2820"; 1281 case RT2860_RF_2850: return "RT2850"; 1282 case RT2860_RF_2720: return "RT2720"; 1283 case RT2860_RF_2750: return "RT2750"; 1284 case RT3070_RF_3020: return "RT3020"; 1285 case RT3070_RF_2020: return "RT2020"; 1286 case RT3070_RF_3021: return "RT3021"; 1287 case RT3070_RF_3022: return "RT3022"; 1288 case RT3070_RF_3052: return "RT3052"; 1289 case RT3070_RF_3053: return "RT3053"; 1290 case RT5592_RF_5592: return "RT5592"; 1291 case RT5390_RF_5370: return "RT5370"; 1292 case RT5390_RF_5372: return "RT5372"; 1293 } 1294 return "unknown"; 1295 } 1296 1297 void 1298 run_rt3593_get_txpower(struct run_softc *sc) 1299 { 1300 uint16_t addr, val; 1301 int i; 1302 1303 /* Read power settings for 2GHz channels. */ 1304 for (i = 0; i < 14; i += 2) { 1305 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : 1306 RT2860_EEPROM_PWR2GHZ_BASE1; 1307 run_srom_read(sc, addr + i / 2, &val); 1308 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1309 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1310 1311 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : 1312 RT2860_EEPROM_PWR2GHZ_BASE2; 1313 run_srom_read(sc, addr + i / 2, &val); 1314 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1315 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1316 1317 if (sc->ntxchains == 3) { 1318 run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, 1319 &val); 1320 sc->txpow3[i + 0] = (int8_t)(val & 0xff); 1321 sc->txpow3[i + 1] = (int8_t)(val >> 8); 1322 } 1323 } 1324 /* Fix broken Tx power entries. */ 1325 for (i = 0; i < 14; i++) { 1326 if (sc->txpow1[i] > 31) 1327 sc->txpow1[i] = 5; 1328 if (sc->txpow2[i] > 31) 1329 sc->txpow2[i] = 5; 1330 if (sc->ntxchains == 3) { 1331 if (sc->txpow3[i] > 31) 1332 sc->txpow3[i] = 5; 1333 } 1334 } 1335 /* Read power settings for 5GHz channels. */ 1336 for (i = 0; i < 40; i += 2) { 1337 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1338 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1339 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1340 1341 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1342 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1343 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1344 1345 if (sc->ntxchains == 3) { 1346 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, 1347 &val); 1348 sc->txpow3[i + 14] = (int8_t)(val & 0xff); 1349 sc->txpow3[i + 15] = (int8_t)(val >> 8); 1350 } 1351 } 1352 } 1353 1354 void 1355 run_get_txpower(struct run_softc *sc) 1356 { 1357 uint16_t val; 1358 int i; 1359 1360 /* Read power settings for 2GHz channels. */ 1361 for (i = 0; i < 14; i += 2) { 1362 run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); 1363 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1364 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1365 1366 if (sc->mac_ver != 0x5390) { 1367 run_srom_read(sc, 1368 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); 1369 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1370 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1371 } 1372 } 1373 /* Fix broken Tx power entries. */ 1374 for (i = 0; i < 14; i++) { 1375 if (sc->mac_ver >= 0x5390) { 1376 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 27) 1377 sc->txpow1[i] = 5; 1378 } else { 1379 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 1380 sc->txpow1[i] = 5; 1381 } 1382 if (sc->mac_ver > 0x5390) { 1383 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 27) 1384 sc->txpow2[i] = 5; 1385 } else if (sc->mac_ver < 0x5390) { 1386 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 1387 sc->txpow2[i] = 5; 1388 } 1389 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1390 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 1391 } 1392 /* Read power settings for 5GHz channels. */ 1393 for (i = 0; i < 40; i += 2) { 1394 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1395 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1396 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1397 1398 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1399 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1400 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1401 } 1402 /* Fix broken Tx power entries. */ 1403 for (i = 0; i < 40; i++ ) { 1404 if (sc->mac_ver != 0x5592) { 1405 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 1406 sc->txpow1[14 + i] = 5; 1407 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 1408 sc->txpow2[14 + i] = 5; 1409 } 1410 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1411 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 1412 sc->txpow2[14 + i])); 1413 } 1414 } 1415 1416 int 1417 run_read_eeprom(struct run_softc *sc) 1418 { 1419 struct ieee80211com *ic = &sc->sc_ic; 1420 int8_t delta_2ghz, delta_5ghz; 1421 uint32_t tmp; 1422 uint16_t val; 1423 int ridx, ant, i; 1424 1425 /* check whether the ROM is eFUSE ROM or EEPROM */ 1426 sc->sc_srom_read = run_eeprom_read_2; 1427 if (sc->mac_ver >= 0x3070) { 1428 run_read(sc, RT3070_EFUSE_CTRL, &tmp); 1429 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 1430 if (tmp & RT3070_SEL_EFUSE || sc->mac_ver == 0x3593) 1431 sc->sc_srom_read = run_efuse_read_2; 1432 } 1433 1434 /* read ROM version */ 1435 run_srom_read(sc, RT2860_EEPROM_VERSION, &val); 1436 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 1437 1438 /* read MAC address */ 1439 run_srom_read(sc, RT2860_EEPROM_MAC01, &val); 1440 ic->ic_myaddr[0] = val & 0xff; 1441 ic->ic_myaddr[1] = val >> 8; 1442 run_srom_read(sc, RT2860_EEPROM_MAC23, &val); 1443 ic->ic_myaddr[2] = val & 0xff; 1444 ic->ic_myaddr[3] = val >> 8; 1445 run_srom_read(sc, RT2860_EEPROM_MAC45, &val); 1446 ic->ic_myaddr[4] = val & 0xff; 1447 ic->ic_myaddr[5] = val >> 8; 1448 1449 if (sc->mac_ver < 0x3593) { 1450 /* read vendor BBP settings */ 1451 for (i = 0; i < 10; i++) { 1452 run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); 1453 sc->bbp[i].val = val & 0xff; 1454 sc->bbp[i].reg = val >> 8; 1455 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, 1456 sc->bbp[i].val)); 1457 } 1458 if (sc->mac_ver >= 0x3071) { 1459 /* read vendor RF settings */ 1460 for (i = 0; i < 10; i++) { 1461 run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, 1462 &val); 1463 sc->rf[i].val = val & 0xff; 1464 sc->rf[i].reg = val >> 8; 1465 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 1466 sc->rf[i].val)); 1467 } 1468 } 1469 } 1470 1471 /* read RF frequency offset from EEPROM */ 1472 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1473 RT3593_EEPROM_FREQ, &val); 1474 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 1475 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 1476 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1477 RT3593_EEPROM_FREQ_LEDS, &val); 1478 if ((val >> 8) != 0xff) { 1479 /* read LEDs operating mode */ 1480 sc->leds = val >> 8; 1481 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED1 : 1482 RT3593_EEPROM_LED1, &sc->led[0]); 1483 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED2 : 1484 RT3593_EEPROM_LED2, &sc->led[1]); 1485 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED3 : 1486 RT3593_EEPROM_LED3, &sc->led[2]); 1487 } else { 1488 /* broken EEPROM, use default settings */ 1489 sc->leds = 0x01; 1490 sc->led[0] = 0x5555; 1491 sc->led[1] = 0x2221; 1492 sc->led[2] = 0x5627; /* differs from RT2860 */ 1493 } 1494 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 1495 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 1496 1497 /* read RF information */ 1498 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) 1499 run_srom_read(sc, 0x00, &val); 1500 else 1501 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1502 if (val == 0xffff) { 1503 DPRINTF(("invalid EEPROM antenna info, using default\n")); 1504 if (sc->mac_ver == 0x3572) { 1505 /* default to RF3052 2T2R */ 1506 sc->rf_rev = RT3070_RF_3052; 1507 sc->ntxchains = 2; 1508 sc->nrxchains = 2; 1509 } else if (sc->mac_ver >= 0x3070) { 1510 /* default to RF3020 1T1R */ 1511 sc->rf_rev = RT3070_RF_3020; 1512 sc->ntxchains = 1; 1513 sc->nrxchains = 1; 1514 } else { 1515 /* default to RF2820 1T2R */ 1516 sc->rf_rev = RT2860_RF_2820; 1517 sc->ntxchains = 1; 1518 sc->nrxchains = 2; 1519 } 1520 } else { 1521 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) { 1522 sc->rf_rev = val; 1523 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1524 } else 1525 sc->rf_rev = (val >> 8) & 0xf; 1526 sc->ntxchains = (val >> 4) & 0xf; 1527 sc->nrxchains = val & 0xf; 1528 } 1529 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 1530 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 1531 1532 /* check if RF supports automatic Tx access gain control */ 1533 run_srom_read(sc, RT2860_EEPROM_CONFIG, &val); 1534 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 1535 /* check if driver should patch the DAC issue */ 1536 if ((val >> 8) != 0xff) 1537 sc->patch_dac = (val >> 15) & 1; 1538 if ((val & 0xff) != 0xff) { 1539 sc->ext_5ghz_lna = (val >> 3) & 1; 1540 sc->ext_2ghz_lna = (val >> 2) & 1; 1541 /* check if RF supports automatic Tx access gain control */ 1542 sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; 1543 /* check if we have a hardware radio switch */ 1544 sc->rfswitch = val & 1; 1545 } 1546 1547 /* Read Tx power settings. */ 1548 if (sc->mac_ver == 0x3593) 1549 run_rt3593_get_txpower(sc); 1550 else 1551 run_get_txpower(sc); 1552 1553 /* read Tx power compensation for each Tx rate */ 1554 run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); 1555 delta_2ghz = delta_5ghz = 0; 1556 if ((val & 0xff) != 0xff && (val & 0x80)) { 1557 delta_2ghz = val & 0xf; 1558 if (!(val & 0x40)) /* negative number */ 1559 delta_2ghz = -delta_2ghz; 1560 } 1561 val >>= 8; 1562 if ((val & 0xff) != 0xff && (val & 0x80)) { 1563 delta_5ghz = val & 0xf; 1564 if (!(val & 0x40)) /* negative number */ 1565 delta_5ghz = -delta_5ghz; 1566 } 1567 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 1568 delta_2ghz, delta_5ghz)); 1569 1570 for (ridx = 0; ridx < 5; ridx++) { 1571 uint32_t reg; 1572 1573 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val); 1574 reg = val; 1575 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val); 1576 reg |= (uint32_t)val << 16; 1577 1578 sc->txpow20mhz[ridx] = reg; 1579 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 1580 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 1581 1582 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 1583 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 1584 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 1585 } 1586 1587 /* read RSSI offsets and LNA gains from EEPROM */ 1588 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_2GHZ : 1589 RT3593_EEPROM_RSSI1_2GHZ, &val); 1590 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 1591 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 1592 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_2GHZ : 1593 RT3593_EEPROM_RSSI2_2GHZ, &val); 1594 if (sc->mac_ver >= 0x3070) { 1595 if (sc->mac_ver == 0x3593) { 1596 sc->txmixgain_2ghz = 0; 1597 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1598 } else { 1599 /* 1600 * On RT3070 chips (limited to 2 Rx chains), this ROM 1601 * field contains the Tx mixer gain for the 2GHz band. 1602 */ 1603 if ((val & 0xff) != 0xff) 1604 sc->txmixgain_2ghz = val & 0x7; 1605 } 1606 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 1607 } else 1608 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1609 if (sc->mac_ver == 0x3593) 1610 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1611 sc->lna[2] = val >> 8; /* channel group 2 */ 1612 1613 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : 1614 RT3593_EEPROM_RSSI1_5GHZ, &val); 1615 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 1616 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 1617 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : 1618 RT3593_EEPROM_RSSI2_5GHZ, &val); 1619 if (sc->mac_ver == 0x3572) { 1620 /* 1621 * On RT3572 chips (limited to 2 Rx chains), this ROM 1622 * field contains the Tx mixer gain for the 5GHz band. 1623 */ 1624 if ((val & 0xff) != 0xff) 1625 sc->txmixgain_5ghz = val & 0x7; 1626 DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz)); 1627 } else 1628 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 1629 if (sc->mac_ver == 0x3593) { 1630 sc->txmixgain_5ghz = 0; 1631 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1632 } 1633 sc->lna[3] = val >> 8; /* channel group 3 */ 1634 1635 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : 1636 RT3593_EEPROM_LNA, &val); 1637 sc->lna[0] = val & 0xff; /* channel group 0 */ 1638 sc->lna[1] = val >> 8; /* channel group 1 */ 1639 1640 /* fix broken 5GHz LNA entries */ 1641 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 1642 DPRINTF(("invalid LNA for channel group %d\n", 2)); 1643 sc->lna[2] = sc->lna[1]; 1644 } 1645 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 1646 DPRINTF(("invalid LNA for channel group %d\n", 3)); 1647 sc->lna[3] = sc->lna[1]; 1648 } 1649 1650 /* fix broken RSSI offset entries */ 1651 for (ant = 0; ant < 3; ant++) { 1652 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 1653 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 1654 ant + 1, sc->rssi_2ghz[ant])); 1655 sc->rssi_2ghz[ant] = 0; 1656 } 1657 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 1658 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 1659 ant + 1, sc->rssi_5ghz[ant])); 1660 sc->rssi_5ghz[ant] = 0; 1661 } 1662 } 1663 return 0; 1664 } 1665 1666 struct ieee80211_node * 1667 run_node_alloc(struct ieee80211com *ic) 1668 { 1669 return malloc(sizeof (struct run_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1670 } 1671 1672 int 1673 run_media_change(struct ifnet *ifp) 1674 { 1675 struct run_softc *sc = ifp->if_softc; 1676 struct ieee80211com *ic = &sc->sc_ic; 1677 uint8_t rate, ridx; 1678 int error; 1679 1680 error = ieee80211_media_change(ifp); 1681 if (error != ENETRESET) 1682 return error; 1683 1684 if (ic->ic_fixed_rate != -1) { 1685 rate = ic->ic_sup_rates[ic->ic_curmode]. 1686 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1687 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 1688 if (rt2860_rates[ridx].rate == rate) 1689 break; 1690 sc->fixed_ridx = ridx; 1691 } 1692 1693 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1694 (IFF_UP | IFF_RUNNING)) { 1695 run_stop(ifp, 0); 1696 error = run_init(ifp); 1697 } 1698 1699 return error; 1700 } 1701 1702 void 1703 run_next_scan(void *arg) 1704 { 1705 struct run_softc *sc = arg; 1706 1707 if (usbd_is_dying(sc->sc_udev)) 1708 return; 1709 1710 usbd_ref_incr(sc->sc_udev); 1711 1712 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1713 ieee80211_next_scan(&sc->sc_ic.ic_if); 1714 1715 usbd_ref_decr(sc->sc_udev); 1716 } 1717 1718 void 1719 run_task(void *arg) 1720 { 1721 struct run_softc *sc = arg; 1722 struct run_host_cmd_ring *ring = &sc->cmdq; 1723 struct run_host_cmd *cmd; 1724 int s; 1725 1726 if (usbd_is_dying(sc->sc_udev)) 1727 return; 1728 1729 /* process host commands */ 1730 s = splusb(); 1731 while (ring->next != ring->cur) { 1732 cmd = &ring->cmd[ring->next]; 1733 splx(s); 1734 /* callback */ 1735 cmd->cb(sc, cmd->data); 1736 s = splusb(); 1737 ring->queued--; 1738 ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT; 1739 } 1740 splx(s); 1741 } 1742 1743 void 1744 run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), 1745 void *arg, int len) 1746 { 1747 struct run_host_cmd_ring *ring = &sc->cmdq; 1748 struct run_host_cmd *cmd; 1749 int s; 1750 1751 if (usbd_is_dying(sc->sc_udev)) 1752 return; 1753 1754 s = splusb(); 1755 cmd = &ring->cmd[ring->cur]; 1756 cmd->cb = cb; 1757 KASSERT(len <= sizeof (cmd->data)); 1758 memcpy(cmd->data, arg, len); 1759 ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT; 1760 1761 /* if there is no pending command already, schedule a task */ 1762 if (++ring->queued == 1) 1763 usb_add_task(sc->sc_udev, &sc->sc_task); 1764 splx(s); 1765 } 1766 1767 int 1768 run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1769 { 1770 struct run_softc *sc = ic->ic_softc; 1771 struct run_cmd_newstate cmd; 1772 1773 /* do it in a process context */ 1774 cmd.state = nstate; 1775 cmd.arg = arg; 1776 run_do_async(sc, run_newstate_cb, &cmd, sizeof cmd); 1777 return 0; 1778 } 1779 1780 void 1781 run_newstate_cb(struct run_softc *sc, void *arg) 1782 { 1783 struct run_cmd_newstate *cmd = arg; 1784 struct ieee80211com *ic = &sc->sc_ic; 1785 enum ieee80211_state ostate; 1786 struct ieee80211_node *ni; 1787 uint32_t tmp, sta[3]; 1788 uint8_t wcid; 1789 int s; 1790 1791 s = splnet(); 1792 ostate = ic->ic_state; 1793 1794 if (ostate == IEEE80211_S_RUN) { 1795 /* turn link LED off */ 1796 run_set_leds(sc, RT2860_LED_RADIO); 1797 } 1798 1799 switch (cmd->state) { 1800 case IEEE80211_S_INIT: 1801 if (ostate == IEEE80211_S_RUN) { 1802 /* abort TSF synchronization */ 1803 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 1804 run_write(sc, RT2860_BCN_TIME_CFG, 1805 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1806 RT2860_TBTT_TIMER_EN)); 1807 } 1808 break; 1809 1810 case IEEE80211_S_SCAN: 1811 run_set_chan(sc, ic->ic_bss->ni_chan); 1812 if (!usbd_is_dying(sc->sc_udev)) 1813 timeout_add_msec(&sc->scan_to, 200); 1814 break; 1815 1816 case IEEE80211_S_AUTH: 1817 case IEEE80211_S_ASSOC: 1818 run_set_chan(sc, ic->ic_bss->ni_chan); 1819 break; 1820 1821 case IEEE80211_S_RUN: 1822 run_set_chan(sc, ic->ic_bss->ni_chan); 1823 1824 ni = ic->ic_bss; 1825 1826 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1827 run_updateslot(ic); 1828 run_enable_mrr(sc); 1829 run_set_txpreamble(sc); 1830 run_set_basicrates(sc); 1831 run_set_bssid(sc, ni->ni_bssid); 1832 } 1833 if (ic->ic_opmode == IEEE80211_M_STA) { 1834 /* add BSS entry to the WCID table */ 1835 wcid = RUN_AID2WCID(ni->ni_associd); 1836 run_write_region_1(sc, RT2860_WCID_ENTRY(wcid), 1837 ni->ni_macaddr, IEEE80211_ADDR_LEN); 1838 1839 /* fake a join to init the tx rate */ 1840 run_newassoc(ic, ni, 1); 1841 } 1842 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1843 run_enable_tsf_sync(sc); 1844 1845 /* clear statistic registers used by AMRR */ 1846 run_read_region_1(sc, RT2860_TX_STA_CNT0, 1847 (uint8_t *)sta, sizeof sta); 1848 /* start calibration timer */ 1849 if (!usbd_is_dying(sc->sc_udev)) 1850 timeout_add_sec(&sc->calib_to, 1); 1851 } 1852 1853 /* turn link LED on */ 1854 run_set_leds(sc, RT2860_LED_RADIO | 1855 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ? 1856 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1857 break; 1858 } 1859 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 1860 splx(s); 1861 } 1862 1863 void 1864 run_updateedca(struct ieee80211com *ic) 1865 { 1866 /* do it in a process context */ 1867 run_do_async(ic->ic_softc, run_updateedca_cb, NULL, 0); 1868 } 1869 1870 /* ARGSUSED */ 1871 void 1872 run_updateedca_cb(struct run_softc *sc, void *arg) 1873 { 1874 struct ieee80211com *ic = &sc->sc_ic; 1875 int s, aci; 1876 1877 s = splnet(); 1878 /* update MAC TX configuration registers */ 1879 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 1880 run_write(sc, RT2860_EDCA_AC_CFG(aci), 1881 ic->ic_edca_ac[aci].ac_ecwmax << 16 | 1882 ic->ic_edca_ac[aci].ac_ecwmin << 12 | 1883 ic->ic_edca_ac[aci].ac_aifsn << 8 | 1884 ic->ic_edca_ac[aci].ac_txoplimit); 1885 } 1886 1887 /* update SCH/DMA registers too */ 1888 run_write(sc, RT2860_WMM_AIFSN_CFG, 1889 ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | 1890 ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | 1891 ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 | 1892 ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn); 1893 run_write(sc, RT2860_WMM_CWMIN_CFG, 1894 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | 1895 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | 1896 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 | 1897 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin); 1898 run_write(sc, RT2860_WMM_CWMAX_CFG, 1899 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | 1900 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | 1901 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 | 1902 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax); 1903 run_write(sc, RT2860_WMM_TXOP0_CFG, 1904 ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | 1905 ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit); 1906 run_write(sc, RT2860_WMM_TXOP1_CFG, 1907 ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | 1908 ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit); 1909 splx(s); 1910 } 1911 1912 int 1913 run_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1914 struct ieee80211_key *k) 1915 { 1916 struct run_softc *sc = ic->ic_softc; 1917 struct run_cmd_key cmd; 1918 1919 /* defer setting of WEP keys until interface is brought up */ 1920 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1921 (IFF_UP | IFF_RUNNING)) 1922 return 0; 1923 1924 /* do it in a process context */ 1925 cmd.key = *k; 1926 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 1927 run_do_async(sc, run_set_key_cb, &cmd, sizeof cmd); 1928 return 0; 1929 } 1930 1931 void 1932 run_set_key_cb(struct run_softc *sc, void *arg) 1933 { 1934 struct run_cmd_key *cmd = arg; 1935 struct ieee80211_key *k = &cmd->key; 1936 uint32_t attr; 1937 uint16_t base; 1938 uint8_t mode, wcid, iv[8]; 1939 1940 /* map net80211 cipher to RT2860 security mode */ 1941 switch (k->k_cipher) { 1942 case IEEE80211_CIPHER_WEP40: 1943 mode = RT2860_MODE_WEP40; 1944 break; 1945 case IEEE80211_CIPHER_WEP104: 1946 mode = RT2860_MODE_WEP104; 1947 break; 1948 case IEEE80211_CIPHER_TKIP: 1949 mode = RT2860_MODE_TKIP; 1950 break; 1951 case IEEE80211_CIPHER_CCMP: 1952 mode = RT2860_MODE_AES_CCMP; 1953 break; 1954 default: 1955 return; 1956 } 1957 1958 if (k->k_flags & IEEE80211_KEY_GROUP) { 1959 wcid = 0; /* NB: update WCID0 for group keys */ 1960 base = RT2860_SKEY(0, k->k_id); 1961 } else { 1962 wcid = RUN_AID2WCID(cmd->associd); 1963 base = RT2860_PKEY(wcid); 1964 } 1965 1966 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 1967 run_write_region_1(sc, base, k->k_key, 16); 1968 run_write_region_1(sc, base + 16, &k->k_key[24], 8); 1969 run_write_region_1(sc, base + 24, &k->k_key[16], 8); 1970 } else { 1971 /* roundup len to 16-bit: XXX fix write_region_1() instead */ 1972 run_write_region_1(sc, base, k->k_key, (k->k_len + 1) & ~1); 1973 } 1974 1975 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 1976 (k->k_flags & IEEE80211_KEY_TX)) { 1977 /* set initial packet number in IV+EIV */ 1978 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 1979 k->k_cipher == IEEE80211_CIPHER_WEP104) { 1980 memset(iv, 0, sizeof iv); 1981 iv[3] = sc->sc_ic.ic_def_txkey << 6; 1982 } else { 1983 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 1984 iv[0] = k->k_tsc >> 8; 1985 iv[1] = (iv[0] | 0x20) & 0x7f; 1986 iv[2] = k->k_tsc; 1987 } else /* CCMP */ { 1988 iv[0] = k->k_tsc; 1989 iv[1] = k->k_tsc >> 8; 1990 iv[2] = 0; 1991 } 1992 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 1993 iv[4] = k->k_tsc >> 16; 1994 iv[5] = k->k_tsc >> 24; 1995 iv[6] = k->k_tsc >> 32; 1996 iv[7] = k->k_tsc >> 40; 1997 } 1998 run_write_region_1(sc, RT2860_IVEIV(wcid), iv, 8); 1999 } 2000 2001 if (k->k_flags & IEEE80211_KEY_GROUP) { 2002 /* install group key */ 2003 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2004 attr &= ~(0xf << (k->k_id * 4)); 2005 attr |= mode << (k->k_id * 4); 2006 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2007 } else { 2008 /* install pairwise key */ 2009 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2010 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2011 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2012 } 2013 } 2014 2015 void 2016 run_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2017 struct ieee80211_key *k) 2018 { 2019 struct run_softc *sc = ic->ic_softc; 2020 struct run_cmd_key cmd; 2021 2022 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 2023 ic->ic_state != IEEE80211_S_RUN) 2024 return; /* nothing to do */ 2025 2026 /* do it in a process context */ 2027 cmd.key = *k; 2028 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2029 run_do_async(sc, run_delete_key_cb, &cmd, sizeof cmd); 2030 } 2031 2032 void 2033 run_delete_key_cb(struct run_softc *sc, void *arg) 2034 { 2035 struct run_cmd_key *cmd = arg; 2036 struct ieee80211_key *k = &cmd->key; 2037 uint32_t attr; 2038 uint8_t wcid; 2039 2040 if (k->k_flags & IEEE80211_KEY_GROUP) { 2041 /* remove group key */ 2042 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2043 attr &= ~(0xf << (k->k_id * 4)); 2044 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2045 2046 } else { 2047 /* remove pairwise key */ 2048 wcid = RUN_AID2WCID(cmd->associd); 2049 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2050 attr &= ~0xf; 2051 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2052 } 2053 } 2054 2055 void 2056 run_calibrate_to(void *arg) 2057 { 2058 /* do it in a process context */ 2059 run_do_async(arg, run_calibrate_cb, NULL, 0); 2060 /* next timeout will be rescheduled in the calibration task */ 2061 } 2062 2063 /* ARGSUSED */ 2064 void 2065 run_calibrate_cb(struct run_softc *sc, void *arg) 2066 { 2067 struct ifnet *ifp = &sc->sc_ic.ic_if; 2068 uint32_t sta[3]; 2069 int s, error; 2070 2071 /* read statistic counters (clear on read) and update AMRR state */ 2072 error = run_read_region_1(sc, RT2860_TX_STA_CNT0, (uint8_t *)sta, 2073 sizeof sta); 2074 if (error != 0) 2075 goto skip; 2076 2077 DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n", 2078 letoh32(sta[1]) >> 16, letoh32(sta[1]) & 0xffff, 2079 letoh32(sta[0]) & 0xffff)); 2080 2081 s = splnet(); 2082 /* count failed TX as errors */ 2083 ifp->if_oerrors += letoh32(sta[0]) & 0xffff; 2084 2085 sc->amn.amn_retrycnt = 2086 (letoh32(sta[0]) & 0xffff) + /* failed TX count */ 2087 (letoh32(sta[1]) >> 16); /* TX retransmission count */ 2088 2089 sc->amn.amn_txcnt = 2090 sc->amn.amn_retrycnt + 2091 (letoh32(sta[1]) & 0xffff); /* successful TX count */ 2092 2093 ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); 2094 splx(s); 2095 2096 skip: 2097 if (!usbd_is_dying(sc->sc_udev)) 2098 timeout_add_sec(&sc->calib_to, 1); 2099 } 2100 2101 void 2102 run_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 2103 { 2104 struct run_softc *sc = ic->ic_softc; 2105 struct run_node *rn = (void *)ni; 2106 struct ieee80211_rateset *rs = &ni->ni_rates; 2107 uint8_t rate; 2108 int ridx, i, j; 2109 2110 DPRINTF(("new assoc isnew=%d addr=%s\n", 2111 isnew, ether_sprintf(ni->ni_macaddr))); 2112 2113 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2114 /* start at lowest available bit-rate, AMRR will raise */ 2115 ni->ni_txrate = 0; 2116 2117 for (i = 0; i < rs->rs_nrates; i++) { 2118 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2119 /* convert 802.11 rate to hardware rate index */ 2120 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 2121 if (rt2860_rates[ridx].rate == rate) 2122 break; 2123 rn->ridx[i] = ridx; 2124 /* determine rate of control response frames */ 2125 for (j = i; j >= 0; j--) { 2126 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 2127 rt2860_rates[rn->ridx[i]].phy == 2128 rt2860_rates[rn->ridx[j]].phy) 2129 break; 2130 } 2131 if (j >= 0) { 2132 rn->ctl_ridx[i] = rn->ridx[j]; 2133 } else { 2134 /* no basic rate found, use mandatory one */ 2135 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 2136 } 2137 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 2138 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 2139 } 2140 } 2141 2142 /* 2143 * Return the Rx chain with the highest RSSI for a given frame. 2144 */ 2145 static __inline uint8_t 2146 run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi) 2147 { 2148 uint8_t rxchain = 0; 2149 2150 if (sc->nrxchains > 1) { 2151 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 2152 rxchain = 1; 2153 if (sc->nrxchains > 2) 2154 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 2155 rxchain = 2; 2156 } 2157 return rxchain; 2158 } 2159 2160 void 2161 run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen) 2162 { 2163 struct ieee80211com *ic = &sc->sc_ic; 2164 struct ifnet *ifp = &ic->ic_if; 2165 struct ieee80211_frame *wh; 2166 struct ieee80211_rxinfo rxi; 2167 struct ieee80211_node *ni; 2168 struct rt2870_rxd *rxd; 2169 struct rt2860_rxwi *rxwi; 2170 struct mbuf *m; 2171 uint32_t flags; 2172 uint16_t len; 2173 #if NBPFILTER > 0 2174 uint16_t phy; 2175 #endif 2176 uint16_t rxwisize; 2177 uint8_t ant, rssi; 2178 int s; 2179 2180 rxwi = (struct rt2860_rxwi *)buf; 2181 rxwisize = sizeof(struct rt2860_rxwi); 2182 if (sc->mac_ver == 0x5592) 2183 rxwisize += sizeof(uint64_t); 2184 else if (sc->mac_ver == 0x3593) 2185 rxwisize += sizeof(uint32_t); 2186 len = letoh16(rxwi->len) & 0xfff; 2187 if (__predict_false(len > dmalen)) { 2188 DPRINTF(("bad RXWI length %u > %u\n", len, dmalen)); 2189 return; 2190 } 2191 if (len > MCLBYTES) { 2192 DPRINTF(("frame too large (length=%d)\n", len)); 2193 ifp->if_ierrors++; 2194 return; 2195 } 2196 /* Rx descriptor is located at the end */ 2197 rxd = (struct rt2870_rxd *)(buf + dmalen); 2198 flags = letoh32(rxd->flags); 2199 2200 if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 2201 ifp->if_ierrors++; 2202 return; 2203 } 2204 2205 if (__predict_false((flags & RT2860_RX_MICERR))) { 2206 /* report MIC failures to net80211 for TKIP */ 2207 ic->ic_stats.is_rx_locmicfail++; 2208 ieee80211_michael_mic_failure(ic, 0/* XXX */); 2209 ifp->if_ierrors++; 2210 return; 2211 } 2212 2213 wh = (struct ieee80211_frame *)(buf + rxwisize); 2214 rxi.rxi_flags = 0; 2215 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2216 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 2217 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 2218 } 2219 2220 if (flags & RT2860_RX_L2PAD) { 2221 u_int hdrlen = ieee80211_get_hdrlen(wh); 2222 memmove((caddr_t)wh + 2, wh, hdrlen); 2223 wh = (struct ieee80211_frame *)((caddr_t)wh + 2); 2224 } 2225 2226 /* could use m_devget but net80211 wants contig mgmt frames */ 2227 MGETHDR(m, M_DONTWAIT, MT_DATA); 2228 if (__predict_false(m == NULL)) { 2229 ifp->if_ierrors++; 2230 return; 2231 } 2232 if (len > MHLEN) { 2233 MCLGET(m, M_DONTWAIT); 2234 if (__predict_false(!(m->m_flags & M_EXT))) { 2235 ifp->if_ierrors++; 2236 m_freem(m); 2237 return; 2238 } 2239 } 2240 /* finalize mbuf */ 2241 memcpy(mtod(m, caddr_t), wh, len); 2242 m->m_pkthdr.len = m->m_len = len; 2243 2244 ant = run_maxrssi_chain(sc, rxwi); 2245 rssi = rxwi->rssi[ant]; 2246 2247 #if NBPFILTER > 0 2248 if (__predict_false(sc->sc_drvbpf != NULL)) { 2249 struct run_rx_radiotap_header *tap = &sc->sc_rxtap; 2250 struct mbuf mb; 2251 2252 tap->wr_flags = 0; 2253 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 2254 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 2255 tap->wr_antsignal = rssi; 2256 tap->wr_antenna = ant; 2257 tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); 2258 tap->wr_rate = 2; /* in case it can't be found below */ 2259 phy = letoh16(rxwi->phy); 2260 switch (phy & RT2860_PHY_MODE) { 2261 case RT2860_PHY_CCK: 2262 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 2263 case 0: tap->wr_rate = 2; break; 2264 case 1: tap->wr_rate = 4; break; 2265 case 2: tap->wr_rate = 11; break; 2266 case 3: tap->wr_rate = 22; break; 2267 } 2268 if (phy & RT2860_PHY_SHPRE) 2269 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2270 break; 2271 case RT2860_PHY_OFDM: 2272 switch (phy & RT2860_PHY_MCS) { 2273 case 0: tap->wr_rate = 12; break; 2274 case 1: tap->wr_rate = 18; break; 2275 case 2: tap->wr_rate = 24; break; 2276 case 3: tap->wr_rate = 36; break; 2277 case 4: tap->wr_rate = 48; break; 2278 case 5: tap->wr_rate = 72; break; 2279 case 6: tap->wr_rate = 96; break; 2280 case 7: tap->wr_rate = 108; break; 2281 } 2282 break; 2283 } 2284 mb.m_data = (caddr_t)tap; 2285 mb.m_len = sc->sc_rxtap_len; 2286 mb.m_next = m; 2287 mb.m_nextpkt = NULL; 2288 mb.m_type = 0; 2289 mb.m_flags = 0; 2290 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 2291 } 2292 #endif 2293 2294 s = splnet(); 2295 ni = ieee80211_find_rxnode(ic, wh); 2296 rxi.rxi_rssi = rssi; 2297 rxi.rxi_tstamp = 0; /* unused */ 2298 ieee80211_input(ifp, m, ni, &rxi); 2299 2300 /* node is no longer needed */ 2301 ieee80211_release_node(ic, ni); 2302 splx(s); 2303 } 2304 2305 void 2306 run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2307 { 2308 struct run_rx_data *data = priv; 2309 struct run_softc *sc = data->sc; 2310 uint8_t *buf; 2311 uint32_t dmalen; 2312 int xferlen; 2313 uint16_t rxwisize; 2314 2315 rxwisize = sizeof(struct rt2860_rxwi); 2316 if (sc->mac_ver == 0x5592) 2317 rxwisize += sizeof(uint64_t); 2318 else if (sc->mac_ver == 0x3593) 2319 rxwisize += sizeof(uint32_t); 2320 2321 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2322 DPRINTF(("RX status=%d\n", status)); 2323 if (status == USBD_STALLED) 2324 usbd_clear_endpoint_stall_async(sc->rxq.pipeh); 2325 if (status != USBD_CANCELLED) 2326 goto skip; 2327 return; 2328 } 2329 usbd_get_xfer_status(xfer, NULL, NULL, &xferlen, NULL); 2330 2331 if (__predict_false(xferlen < sizeof (uint32_t) + rxwisize + 2332 sizeof(struct rt2870_rxd))) { 2333 DPRINTF(("xfer too short %d\n", xferlen)); 2334 goto skip; 2335 } 2336 2337 /* HW can aggregate multiple 802.11 frames in a single USB xfer */ 2338 buf = data->buf; 2339 while (xferlen > 8) { 2340 dmalen = letoh32(*(uint32_t *)buf) & 0xffff; 2341 2342 if (__predict_false(dmalen == 0 || (dmalen & 3) != 0)) { 2343 DPRINTF(("bad DMA length %u\n", dmalen)); 2344 break; 2345 } 2346 if (__predict_false(dmalen + 8 > xferlen)) { 2347 DPRINTF(("bad DMA length %u > %d\n", 2348 dmalen + 8, xferlen)); 2349 break; 2350 } 2351 run_rx_frame(sc, buf + sizeof (uint32_t), dmalen); 2352 buf += dmalen + 8; 2353 xferlen -= dmalen + 8; 2354 } 2355 2356 skip: /* setup a new transfer */ 2357 usbd_setup_xfer(xfer, sc->rxq.pipeh, data, data->buf, RUN_MAX_RXSZ, 2358 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, run_rxeof); 2359 (void)usbd_transfer(data->xfer); 2360 } 2361 2362 void 2363 run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2364 { 2365 struct run_tx_data *data = priv; 2366 struct run_softc *sc = data->sc; 2367 struct run_tx_ring *txq = &sc->txq[data->qid]; 2368 struct ifnet *ifp = &sc->sc_ic.ic_if; 2369 int s; 2370 2371 s = splnet(); 2372 txq->queued--; 2373 sc->qfullmsk &= ~(1 << data->qid); 2374 2375 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2376 DPRINTF(("TX status=%d\n", status)); 2377 if (status == USBD_STALLED) 2378 usbd_clear_endpoint_stall_async(txq->pipeh); 2379 ifp->if_oerrors++; 2380 splx(s); 2381 return; 2382 } 2383 2384 sc->sc_tx_timer = 0; 2385 ifq_clr_oactive(&ifp->if_snd); 2386 run_start(ifp); 2387 splx(s); 2388 } 2389 2390 int 2391 run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2392 { 2393 struct ieee80211com *ic = &sc->sc_ic; 2394 struct run_node *rn = (void *)ni; 2395 struct ieee80211_frame *wh; 2396 struct run_tx_ring *ring; 2397 struct run_tx_data *data; 2398 struct rt2870_txd *txd; 2399 struct rt2860_txwi *txwi; 2400 uint16_t qos, dur; 2401 uint16_t txwisize; 2402 uint8_t type, mcs, tid, qid; 2403 int error, hasqos, ridx, ctl_ridx, xferlen; 2404 2405 wh = mtod(m, struct ieee80211_frame *); 2406 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2407 2408 if ((hasqos = ieee80211_has_qos(wh))) { 2409 qos = ieee80211_get_qos(wh); 2410 tid = qos & IEEE80211_QOS_TID; 2411 qid = ieee80211_up_to_ac(ic, tid); 2412 } else { 2413 qos = 0; 2414 tid = 0; 2415 qid = EDCA_AC_BE; 2416 } 2417 ring = &sc->txq[qid]; 2418 data = &ring->data[ring->cur]; 2419 2420 /* pickup a rate index */ 2421 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2422 type != IEEE80211_FC0_TYPE_DATA) { 2423 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2424 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 2425 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2426 } else if (ic->ic_fixed_rate != -1) { 2427 ridx = sc->fixed_ridx; 2428 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2429 } else { 2430 ridx = rn->ridx[ni->ni_txrate]; 2431 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 2432 } 2433 2434 /* get MCS code from rate index */ 2435 mcs = rt2860_rates[ridx].mcs; 2436 2437 txwisize = sizeof(struct rt2860_txwi); 2438 if (sc->mac_ver == 0x5592) 2439 txwisize += sizeof(uint32_t); 2440 xferlen = txwisize + m->m_pkthdr.len; 2441 2442 /* roundup to 32-bit alignment */ 2443 xferlen = (xferlen + 3) & ~3; 2444 2445 txd = (struct rt2870_txd *)data->buf; 2446 txd->flags = RT2860_TX_QSEL_EDCA; 2447 txd->len = htole16(xferlen); 2448 2449 /* setup TX Wireless Information */ 2450 txwi = (struct rt2860_txwi *)(txd + 1); 2451 txwi->flags = 0; 2452 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 2453 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? 2454 RUN_AID2WCID(ni->ni_associd) : 0xff; 2455 txwi->len = htole16(m->m_pkthdr.len); 2456 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 2457 txwi->phy = htole16(RT2860_PHY_CCK); 2458 if (ridx != RT2860_RIDX_CCK1 && 2459 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 2460 mcs |= RT2860_PHY_SHPRE; 2461 } else 2462 txwi->phy = htole16(RT2860_PHY_OFDM); 2463 txwi->phy |= htole16(mcs); 2464 2465 txwi->txop = RT2860_TX_TXOP_BACKOFF; 2466 2467 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2468 (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 2469 IEEE80211_QOS_ACK_POLICY_NOACK)) { 2470 txwi->xflags |= RT2860_TX_ACK; 2471 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2472 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 2473 else 2474 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 2475 *(uint16_t *)wh->i_dur = htole16(dur); 2476 } 2477 2478 #if NBPFILTER > 0 2479 if (__predict_false(sc->sc_drvbpf != NULL)) { 2480 struct run_tx_radiotap_header *tap = &sc->sc_txtap; 2481 struct mbuf mb; 2482 2483 tap->wt_flags = 0; 2484 tap->wt_rate = rt2860_rates[ridx].rate; 2485 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2486 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2487 tap->wt_hwqueue = qid; 2488 if (mcs & RT2860_PHY_SHPRE) 2489 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2490 2491 mb.m_data = (caddr_t)tap; 2492 mb.m_len = sc->sc_txtap_len; 2493 mb.m_next = m; 2494 mb.m_nextpkt = NULL; 2495 mb.m_type = 0; 2496 mb.m_flags = 0; 2497 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 2498 } 2499 #endif 2500 2501 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)txwi + txwisize); 2502 m_freem(m); 2503 2504 xferlen += sizeof (*txd) + 4; 2505 2506 usbd_setup_xfer(data->xfer, ring->pipeh, data, data->buf, xferlen, 2507 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, RUN_TX_TIMEOUT, run_txeof); 2508 error = usbd_transfer(data->xfer); 2509 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) 2510 return error; 2511 2512 ieee80211_release_node(ic, ni); 2513 2514 ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT; 2515 if (++ring->queued >= RUN_TX_RING_COUNT) 2516 sc->qfullmsk |= 1 << qid; 2517 2518 return 0; 2519 } 2520 2521 void 2522 run_start(struct ifnet *ifp) 2523 { 2524 struct run_softc *sc = ifp->if_softc; 2525 struct ieee80211com *ic = &sc->sc_ic; 2526 struct ieee80211_node *ni; 2527 struct mbuf *m; 2528 2529 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 2530 return; 2531 2532 for (;;) { 2533 if (sc->qfullmsk != 0) { 2534 ifq_set_oactive(&ifp->if_snd); 2535 break; 2536 } 2537 /* send pending management frames first */ 2538 m = mq_dequeue(&ic->ic_mgtq); 2539 if (m != NULL) { 2540 ni = m->m_pkthdr.ph_cookie; 2541 goto sendit; 2542 } 2543 if (ic->ic_state != IEEE80211_S_RUN) 2544 break; 2545 2546 /* encapsulate and send data frames */ 2547 IFQ_DEQUEUE(&ifp->if_snd, m); 2548 if (m == NULL) 2549 break; 2550 #if NBPFILTER > 0 2551 if (ifp->if_bpf != NULL) 2552 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 2553 #endif 2554 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 2555 continue; 2556 sendit: 2557 #if NBPFILTER > 0 2558 if (ic->ic_rawbpf != NULL) 2559 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 2560 #endif 2561 if (run_tx(sc, m, ni) != 0) { 2562 ieee80211_release_node(ic, ni); 2563 ifp->if_oerrors++; 2564 continue; 2565 } 2566 2567 sc->sc_tx_timer = 5; 2568 ifp->if_timer = 1; 2569 } 2570 } 2571 2572 void 2573 run_watchdog(struct ifnet *ifp) 2574 { 2575 struct run_softc *sc = ifp->if_softc; 2576 2577 ifp->if_timer = 0; 2578 2579 if (sc->sc_tx_timer > 0) { 2580 if (--sc->sc_tx_timer == 0) { 2581 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2582 /* run_init(ifp); XXX needs a process context! */ 2583 ifp->if_oerrors++; 2584 return; 2585 } 2586 ifp->if_timer = 1; 2587 } 2588 2589 ieee80211_watchdog(ifp); 2590 } 2591 2592 int 2593 run_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2594 { 2595 struct run_softc *sc = ifp->if_softc; 2596 struct ieee80211com *ic = &sc->sc_ic; 2597 int s, error = 0; 2598 2599 if (usbd_is_dying(sc->sc_udev)) 2600 return ENXIO; 2601 2602 usbd_ref_incr(sc->sc_udev); 2603 2604 s = splnet(); 2605 2606 switch (cmd) { 2607 case SIOCSIFADDR: 2608 ifp->if_flags |= IFF_UP; 2609 /* FALLTHROUGH */ 2610 case SIOCSIFFLAGS: 2611 if (ifp->if_flags & IFF_UP) { 2612 if (!(ifp->if_flags & IFF_RUNNING)) 2613 run_init(ifp); 2614 } else { 2615 if (ifp->if_flags & IFF_RUNNING) 2616 run_stop(ifp, 1); 2617 } 2618 break; 2619 2620 case SIOCS80211CHANNEL: 2621 /* 2622 * This allows for fast channel switching in monitor mode 2623 * (used by kismet). 2624 */ 2625 error = ieee80211_ioctl(ifp, cmd, data); 2626 if (error == ENETRESET && 2627 ic->ic_opmode == IEEE80211_M_MONITOR) { 2628 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2629 (IFF_UP | IFF_RUNNING)) 2630 run_set_chan(sc, ic->ic_ibss_chan); 2631 error = 0; 2632 } 2633 break; 2634 2635 default: 2636 error = ieee80211_ioctl(ifp, cmd, data); 2637 } 2638 2639 if (error == ENETRESET) { 2640 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2641 (IFF_UP | IFF_RUNNING)) { 2642 run_stop(ifp, 0); 2643 run_init(ifp); 2644 } 2645 error = 0; 2646 } 2647 2648 splx(s); 2649 2650 usbd_ref_decr(sc->sc_udev); 2651 2652 return error; 2653 } 2654 2655 void 2656 run_iq_calib(struct run_softc *sc, u_int chan) 2657 { 2658 uint16_t val; 2659 2660 /* Tx0 IQ gain. */ 2661 run_bbp_write(sc, 158, 0x2c); 2662 if (chan <= 14) 2663 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val); 2664 else if (chan <= 64) { 2665 run_efuse_read(sc, 2666 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, &val); 2667 } else if (chan <= 138) { 2668 run_efuse_read(sc, 2669 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, &val); 2670 } else if (chan <= 165) { 2671 run_efuse_read(sc, 2672 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, 2673 &val); 2674 } else 2675 val = 0; 2676 run_bbp_write(sc, 159, val); 2677 2678 /* Tx0 IQ phase. */ 2679 run_bbp_write(sc, 158, 0x2d); 2680 if (chan <= 14) { 2681 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, &val); 2682 } else if (chan <= 64) { 2683 run_efuse_read(sc, 2684 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, &val); 2685 } else if (chan <= 138) { 2686 run_efuse_read(sc, 2687 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, &val); 2688 } else if (chan <= 165) { 2689 run_efuse_read(sc, 2690 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, &val); 2691 } else 2692 val = 0; 2693 run_bbp_write(sc, 159, val); 2694 2695 /* Tx1 IQ gain. */ 2696 run_bbp_write(sc, 158, 0x4a); 2697 if (chan <= 14) { 2698 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, &val); 2699 } else if (chan <= 64) { 2700 run_efuse_read(sc, 2701 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, &val); 2702 } else if (chan <= 138) { 2703 run_efuse_read(sc, 2704 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, &val); 2705 } else if (chan <= 165) { 2706 run_efuse_read(sc, 2707 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, &val); 2708 } else 2709 val = 0; 2710 run_bbp_write(sc, 159, val); 2711 2712 /* Tx1 IQ phase. */ 2713 run_bbp_write(sc, 158, 0x4b); 2714 if (chan <= 14) { 2715 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, &val); 2716 } else if (chan <= 64) { 2717 run_efuse_read(sc, 2718 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, &val); 2719 } else if (chan <= 138) { 2720 run_efuse_read(sc, 2721 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, &val); 2722 } else if (chan <= 165) { 2723 run_efuse_read(sc, 2724 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, &val); 2725 } else 2726 val = 0; 2727 run_bbp_write(sc, 159, val); 2728 2729 /* RF IQ compensation control. */ 2730 run_bbp_write(sc, 158, 0x04); 2731 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, &val); 2732 run_bbp_write(sc, 159, val); 2733 2734 /* RF IQ imbalance compensation control. */ 2735 run_bbp_write(sc, 158, 0x03); 2736 run_efuse_read(sc, 2737 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val); 2738 run_bbp_write(sc, 159, val); 2739 } 2740 2741 void 2742 run_select_chan_group(struct run_softc *sc, int group) 2743 { 2744 uint32_t tmp; 2745 uint8_t agc; 2746 2747 run_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2748 run_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2749 run_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2750 if (sc->mac_ver < 0x3572) 2751 run_bbp_write(sc, 86, 0x00); 2752 2753 if (sc->mac_ver == 0x3593) { 2754 run_bbp_write(sc, 77, 0x98); 2755 run_bbp_write(sc, 83, (group == 0) ? 0x8a : 0x9a); 2756 } 2757 2758 if (group == 0) { 2759 if (sc->ext_2ghz_lna) { 2760 if (sc->mac_ver >= 0x5390) 2761 run_bbp_write(sc, 75, 0x52); 2762 else { 2763 run_bbp_write(sc, 82, 0x62); 2764 run_bbp_write(sc, 75, 0x46); 2765 } 2766 } else { 2767 if (sc->mac_ver == 0x5592) { 2768 run_bbp_write(sc, 79, 0x1c); 2769 run_bbp_write(sc, 80, 0x0e); 2770 run_bbp_write(sc, 81, 0x3a); 2771 run_bbp_write(sc, 82, 0x62); 2772 2773 run_bbp_write(sc, 195, 0x80); 2774 run_bbp_write(sc, 196, 0xe0); 2775 run_bbp_write(sc, 195, 0x81); 2776 run_bbp_write(sc, 196, 0x1f); 2777 run_bbp_write(sc, 195, 0x82); 2778 run_bbp_write(sc, 196, 0x38); 2779 run_bbp_write(sc, 195, 0x83); 2780 run_bbp_write(sc, 196, 0x32); 2781 run_bbp_write(sc, 195, 0x85); 2782 run_bbp_write(sc, 196, 0x28); 2783 run_bbp_write(sc, 195, 0x86); 2784 run_bbp_write(sc, 196, 0x19); 2785 } else if (sc->mac_ver >= 0x5390) 2786 run_bbp_write(sc, 75, 0x50); 2787 else { 2788 run_bbp_write(sc, 82, 2789 (sc->mac_ver == 0x3593) ? 0x62 : 0x84); 2790 run_bbp_write(sc, 75, 0x50); 2791 } 2792 } 2793 } else { 2794 if (sc->mac_ver == 0x5592) { 2795 run_bbp_write(sc, 79, 0x18); 2796 run_bbp_write(sc, 80, 0x08); 2797 run_bbp_write(sc, 81, 0x38); 2798 run_bbp_write(sc, 82, 0x92); 2799 2800 run_bbp_write(sc, 195, 0x80); 2801 run_bbp_write(sc, 196, 0xf0); 2802 run_bbp_write(sc, 195, 0x81); 2803 run_bbp_write(sc, 196, 0x1e); 2804 run_bbp_write(sc, 195, 0x82); 2805 run_bbp_write(sc, 196, 0x28); 2806 run_bbp_write(sc, 195, 0x83); 2807 run_bbp_write(sc, 196, 0x20); 2808 run_bbp_write(sc, 195, 0x85); 2809 run_bbp_write(sc, 196, 0x7f); 2810 run_bbp_write(sc, 195, 0x86); 2811 run_bbp_write(sc, 196, 0x7f); 2812 } else if (sc->mac_ver == 0x3572) 2813 run_bbp_write(sc, 82, 0x94); 2814 else 2815 run_bbp_write(sc, 82, 2816 (sc->mac_ver == 0x3593) ? 0x82 : 0xf2); 2817 if (sc->ext_5ghz_lna) 2818 run_bbp_write(sc, 75, 0x46); 2819 else 2820 run_bbp_write(sc, 75, 0x50); 2821 } 2822 2823 run_read(sc, RT2860_TX_BAND_CFG, &tmp); 2824 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2825 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2826 run_write(sc, RT2860_TX_BAND_CFG, tmp); 2827 2828 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2829 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2830 if (sc->mac_ver == 0x3593) 2831 tmp |= 1 << 29 | 1 << 28; 2832 if (sc->nrxchains > 1) 2833 tmp |= RT2860_LNA_PE1_EN; 2834 if (group == 0) { /* 2GHz */ 2835 tmp |= RT2860_PA_PE_G0_EN; 2836 if (sc->ntxchains > 1) 2837 tmp |= RT2860_PA_PE_G1_EN; 2838 if (sc->mac_ver == 0x3593) { 2839 if (sc->ntxchains > 2) 2840 tmp |= 1 << 25; 2841 } 2842 } else { /* 5GHz */ 2843 tmp |= RT2860_PA_PE_A0_EN; 2844 if (sc->ntxchains > 1) 2845 tmp |= RT2860_PA_PE_A1_EN; 2846 } 2847 if (sc->mac_ver == 0x3572) { 2848 run_rt3070_rf_write(sc, 8, 0x00); 2849 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2850 run_rt3070_rf_write(sc, 8, 0x80); 2851 } else 2852 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2853 2854 if (sc->mac_ver == 0x5592) { 2855 run_bbp_write(sc, 195, 0x8d); 2856 run_bbp_write(sc, 196, 0x1a); 2857 } 2858 2859 if (sc->mac_ver == 0x3593) { 2860 run_read(sc, RT2860_GPIO_CTRL, &tmp); 2861 tmp &= ~0x01010000; 2862 if (group == 0) 2863 tmp |= 0x00010000; 2864 tmp = (tmp & ~0x00009090) | 0x00000090; 2865 run_write(sc, RT2860_GPIO_CTRL, tmp); 2866 } 2867 2868 /* set initial AGC value */ 2869 if (group == 0) { /* 2GHz band */ 2870 if (sc->mac_ver >= 0x3070) 2871 agc = 0x1c + sc->lna[0] * 2; 2872 else 2873 agc = 0x2e + sc->lna[0]; 2874 } else { /* 5GHz band */ 2875 if (sc->mac_ver == 0x5592) 2876 agc = 0x24 + sc->lna[group] * 2; 2877 else if (sc->mac_ver == 0x3572 || sc->mac_ver == 0x3593) 2878 agc = 0x22 + (sc->lna[group] * 5) / 3; 2879 else 2880 agc = 0x32 + (sc->lna[group] * 5) / 3; 2881 } 2882 run_set_agc(sc, agc); 2883 } 2884 2885 void 2886 run_rt2870_set_chan(struct run_softc *sc, u_int chan) 2887 { 2888 const struct rfprog *rfprog = rt2860_rf2850; 2889 uint32_t r2, r3, r4; 2890 int8_t txpow1, txpow2; 2891 int i; 2892 2893 /* find the settings for this channel (we know it exists) */ 2894 for (i = 0; rfprog[i].chan != chan; i++); 2895 2896 r2 = rfprog[i].r2; 2897 if (sc->ntxchains == 1) 2898 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2899 if (sc->nrxchains == 1) 2900 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2901 else if (sc->nrxchains == 2) 2902 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2903 2904 /* use Tx power values from EEPROM */ 2905 txpow1 = sc->txpow1[i]; 2906 txpow2 = sc->txpow2[i]; 2907 if (chan > 14) { 2908 if (txpow1 >= 0) 2909 txpow1 = txpow1 << 1 | 1; 2910 else 2911 txpow1 = (7 + txpow1) << 1; 2912 if (txpow2 >= 0) 2913 txpow2 = txpow2 << 1 | 1; 2914 else 2915 txpow2 = (7 + txpow2) << 1; 2916 } 2917 r3 = rfprog[i].r3 | txpow1 << 7; 2918 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2919 2920 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2921 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2922 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2923 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2924 2925 DELAY(200); 2926 2927 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2928 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2929 run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1); 2930 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2931 2932 DELAY(200); 2933 2934 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2935 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2936 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2937 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2938 } 2939 2940 void 2941 run_rt3070_set_chan(struct run_softc *sc, u_int chan) 2942 { 2943 int8_t txpow1, txpow2; 2944 uint8_t rf; 2945 int i; 2946 2947 /* find the settings for this channel (we know it exists) */ 2948 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2949 2950 /* use Tx power values from EEPROM */ 2951 txpow1 = sc->txpow1[i]; 2952 txpow2 = sc->txpow2[i]; 2953 2954 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2955 2956 /* RT3370/RT3390: RF R3 [7:4] is not reserved bits. */ 2957 run_rt3070_rf_read(sc, 3, &rf); 2958 rf = (rf & ~0x0f) | rt3070_freqs[i].k; 2959 run_rt3070_rf_write(sc, 3, rf); 2960 2961 run_rt3070_rf_read(sc, 6, &rf); 2962 rf = (rf & ~0x03) | rt3070_freqs[i].r; 2963 run_rt3070_rf_write(sc, 6, rf); 2964 2965 /* set Tx0 power */ 2966 run_rt3070_rf_read(sc, 12, &rf); 2967 rf = (rf & ~0x1f) | txpow1; 2968 run_rt3070_rf_write(sc, 12, rf); 2969 2970 /* set Tx1 power */ 2971 run_rt3070_rf_read(sc, 13, &rf); 2972 rf = (rf & ~0x1f) | txpow2; 2973 run_rt3070_rf_write(sc, 13, rf); 2974 2975 run_rt3070_rf_read(sc, 1, &rf); 2976 rf &= ~0xfc; 2977 if (sc->ntxchains == 1) 2978 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 2979 else if (sc->ntxchains == 2) 2980 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 2981 if (sc->nrxchains == 1) 2982 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2983 else if (sc->nrxchains == 2) 2984 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 2985 run_rt3070_rf_write(sc, 1, rf); 2986 2987 /* set RF offset */ 2988 run_rt3070_rf_read(sc, 23, &rf); 2989 rf = (rf & ~0x7f) | sc->freq; 2990 run_rt3070_rf_write(sc, 23, rf); 2991 2992 /* program RF filter */ 2993 run_rt3070_rf_read(sc, 24, &rf); /* Tx */ 2994 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2995 run_rt3070_rf_write(sc, 24, rf); 2996 run_rt3070_rf_read(sc, 31, &rf); /* Rx */ 2997 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2998 run_rt3070_rf_write(sc, 31, rf); 2999 3000 /* enable RF tuning */ 3001 run_rt3070_rf_read(sc, 7, &rf); 3002 run_rt3070_rf_write(sc, 7, rf | 0x01); 3003 } 3004 3005 void 3006 run_rt3572_set_chan(struct run_softc *sc, u_int chan) 3007 { 3008 int8_t txpow1, txpow2; 3009 uint32_t tmp; 3010 uint8_t rf; 3011 int i; 3012 3013 /* find the settings for this channel (we know it exists) */ 3014 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3015 3016 /* use Tx power values from EEPROM */ 3017 txpow1 = sc->txpow1[i]; 3018 txpow2 = sc->txpow2[i]; 3019 3020 if (chan <= 14) { 3021 run_bbp_write(sc, 25, sc->bbp25); 3022 run_bbp_write(sc, 26, sc->bbp26); 3023 } else { 3024 /* enable IQ phase correction */ 3025 run_bbp_write(sc, 25, 0x09); 3026 run_bbp_write(sc, 26, 0xff); 3027 } 3028 3029 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 3030 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 3031 run_rt3070_rf_read(sc, 6, &rf); 3032 rf = (rf & ~0x0f) | rt3070_freqs[i].r; 3033 rf |= (chan <= 14) ? 0x08 : 0x04; 3034 run_rt3070_rf_write(sc, 6, rf); 3035 3036 /* set PLL mode */ 3037 run_rt3070_rf_read(sc, 5, &rf); 3038 rf &= ~(0x08 | 0x04); 3039 rf |= (chan <= 14) ? 0x04 : 0x08; 3040 run_rt3070_rf_write(sc, 5, rf); 3041 3042 /* set Tx power for chain 0 */ 3043 if (chan <= 14) 3044 rf = 0x60 | txpow1; 3045 else 3046 rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); 3047 run_rt3070_rf_write(sc, 12, rf); 3048 3049 /* set Tx power for chain 1 */ 3050 if (chan <= 14) 3051 rf = 0x60 | txpow2; 3052 else 3053 rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); 3054 run_rt3070_rf_write(sc, 13, rf); 3055 3056 /* set Tx/Rx streams */ 3057 run_rt3070_rf_read(sc, 1, &rf); 3058 rf &= ~0xfc; 3059 if (sc->ntxchains == 1) 3060 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 3061 else if (sc->ntxchains == 2) 3062 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 3063 if (sc->nrxchains == 1) 3064 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 3065 else if (sc->nrxchains == 2) 3066 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 3067 run_rt3070_rf_write(sc, 1, rf); 3068 3069 /* set RF offset */ 3070 run_rt3070_rf_read(sc, 23, &rf); 3071 rf = (rf & ~0x7f) | sc->freq; 3072 run_rt3070_rf_write(sc, 23, rf); 3073 3074 /* program RF filter */ 3075 rf = sc->rf24_20mhz; 3076 run_rt3070_rf_write(sc, 24, rf); /* Tx */ 3077 run_rt3070_rf_write(sc, 31, rf); /* Rx */ 3078 3079 /* enable RF tuning */ 3080 run_rt3070_rf_read(sc, 7, &rf); 3081 rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); 3082 run_rt3070_rf_write(sc, 7, rf); 3083 3084 /* TSSI */ 3085 rf = (chan <= 14) ? 0xc3 : 0xc0; 3086 run_rt3070_rf_write(sc, 9, rf); 3087 3088 /* set loop filter 1 */ 3089 run_rt3070_rf_write(sc, 10, 0xf1); 3090 /* set loop filter 2 */ 3091 run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); 3092 3093 /* set tx_mx2_ic */ 3094 run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); 3095 /* set tx_mx1_ic */ 3096 if (chan <= 14) 3097 rf = 0x48 | sc->txmixgain_2ghz; 3098 else 3099 rf = 0x78 | sc->txmixgain_5ghz; 3100 run_rt3070_rf_write(sc, 16, rf); 3101 3102 /* set tx_lo1 */ 3103 run_rt3070_rf_write(sc, 17, 0x23); 3104 /* set tx_lo2 */ 3105 if (chan <= 14) 3106 rf = 0x93; 3107 else if (chan <= 64) 3108 rf = 0xb7; 3109 else if (chan <= 128) 3110 rf = 0x74; 3111 else 3112 rf = 0x72; 3113 run_rt3070_rf_write(sc, 19, rf); 3114 3115 /* set rx_lo1 */ 3116 if (chan <= 14) 3117 rf = 0xb3; 3118 else if (chan <= 64) 3119 rf = 0xf6; 3120 else if (chan <= 128) 3121 rf = 0xf4; 3122 else 3123 rf = 0xf3; 3124 run_rt3070_rf_write(sc, 20, rf); 3125 3126 /* set pfd_delay */ 3127 if (chan <= 14) 3128 rf = 0x15; 3129 else if (chan <= 64) 3130 rf = 0x3d; 3131 else 3132 rf = 0x01; 3133 run_rt3070_rf_write(sc, 25, rf); 3134 3135 /* set rx_lo2 */ 3136 run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); 3137 /* set ldo_rf_vc */ 3138 run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); 3139 /* set drv_cc */ 3140 run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); 3141 3142 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3143 tmp &= ~0x8080; 3144 if (chan <= 14) 3145 tmp |= 0x80; 3146 run_write(sc, RT2860_GPIO_CTRL, tmp); 3147 3148 /* enable RF tuning */ 3149 run_rt3070_rf_read(sc, 7, &rf); 3150 run_rt3070_rf_write(sc, 7, rf | 0x01); 3151 3152 DELAY(2000); 3153 } 3154 3155 void 3156 run_rt3593_set_chan(struct run_softc *sc, u_int chan) 3157 { 3158 int8_t txpow1, txpow2, txpow3; 3159 uint8_t h20mhz, rf; 3160 int i; 3161 3162 /* find the settings for this channel (we know it exists) */ 3163 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3164 3165 /* use Tx power values from EEPROM */ 3166 txpow1 = sc->txpow1[i]; 3167 txpow2 = sc->txpow2[i]; 3168 txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; 3169 3170 if (chan <= 14) { 3171 run_bbp_write(sc, 25, sc->bbp25); 3172 run_bbp_write(sc, 26, sc->bbp26); 3173 } else { 3174 /* Enable IQ phase correction. */ 3175 run_bbp_write(sc, 25, 0x09); 3176 run_bbp_write(sc, 26, 0xff); 3177 } 3178 3179 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3180 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3181 run_rt3070_rf_read(sc, 11, &rf); 3182 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3183 run_rt3070_rf_write(sc, 11, rf); 3184 3185 /* Set pll_idoh. */ 3186 run_rt3070_rf_read(sc, 11, &rf); 3187 rf &= ~0x4c; 3188 rf |= (chan <= 14) ? 0x44 : 0x48; 3189 run_rt3070_rf_write(sc, 11, rf); 3190 3191 if (chan <= 14) 3192 rf = txpow1 & 0x1f; 3193 else 3194 rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); 3195 run_rt3070_rf_write(sc, 53, rf); 3196 3197 if (chan <= 14) 3198 rf = txpow2 & 0x1f; 3199 else 3200 rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); 3201 run_rt3070_rf_write(sc, 55, rf); 3202 3203 if (chan <= 14) 3204 rf = txpow3 & 0x1f; 3205 else 3206 rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); 3207 run_rt3070_rf_write(sc, 54, rf); 3208 3209 rf = RT3070_RF_BLOCK | RT3070_PLL_PD; 3210 if (sc->ntxchains == 3) 3211 rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; 3212 else 3213 rf |= RT3070_TX0_PD | RT3070_TX1_PD; 3214 rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; 3215 run_rt3070_rf_write(sc, 1, rf); 3216 3217 run_adjust_freq_offset(sc); 3218 3219 run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); 3220 3221 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 3222 run_rt3070_rf_read(sc, 30, &rf); 3223 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 3224 run_rt3070_rf_write(sc, 30, rf); 3225 3226 run_rt3070_rf_read(sc, 36, &rf); 3227 if (chan <= 14) 3228 rf |= 0x80; 3229 else 3230 rf &= ~0x80; 3231 run_rt3070_rf_write(sc, 36, rf); 3232 3233 /* Set vcolo_bs. */ 3234 run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); 3235 /* Set pfd_delay. */ 3236 run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); 3237 3238 /* Set vco bias current control. */ 3239 run_rt3070_rf_read(sc, 6, &rf); 3240 rf &= ~0xc0; 3241 if (chan <= 14) 3242 rf |= 0x40; 3243 else if (chan <= 128) 3244 rf |= 0x80; 3245 else 3246 rf |= 0x40; 3247 run_rt3070_rf_write(sc, 6, rf); 3248 3249 run_rt3070_rf_read(sc, 30, &rf); 3250 rf = (rf & ~0x18) | 0x10; 3251 run_rt3070_rf_write(sc, 30, rf); 3252 3253 run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); 3254 run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); 3255 3256 run_rt3070_rf_read(sc, 51, &rf); 3257 rf = (rf & ~0x03) | 0x01; 3258 run_rt3070_rf_write(sc, 51, rf); 3259 /* Set tx_mx1_cc. */ 3260 run_rt3070_rf_read(sc, 51, &rf); 3261 rf &= ~0x1c; 3262 rf |= (chan <= 14) ? 0x14 : 0x10; 3263 run_rt3070_rf_write(sc, 51, rf); 3264 /* Set tx_mx1_ic. */ 3265 run_rt3070_rf_read(sc, 51, &rf); 3266 rf &= ~0xe0; 3267 rf |= (chan <= 14) ? 0x60 : 0x40; 3268 run_rt3070_rf_write(sc, 51, rf); 3269 /* Set tx_lo1_ic. */ 3270 run_rt3070_rf_read(sc, 49, &rf); 3271 rf &= ~0x1c; 3272 rf |= (chan <= 14) ? 0x0c : 0x08; 3273 run_rt3070_rf_write(sc, 49, rf); 3274 /* Set tx_lo1_en. */ 3275 run_rt3070_rf_read(sc, 50, &rf); 3276 run_rt3070_rf_write(sc, 50, rf & ~0x20); 3277 /* Set drv_cc. */ 3278 run_rt3070_rf_read(sc, 57, &rf); 3279 rf &= ~0xfc; 3280 rf |= (chan <= 14) ? 0x6c : 0x3c; 3281 run_rt3070_rf_write(sc, 57, rf); 3282 /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ 3283 run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); 3284 /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ 3285 run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); 3286 /* Enable VCO calibration. */ 3287 run_rt3070_rf_read(sc, 3, &rf); 3288 rf &= ~RT3593_VCOCAL; 3289 rf |= (chan <= 14) ? RT3593_VCOCAL : 0xbe; 3290 run_rt3070_rf_write(sc, 3, rf); 3291 3292 if (chan <= 14) 3293 rf = 0x23; 3294 else if (chan <= 64) 3295 rf = 0x36; 3296 else if (chan <= 128) 3297 rf = 0x32; 3298 else 3299 rf = 0x30; 3300 run_rt3070_rf_write(sc, 39, rf); 3301 if (chan <= 14) 3302 rf = 0xbb; 3303 else if (chan <= 64) 3304 rf = 0xeb; 3305 else if (chan <= 128) 3306 rf = 0xb3; 3307 else 3308 rf = 0x9b; 3309 run_rt3070_rf_write(sc, 45, rf); 3310 3311 /* Set FEQ/AEQ control. */ 3312 run_bbp_write(sc, 105, 0x34); 3313 } 3314 3315 void 3316 run_rt5390_set_chan(struct run_softc *sc, u_int chan) 3317 { 3318 int8_t txpow1, txpow2; 3319 uint8_t rf; 3320 int i; 3321 3322 /* find the settings for this channel (we know it exists) */ 3323 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3324 3325 /* use Tx power values from EEPROM */ 3326 txpow1 = sc->txpow1[i]; 3327 txpow2 = sc->txpow2[i]; 3328 3329 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3330 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3331 run_rt3070_rf_read(sc, 11, &rf); 3332 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3333 run_rt3070_rf_write(sc, 11, rf); 3334 3335 run_rt3070_rf_read(sc, 49, &rf); 3336 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3337 /* The valid range of the RF R49 is 0x00 to 0x27. */ 3338 if ((rf & 0x3f) > 0x27) 3339 rf = (rf & ~0x3f) | 0x27; 3340 run_rt3070_rf_write(sc, 49, rf); 3341 3342 if (sc->mac_ver == 0x5392) { 3343 run_rt3070_rf_read(sc, 50, &rf); 3344 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3345 /* The valid range of the RF R50 is 0x00 to 0x27. */ 3346 if ((rf & 0x3f) > 0x27) 3347 rf = (rf & ~0x3f) | 0x27; 3348 run_rt3070_rf_write(sc, 50, rf); 3349 } 3350 3351 run_rt3070_rf_read(sc, 1, &rf); 3352 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 3353 if (sc->mac_ver == 0x5392) 3354 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 3355 run_rt3070_rf_write(sc, 1, rf); 3356 3357 if (sc->mac_ver != 0x5392) { 3358 run_rt3070_rf_read(sc, 2, &rf); 3359 rf |= 0x80; 3360 run_rt3070_rf_write(sc, 2, rf); 3361 DELAY(10); 3362 rf &= 0x7f; 3363 run_rt3070_rf_write(sc, 2, rf); 3364 } 3365 3366 run_adjust_freq_offset(sc); 3367 3368 if (sc->mac_ver == 0x5392) { 3369 /* Fix for RT5392C. */ 3370 if (sc->mac_rev >= 0x0223) { 3371 if (chan <= 4) 3372 rf = 0x0f; 3373 else if (chan >= 5 && chan <= 7) 3374 rf = 0x0e; 3375 else 3376 rf = 0x0d; 3377 run_rt3070_rf_write(sc, 23, rf); 3378 3379 if (chan <= 4) 3380 rf = 0x0c; 3381 else if (chan == 5) 3382 rf = 0x0b; 3383 else if (chan >= 6 && chan <= 7) 3384 rf = 0x0a; 3385 else if (chan >= 8 && chan <= 10) 3386 rf = 0x09; 3387 else 3388 rf = 0x08; 3389 run_rt3070_rf_write(sc, 59, rf); 3390 } else { 3391 if (chan <= 11) 3392 rf = 0x0f; 3393 else 3394 rf = 0x0b; 3395 run_rt3070_rf_write(sc, 59, rf); 3396 } 3397 } else { 3398 /* Fix for RT5390F. */ 3399 if (sc->mac_rev >= 0x0502) { 3400 if (chan <= 11) 3401 rf = 0x43; 3402 else 3403 rf = 0x23; 3404 run_rt3070_rf_write(sc, 55, rf); 3405 3406 if (chan <= 11) 3407 rf = 0x0f; 3408 else if (chan == 12) 3409 rf = 0x0d; 3410 else 3411 rf = 0x0b; 3412 run_rt3070_rf_write(sc, 59, rf); 3413 } else { 3414 run_rt3070_rf_write(sc, 55, 0x44); 3415 run_rt3070_rf_write(sc, 59, 0x8f); 3416 } 3417 } 3418 3419 /* Enable VCO calibration. */ 3420 run_rt3070_rf_read(sc, 3, &rf); 3421 rf |= RT3593_VCOCAL; 3422 run_rt3070_rf_write(sc, 3, rf); 3423 } 3424 3425 void 3426 run_rt5592_set_chan(struct run_softc *sc, u_int chan) 3427 { 3428 const struct rt5592_freqs *freqs; 3429 uint32_t tmp; 3430 uint8_t reg, rf, txpow_bound; 3431 int8_t txpow1, txpow2; 3432 int i; 3433 3434 run_read(sc, RT5592_DEBUG_INDEX, &tmp); 3435 freqs = (tmp & RT5592_SEL_XTAL) ? 3436 rt5592_freqs_40mhz : rt5592_freqs_20mhz; 3437 3438 /* find the settings for this channel (we know it exists) */ 3439 for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); 3440 3441 /* use Tx power values from EEPROM */ 3442 txpow1 = sc->txpow1[i]; 3443 txpow2 = sc->txpow2[i]; 3444 3445 run_read(sc, RT3070_LDO_CFG0, &tmp); 3446 tmp &= ~0x1c000000; 3447 if (chan > 14) 3448 tmp |= 0x14000000; 3449 run_write(sc, RT3070_LDO_CFG0, tmp); 3450 3451 /* N setting. */ 3452 run_rt3070_rf_write(sc, 8, freqs->n & 0xff); 3453 run_rt3070_rf_read(sc, 9, &rf); 3454 rf &= ~(1 << 4); 3455 rf |= ((freqs->n & 0x0100) >> 8) << 4; 3456 run_rt3070_rf_write(sc, 9, rf); 3457 3458 /* K setting. */ 3459 run_rt3070_rf_read(sc, 9, &rf); 3460 rf &= ~0x0f; 3461 rf |= (freqs->k & 0x0f); 3462 run_rt3070_rf_write(sc, 9, rf); 3463 3464 /* Mode setting. */ 3465 run_rt3070_rf_read(sc, 11, &rf); 3466 rf &= ~0x0c; 3467 rf |= ((freqs->m - 0x8) & 0x3) << 2; 3468 run_rt3070_rf_write(sc, 11, rf); 3469 run_rt3070_rf_read(sc, 9, &rf); 3470 rf &= ~(1 << 7); 3471 rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; 3472 run_rt3070_rf_write(sc, 9, rf); 3473 3474 /* R setting. */ 3475 run_rt3070_rf_read(sc, 11, &rf); 3476 rf &= ~0x03; 3477 rf |= (freqs->r - 0x1); 3478 run_rt3070_rf_write(sc, 11, rf); 3479 3480 if (chan <= 14) { 3481 /* Initialize RF registers for 2GHZ. */ 3482 for (i = 0; i < nitems(rt5592_2ghz_def_rf); i++) { 3483 run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, 3484 rt5592_2ghz_def_rf[i].val); 3485 } 3486 3487 rf = (chan <= 10) ? 0x07 : 0x06; 3488 run_rt3070_rf_write(sc, 23, rf); 3489 run_rt3070_rf_write(sc, 59, rf); 3490 3491 run_rt3070_rf_write(sc, 55, 0x43); 3492 3493 /* 3494 * RF R49/R50 Tx power ALC code. 3495 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. 3496 */ 3497 reg = 2; 3498 txpow_bound = 0x27; 3499 } else { 3500 /* Initialize RF registers for 5GHZ. */ 3501 for (i = 0; i < nitems(rt5592_5ghz_def_rf); i++) { 3502 run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, 3503 rt5592_5ghz_def_rf[i].val); 3504 } 3505 for (i = 0; i < nitems(rt5592_chan_5ghz); i++) { 3506 if (chan >= rt5592_chan_5ghz[i].firstchan && 3507 chan <= rt5592_chan_5ghz[i].lastchan) { 3508 run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, 3509 rt5592_chan_5ghz[i].val); 3510 } 3511 } 3512 3513 /* 3514 * RF R49/R50 Tx power ALC code. 3515 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. 3516 */ 3517 reg = 3; 3518 txpow_bound = 0x2b; 3519 } 3520 3521 /* RF R49 ch0 Tx power ALC code. */ 3522 run_rt3070_rf_read(sc, 49, &rf); 3523 rf &= ~0xc0; 3524 rf |= (reg << 6); 3525 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3526 if ((rf & 0x3f) > txpow_bound) 3527 rf = (rf & ~0x3f) | txpow_bound; 3528 run_rt3070_rf_write(sc, 49, rf); 3529 3530 /* RF R50 ch1 Tx power ALC code. */ 3531 run_rt3070_rf_read(sc, 50, &rf); 3532 rf &= ~(1 << 7 | 1 << 6); 3533 rf |= (reg << 6); 3534 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3535 if ((rf & 0x3f) > txpow_bound) 3536 rf = (rf & ~0x3f) | txpow_bound; 3537 run_rt3070_rf_write(sc, 50, rf); 3538 3539 /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ 3540 run_rt3070_rf_read(sc, 1, &rf); 3541 rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD); 3542 if (sc->ntxchains > 1) 3543 rf |= RT3070_TX1_PD; 3544 if (sc->nrxchains > 1) 3545 rf |= RT3070_RX1_PD; 3546 run_rt3070_rf_write(sc, 1, rf); 3547 3548 run_rt3070_rf_write(sc, 6, 0xe4); 3549 3550 run_rt3070_rf_write(sc, 30, 0x10); 3551 run_rt3070_rf_write(sc, 31, 0x80); 3552 run_rt3070_rf_write(sc, 32, 0x80); 3553 3554 run_adjust_freq_offset(sc); 3555 3556 /* Enable VCO calibration. */ 3557 run_rt3070_rf_read(sc, 3, &rf); 3558 rf |= RT3593_VCOCAL; 3559 run_rt3070_rf_write(sc, 3, rf); 3560 } 3561 3562 void 3563 run_set_agc(struct run_softc *sc, uint8_t agc) 3564 { 3565 uint8_t bbp; 3566 3567 if (sc->mac_ver == 0x3572) { 3568 run_bbp_read(sc, 27, &bbp); 3569 bbp &= ~(0x3 << 5); 3570 run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ 3571 run_bbp_write(sc, 66, agc); 3572 run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ 3573 run_bbp_write(sc, 66, agc); 3574 } else 3575 run_bbp_write(sc, 66, agc); 3576 } 3577 3578 void 3579 run_set_rx_antenna(struct run_softc *sc, int aux) 3580 { 3581 uint32_t tmp; 3582 uint8_t bbp152; 3583 3584 if (aux) { 3585 if (sc->rf_rev == RT5390_RF_5370) { 3586 run_bbp_read(sc, 152, &bbp152); 3587 run_bbp_write(sc, 152, bbp152 & ~0x80); 3588 } else { 3589 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 0); 3590 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3591 run_write(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 3592 } 3593 } else { 3594 if (sc->rf_rev == RT5390_RF_5370) { 3595 run_bbp_read(sc, 152, &bbp152); 3596 run_bbp_write(sc, 152, bbp152 | 0x80); 3597 } else { 3598 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 1); 3599 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3600 run_write(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 3601 } 3602 } 3603 } 3604 3605 int 3606 run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) 3607 { 3608 struct ieee80211com *ic = &sc->sc_ic; 3609 u_int chan, group; 3610 3611 chan = ieee80211_chan2ieee(ic, c); 3612 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3613 return EINVAL; 3614 3615 if (sc->mac_ver == 0x5592) 3616 run_rt5592_set_chan(sc, chan); 3617 else if (sc->mac_ver >= 0x5390) 3618 run_rt5390_set_chan(sc, chan); 3619 else if (sc->mac_ver == 0x3593) 3620 run_rt3593_set_chan(sc, chan); 3621 else if (sc->mac_ver == 0x3572) 3622 run_rt3572_set_chan(sc, chan); 3623 else if (sc->mac_ver >= 0x3070) 3624 run_rt3070_set_chan(sc, chan); 3625 else 3626 run_rt2870_set_chan(sc, chan); 3627 3628 /* determine channel group */ 3629 if (chan <= 14) 3630 group = 0; 3631 else if (chan <= 64) 3632 group = 1; 3633 else if (chan <= 128) 3634 group = 2; 3635 else 3636 group = 3; 3637 3638 /* XXX necessary only when group has changed! */ 3639 run_select_chan_group(sc, group); 3640 3641 DELAY(1000); 3642 3643 /* Perform IQ calibration. */ 3644 if (sc->mac_ver >= 0x5392) 3645 run_iq_calib(sc, chan); 3646 3647 return 0; 3648 } 3649 3650 void 3651 run_enable_tsf_sync(struct run_softc *sc) 3652 { 3653 struct ieee80211com *ic = &sc->sc_ic; 3654 uint32_t tmp; 3655 3656 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 3657 tmp &= ~0x1fffff; 3658 tmp |= ic->ic_bss->ni_intval * 16; 3659 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3660 /* local TSF is always updated with remote TSF on beacon reception */ 3661 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3662 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 3663 } 3664 3665 void 3666 run_enable_mrr(struct run_softc *sc) 3667 { 3668 #define CCK(mcs) (mcs) 3669 #define OFDM(mcs) (1 << 3 | (mcs)) 3670 run_write(sc, RT2860_LG_FBK_CFG0, 3671 OFDM(6) << 28 | /* 54->48 */ 3672 OFDM(5) << 24 | /* 48->36 */ 3673 OFDM(4) << 20 | /* 36->24 */ 3674 OFDM(3) << 16 | /* 24->18 */ 3675 OFDM(2) << 12 | /* 18->12 */ 3676 OFDM(1) << 8 | /* 12-> 9 */ 3677 OFDM(0) << 4 | /* 9-> 6 */ 3678 OFDM(0)); /* 6-> 6 */ 3679 3680 run_write(sc, RT2860_LG_FBK_CFG1, 3681 CCK(2) << 12 | /* 11->5.5 */ 3682 CCK(1) << 8 | /* 5.5-> 2 */ 3683 CCK(0) << 4 | /* 2-> 1 */ 3684 CCK(0)); /* 1-> 1 */ 3685 #undef OFDM 3686 #undef CCK 3687 } 3688 3689 void 3690 run_set_txpreamble(struct run_softc *sc) 3691 { 3692 uint32_t tmp; 3693 3694 run_read(sc, RT2860_AUTO_RSP_CFG, &tmp); 3695 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 3696 tmp |= RT2860_CCK_SHORT_EN; 3697 else 3698 tmp &= ~RT2860_CCK_SHORT_EN; 3699 run_write(sc, RT2860_AUTO_RSP_CFG, tmp); 3700 } 3701 3702 void 3703 run_set_basicrates(struct run_softc *sc) 3704 { 3705 struct ieee80211com *ic = &sc->sc_ic; 3706 3707 /* set basic rates mask */ 3708 if (ic->ic_curmode == IEEE80211_MODE_11B) 3709 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 3710 else if (ic->ic_curmode == IEEE80211_MODE_11A) 3711 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 3712 else /* 11g */ 3713 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 3714 } 3715 3716 void 3717 run_set_leds(struct run_softc *sc, uint16_t which) 3718 { 3719 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3720 which | (sc->leds & 0x7f)); 3721 } 3722 3723 void 3724 run_set_bssid(struct run_softc *sc, const uint8_t *bssid) 3725 { 3726 run_write(sc, RT2860_MAC_BSSID_DW0, 3727 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3728 run_write(sc, RT2860_MAC_BSSID_DW1, 3729 bssid[4] | bssid[5] << 8); 3730 } 3731 3732 void 3733 run_set_macaddr(struct run_softc *sc, const uint8_t *addr) 3734 { 3735 run_write(sc, RT2860_MAC_ADDR_DW0, 3736 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3737 run_write(sc, RT2860_MAC_ADDR_DW1, 3738 addr[4] | addr[5] << 8 | 0xff << 16); 3739 } 3740 3741 void 3742 run_updateslot(struct ieee80211com *ic) 3743 { 3744 /* do it in a process context */ 3745 run_do_async(ic->ic_softc, run_updateslot_cb, NULL, 0); 3746 } 3747 3748 /* ARGSUSED */ 3749 void 3750 run_updateslot_cb(struct run_softc *sc, void *arg) 3751 { 3752 uint32_t tmp; 3753 3754 run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp); 3755 tmp &= ~0xff; 3756 tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 3757 IEEE80211_DUR_DS_SHSLOT : IEEE80211_DUR_DS_SLOT; 3758 run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3759 } 3760 3761 #if NBPFILTER > 0 3762 int8_t 3763 run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain) 3764 { 3765 struct ieee80211com *ic = &sc->sc_ic; 3766 struct ieee80211_channel *c = ic->ic_ibss_chan; 3767 int delta; 3768 3769 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3770 u_int chan = ieee80211_chan2ieee(ic, c); 3771 delta = sc->rssi_5ghz[rxchain]; 3772 3773 /* determine channel group */ 3774 if (chan <= 64) 3775 delta -= sc->lna[1]; 3776 else if (chan <= 128) 3777 delta -= sc->lna[2]; 3778 else 3779 delta -= sc->lna[3]; 3780 } else 3781 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3782 3783 return -12 - delta - rssi; 3784 } 3785 #endif 3786 3787 void 3788 run_rt5390_bbp_init(struct run_softc *sc) 3789 { 3790 int i; 3791 uint8_t bbp; 3792 3793 /* Apply maximum likelihood detection for 2 stream case. */ 3794 run_bbp_read(sc, 105, &bbp); 3795 if (sc->nrxchains > 1) 3796 run_bbp_write(sc, 105, bbp | RT5390_MLD); 3797 3798 /* Avoid data lost and CRC error. */ 3799 run_bbp_read(sc, 4, &bbp); 3800 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3801 3802 if (sc->mac_ver == 0x5592) { 3803 for (i = 0; i < nitems(rt5592_def_bbp); i++) { 3804 run_bbp_write(sc, rt5592_def_bbp[i].reg, 3805 rt5592_def_bbp[i].val); 3806 } 3807 for (i = 0; i < nitems(rt5592_bbp_r196); i++) { 3808 run_bbp_write(sc, 195, i + 0x80); 3809 run_bbp_write(sc, 196, rt5592_bbp_r196[i]); 3810 } 3811 } else { 3812 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3813 run_bbp_write(sc, rt5390_def_bbp[i].reg, 3814 rt5390_def_bbp[i].val); 3815 } 3816 } 3817 if (sc->mac_ver == 0x5392) { 3818 run_bbp_write(sc, 88, 0x90); 3819 run_bbp_write(sc, 95, 0x9a); 3820 run_bbp_write(sc, 98, 0x12); 3821 run_bbp_write(sc, 106, 0x12); 3822 run_bbp_write(sc, 134, 0xd0); 3823 run_bbp_write(sc, 135, 0xf6); 3824 run_bbp_write(sc, 148, 0x84); 3825 } 3826 3827 run_bbp_read(sc, 152, &bbp); 3828 run_bbp_write(sc, 152, bbp | 0x80); 3829 3830 /* Fix BBP254 for RT5592C. */ 3831 if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { 3832 run_bbp_read(sc, 254, &bbp); 3833 run_bbp_write(sc, 254, bbp | 0x80); 3834 } 3835 3836 /* Disable hardware antenna diversity. */ 3837 if (sc->mac_ver == 0x5390) 3838 run_bbp_write(sc, 154, 0); 3839 3840 /* Initialize Rx CCK/OFDM frequency offset report. */ 3841 run_bbp_write(sc, 142, 1); 3842 run_bbp_write(sc, 143, 57); 3843 } 3844 3845 int 3846 run_bbp_init(struct run_softc *sc) 3847 { 3848 int i, error, ntries; 3849 uint8_t bbp0; 3850 3851 /* wait for BBP to wake up */ 3852 for (ntries = 0; ntries < 20; ntries++) { 3853 if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) 3854 return error; 3855 if (bbp0 != 0 && bbp0 != 0xff) 3856 break; 3857 } 3858 if (ntries == 20) 3859 return ETIMEDOUT; 3860 3861 /* initialize BBP registers to default values */ 3862 if (sc->mac_ver >= 0x5390) 3863 run_rt5390_bbp_init(sc); 3864 else { 3865 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3866 run_bbp_write(sc, rt2860_def_bbp[i].reg, 3867 rt2860_def_bbp[i].val); 3868 } 3869 } 3870 3871 if (sc->mac_ver == 0x3593) { 3872 run_bbp_write(sc, 79, 0x13); 3873 run_bbp_write(sc, 80, 0x05); 3874 run_bbp_write(sc, 81, 0x33); 3875 run_bbp_write(sc, 86, 0x46); 3876 run_bbp_write(sc, 137, 0x0f); 3877 } 3878 3879 /* fix BBP84 for RT2860E */ 3880 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3881 run_bbp_write(sc, 84, 0x19); 3882 3883 if (sc->mac_ver >= 0x3070 && (sc->mac_ver != 0x3593 && 3884 sc->mac_ver != 0x5592)) { 3885 run_bbp_write(sc, 79, 0x13); 3886 run_bbp_write(sc, 80, 0x05); 3887 run_bbp_write(sc, 81, 0x33); 3888 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3889 run_bbp_write(sc, 69, 0x16); 3890 run_bbp_write(sc, 73, 0x12); 3891 } 3892 return 0; 3893 } 3894 3895 int 3896 run_rt3070_rf_init(struct run_softc *sc) 3897 { 3898 uint32_t tmp; 3899 uint8_t bbp4, mingain, rf, target; 3900 int i; 3901 3902 run_rt3070_rf_read(sc, 30, &rf); 3903 /* toggle RF R30 bit 7 */ 3904 run_rt3070_rf_write(sc, 30, rf | 0x80); 3905 DELAY(1000); 3906 run_rt3070_rf_write(sc, 30, rf & ~0x80); 3907 3908 /* initialize RF registers to default value */ 3909 if (sc->mac_ver == 0x3572) { 3910 for (i = 0; i < nitems(rt3572_def_rf); i++) { 3911 run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, 3912 rt3572_def_rf[i].val); 3913 } 3914 } else { 3915 for (i = 0; i < nitems(rt3070_def_rf); i++) { 3916 run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, 3917 rt3070_def_rf[i].val); 3918 } 3919 } 3920 if (sc->mac_ver == 0x3070 && sc->mac_rev < 0x0201) { 3921 /* 3922 * Change voltage from 1.2V to 1.35V for RT3070. 3923 * The DAC issue (RT3070_LDO_CFG0) has been fixed 3924 * in RT3070(F). 3925 */ 3926 run_read(sc, RT3070_LDO_CFG0, &tmp); 3927 tmp = (tmp & ~0x0f000000) | 0x0d000000; 3928 run_write(sc, RT3070_LDO_CFG0, tmp); 3929 3930 } else if (sc->mac_ver == 0x3071) { 3931 run_rt3070_rf_read(sc, 6, &rf); 3932 run_rt3070_rf_write(sc, 6, rf | 0x40); 3933 run_rt3070_rf_write(sc, 31, 0x14); 3934 3935 run_read(sc, RT3070_LDO_CFG0, &tmp); 3936 tmp &= ~0x1f000000; 3937 if (sc->mac_rev < 0x0211) 3938 tmp |= 0x0d000000; /* 1.35V */ 3939 else 3940 tmp |= 0x01000000; /* 1.2V */ 3941 run_write(sc, RT3070_LDO_CFG0, tmp); 3942 3943 /* patch LNA_PE_G1 */ 3944 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 3945 run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 3946 3947 } else if (sc->mac_ver == 0x3572) { 3948 run_rt3070_rf_read(sc, 6, &rf); 3949 run_rt3070_rf_write(sc, 6, rf | 0x40); 3950 /* increase voltage from 1.2V to 1.35V */ 3951 run_read(sc, RT3070_LDO_CFG0, &tmp); 3952 tmp = (tmp & ~0x1f000000) | 0x0d000000; 3953 run_write(sc, RT3070_LDO_CFG0, tmp); 3954 3955 if (sc->mac_rev < 0x0211 || !sc->patch_dac) { 3956 DELAY(1); /* wait for 1msec */ 3957 /* decrease voltage back to 1.2V */ 3958 tmp = (tmp & ~0x1f000000) | 0x01000000; 3959 run_write(sc, RT3070_LDO_CFG0, tmp); 3960 } 3961 } 3962 3963 /* select 20MHz bandwidth */ 3964 run_rt3070_rf_read(sc, 31, &rf); 3965 run_rt3070_rf_write(sc, 31, rf & ~0x20); 3966 3967 /* calibrate filter for 20MHz bandwidth */ 3968 sc->rf24_20mhz = 0x1f; /* default value */ 3969 target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; 3970 run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); 3971 3972 /* select 40MHz bandwidth */ 3973 run_bbp_read(sc, 4, &bbp4); 3974 run_bbp_write(sc, 4, (bbp4 & ~0x18) | 0x10); 3975 run_rt3070_rf_read(sc, 31, &rf); 3976 run_rt3070_rf_write(sc, 31, rf | 0x20); 3977 3978 /* calibrate filter for 40MHz bandwidth */ 3979 sc->rf24_40mhz = 0x2f; /* default value */ 3980 target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; 3981 run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); 3982 3983 /* go back to 20MHz bandwidth */ 3984 run_bbp_read(sc, 4, &bbp4); 3985 run_bbp_write(sc, 4, bbp4 & ~0x18); 3986 3987 if (sc->mac_ver == 0x3572) { 3988 /* save default BBP registers 25 and 26 values */ 3989 run_bbp_read(sc, 25, &sc->bbp25); 3990 run_bbp_read(sc, 26, &sc->bbp26); 3991 3992 } else if (sc->mac_rev < 0x0201 || sc->mac_rev < 0x0211) 3993 run_rt3070_rf_write(sc, 27, 0x03); 3994 3995 run_read(sc, RT3070_OPT_14, &tmp); 3996 run_write(sc, RT3070_OPT_14, tmp | 1); 3997 3998 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 3999 run_rt3070_rf_read(sc, 17, &rf); 4000 rf &= ~RT3070_TX_LO1; 4001 if ((sc->mac_ver == 0x3070 || 4002 (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && 4003 !sc->ext_2ghz_lna) 4004 rf |= 0x20; /* fix for long range Rx issue */ 4005 mingain = (sc->mac_ver == 0x3070) ? 1 : 2; 4006 if (sc->txmixgain_2ghz >= mingain) 4007 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 4008 run_rt3070_rf_write(sc, 17, rf); 4009 } 4010 if (sc->mac_ver == 0x3071) { 4011 run_rt3070_rf_read(sc, 1, &rf); 4012 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 4013 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 4014 run_rt3070_rf_write(sc, 1, rf); 4015 4016 run_rt3070_rf_read(sc, 15, &rf); 4017 run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 4018 4019 run_rt3070_rf_read(sc, 20, &rf); 4020 run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 4021 4022 run_rt3070_rf_read(sc, 21, &rf); 4023 run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 4024 } 4025 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4026 /* fix Tx to Rx IQ glitch by raising RF voltage */ 4027 run_rt3070_rf_read(sc, 27, &rf); 4028 rf &= ~0x77; 4029 if (sc->mac_rev < 0x0211) 4030 rf |= 0x03; 4031 run_rt3070_rf_write(sc, 27, rf); 4032 } 4033 return 0; 4034 } 4035 4036 void 4037 run_rt3593_rf_init(struct run_softc *sc) 4038 { 4039 uint32_t tmp; 4040 uint8_t rf; 4041 int i; 4042 4043 /* Disable the GPIO bits 4 and 7 for LNA PE control. */ 4044 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4045 tmp &= ~(1 << 4 | 1 << 7); 4046 run_write(sc, RT3070_GPIO_SWITCH, tmp); 4047 4048 /* Initialize RF registers to default value. */ 4049 for (i = 0; i < nitems(rt3593_def_rf); i++) { 4050 run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, 4051 rt3593_def_rf[i].val); 4052 } 4053 4054 /* Toggle RF R2 to initiate calibration. */ 4055 run_rt3070_rf_write(sc, 2, RT3593_RESCAL); 4056 4057 /* Initialize RF frequency offset. */ 4058 run_adjust_freq_offset(sc); 4059 4060 run_rt3070_rf_read(sc, 18, &rf); 4061 run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); 4062 4063 /* 4064 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to 4065 * decrease voltage back to 1.2V. 4066 */ 4067 run_read(sc, RT3070_LDO_CFG0, &tmp); 4068 tmp = (tmp & ~0x1f000000) | 0x0d000000; 4069 run_write(sc, RT3070_LDO_CFG0, tmp); 4070 DELAY(1); 4071 tmp = (tmp & ~0x1f000000) | 0x01000000; 4072 run_write(sc, RT3070_LDO_CFG0, tmp); 4073 4074 sc->rf24_20mhz = 0x1f; 4075 sc->rf24_40mhz = 0x2f; 4076 4077 /* Save default BBP registers 25 and 26 values. */ 4078 run_bbp_read(sc, 25, &sc->bbp25); 4079 run_bbp_read(sc, 26, &sc->bbp26); 4080 4081 run_read(sc, RT3070_OPT_14, &tmp); 4082 run_write(sc, RT3070_OPT_14, tmp | 1); 4083 } 4084 4085 void 4086 run_rt5390_rf_init(struct run_softc *sc) 4087 { 4088 uint32_t tmp; 4089 uint8_t rf; 4090 int i; 4091 4092 /* Toggle RF R2 to initiate calibration. */ 4093 if (sc->mac_ver == 0x5390) { 4094 run_rt3070_rf_read(sc, 2, &rf); 4095 run_rt3070_rf_write(sc, 2, rf | RT3593_RESCAL); 4096 DELAY(10); 4097 run_rt3070_rf_write(sc, 2, rf & ~RT3593_RESCAL); 4098 } else { 4099 run_rt3070_rf_write(sc, 2, RT3593_RESCAL); 4100 DELAY(10); 4101 } 4102 4103 /* Initialize RF registers to default value. */ 4104 if (sc->mac_ver == 0x5592) { 4105 for (i = 0; i < nitems(rt5592_def_rf); i++) { 4106 run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, 4107 rt5592_def_rf[i].val); 4108 } 4109 /* Initialize RF frequency offset. */ 4110 run_adjust_freq_offset(sc); 4111 } else if (sc->mac_ver == 0x5392) { 4112 for (i = 0; i < nitems(rt5392_def_rf); i++) { 4113 run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, 4114 rt5392_def_rf[i].val); 4115 } 4116 if (sc->mac_rev >= 0x0223) { 4117 run_rt3070_rf_write(sc, 23, 0x0f); 4118 run_rt3070_rf_write(sc, 24, 0x3e); 4119 run_rt3070_rf_write(sc, 51, 0x32); 4120 run_rt3070_rf_write(sc, 53, 0x22); 4121 run_rt3070_rf_write(sc, 56, 0xc1); 4122 run_rt3070_rf_write(sc, 59, 0x0f); 4123 } 4124 } else { 4125 for (i = 0; i < nitems(rt5390_def_rf); i++) { 4126 run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, 4127 rt5390_def_rf[i].val); 4128 } 4129 if (sc->mac_rev >= 0x0502) { 4130 run_rt3070_rf_write(sc, 6, 0xe0); 4131 run_rt3070_rf_write(sc, 25, 0x80); 4132 run_rt3070_rf_write(sc, 46, 0x73); 4133 run_rt3070_rf_write(sc, 53, 0x00); 4134 run_rt3070_rf_write(sc, 56, 0x42); 4135 run_rt3070_rf_write(sc, 61, 0xd1); 4136 } 4137 } 4138 4139 sc->rf24_20mhz = 0x1f; /* default value */ 4140 sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; 4141 4142 if (sc->mac_rev < 0x0211) 4143 run_rt3070_rf_write(sc, 27, 0x3); 4144 4145 run_read(sc, RT3070_OPT_14, &tmp); 4146 run_write(sc, RT3070_OPT_14, tmp | 1); 4147 } 4148 4149 int 4150 run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, 4151 uint8_t *val) 4152 { 4153 uint8_t rf22, rf24; 4154 uint8_t bbp55_pb, bbp55_sb, delta; 4155 int ntries; 4156 4157 /* program filter */ 4158 run_rt3070_rf_read(sc, 24, &rf24); 4159 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 4160 run_rt3070_rf_write(sc, 24, rf24); 4161 4162 /* enable baseband loopback mode */ 4163 run_rt3070_rf_read(sc, 22, &rf22); 4164 run_rt3070_rf_write(sc, 22, rf22 | 0x01); 4165 4166 /* set power and frequency of passband test tone */ 4167 run_bbp_write(sc, 24, 0x00); 4168 for (ntries = 0; ntries < 100; ntries++) { 4169 /* transmit test tone */ 4170 run_bbp_write(sc, 25, 0x90); 4171 DELAY(1000); 4172 /* read received power */ 4173 run_bbp_read(sc, 55, &bbp55_pb); 4174 if (bbp55_pb != 0) 4175 break; 4176 } 4177 if (ntries == 100) 4178 return ETIMEDOUT; 4179 4180 /* set power and frequency of stopband test tone */ 4181 run_bbp_write(sc, 24, 0x06); 4182 for (ntries = 0; ntries < 100; ntries++) { 4183 /* transmit test tone */ 4184 run_bbp_write(sc, 25, 0x90); 4185 DELAY(1000); 4186 /* read received power */ 4187 run_bbp_read(sc, 55, &bbp55_sb); 4188 4189 delta = bbp55_pb - bbp55_sb; 4190 if (delta > target) 4191 break; 4192 4193 /* reprogram filter */ 4194 rf24++; 4195 run_rt3070_rf_write(sc, 24, rf24); 4196 } 4197 if (ntries < 100) { 4198 if (rf24 != init) 4199 rf24--; /* backtrack */ 4200 *val = rf24; 4201 run_rt3070_rf_write(sc, 24, rf24); 4202 } 4203 4204 /* restore initial state */ 4205 run_bbp_write(sc, 24, 0x00); 4206 4207 /* disable baseband loopback mode */ 4208 run_rt3070_rf_read(sc, 22, &rf22); 4209 run_rt3070_rf_write(sc, 22, rf22 & ~0x01); 4210 4211 return 0; 4212 } 4213 4214 void 4215 run_rt3070_rf_setup(struct run_softc *sc) 4216 { 4217 uint8_t bbp, rf; 4218 int i; 4219 4220 if (sc->mac_ver == 0x3572) { 4221 /* enable DC filter */ 4222 if (sc->mac_rev >= 0x0201) 4223 run_bbp_write(sc, 103, 0xc0); 4224 4225 run_bbp_read(sc, 138, &bbp); 4226 if (sc->ntxchains == 1) 4227 bbp |= 0x20; /* turn off DAC1 */ 4228 if (sc->nrxchains == 1) 4229 bbp &= ~0x02; /* turn off ADC1 */ 4230 run_bbp_write(sc, 138, bbp); 4231 4232 if (sc->mac_rev >= 0x0211) { 4233 /* improve power consumption */ 4234 run_bbp_read(sc, 31, &bbp); 4235 run_bbp_write(sc, 31, bbp & ~0x03); 4236 } 4237 4238 run_rt3070_rf_read(sc, 16, &rf); 4239 rf = (rf & ~0x07) | sc->txmixgain_2ghz; 4240 run_rt3070_rf_write(sc, 16, rf); 4241 4242 } else if (sc->mac_ver == 0x3071) { 4243 /* enable DC filter */ 4244 if (sc->mac_rev >= 0x0211) { 4245 run_bbp_write(sc, 103, 0xc0); 4246 4247 /* improve power consumption */ 4248 run_bbp_read(sc, 31, &bbp); 4249 run_bbp_write(sc, 31, bbp & ~0x03); 4250 } 4251 4252 run_bbp_read(sc, 138, &bbp); 4253 if (sc->ntxchains == 1) 4254 bbp |= 0x20; /* turn off DAC1 */ 4255 if (sc->nrxchains == 1) 4256 bbp &= ~0x02; /* turn off ADC1 */ 4257 run_bbp_write(sc, 138, bbp); 4258 4259 run_write(sc, RT2860_TX_SW_CFG1, 0); 4260 if (sc->mac_rev < 0x0211) { 4261 run_write(sc, RT2860_TX_SW_CFG2, 4262 sc->patch_dac ? 0x2c : 0x0f); 4263 } else 4264 run_write(sc, RT2860_TX_SW_CFG2, 0); 4265 4266 } else if (sc->mac_ver == 0x3070) { 4267 if (sc->mac_rev >= 0x0201) { 4268 /* enable DC filter */ 4269 run_bbp_write(sc, 103, 0xc0); 4270 4271 /* improve power consumption */ 4272 run_bbp_read(sc, 31, &bbp); 4273 run_bbp_write(sc, 31, bbp & ~0x03); 4274 } 4275 4276 if (sc->mac_rev < 0x0201) { 4277 run_write(sc, RT2860_TX_SW_CFG1, 0); 4278 run_write(sc, RT2860_TX_SW_CFG2, 0x2c); 4279 } else 4280 run_write(sc, RT2860_TX_SW_CFG2, 0); 4281 } 4282 4283 /* initialize RF registers from ROM for >=RT3071*/ 4284 if (sc->mac_ver >= 0x3071) { 4285 for (i = 0; i < 10; i++) { 4286 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 4287 continue; 4288 run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 4289 } 4290 } 4291 } 4292 4293 void 4294 run_rt3593_rf_setup(struct run_softc *sc) 4295 { 4296 uint8_t bbp, rf; 4297 4298 if (sc->mac_rev >= 0x0211) { 4299 /* Enable DC filter. */ 4300 run_bbp_write(sc, 103, 0xc0); 4301 } 4302 run_write(sc, RT2860_TX_SW_CFG1, 0); 4303 if (sc->mac_rev < 0x0211) { 4304 run_write(sc, RT2860_TX_SW_CFG2, 4305 sc->patch_dac ? 0x2c : 0x0f); 4306 } else 4307 run_write(sc, RT2860_TX_SW_CFG2, 0); 4308 4309 run_rt3070_rf_read(sc, 50, &rf); 4310 run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); 4311 4312 run_rt3070_rf_read(sc, 51, &rf); 4313 rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | 4314 ((sc->txmixgain_2ghz & 0x07) << 2); 4315 run_rt3070_rf_write(sc, 51, rf); 4316 4317 run_rt3070_rf_read(sc, 38, &rf); 4318 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4319 4320 run_rt3070_rf_read(sc, 39, &rf); 4321 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4322 4323 run_rt3070_rf_read(sc, 1, &rf); 4324 run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); 4325 4326 run_rt3070_rf_read(sc, 30, &rf); 4327 rf = (rf & ~0x18) | 0x10; 4328 run_rt3070_rf_write(sc, 30, rf); 4329 4330 /* Apply maximum likelihood detection for 2 stream case. */ 4331 run_bbp_read(sc, 105, &bbp); 4332 if (sc->nrxchains > 1) 4333 run_bbp_write(sc, 105, bbp | RT5390_MLD); 4334 4335 /* Avoid data lost and CRC error. */ 4336 run_bbp_read(sc, 4, &bbp); 4337 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4338 4339 run_bbp_write(sc, 92, 0x02); 4340 run_bbp_write(sc, 82, 0x82); 4341 run_bbp_write(sc, 106, 0x05); 4342 run_bbp_write(sc, 104, 0x92); 4343 run_bbp_write(sc, 88, 0x90); 4344 run_bbp_write(sc, 148, 0xc8); 4345 run_bbp_write(sc, 47, 0x48); 4346 run_bbp_write(sc, 120, 0x50); 4347 4348 run_bbp_write(sc, 163, 0x9d); 4349 4350 /* SNR mapping. */ 4351 run_bbp_write(sc, 142, 0x06); 4352 run_bbp_write(sc, 143, 0xa0); 4353 run_bbp_write(sc, 142, 0x07); 4354 run_bbp_write(sc, 143, 0xa1); 4355 run_bbp_write(sc, 142, 0x08); 4356 run_bbp_write(sc, 143, 0xa2); 4357 4358 run_bbp_write(sc, 31, 0x08); 4359 run_bbp_write(sc, 68, 0x0b); 4360 run_bbp_write(sc, 105, 0x04); 4361 } 4362 4363 void 4364 run_rt5390_rf_setup(struct run_softc *sc) 4365 { 4366 uint8_t bbp, rf; 4367 4368 if (sc->mac_rev >= 0x0211) { 4369 /* Enable DC filter. */ 4370 run_bbp_write(sc, 103, 0xc0); 4371 4372 if (sc->mac_ver != 0x5592) { 4373 /* Improve power consumption. */ 4374 run_bbp_read(sc, 31, &bbp); 4375 run_bbp_write(sc, 31, bbp & ~0x03); 4376 } 4377 } 4378 4379 run_bbp_read(sc, 138, &bbp); 4380 if (sc->ntxchains == 1) 4381 bbp |= 0x20; /* turn off DAC1 */ 4382 if (sc->nrxchains == 1) 4383 bbp &= ~0x02; /* turn off ADC1 */ 4384 run_bbp_write(sc, 138, bbp); 4385 4386 run_rt3070_rf_read(sc, 38, &rf); 4387 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4388 4389 run_rt3070_rf_read(sc, 39, &rf); 4390 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4391 4392 /* Avoid data lost and CRC error. */ 4393 run_bbp_read(sc, 4, &bbp); 4394 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4395 4396 run_rt3070_rf_read(sc, 30, &rf); 4397 rf = (rf & ~0x18) | 0x10; 4398 run_rt3070_rf_write(sc, 30, rf); 4399 4400 if (sc->mac_ver != 0x5592) { 4401 run_write(sc, RT2860_TX_SW_CFG1, 0); 4402 if (sc->mac_rev < 0x0211) { 4403 run_write(sc, RT2860_TX_SW_CFG2, 4404 sc->patch_dac ? 0x2c : 0x0f); 4405 } else 4406 run_write(sc, RT2860_TX_SW_CFG2, 0); 4407 } 4408 } 4409 4410 int 4411 run_txrx_enable(struct run_softc *sc) 4412 { 4413 uint32_t tmp; 4414 int error, ntries; 4415 4416 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 4417 for (ntries = 0; ntries < 200; ntries++) { 4418 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4419 return error; 4420 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4421 break; 4422 DELAY(1000); 4423 } 4424 if (ntries == 200) 4425 return ETIMEDOUT; 4426 4427 DELAY(50); 4428 4429 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE; 4430 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4431 4432 /* enable Rx bulk aggregation (set timeout and limit) */ 4433 tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN | 4434 RT2860_USB_RX_AGG_TO(128) | RT2860_USB_RX_AGG_LMT(2); 4435 run_write(sc, RT2860_USB_DMA_CFG, tmp); 4436 4437 /* set Rx filter */ 4438 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 4439 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 4440 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 4441 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 4442 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 4443 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 4444 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 4445 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 4446 } 4447 run_write(sc, RT2860_RX_FILTR_CFG, tmp); 4448 4449 run_write(sc, RT2860_MAC_SYS_CTRL, 4450 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4451 4452 return 0; 4453 } 4454 4455 void 4456 run_adjust_freq_offset(struct run_softc *sc) 4457 { 4458 uint8_t rf, tmp; 4459 4460 run_rt3070_rf_read(sc, 17, &rf); 4461 tmp = rf; 4462 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 4463 rf = MIN(rf, 0x5f); 4464 4465 if (tmp != rf) 4466 run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); 4467 } 4468 4469 int 4470 run_init(struct ifnet *ifp) 4471 { 4472 struct run_softc *sc = ifp->if_softc; 4473 struct ieee80211com *ic = &sc->sc_ic; 4474 uint32_t tmp; 4475 uint8_t bbp1, bbp3; 4476 int i, error, qid, ridx, ntries; 4477 4478 if (usbd_is_dying(sc->sc_udev)) 4479 return ENXIO; 4480 4481 for (ntries = 0; ntries < 100; ntries++) { 4482 if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0) 4483 goto fail; 4484 if (tmp != 0 && tmp != 0xffffffff) 4485 break; 4486 DELAY(10); 4487 } 4488 if (ntries == 100) { 4489 error = ETIMEDOUT; 4490 goto fail; 4491 } 4492 4493 if ((error = run_load_microcode(sc)) != 0) { 4494 printf("%s: could not load 8051 microcode\n", 4495 sc->sc_dev.dv_xname); 4496 goto fail; 4497 } 4498 4499 /* init host command ring */ 4500 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4501 4502 /* init Tx rings (4 EDCAs) */ 4503 for (qid = 0; qid < 4; qid++) { 4504 if ((error = run_alloc_tx_ring(sc, qid)) != 0) 4505 goto fail; 4506 } 4507 /* init Rx ring */ 4508 if ((error = run_alloc_rx_ring(sc)) != 0) 4509 goto fail; 4510 4511 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 4512 run_set_macaddr(sc, ic->ic_myaddr); 4513 4514 for (ntries = 0; ntries < 100; ntries++) { 4515 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4516 goto fail; 4517 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4518 break; 4519 DELAY(1000); 4520 } 4521 if (ntries == 100) { 4522 printf("%s: timeout waiting for DMA engine\n", 4523 sc->sc_dev.dv_xname); 4524 error = ETIMEDOUT; 4525 goto fail; 4526 } 4527 tmp &= 0xff0; 4528 tmp |= RT2860_TX_WB_DDONE; 4529 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4530 4531 /* turn off PME_OEN to solve high-current issue */ 4532 run_read(sc, RT2860_SYS_CTRL, &tmp); 4533 run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN); 4534 4535 run_write(sc, RT2860_MAC_SYS_CTRL, 4536 RT2860_BBP_HRST | RT2860_MAC_SRST); 4537 run_write(sc, RT2860_USB_DMA_CFG, 0); 4538 4539 if ((error = run_reset(sc)) != 0) { 4540 printf("%s: could not reset chipset\n", sc->sc_dev.dv_xname); 4541 goto fail; 4542 } 4543 4544 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4545 4546 /* init Tx power for all Tx rates (from EEPROM) */ 4547 for (ridx = 0; ridx < 5; ridx++) { 4548 if (sc->txpow20mhz[ridx] == 0xffffffff) 4549 continue; 4550 run_write(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 4551 } 4552 4553 for (i = 0; i < nitems(rt2870_def_mac); i++) 4554 run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); 4555 run_write(sc, RT2860_WMM_AIFSN_CFG, 0x00002273); 4556 run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344); 4557 run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa); 4558 4559 if (sc->mac_ver >= 0x5390) { 4560 run_write(sc, RT2860_TX_SW_CFG0, 4561 4 << RT2860_DLY_PAPE_EN_SHIFT | 4); 4562 if (sc->mac_ver >= 0x5392) { 4563 run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff); 4564 if (sc->mac_ver == 0x5592) { 4565 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980); 4566 run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082); 4567 } else { 4568 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980); 4569 run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); 4570 } 4571 } 4572 } else if (sc->mac_ver == 0x3593) { 4573 run_write(sc, RT2860_TX_SW_CFG0, 4574 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); 4575 } else if (sc->mac_ver >= 0x3070) { 4576 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 4577 run_write(sc, RT2860_TX_SW_CFG0, 4578 4 << RT2860_DLY_PAPE_EN_SHIFT); 4579 } 4580 4581 /* wait while MAC is busy */ 4582 for (ntries = 0; ntries < 100; ntries++) { 4583 if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0) 4584 goto fail; 4585 if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 4586 break; 4587 DELAY(1000); 4588 } 4589 if (ntries == 100) { 4590 error = ETIMEDOUT; 4591 goto fail; 4592 } 4593 4594 /* clear Host to MCU mailbox */ 4595 run_write(sc, RT2860_H2M_BBPAGENT, 0); 4596 run_write(sc, RT2860_H2M_MAILBOX, 0); 4597 DELAY(1000); 4598 4599 if ((error = run_bbp_init(sc)) != 0) { 4600 printf("%s: could not initialize BBP\n", sc->sc_dev.dv_xname); 4601 goto fail; 4602 } 4603 4604 /* abort TSF synchronization */ 4605 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 4606 tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 4607 RT2860_TBTT_TIMER_EN); 4608 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 4609 4610 /* clear RX WCID search table */ 4611 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4612 /* clear WCID attribute table */ 4613 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4614 /* clear shared key table */ 4615 run_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 4616 /* clear shared key mode */ 4617 run_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 4618 4619 run_read(sc, RT2860_US_CYC_CNT, &tmp); 4620 tmp = (tmp & ~0xff) | 0x1e; 4621 run_write(sc, RT2860_US_CYC_CNT, tmp); 4622 4623 if (sc->mac_rev != 0x0101) 4624 run_write(sc, RT2860_TXOP_CTRL_CFG, 0x0000583f); 4625 4626 run_write(sc, RT2860_WMM_TXOP0_CFG, 0); 4627 run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); 4628 4629 /* write vendor-specific BBP values (from EEPROM) */ 4630 if (sc->mac_ver < 0x3593) { 4631 for (i = 0; i < 8; i++) { 4632 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4633 continue; 4634 run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4635 } 4636 } 4637 4638 /* select Main antenna for 1T1R devices */ 4639 if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370) 4640 run_set_rx_antenna(sc, 0); 4641 4642 /* send LEDs operating mode to microcontroller */ 4643 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); 4644 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); 4645 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); 4646 4647 if (sc->mac_ver >= 0x5390) 4648 run_rt5390_rf_init(sc); 4649 else if (sc->mac_ver == 0x3593) 4650 run_rt3593_rf_init(sc); 4651 else if (sc->mac_ver >= 0x3070) 4652 run_rt3070_rf_init(sc); 4653 4654 /* disable non-existing Rx chains */ 4655 run_bbp_read(sc, 3, &bbp3); 4656 bbp3 &= ~(1 << 3 | 1 << 4); 4657 if (sc->nrxchains == 2) 4658 bbp3 |= 1 << 3; 4659 else if (sc->nrxchains == 3) 4660 bbp3 |= 1 << 4; 4661 run_bbp_write(sc, 3, bbp3); 4662 4663 /* disable non-existing Tx chains */ 4664 run_bbp_read(sc, 1, &bbp1); 4665 if (sc->ntxchains == 1) 4666 bbp1 &= ~(1 << 3 | 1 << 4); 4667 run_bbp_write(sc, 1, bbp1); 4668 4669 if (sc->mac_ver >= 0x5390) 4670 run_rt5390_rf_setup(sc); 4671 else if (sc->mac_ver == 0x3593) 4672 run_rt3593_rf_setup(sc); 4673 else if (sc->mac_ver >= 0x3070) 4674 run_rt3070_rf_setup(sc); 4675 4676 /* select default channel */ 4677 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 4678 run_set_chan(sc, ic->ic_ibss_chan); 4679 4680 /* turn radio LED on */ 4681 run_set_leds(sc, RT2860_LED_RADIO); 4682 4683 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 4684 struct run_rx_data *data = &sc->rxq.data[i]; 4685 4686 usbd_setup_xfer(data->xfer, sc->rxq.pipeh, data, data->buf, 4687 RUN_MAX_RXSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 4688 USBD_NO_TIMEOUT, run_rxeof); 4689 error = usbd_transfer(data->xfer); 4690 if (error != 0 && error != USBD_IN_PROGRESS) 4691 goto fail; 4692 } 4693 4694 if ((error = run_txrx_enable(sc)) != 0) 4695 goto fail; 4696 4697 ifp->if_flags |= IFF_RUNNING; 4698 ifq_clr_oactive(&ifp->if_snd); 4699 4700 if (ic->ic_flags & IEEE80211_F_WEPON) { 4701 /* install WEP keys */ 4702 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4703 (void)run_set_key(ic, NULL, &ic->ic_nw_keys[i]); 4704 } 4705 4706 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4707 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4708 else 4709 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4710 4711 if (error != 0) 4712 fail: run_stop(ifp, 1); 4713 return error; 4714 } 4715 4716 void 4717 run_stop(struct ifnet *ifp, int disable) 4718 { 4719 struct run_softc *sc = ifp->if_softc; 4720 struct ieee80211com *ic = &sc->sc_ic; 4721 uint32_t tmp; 4722 int s, ntries, qid; 4723 4724 if (ifp->if_flags & IFF_RUNNING) 4725 run_set_leds(sc, 0); /* turn all LEDs off */ 4726 4727 sc->sc_tx_timer = 0; 4728 ifp->if_timer = 0; 4729 ifp->if_flags &= ~IFF_RUNNING; 4730 ifq_clr_oactive(&ifp->if_snd); 4731 4732 timeout_del(&sc->scan_to); 4733 timeout_del(&sc->calib_to); 4734 4735 s = splusb(); 4736 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4737 /* wait for all queued asynchronous commands to complete */ 4738 usb_wait_task(sc->sc_udev, &sc->sc_task); 4739 splx(s); 4740 4741 /* Disable Tx/Rx DMA. */ 4742 run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp); 4743 tmp &= ~(RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 4744 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4745 4746 for (ntries = 0; ntries < 100; ntries++) { 4747 if (run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp) != 0) 4748 break; 4749 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4750 break; 4751 DELAY(10); 4752 } 4753 if (ntries == 100) { 4754 printf("%s: timeout waiting for DMA engine\n", 4755 sc->sc_dev.dv_xname); 4756 } 4757 4758 /* disable Tx/Rx */ 4759 run_read(sc, RT2860_MAC_SYS_CTRL, &tmp); 4760 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4761 run_write(sc, RT2860_MAC_SYS_CTRL, tmp); 4762 4763 /* wait for pending Tx to complete */ 4764 for (ntries = 0; ntries < 100; ntries++) { 4765 if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) 4766 break; 4767 if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) 4768 break; 4769 } 4770 DELAY(1000); 4771 run_write(sc, RT2860_USB_DMA_CFG, 0); 4772 4773 /* reset adapter */ 4774 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4775 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4776 4777 /* reset Tx and Rx rings */ 4778 sc->qfullmsk = 0; 4779 for (qid = 0; qid < 4; qid++) 4780 run_free_tx_ring(sc, qid); 4781 run_free_rx_ring(sc); 4782 } 4783