1 /* $OpenBSD: if_run.c,v 1.124 2017/10/26 15:00:28 mpi Exp $ */ 2 3 /*- 4 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2013-2014 Kevin Lo 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2700U/RT2800U/RT3000U/RT3900E chipset driver. 22 * http://www.ralinktech.com/ 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/timeout.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 #include <sys/endian.h> 37 38 #include <machine/intr.h> 39 40 #if NBPFILTER > 0 41 #include <net/bpf.h> 42 #endif 43 #include <net/if.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <netinet/in.h> 48 #include <netinet/if_ether.h> 49 50 #include <net80211/ieee80211_var.h> 51 #include <net80211/ieee80211_amrr.h> 52 #include <net80211/ieee80211_radiotap.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include <dev/usb/usbdevs.h> 58 59 #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ 60 #include <dev/usb/if_runvar.h> 61 62 #ifdef RUN_DEBUG 63 #define DPRINTF(x) do { if (run_debug) printf x; } while (0) 64 #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) 65 int run_debug = 0; 66 #else 67 #define DPRINTF(x) 68 #define DPRINTFN(n, x) 69 #endif 70 71 #define USB_ID(v, p) { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } 72 static const struct usb_devno run_devs[] = { 73 USB_ID(ABOCOM, RT2770), 74 USB_ID(ABOCOM, RT2870), 75 USB_ID(ABOCOM, RT3070), 76 USB_ID(ABOCOM, RT3071), 77 USB_ID(ABOCOM, RT3072), 78 USB_ID(ABOCOM2, RT2870_1), 79 USB_ID(ACCTON, RT2770), 80 USB_ID(ACCTON, RT2870_1), 81 USB_ID(ACCTON, RT2870_2), 82 USB_ID(ACCTON, RT2870_3), 83 USB_ID(ACCTON, RT2870_4), 84 USB_ID(ACCTON, RT2870_5), 85 USB_ID(ACCTON, RT3070), 86 USB_ID(ACCTON, RT3070_1), 87 USB_ID(ACCTON, RT3070_2), 88 USB_ID(ACCTON, RT3070_3), 89 USB_ID(ACCTON, RT3070_4), 90 USB_ID(ACCTON, RT3070_5), 91 USB_ID(ACCTON, RT3070_6), 92 USB_ID(AIRTIES, RT3070), 93 USB_ID(AIRTIES, RT3070_2), 94 USB_ID(ALLWIN, RT2070), 95 USB_ID(ALLWIN, RT2770), 96 USB_ID(ALLWIN, RT2870), 97 USB_ID(ALLWIN, RT3070), 98 USB_ID(ALLWIN, RT3071), 99 USB_ID(ALLWIN, RT3072), 100 USB_ID(ALLWIN, RT3572), 101 USB_ID(AMIGO, RT2870_1), 102 USB_ID(AMIGO, RT2870_2), 103 USB_ID(AMIT, CGWLUSB2GNR), 104 USB_ID(AMIT, RT2870_1), 105 USB_ID(AMIT2, RT2870), 106 USB_ID(ASUS, RT2870_1), 107 USB_ID(ASUS, RT2870_2), 108 USB_ID(ASUS, RT2870_3), 109 USB_ID(ASUS, RT2870_4), 110 USB_ID(ASUS, RT2870_5), 111 USB_ID(ASUS, RT3070_1), 112 USB_ID(ASUS, USBN13), 113 USB_ID(ASUS, USBN53), 114 USB_ID(ASUS, USBN66), 115 USB_ID(ASUS2, USBN11), 116 USB_ID(AZUREWAVE, RT2870_1), 117 USB_ID(AZUREWAVE, RT2870_2), 118 USB_ID(AZUREWAVE, RT3070_1), 119 USB_ID(AZUREWAVE, RT3070_2), 120 USB_ID(AZUREWAVE, RT3070_3), 121 USB_ID(AZUREWAVE, RT3070_4), 122 USB_ID(AZUREWAVE, RT3070_5), 123 USB_ID(BELKIN, F9L1103), 124 USB_ID(BELKIN, F5D8053V3), 125 USB_ID(BELKIN, F5D8055), 126 USB_ID(BELKIN, F5D8055V2), 127 USB_ID(BELKIN, F6D4050V1), 128 USB_ID(BELKIN, F6D4050V2), 129 USB_ID(BELKIN, F7D1101V2), 130 USB_ID(BELKIN, RT2870_1), 131 USB_ID(BELKIN, RT2870_2), 132 USB_ID(BEWAN, RT3070), 133 USB_ID(CISCOLINKSYS, AE1000), 134 USB_ID(CISCOLINKSYS, AM10), 135 USB_ID(CISCOLINKSYS2, RT3070), 136 USB_ID(CISCOLINKSYS3, RT3070), 137 USB_ID(CONCEPTRONIC2, RT2870_1), 138 USB_ID(CONCEPTRONIC2, RT2870_2), 139 USB_ID(CONCEPTRONIC2, RT2870_3), 140 USB_ID(CONCEPTRONIC2, RT2870_4), 141 USB_ID(CONCEPTRONIC2, RT2870_5), 142 USB_ID(CONCEPTRONIC2, RT2870_6), 143 USB_ID(CONCEPTRONIC2, RT2870_7), 144 USB_ID(CONCEPTRONIC2, RT2870_8), 145 USB_ID(CONCEPTRONIC2, RT3070_1), 146 USB_ID(CONCEPTRONIC2, RT3070_2), 147 USB_ID(CONCEPTRONIC2, RT3070_3), 148 USB_ID(CONCEPTRONIC2, VIGORN61), 149 USB_ID(COREGA, CGWLUSB300GNM), 150 USB_ID(COREGA, RT2870_1), 151 USB_ID(COREGA, RT2870_2), 152 USB_ID(COREGA, RT2870_3), 153 USB_ID(COREGA, RT3070), 154 USB_ID(CYBERTAN, RT2870), 155 USB_ID(DLINK, DWA127), 156 USB_ID(DLINK, DWA130F1), 157 USB_ID(DLINK, DWA137A1), 158 USB_ID(DLINK, DWA140B3), 159 USB_ID(DLINK, DWA140D1), 160 USB_ID(DLINK, DWA160B2), 161 USB_ID(DLINK, DWA162), 162 USB_ID(DLINK, RT2870), 163 USB_ID(DLINK, RT3072), 164 USB_ID(DLINK2, DWA130), 165 USB_ID(DLINK2, RT2870_1), 166 USB_ID(DLINK2, RT2870_2), 167 USB_ID(DLINK2, RT3070_1), 168 USB_ID(DLINK2, RT3070_2), 169 USB_ID(DLINK2, RT3070_3), 170 USB_ID(DLINK2, RT3070_4), 171 USB_ID(DLINK2, RT3070_5), 172 USB_ID(DLINK2, RT3072), 173 USB_ID(DLINK2, RT3072_1), 174 USB_ID(DVICO, RT3070), 175 USB_ID(EDIMAX, EW7717), 176 USB_ID(EDIMAX, EW7718), 177 USB_ID(EDIMAX, EW7722UTN), 178 USB_ID(EDIMAX, RT2870_1), 179 USB_ID(ENCORE, RT3070_1), 180 USB_ID(ENCORE, RT3070_2), 181 USB_ID(ENCORE, RT3070_3), 182 USB_ID(GIGABYTE, GNWB31N), 183 USB_ID(GIGABYTE, GNWB32L), 184 USB_ID(GIGABYTE, RT2870_1), 185 USB_ID(GIGASET, RT3070_1), 186 USB_ID(GIGASET, RT3070_2), 187 USB_ID(GUILLEMOT, HWNU300), 188 USB_ID(HAWKING, HWDN2), 189 USB_ID(HAWKING, HWUN2), 190 USB_ID(HAWKING, RT2870_1), 191 USB_ID(HAWKING, RT2870_2), 192 USB_ID(HAWKING, RT2870_3), 193 USB_ID(HAWKING, RT2870_4), 194 USB_ID(HAWKING, RT2870_5), 195 USB_ID(IODATA, RT3072_1), 196 USB_ID(IODATA, RT3072_2), 197 USB_ID(IODATA, RT3072_3), 198 USB_ID(IODATA, RT3072_4), 199 USB_ID(LINKSYS4, RT3070), 200 USB_ID(LINKSYS4, WUSB100), 201 USB_ID(LINKSYS4, WUSB54GCV3), 202 USB_ID(LINKSYS4, WUSB600N), 203 USB_ID(LINKSYS4, WUSB600NV2), 204 USB_ID(LOGITEC, LANW150NU2), 205 USB_ID(LOGITEC, LANW300NU2), 206 USB_ID(LOGITEC, LANW300NU2S), 207 USB_ID(LOGITEC, RT2870_1), 208 USB_ID(LOGITEC, RT2870_2), 209 USB_ID(LOGITEC, RT2870_3), 210 USB_ID(MELCO, RT2870_1), 211 USB_ID(MELCO, RT2870_2), 212 USB_ID(MELCO, WLIUCAG300N), 213 USB_ID(MELCO, WLIUCG300N), 214 USB_ID(MELCO, WLIUCG301N), 215 USB_ID(MELCO, WLIUCGN), 216 USB_ID(MELCO, WLIUCGNHP), 217 USB_ID(MELCO, WLIUCGNM), 218 USB_ID(MELCO, WLIUCGNM2), 219 USB_ID(MOTOROLA4, RT2770), 220 USB_ID(MOTOROLA4, RT3070), 221 USB_ID(MSI, RT3070_1), 222 USB_ID(MSI, RT3070_2), 223 USB_ID(MSI, RT3070_3), 224 USB_ID(MSI, RT3070_4), 225 USB_ID(MSI, RT3070_5), 226 USB_ID(MSI, RT3070_6), 227 USB_ID(MSI, RT3070_7), 228 USB_ID(MSI, RT3070_8), 229 USB_ID(MSI, RT3070_9), 230 USB_ID(MSI, RT3070_10), 231 USB_ID(MSI, RT3070_11), 232 USB_ID(MSI, RT3070_12), 233 USB_ID(MSI, RT3070_13), 234 USB_ID(MSI, RT3070_14), 235 USB_ID(MSI, RT3070_15), 236 USB_ID(OVISLINK, RT3071), 237 USB_ID(OVISLINK, RT3072), 238 USB_ID(PARA, RT3070), 239 USB_ID(PEGATRON, RT2870), 240 USB_ID(PEGATRON, RT3070), 241 USB_ID(PEGATRON, RT3070_2), 242 USB_ID(PEGATRON, RT3070_3), 243 USB_ID(PEGATRON, RT3072), 244 USB_ID(PHILIPS, RT2870), 245 USB_ID(PLANEX2, GWUS300MINIS), 246 USB_ID(PLANEX2, GWUSMICRO300), 247 USB_ID(PLANEX2, GWUSMICRON), 248 USB_ID(PLANEX2, RT2870), 249 USB_ID(PLANEX2, RT3070), 250 USB_ID(QCOM, RT2870), 251 USB_ID(QUANTA, RT3070), 252 USB_ID(RALINK, RT2070), 253 USB_ID(RALINK, RT2770), 254 USB_ID(RALINK, RT2870), 255 USB_ID(RALINK, RT3070), 256 USB_ID(RALINK, RT3071), 257 USB_ID(RALINK, RT3072), 258 USB_ID(RALINK, RT3370), 259 USB_ID(RALINK, RT3572), 260 USB_ID(RALINK, RT3573), 261 USB_ID(RALINK, RT5370), 262 USB_ID(RALINK, RT5572), 263 USB_ID(RALINK, RT8070), 264 USB_ID(SAMSUNG, WIS09ABGN), 265 USB_ID(SAMSUNG2, RT2870_1), 266 USB_ID(SENAO, RT2870_1), 267 USB_ID(SENAO, RT2870_2), 268 USB_ID(SENAO, RT2870_3), 269 USB_ID(SENAO, RT2870_4), 270 USB_ID(SENAO, RT3070), 271 USB_ID(SENAO, RT3071), 272 USB_ID(SENAO, RT3072_1), 273 USB_ID(SENAO, RT3072_2), 274 USB_ID(SENAO, RT3072_3), 275 USB_ID(SENAO, RT3072_4), 276 USB_ID(SENAO, RT3072_5), 277 USB_ID(SITECOMEU, WL302), 278 USB_ID(SITECOMEU, WL315), 279 USB_ID(SITECOMEU, WL321), 280 USB_ID(SITECOMEU, RT3070_3), 281 USB_ID(SITECOMEU, WL302), 282 USB_ID(SITECOMEU, WL344), 283 USB_ID(SITECOMEU, WL329), 284 USB_ID(SITECOMEU, WL345), 285 USB_ID(SITECOMEU, RT2870_1), 286 USB_ID(SITECOMEU, RT2870_2), 287 USB_ID(SITECOMEU, RT2870_3), 288 USB_ID(SITECOMEU, RT3070_1), 289 USB_ID(SITECOMEU, RT3072_3), 290 USB_ID(SITECOMEU, RT3072_4), 291 USB_ID(SITECOMEU, RT3072_5), 292 USB_ID(SITECOMEU, RT3072_6), 293 USB_ID(SITECOMEU, WL302), 294 USB_ID(SITECOMEU, WL315), 295 USB_ID(SITECOMEU, WL321), 296 USB_ID(SITECOMEU, WL324), 297 USB_ID(SITECOMEU, WL329), 298 USB_ID(SITECOMEU, WL343), 299 USB_ID(SITECOMEU, WL344), 300 USB_ID(SITECOMEU, WL345), 301 USB_ID(SITECOMEU, WL349V4), 302 USB_ID(SITECOMEU, WL608), 303 USB_ID(SITECOMEU, WLA4000), 304 USB_ID(SITECOMEU, WLA5000), 305 USB_ID(SPARKLAN, RT2870_1), 306 USB_ID(SPARKLAN, RT2870_2), 307 USB_ID(SPARKLAN, RT3070), 308 USB_ID(SWEEX2, LW153), 309 USB_ID(SWEEX2, LW303), 310 USB_ID(SWEEX2, LW313), 311 USB_ID(TOSHIBA, RT3070), 312 USB_ID(UMEDIA, RT2870_1), 313 USB_ID(UMEDIA, TEW645UB), 314 USB_ID(ZCOM, RT2870_1), 315 USB_ID(ZCOM, RT2870_2), 316 USB_ID(ZINWELL, RT2870_1), 317 USB_ID(ZINWELL, RT2870_2), 318 USB_ID(ZINWELL, RT3070), 319 USB_ID(ZINWELL, RT3072_1), 320 USB_ID(ZINWELL, RT3072_2), 321 USB_ID(ZYXEL, NWD2105), 322 USB_ID(ZYXEL, NWD211AN), 323 USB_ID(ZYXEL, RT2870_1), 324 USB_ID(ZYXEL, RT2870_2), 325 USB_ID(ZYXEL, RT3070) 326 }; 327 328 int run_match(struct device *, void *, void *); 329 void run_attach(struct device *, struct device *, void *); 330 int run_detach(struct device *, int); 331 int run_alloc_rx_ring(struct run_softc *); 332 void run_free_rx_ring(struct run_softc *); 333 int run_alloc_tx_ring(struct run_softc *, int); 334 void run_free_tx_ring(struct run_softc *, int); 335 int run_load_microcode(struct run_softc *); 336 int run_reset(struct run_softc *); 337 int run_read(struct run_softc *, uint16_t, uint32_t *); 338 int run_read_region_1(struct run_softc *, uint16_t, uint8_t *, 339 int); 340 int run_write_2(struct run_softc *, uint16_t, uint16_t); 341 int run_write(struct run_softc *, uint16_t, uint32_t); 342 int run_write_region_1(struct run_softc *, uint16_t, 343 const uint8_t *, int); 344 int run_set_region_4(struct run_softc *, uint16_t, uint32_t, int); 345 int run_efuse_read(struct run_softc *, uint16_t, uint16_t *); 346 int run_efuse_read_2(struct run_softc *, uint16_t, uint16_t *); 347 int run_eeprom_read_2(struct run_softc *, uint16_t, uint16_t *); 348 int run_rt2870_rf_write(struct run_softc *, uint8_t, uint32_t); 349 int run_rt3070_rf_read(struct run_softc *, uint8_t, uint8_t *); 350 int run_rt3070_rf_write(struct run_softc *, uint8_t, uint8_t); 351 int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); 352 int run_bbp_write(struct run_softc *, uint8_t, uint8_t); 353 int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); 354 const char * run_get_rf(int); 355 void run_get_txpower(struct run_softc *); 356 void run_rt3593_get_txpower(struct run_softc *); 357 int run_read_eeprom(struct run_softc *); 358 struct ieee80211_node *run_node_alloc(struct ieee80211com *); 359 int run_media_change(struct ifnet *); 360 void run_next_scan(void *); 361 void run_task(void *); 362 void run_do_async(struct run_softc *, void (*)(struct run_softc *, 363 void *), void *, int); 364 int run_newstate(struct ieee80211com *, enum ieee80211_state, int); 365 void run_newstate_cb(struct run_softc *, void *); 366 void run_updateedca(struct ieee80211com *); 367 void run_updateedca_cb(struct run_softc *, void *); 368 int run_set_key(struct ieee80211com *, struct ieee80211_node *, 369 struct ieee80211_key *); 370 void run_set_key_cb(struct run_softc *, void *); 371 void run_delete_key(struct ieee80211com *, struct ieee80211_node *, 372 struct ieee80211_key *); 373 void run_delete_key_cb(struct run_softc *, void *); 374 void run_calibrate_to(void *); 375 void run_calibrate_cb(struct run_softc *, void *); 376 void run_newassoc(struct ieee80211com *, struct ieee80211_node *, 377 int); 378 void run_rx_frame(struct run_softc *, uint8_t *, int); 379 void run_rxeof(struct usbd_xfer *, void *, usbd_status); 380 void run_txeof(struct usbd_xfer *, void *, usbd_status); 381 int run_tx(struct run_softc *, struct mbuf *, 382 struct ieee80211_node *); 383 void run_start(struct ifnet *); 384 void run_watchdog(struct ifnet *); 385 int run_ioctl(struct ifnet *, u_long, caddr_t); 386 void run_iq_calib(struct run_softc *, u_int); 387 void run_select_chan_group(struct run_softc *, int); 388 void run_set_agc(struct run_softc *, uint8_t); 389 void run_set_rx_antenna(struct run_softc *, int); 390 void run_rt2870_set_chan(struct run_softc *, u_int); 391 void run_rt3070_set_chan(struct run_softc *, u_int); 392 void run_rt3572_set_chan(struct run_softc *, u_int); 393 void run_rt3593_set_chan(struct run_softc *, u_int); 394 void run_rt5390_set_chan(struct run_softc *, u_int); 395 void run_rt5592_set_chan(struct run_softc *, u_int); 396 int run_set_chan(struct run_softc *, struct ieee80211_channel *); 397 void run_enable_tsf_sync(struct run_softc *); 398 void run_enable_mrr(struct run_softc *); 399 void run_set_txpreamble(struct run_softc *); 400 void run_set_basicrates(struct run_softc *); 401 void run_set_leds(struct run_softc *, uint16_t); 402 void run_set_bssid(struct run_softc *, const uint8_t *); 403 void run_set_macaddr(struct run_softc *, const uint8_t *); 404 void run_updateslot(struct ieee80211com *); 405 void run_updateslot_cb(struct run_softc *, void *); 406 #if NBPFILTER > 0 407 int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); 408 #endif 409 void run_rt5390_bbp_init(struct run_softc *); 410 int run_bbp_init(struct run_softc *); 411 int run_rt3070_rf_init(struct run_softc *); 412 void run_rt3593_rf_init(struct run_softc *); 413 void run_rt5390_rf_init(struct run_softc *); 414 int run_rt3070_filter_calib(struct run_softc *, uint8_t, uint8_t, 415 uint8_t *); 416 void run_rt3070_rf_setup(struct run_softc *); 417 void run_rt3593_rf_setup(struct run_softc *); 418 void run_rt5390_rf_setup(struct run_softc *); 419 int run_txrx_enable(struct run_softc *); 420 void run_adjust_freq_offset(struct run_softc *); 421 int run_init(struct ifnet *); 422 void run_stop(struct ifnet *, int); 423 424 struct cfdriver run_cd = { 425 NULL, "run", DV_IFNET 426 }; 427 428 const struct cfattach run_ca = { 429 sizeof (struct run_softc), run_match, run_attach, run_detach 430 }; 431 432 static const struct { 433 uint32_t reg; 434 uint32_t val; 435 } rt2870_def_mac[] = { 436 RT2870_DEF_MAC 437 }; 438 439 static const struct { 440 uint8_t reg; 441 uint8_t val; 442 } rt2860_def_bbp[] = { 443 RT2860_DEF_BBP 444 },rt5390_def_bbp[] = { 445 RT5390_DEF_BBP 446 },rt5592_def_bbp[] = { 447 RT5592_DEF_BBP 448 }; 449 450 /* 451 * Default values for BBP register R196 for RT5592. 452 */ 453 static const uint8_t rt5592_bbp_r196[] = { 454 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, 455 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, 456 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, 457 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, 458 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, 459 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 460 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 461 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, 462 0x2e, 0x36, 0x30, 0x6e 463 }; 464 465 static const struct rfprog { 466 uint8_t chan; 467 uint32_t r1, r2, r3, r4; 468 } rt2860_rf2850[] = { 469 RT2860_RF2850 470 }; 471 472 struct { 473 uint8_t n, r, k; 474 } rt3070_freqs[] = { 475 RT3070_RF3052 476 }; 477 478 static const struct rt5592_freqs { 479 uint16_t n; 480 uint8_t k, m, r; 481 } rt5592_freqs_20mhz[] = { 482 RT5592_RF5592_20MHZ 483 },rt5592_freqs_40mhz[] = { 484 RT5592_RF5592_40MHZ 485 }; 486 487 static const struct { 488 uint8_t reg; 489 uint8_t val; 490 } rt3070_def_rf[] = { 491 RT3070_DEF_RF 492 },rt3572_def_rf[] = { 493 RT3572_DEF_RF 494 },rt3593_def_rf[] = { 495 RT3593_DEF_RF 496 },rt5390_def_rf[] = { 497 RT5390_DEF_RF 498 },rt5392_def_rf[] = { 499 RT5392_DEF_RF 500 },rt5592_def_rf[] = { 501 RT5592_DEF_RF 502 },rt5592_2ghz_def_rf[] = { 503 RT5592_2GHZ_DEF_RF 504 },rt5592_5ghz_def_rf[] = { 505 RT5592_5GHZ_DEF_RF 506 }; 507 508 static const struct { 509 u_int firstchan; 510 u_int lastchan; 511 uint8_t reg; 512 uint8_t val; 513 } rt5592_chan_5ghz[] = { 514 RT5592_CHAN_5GHZ 515 }; 516 517 int 518 run_match(struct device *parent, void *match, void *aux) 519 { 520 struct usb_attach_arg *uaa = aux; 521 522 if (uaa->iface == NULL || uaa->configno != 1) 523 return UMATCH_NONE; 524 525 return (usb_lookup(run_devs, uaa->vendor, uaa->product) != NULL) ? 526 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE; 527 } 528 529 void 530 run_attach(struct device *parent, struct device *self, void *aux) 531 { 532 struct run_softc *sc = (struct run_softc *)self; 533 struct usb_attach_arg *uaa = aux; 534 struct ieee80211com *ic = &sc->sc_ic; 535 struct ifnet *ifp = &ic->ic_if; 536 usb_interface_descriptor_t *id; 537 usb_endpoint_descriptor_t *ed; 538 int i, nrx, ntx, ntries; 539 uint32_t ver; 540 541 sc->sc_udev = uaa->device; 542 sc->sc_iface = uaa->iface; 543 544 /* 545 * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX 546 * and 6 for TX (4 EDCAs + HCCA + Prio). 547 * Update 03-14-2009: some devices like the Planex GW-US300MiniS 548 * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). 549 */ 550 nrx = ntx = 0; 551 id = usbd_get_interface_descriptor(sc->sc_iface); 552 for (i = 0; i < id->bNumEndpoints; i++) { 553 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 554 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 555 continue; 556 557 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 558 sc->rxq.pipe_no = ed->bEndpointAddress; 559 nrx++; 560 } else if (ntx < 4) { 561 sc->txq[ntx].pipe_no = ed->bEndpointAddress; 562 ntx++; 563 } 564 } 565 /* make sure we've got them all */ 566 if (nrx < 1 || ntx < 4) { 567 printf("%s: missing endpoint\n", sc->sc_dev.dv_xname); 568 return; 569 } 570 571 usb_init_task(&sc->sc_task, run_task, sc, USB_TASK_TYPE_GENERIC); 572 timeout_set(&sc->scan_to, run_next_scan, sc); 573 timeout_set(&sc->calib_to, run_calibrate_to, sc); 574 575 sc->amrr.amrr_min_success_threshold = 1; 576 sc->amrr.amrr_max_success_threshold = 10; 577 578 /* wait for the chip to settle */ 579 for (ntries = 0; ntries < 100; ntries++) { 580 if (run_read(sc, RT2860_ASIC_VER_ID, &ver) != 0) 581 return; 582 if (ver != 0 && ver != 0xffffffff) 583 break; 584 DELAY(10); 585 } 586 if (ntries == 100) { 587 printf("%s: timeout waiting for NIC to initialize\n", 588 sc->sc_dev.dv_xname); 589 return; 590 } 591 sc->mac_ver = ver >> 16; 592 sc->mac_rev = ver & 0xffff; 593 594 /* retrieve RF rev. no and various other things from EEPROM */ 595 run_read_eeprom(sc); 596 597 printf("%s: MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), " 598 "address %s\n", sc->sc_dev.dv_xname, sc->mac_ver, 599 sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, 600 sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 601 602 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 603 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 604 ic->ic_state = IEEE80211_S_INIT; 605 606 /* set device capabilities */ 607 ic->ic_caps = 608 IEEE80211_C_MONITOR | /* monitor mode supported */ 609 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 610 IEEE80211_C_SHSLOT | /* short slot time supported */ 611 IEEE80211_C_WEP | /* WEP */ 612 IEEE80211_C_RSN; /* WPA/RSN */ 613 614 if (sc->rf_rev == RT2860_RF_2750 || 615 sc->rf_rev == RT2860_RF_2850 || 616 sc->rf_rev == RT3070_RF_3052 || 617 sc->rf_rev == RT3070_RF_3053 || 618 sc->rf_rev == RT5592_RF_5592) { 619 /* set supported .11a rates */ 620 ic->ic_sup_rates[IEEE80211_MODE_11A] = 621 ieee80211_std_rateset_11a; 622 623 /* set supported .11a channels */ 624 for (i = 14; i < nitems(rt2860_rf2850); i++) { 625 uint8_t chan = rt2860_rf2850[i].chan; 626 ic->ic_channels[chan].ic_freq = 627 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 628 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 629 } 630 } 631 632 /* set supported .11b and .11g rates */ 633 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 634 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 635 636 /* set supported .11b and .11g channels (1 through 14) */ 637 for (i = 1; i <= 14; i++) { 638 ic->ic_channels[i].ic_freq = 639 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 640 ic->ic_channels[i].ic_flags = 641 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 642 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 643 } 644 645 ifp->if_softc = sc; 646 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 647 ifp->if_ioctl = run_ioctl; 648 ifp->if_start = run_start; 649 ifp->if_watchdog = run_watchdog; 650 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 651 652 if_attach(ifp); 653 ieee80211_ifattach(ifp); 654 ic->ic_node_alloc = run_node_alloc; 655 ic->ic_newassoc = run_newassoc; 656 ic->ic_updateslot = run_updateslot; 657 ic->ic_updateedca = run_updateedca; 658 ic->ic_set_key = run_set_key; 659 ic->ic_delete_key = run_delete_key; 660 /* override state transition machine */ 661 sc->sc_newstate = ic->ic_newstate; 662 ic->ic_newstate = run_newstate; 663 ieee80211_media_init(ifp, run_media_change, ieee80211_media_status); 664 665 #if NBPFILTER > 0 666 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 667 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 668 669 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 670 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 671 sc->sc_rxtap.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT); 672 673 sc->sc_txtap_len = sizeof sc->sc_txtapu; 674 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 675 sc->sc_txtap.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT); 676 #endif 677 } 678 679 int 680 run_detach(struct device *self, int flags) 681 { 682 struct run_softc *sc = (struct run_softc *)self; 683 struct ifnet *ifp = &sc->sc_ic.ic_if; 684 int qid, s; 685 686 s = splusb(); 687 688 if (timeout_initialized(&sc->scan_to)) 689 timeout_del(&sc->scan_to); 690 if (timeout_initialized(&sc->calib_to)) 691 timeout_del(&sc->calib_to); 692 693 /* wait for all queued asynchronous commands to complete */ 694 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 695 696 usbd_ref_wait(sc->sc_udev); 697 698 if (ifp->if_softc != NULL) { 699 ifp->if_flags &= ~IFF_RUNNING; 700 ifq_clr_oactive(&ifp->if_snd); 701 ieee80211_ifdetach(ifp); 702 if_detach(ifp); 703 } 704 705 for (qid = 0; qid < 4; qid++) 706 run_free_tx_ring(sc, qid); 707 run_free_rx_ring(sc); 708 709 splx(s); 710 711 return 0; 712 } 713 714 int 715 run_alloc_rx_ring(struct run_softc *sc) 716 { 717 struct run_rx_ring *rxq = &sc->rxq; 718 int i, error; 719 720 error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); 721 if (error != 0) 722 goto fail; 723 724 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 725 struct run_rx_data *data = &rxq->data[i]; 726 727 data->sc = sc; /* backpointer for callbacks */ 728 729 data->xfer = usbd_alloc_xfer(sc->sc_udev); 730 if (data->xfer == NULL) { 731 error = ENOMEM; 732 goto fail; 733 } 734 data->buf = usbd_alloc_buffer(data->xfer, RUN_MAX_RXSZ); 735 if (data->buf == NULL) { 736 error = ENOMEM; 737 goto fail; 738 } 739 } 740 if (error != 0) 741 fail: run_free_rx_ring(sc); 742 return error; 743 } 744 745 void 746 run_free_rx_ring(struct run_softc *sc) 747 { 748 struct run_rx_ring *rxq = &sc->rxq; 749 int i; 750 751 if (rxq->pipeh != NULL) { 752 usbd_abort_pipe(rxq->pipeh); 753 usbd_close_pipe(rxq->pipeh); 754 rxq->pipeh = NULL; 755 } 756 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 757 if (rxq->data[i].xfer != NULL) 758 usbd_free_xfer(rxq->data[i].xfer); 759 rxq->data[i].xfer = NULL; 760 } 761 } 762 763 int 764 run_alloc_tx_ring(struct run_softc *sc, int qid) 765 { 766 struct run_tx_ring *txq = &sc->txq[qid]; 767 int i, error; 768 uint16_t txwisize; 769 770 txwisize = sizeof(struct rt2860_txwi); 771 if (sc->mac_ver == 0x5592) 772 txwisize += sizeof(uint32_t); 773 774 txq->cur = txq->queued = 0; 775 776 error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); 777 if (error != 0) 778 goto fail; 779 780 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 781 struct run_tx_data *data = &txq->data[i]; 782 783 data->sc = sc; /* backpointer for callbacks */ 784 data->qid = qid; 785 786 data->xfer = usbd_alloc_xfer(sc->sc_udev); 787 if (data->xfer == NULL) { 788 error = ENOMEM; 789 goto fail; 790 } 791 data->buf = usbd_alloc_buffer(data->xfer, RUN_MAX_TXSZ); 792 if (data->buf == NULL) { 793 error = ENOMEM; 794 goto fail; 795 } 796 /* zeroize the TXD + TXWI part */ 797 memset(data->buf, 0, sizeof(struct rt2870_txd) + txwisize); 798 } 799 if (error != 0) 800 fail: run_free_tx_ring(sc, qid); 801 return error; 802 } 803 804 void 805 run_free_tx_ring(struct run_softc *sc, int qid) 806 { 807 struct run_tx_ring *txq = &sc->txq[qid]; 808 int i; 809 810 if (txq->pipeh != NULL) { 811 usbd_abort_pipe(txq->pipeh); 812 usbd_close_pipe(txq->pipeh); 813 txq->pipeh = NULL; 814 } 815 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 816 if (txq->data[i].xfer != NULL) 817 usbd_free_xfer(txq->data[i].xfer); 818 txq->data[i].xfer = NULL; 819 } 820 } 821 822 int 823 run_load_microcode(struct run_softc *sc) 824 { 825 usb_device_request_t req; 826 const char *fwname; 827 u_char *ucode; 828 size_t size; 829 uint32_t tmp; 830 int ntries, error; 831 832 /* RT3071/RT3072 use a different firmware */ 833 if (sc->mac_ver != 0x2860 && 834 sc->mac_ver != 0x2872 && 835 sc->mac_ver != 0x3070) 836 fwname = "run-rt3071"; 837 else 838 fwname = "run-rt2870"; 839 840 if ((error = loadfirmware(fwname, &ucode, &size)) != 0) { 841 printf("%s: failed loadfirmware of file %s (error %d)\n", 842 sc->sc_dev.dv_xname, fwname, error); 843 return error; 844 } 845 if (size != 4096) { 846 printf("%s: invalid firmware size (should be 4KB)\n", 847 sc->sc_dev.dv_xname); 848 free(ucode, M_DEVBUF, size); 849 return EINVAL; 850 } 851 852 /* write microcode image */ 853 run_write_region_1(sc, RT2870_FW_BASE, ucode, size); 854 free(ucode, M_DEVBUF, size); 855 run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 856 run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 857 858 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 859 req.bRequest = RT2870_RESET; 860 USETW(req.wValue, 8); 861 USETW(req.wIndex, 0); 862 USETW(req.wLength, 0); 863 if ((error = usbd_do_request(sc->sc_udev, &req, NULL)) != 0) 864 return error; 865 866 usbd_delay_ms(sc->sc_udev, 10); 867 run_write(sc, RT2860_H2M_BBPAGENT, 0); 868 run_write(sc, RT2860_H2M_MAILBOX, 0); 869 run_write(sc, RT2860_H2M_INTSRC, 0); 870 if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) 871 return error; 872 873 /* wait until microcontroller is ready */ 874 for (ntries = 0; ntries < 1000; ntries++) { 875 if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) 876 return error; 877 if (tmp & RT2860_MCU_READY) 878 break; 879 DELAY(1000); 880 } 881 if (ntries == 1000) { 882 printf("%s: timeout waiting for MCU to initialize\n", 883 sc->sc_dev.dv_xname); 884 return ETIMEDOUT; 885 } 886 DPRINTF(("microcode successfully loaded after %d tries\n", ntries)); 887 return 0; 888 } 889 890 int 891 run_reset(struct run_softc *sc) 892 { 893 usb_device_request_t req; 894 895 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 896 req.bRequest = RT2870_RESET; 897 USETW(req.wValue, 1); 898 USETW(req.wIndex, 0); 899 USETW(req.wLength, 0); 900 return usbd_do_request(sc->sc_udev, &req, NULL); 901 } 902 903 int 904 run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) 905 { 906 uint32_t tmp; 907 int error; 908 909 error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp); 910 if (error == 0) 911 *val = letoh32(tmp); 912 else 913 *val = 0xffffffff; 914 return error; 915 } 916 917 int 918 run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) 919 { 920 usb_device_request_t req; 921 922 req.bmRequestType = UT_READ_VENDOR_DEVICE; 923 req.bRequest = RT2870_READ_REGION_1; 924 USETW(req.wValue, 0); 925 USETW(req.wIndex, reg); 926 USETW(req.wLength, len); 927 return usbd_do_request(sc->sc_udev, &req, buf); 928 } 929 930 int 931 run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) 932 { 933 usb_device_request_t req; 934 935 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 936 req.bRequest = RT2870_WRITE_2; 937 USETW(req.wValue, val); 938 USETW(req.wIndex, reg); 939 USETW(req.wLength, 0); 940 return usbd_do_request(sc->sc_udev, &req, NULL); 941 } 942 943 int 944 run_write(struct run_softc *sc, uint16_t reg, uint32_t val) 945 { 946 int error; 947 948 if ((error = run_write_2(sc, reg, val & 0xffff)) == 0) 949 error = run_write_2(sc, reg + 2, val >> 16); 950 return error; 951 } 952 953 int 954 run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, 955 int len) 956 { 957 #if 1 958 int i, error = 0; 959 /* 960 * NB: the WRITE_REGION_1 command is not stable on RT2860. 961 * We thus issue multiple WRITE_2 commands instead. 962 */ 963 KASSERT((len & 1) == 0); 964 for (i = 0; i < len && error == 0; i += 2) 965 error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); 966 return error; 967 #else 968 usb_device_request_t req; 969 970 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 971 req.bRequest = RT2870_WRITE_REGION_1; 972 USETW(req.wValue, 0); 973 USETW(req.wIndex, reg); 974 USETW(req.wLength, len); 975 return usbd_do_request(sc->sc_udev, &req, buf); 976 #endif 977 } 978 979 int 980 run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) 981 { 982 int error = 0; 983 984 for (; count > 0 && error == 0; count--, reg += 4) 985 error = run_write(sc, reg, val); 986 return error; 987 } 988 989 /* Read 16-bit from eFUSE ROM. */ 990 int 991 run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 992 { 993 uint32_t tmp; 994 uint16_t reg; 995 int error, ntries; 996 997 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 998 return error; 999 1000 /*- 1001 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1002 * DATA0: F E D C 1003 * DATA1: B A 9 8 1004 * DATA2: 7 6 5 4 1005 * DATA3: 3 2 1 0 1006 */ 1007 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1008 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1009 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1010 for (ntries = 0; ntries < 100; ntries++) { 1011 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1012 return error; 1013 if (!(tmp & RT3070_EFSROM_KICK)) 1014 break; 1015 DELAY(2); 1016 } 1017 if (ntries == 100) 1018 return ETIMEDOUT; 1019 1020 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1021 *val = 0xffff; /* address not found */ 1022 return 0; 1023 } 1024 /* determine to which 32-bit register our 16-bit word belongs */ 1025 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1026 if ((error = run_read(sc, reg, &tmp)) != 0) 1027 return error; 1028 1029 tmp >>= (8 * (addr & 0x3)); 1030 *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; 1031 return 0; 1032 } 1033 1034 /* Read 16-bit from eFUSE ROM for RT3xxx. */ 1035 int 1036 run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1037 { 1038 uint32_t tmp; 1039 uint16_t reg; 1040 int error, ntries; 1041 1042 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1043 return error; 1044 1045 addr *= 2; 1046 /*- 1047 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1048 * DATA0: F E D C 1049 * DATA1: B A 9 8 1050 * DATA2: 7 6 5 4 1051 * DATA3: 3 2 1 0 1052 */ 1053 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1054 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1055 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1056 for (ntries = 0; ntries < 100; ntries++) { 1057 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1058 return error; 1059 if (!(tmp & RT3070_EFSROM_KICK)) 1060 break; 1061 DELAY(2); 1062 } 1063 if (ntries == 100) 1064 return ETIMEDOUT; 1065 1066 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1067 *val = 0xffff; /* address not found */ 1068 return 0; 1069 } 1070 /* determine to which 32-bit register our 16-bit word belongs */ 1071 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1072 if ((error = run_read(sc, reg, &tmp)) != 0) 1073 return error; 1074 1075 *val = (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1076 return 0; 1077 } 1078 1079 int 1080 run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1081 { 1082 usb_device_request_t req; 1083 uint16_t tmp; 1084 int error; 1085 1086 addr *= 2; 1087 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1088 req.bRequest = RT2870_EEPROM_READ; 1089 USETW(req.wValue, 0); 1090 USETW(req.wIndex, addr); 1091 USETW(req.wLength, sizeof tmp); 1092 error = usbd_do_request(sc->sc_udev, &req, &tmp); 1093 if (error == 0) 1094 *val = letoh16(tmp); 1095 else 1096 *val = 0xffff; 1097 return error; 1098 } 1099 1100 static __inline int 1101 run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 1102 { 1103 /* either eFUSE ROM or EEPROM */ 1104 return sc->sc_srom_read(sc, addr, val); 1105 } 1106 1107 int 1108 run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) 1109 { 1110 uint32_t tmp; 1111 int error, ntries; 1112 1113 for (ntries = 0; ntries < 10; ntries++) { 1114 if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0) 1115 return error; 1116 if (!(tmp & RT2860_RF_REG_CTRL)) 1117 break; 1118 } 1119 if (ntries == 10) 1120 return ETIMEDOUT; 1121 1122 /* RF registers are 24-bit on the RT2860 */ 1123 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1124 (val & 0x3fffff) << 2 | (reg & 3); 1125 return run_write(sc, RT2860_RF_CSR_CFG0, tmp); 1126 } 1127 1128 int 1129 run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1130 { 1131 uint32_t tmp; 1132 int error, ntries; 1133 1134 for (ntries = 0; ntries < 100; ntries++) { 1135 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1136 return error; 1137 if (!(tmp & RT3070_RF_KICK)) 1138 break; 1139 } 1140 if (ntries == 100) 1141 return ETIMEDOUT; 1142 1143 tmp = RT3070_RF_KICK | reg << 8; 1144 if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0) 1145 return error; 1146 1147 for (ntries = 0; ntries < 100; ntries++) { 1148 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1149 return error; 1150 if (!(tmp & RT3070_RF_KICK)) 1151 break; 1152 } 1153 if (ntries == 100) 1154 return ETIMEDOUT; 1155 1156 *val = tmp & 0xff; 1157 return 0; 1158 } 1159 1160 int 1161 run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1162 { 1163 uint32_t tmp; 1164 int error, ntries; 1165 1166 for (ntries = 0; ntries < 10; ntries++) { 1167 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1168 return error; 1169 if (!(tmp & RT3070_RF_KICK)) 1170 break; 1171 } 1172 if (ntries == 10) 1173 return ETIMEDOUT; 1174 1175 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 1176 return run_write(sc, RT3070_RF_CSR_CFG, tmp); 1177 } 1178 1179 int 1180 run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1181 { 1182 uint32_t tmp; 1183 int ntries, error; 1184 1185 for (ntries = 0; ntries < 10; ntries++) { 1186 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1187 return error; 1188 if (!(tmp & RT2860_BBP_CSR_KICK)) 1189 break; 1190 } 1191 if (ntries == 10) 1192 return ETIMEDOUT; 1193 1194 tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8; 1195 if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0) 1196 return error; 1197 1198 for (ntries = 0; ntries < 10; ntries++) { 1199 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1200 return error; 1201 if (!(tmp & RT2860_BBP_CSR_KICK)) 1202 break; 1203 } 1204 if (ntries == 10) 1205 return ETIMEDOUT; 1206 1207 *val = tmp & 0xff; 1208 return 0; 1209 } 1210 1211 int 1212 run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1213 { 1214 uint32_t tmp; 1215 int ntries, error; 1216 1217 for (ntries = 0; ntries < 10; ntries++) { 1218 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1219 return error; 1220 if (!(tmp & RT2860_BBP_CSR_KICK)) 1221 break; 1222 } 1223 if (ntries == 10) 1224 return ETIMEDOUT; 1225 1226 tmp = RT2860_BBP_CSR_KICK | reg << 8 | val; 1227 return run_write(sc, RT2860_BBP_CSR_CFG, tmp); 1228 } 1229 1230 /* 1231 * Send a command to the 8051 microcontroller unit. 1232 */ 1233 int 1234 run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) 1235 { 1236 uint32_t tmp; 1237 int error, ntries; 1238 1239 for (ntries = 0; ntries < 100; ntries++) { 1240 if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0) 1241 return error; 1242 if (!(tmp & RT2860_H2M_BUSY)) 1243 break; 1244 } 1245 if (ntries == 100) 1246 return ETIMEDOUT; 1247 1248 tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg; 1249 if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0) 1250 error = run_write(sc, RT2860_HOST_CMD, cmd); 1251 return error; 1252 } 1253 1254 /* 1255 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 1256 * Used to adjust per-rate Tx power registers. 1257 */ 1258 static __inline uint32_t 1259 b4inc(uint32_t b32, int8_t delta) 1260 { 1261 int8_t i, b4; 1262 1263 for (i = 0; i < 8; i++) { 1264 b4 = b32 & 0xf; 1265 b4 += delta; 1266 if (b4 < 0) 1267 b4 = 0; 1268 else if (b4 > 0xf) 1269 b4 = 0xf; 1270 b32 = b32 >> 4 | b4 << 28; 1271 } 1272 return b32; 1273 } 1274 1275 const char * 1276 run_get_rf(int rev) 1277 { 1278 switch (rev) { 1279 case RT2860_RF_2820: return "RT2820"; 1280 case RT2860_RF_2850: return "RT2850"; 1281 case RT2860_RF_2720: return "RT2720"; 1282 case RT2860_RF_2750: return "RT2750"; 1283 case RT3070_RF_3020: return "RT3020"; 1284 case RT3070_RF_2020: return "RT2020"; 1285 case RT3070_RF_3021: return "RT3021"; 1286 case RT3070_RF_3022: return "RT3022"; 1287 case RT3070_RF_3052: return "RT3052"; 1288 case RT3070_RF_3053: return "RT3053"; 1289 case RT5592_RF_5592: return "RT5592"; 1290 case RT5390_RF_5370: return "RT5370"; 1291 case RT5390_RF_5372: return "RT5372"; 1292 } 1293 return "unknown"; 1294 } 1295 1296 void 1297 run_rt3593_get_txpower(struct run_softc *sc) 1298 { 1299 uint16_t addr, val; 1300 int i; 1301 1302 /* Read power settings for 2GHz channels. */ 1303 for (i = 0; i < 14; i += 2) { 1304 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : 1305 RT2860_EEPROM_PWR2GHZ_BASE1; 1306 run_srom_read(sc, addr + i / 2, &val); 1307 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1308 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1309 1310 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : 1311 RT2860_EEPROM_PWR2GHZ_BASE2; 1312 run_srom_read(sc, addr + i / 2, &val); 1313 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1314 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1315 1316 if (sc->ntxchains == 3) { 1317 run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, 1318 &val); 1319 sc->txpow3[i + 0] = (int8_t)(val & 0xff); 1320 sc->txpow3[i + 1] = (int8_t)(val >> 8); 1321 } 1322 } 1323 /* Fix broken Tx power entries. */ 1324 for (i = 0; i < 14; i++) { 1325 if (sc->txpow1[i] > 31) 1326 sc->txpow1[i] = 5; 1327 if (sc->txpow2[i] > 31) 1328 sc->txpow2[i] = 5; 1329 if (sc->ntxchains == 3) { 1330 if (sc->txpow3[i] > 31) 1331 sc->txpow3[i] = 5; 1332 } 1333 } 1334 /* Read power settings for 5GHz channels. */ 1335 for (i = 0; i < 40; i += 2) { 1336 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1337 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1338 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1339 1340 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1341 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1342 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1343 1344 if (sc->ntxchains == 3) { 1345 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, 1346 &val); 1347 sc->txpow3[i + 14] = (int8_t)(val & 0xff); 1348 sc->txpow3[i + 15] = (int8_t)(val >> 8); 1349 } 1350 } 1351 } 1352 1353 void 1354 run_get_txpower(struct run_softc *sc) 1355 { 1356 uint16_t val; 1357 int i; 1358 1359 /* Read power settings for 2GHz channels. */ 1360 for (i = 0; i < 14; i += 2) { 1361 run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); 1362 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1363 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1364 1365 if (sc->mac_ver != 0x5390) { 1366 run_srom_read(sc, 1367 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); 1368 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1369 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1370 } 1371 } 1372 /* Fix broken Tx power entries. */ 1373 for (i = 0; i < 14; i++) { 1374 if (sc->mac_ver >= 0x5390) { 1375 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 27) 1376 sc->txpow1[i] = 5; 1377 } else { 1378 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 1379 sc->txpow1[i] = 5; 1380 } 1381 if (sc->mac_ver > 0x5390) { 1382 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 27) 1383 sc->txpow2[i] = 5; 1384 } else if (sc->mac_ver < 0x5390) { 1385 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 1386 sc->txpow2[i] = 5; 1387 } 1388 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1389 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 1390 } 1391 /* Read power settings for 5GHz channels. */ 1392 for (i = 0; i < 40; i += 2) { 1393 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1394 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1395 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1396 1397 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1398 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1399 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1400 } 1401 /* Fix broken Tx power entries. */ 1402 for (i = 0; i < 40; i++ ) { 1403 if (sc->mac_ver != 0x5592) { 1404 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 1405 sc->txpow1[14 + i] = 5; 1406 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 1407 sc->txpow2[14 + i] = 5; 1408 } 1409 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1410 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 1411 sc->txpow2[14 + i])); 1412 } 1413 } 1414 1415 int 1416 run_read_eeprom(struct run_softc *sc) 1417 { 1418 struct ieee80211com *ic = &sc->sc_ic; 1419 int8_t delta_2ghz, delta_5ghz; 1420 uint32_t tmp; 1421 uint16_t val; 1422 int ridx, ant, i; 1423 1424 /* check whether the ROM is eFUSE ROM or EEPROM */ 1425 sc->sc_srom_read = run_eeprom_read_2; 1426 if (sc->mac_ver >= 0x3070) { 1427 run_read(sc, RT3070_EFUSE_CTRL, &tmp); 1428 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 1429 if (tmp & RT3070_SEL_EFUSE || sc->mac_ver == 0x3593) 1430 sc->sc_srom_read = run_efuse_read_2; 1431 } 1432 1433 /* read ROM version */ 1434 run_srom_read(sc, RT2860_EEPROM_VERSION, &val); 1435 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 1436 1437 /* read MAC address */ 1438 run_srom_read(sc, RT2860_EEPROM_MAC01, &val); 1439 ic->ic_myaddr[0] = val & 0xff; 1440 ic->ic_myaddr[1] = val >> 8; 1441 run_srom_read(sc, RT2860_EEPROM_MAC23, &val); 1442 ic->ic_myaddr[2] = val & 0xff; 1443 ic->ic_myaddr[3] = val >> 8; 1444 run_srom_read(sc, RT2860_EEPROM_MAC45, &val); 1445 ic->ic_myaddr[4] = val & 0xff; 1446 ic->ic_myaddr[5] = val >> 8; 1447 1448 if (sc->mac_ver < 0x3593) { 1449 /* read vendor BBP settings */ 1450 for (i = 0; i < 10; i++) { 1451 run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); 1452 sc->bbp[i].val = val & 0xff; 1453 sc->bbp[i].reg = val >> 8; 1454 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, 1455 sc->bbp[i].val)); 1456 } 1457 if (sc->mac_ver >= 0x3071) { 1458 /* read vendor RF settings */ 1459 for (i = 0; i < 10; i++) { 1460 run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, 1461 &val); 1462 sc->rf[i].val = val & 0xff; 1463 sc->rf[i].reg = val >> 8; 1464 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 1465 sc->rf[i].val)); 1466 } 1467 } 1468 } 1469 1470 /* read RF frequency offset from EEPROM */ 1471 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1472 RT3593_EEPROM_FREQ, &val); 1473 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 1474 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 1475 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1476 RT3593_EEPROM_FREQ_LEDS, &val); 1477 if ((val >> 8) != 0xff) { 1478 /* read LEDs operating mode */ 1479 sc->leds = val >> 8; 1480 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED1 : 1481 RT3593_EEPROM_LED1, &sc->led[0]); 1482 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED2 : 1483 RT3593_EEPROM_LED2, &sc->led[1]); 1484 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED3 : 1485 RT3593_EEPROM_LED3, &sc->led[2]); 1486 } else { 1487 /* broken EEPROM, use default settings */ 1488 sc->leds = 0x01; 1489 sc->led[0] = 0x5555; 1490 sc->led[1] = 0x2221; 1491 sc->led[2] = 0x5627; /* differs from RT2860 */ 1492 } 1493 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 1494 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 1495 1496 /* read RF information */ 1497 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) 1498 run_srom_read(sc, 0x00, &val); 1499 else 1500 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1501 if (val == 0xffff) { 1502 DPRINTF(("invalid EEPROM antenna info, using default\n")); 1503 if (sc->mac_ver == 0x3572) { 1504 /* default to RF3052 2T2R */ 1505 sc->rf_rev = RT3070_RF_3052; 1506 sc->ntxchains = 2; 1507 sc->nrxchains = 2; 1508 } else if (sc->mac_ver >= 0x3070) { 1509 /* default to RF3020 1T1R */ 1510 sc->rf_rev = RT3070_RF_3020; 1511 sc->ntxchains = 1; 1512 sc->nrxchains = 1; 1513 } else { 1514 /* default to RF2820 1T2R */ 1515 sc->rf_rev = RT2860_RF_2820; 1516 sc->ntxchains = 1; 1517 sc->nrxchains = 2; 1518 } 1519 } else { 1520 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) { 1521 sc->rf_rev = val; 1522 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1523 } else 1524 sc->rf_rev = (val >> 8) & 0xf; 1525 sc->ntxchains = (val >> 4) & 0xf; 1526 sc->nrxchains = val & 0xf; 1527 } 1528 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 1529 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 1530 1531 /* check if RF supports automatic Tx access gain control */ 1532 run_srom_read(sc, RT2860_EEPROM_CONFIG, &val); 1533 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 1534 /* check if driver should patch the DAC issue */ 1535 if ((val >> 8) != 0xff) 1536 sc->patch_dac = (val >> 15) & 1; 1537 if ((val & 0xff) != 0xff) { 1538 sc->ext_5ghz_lna = (val >> 3) & 1; 1539 sc->ext_2ghz_lna = (val >> 2) & 1; 1540 /* check if RF supports automatic Tx access gain control */ 1541 sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; 1542 /* check if we have a hardware radio switch */ 1543 sc->rfswitch = val & 1; 1544 } 1545 1546 /* Read Tx power settings. */ 1547 if (sc->mac_ver == 0x3593) 1548 run_rt3593_get_txpower(sc); 1549 else 1550 run_get_txpower(sc); 1551 1552 /* read Tx power compensation for each Tx rate */ 1553 run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); 1554 delta_2ghz = delta_5ghz = 0; 1555 if ((val & 0xff) != 0xff && (val & 0x80)) { 1556 delta_2ghz = val & 0xf; 1557 if (!(val & 0x40)) /* negative number */ 1558 delta_2ghz = -delta_2ghz; 1559 } 1560 val >>= 8; 1561 if ((val & 0xff) != 0xff && (val & 0x80)) { 1562 delta_5ghz = val & 0xf; 1563 if (!(val & 0x40)) /* negative number */ 1564 delta_5ghz = -delta_5ghz; 1565 } 1566 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 1567 delta_2ghz, delta_5ghz)); 1568 1569 for (ridx = 0; ridx < 5; ridx++) { 1570 uint32_t reg; 1571 1572 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val); 1573 reg = val; 1574 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val); 1575 reg |= (uint32_t)val << 16; 1576 1577 sc->txpow20mhz[ridx] = reg; 1578 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 1579 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 1580 1581 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 1582 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 1583 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 1584 } 1585 1586 /* read RSSI offsets and LNA gains from EEPROM */ 1587 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_2GHZ : 1588 RT3593_EEPROM_RSSI1_2GHZ, &val); 1589 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 1590 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 1591 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_2GHZ : 1592 RT3593_EEPROM_RSSI2_2GHZ, &val); 1593 if (sc->mac_ver >= 0x3070) { 1594 if (sc->mac_ver == 0x3593) { 1595 sc->txmixgain_2ghz = 0; 1596 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1597 } else { 1598 /* 1599 * On RT3070 chips (limited to 2 Rx chains), this ROM 1600 * field contains the Tx mixer gain for the 2GHz band. 1601 */ 1602 if ((val & 0xff) != 0xff) 1603 sc->txmixgain_2ghz = val & 0x7; 1604 } 1605 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 1606 } else 1607 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1608 if (sc->mac_ver == 0x3593) 1609 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1610 sc->lna[2] = val >> 8; /* channel group 2 */ 1611 1612 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : 1613 RT3593_EEPROM_RSSI1_5GHZ, &val); 1614 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 1615 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 1616 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : 1617 RT3593_EEPROM_RSSI2_5GHZ, &val); 1618 if (sc->mac_ver == 0x3572) { 1619 /* 1620 * On RT3572 chips (limited to 2 Rx chains), this ROM 1621 * field contains the Tx mixer gain for the 5GHz band. 1622 */ 1623 if ((val & 0xff) != 0xff) 1624 sc->txmixgain_5ghz = val & 0x7; 1625 DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz)); 1626 } else 1627 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 1628 if (sc->mac_ver == 0x3593) { 1629 sc->txmixgain_5ghz = 0; 1630 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1631 } 1632 sc->lna[3] = val >> 8; /* channel group 3 */ 1633 1634 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : 1635 RT3593_EEPROM_LNA, &val); 1636 sc->lna[0] = val & 0xff; /* channel group 0 */ 1637 sc->lna[1] = val >> 8; /* channel group 1 */ 1638 1639 /* fix broken 5GHz LNA entries */ 1640 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 1641 DPRINTF(("invalid LNA for channel group %d\n", 2)); 1642 sc->lna[2] = sc->lna[1]; 1643 } 1644 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 1645 DPRINTF(("invalid LNA for channel group %d\n", 3)); 1646 sc->lna[3] = sc->lna[1]; 1647 } 1648 1649 /* fix broken RSSI offset entries */ 1650 for (ant = 0; ant < 3; ant++) { 1651 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 1652 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 1653 ant + 1, sc->rssi_2ghz[ant])); 1654 sc->rssi_2ghz[ant] = 0; 1655 } 1656 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 1657 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 1658 ant + 1, sc->rssi_5ghz[ant])); 1659 sc->rssi_5ghz[ant] = 0; 1660 } 1661 } 1662 return 0; 1663 } 1664 1665 struct ieee80211_node * 1666 run_node_alloc(struct ieee80211com *ic) 1667 { 1668 return malloc(sizeof (struct run_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1669 } 1670 1671 int 1672 run_media_change(struct ifnet *ifp) 1673 { 1674 struct run_softc *sc = ifp->if_softc; 1675 struct ieee80211com *ic = &sc->sc_ic; 1676 uint8_t rate, ridx; 1677 int error; 1678 1679 error = ieee80211_media_change(ifp); 1680 if (error != ENETRESET) 1681 return error; 1682 1683 if (ic->ic_fixed_rate != -1) { 1684 rate = ic->ic_sup_rates[ic->ic_curmode]. 1685 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1686 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 1687 if (rt2860_rates[ridx].rate == rate) 1688 break; 1689 sc->fixed_ridx = ridx; 1690 } 1691 1692 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1693 (IFF_UP | IFF_RUNNING)) { 1694 run_stop(ifp, 0); 1695 run_init(ifp); 1696 } 1697 1698 return 0; 1699 } 1700 1701 void 1702 run_next_scan(void *arg) 1703 { 1704 struct run_softc *sc = arg; 1705 1706 if (usbd_is_dying(sc->sc_udev)) 1707 return; 1708 1709 usbd_ref_incr(sc->sc_udev); 1710 1711 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1712 ieee80211_next_scan(&sc->sc_ic.ic_if); 1713 1714 usbd_ref_decr(sc->sc_udev); 1715 } 1716 1717 void 1718 run_task(void *arg) 1719 { 1720 struct run_softc *sc = arg; 1721 struct run_host_cmd_ring *ring = &sc->cmdq; 1722 struct run_host_cmd *cmd; 1723 int s; 1724 1725 if (usbd_is_dying(sc->sc_udev)) 1726 return; 1727 1728 /* process host commands */ 1729 s = splusb(); 1730 while (ring->next != ring->cur) { 1731 cmd = &ring->cmd[ring->next]; 1732 splx(s); 1733 /* callback */ 1734 cmd->cb(sc, cmd->data); 1735 s = splusb(); 1736 ring->queued--; 1737 ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT; 1738 } 1739 splx(s); 1740 } 1741 1742 void 1743 run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), 1744 void *arg, int len) 1745 { 1746 struct run_host_cmd_ring *ring = &sc->cmdq; 1747 struct run_host_cmd *cmd; 1748 int s; 1749 1750 if (usbd_is_dying(sc->sc_udev)) 1751 return; 1752 1753 s = splusb(); 1754 cmd = &ring->cmd[ring->cur]; 1755 cmd->cb = cb; 1756 KASSERT(len <= sizeof (cmd->data)); 1757 memcpy(cmd->data, arg, len); 1758 ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT; 1759 1760 /* if there is no pending command already, schedule a task */ 1761 if (++ring->queued == 1) 1762 usb_add_task(sc->sc_udev, &sc->sc_task); 1763 splx(s); 1764 } 1765 1766 int 1767 run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1768 { 1769 struct run_softc *sc = ic->ic_softc; 1770 struct run_cmd_newstate cmd; 1771 1772 /* do it in a process context */ 1773 cmd.state = nstate; 1774 cmd.arg = arg; 1775 run_do_async(sc, run_newstate_cb, &cmd, sizeof cmd); 1776 return 0; 1777 } 1778 1779 void 1780 run_newstate_cb(struct run_softc *sc, void *arg) 1781 { 1782 struct run_cmd_newstate *cmd = arg; 1783 struct ieee80211com *ic = &sc->sc_ic; 1784 enum ieee80211_state ostate; 1785 struct ieee80211_node *ni; 1786 uint32_t tmp, sta[3]; 1787 uint8_t wcid; 1788 int s; 1789 1790 s = splnet(); 1791 ostate = ic->ic_state; 1792 1793 if (ostate == IEEE80211_S_RUN) { 1794 /* turn link LED off */ 1795 run_set_leds(sc, RT2860_LED_RADIO); 1796 } 1797 1798 switch (cmd->state) { 1799 case IEEE80211_S_INIT: 1800 if (ostate == IEEE80211_S_RUN) { 1801 /* abort TSF synchronization */ 1802 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 1803 run_write(sc, RT2860_BCN_TIME_CFG, 1804 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1805 RT2860_TBTT_TIMER_EN)); 1806 } 1807 break; 1808 1809 case IEEE80211_S_SCAN: 1810 run_set_chan(sc, ic->ic_bss->ni_chan); 1811 if (!usbd_is_dying(sc->sc_udev)) 1812 timeout_add_msec(&sc->scan_to, 200); 1813 break; 1814 1815 case IEEE80211_S_AUTH: 1816 case IEEE80211_S_ASSOC: 1817 run_set_chan(sc, ic->ic_bss->ni_chan); 1818 break; 1819 1820 case IEEE80211_S_RUN: 1821 run_set_chan(sc, ic->ic_bss->ni_chan); 1822 1823 ni = ic->ic_bss; 1824 1825 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1826 run_updateslot(ic); 1827 run_enable_mrr(sc); 1828 run_set_txpreamble(sc); 1829 run_set_basicrates(sc); 1830 run_set_bssid(sc, ni->ni_bssid); 1831 } 1832 if (ic->ic_opmode == IEEE80211_M_STA) { 1833 /* add BSS entry to the WCID table */ 1834 wcid = RUN_AID2WCID(ni->ni_associd); 1835 run_write_region_1(sc, RT2860_WCID_ENTRY(wcid), 1836 ni->ni_macaddr, IEEE80211_ADDR_LEN); 1837 1838 /* fake a join to init the tx rate */ 1839 run_newassoc(ic, ni, 1); 1840 } 1841 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1842 run_enable_tsf_sync(sc); 1843 1844 /* clear statistic registers used by AMRR */ 1845 run_read_region_1(sc, RT2860_TX_STA_CNT0, 1846 (uint8_t *)sta, sizeof sta); 1847 /* start calibration timer */ 1848 if (!usbd_is_dying(sc->sc_udev)) 1849 timeout_add_sec(&sc->calib_to, 1); 1850 } 1851 1852 /* turn link LED on */ 1853 run_set_leds(sc, RT2860_LED_RADIO | 1854 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ? 1855 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1856 break; 1857 } 1858 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 1859 splx(s); 1860 } 1861 1862 void 1863 run_updateedca(struct ieee80211com *ic) 1864 { 1865 /* do it in a process context */ 1866 run_do_async(ic->ic_softc, run_updateedca_cb, NULL, 0); 1867 } 1868 1869 /* ARGSUSED */ 1870 void 1871 run_updateedca_cb(struct run_softc *sc, void *arg) 1872 { 1873 struct ieee80211com *ic = &sc->sc_ic; 1874 int s, aci; 1875 1876 s = splnet(); 1877 /* update MAC TX configuration registers */ 1878 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 1879 run_write(sc, RT2860_EDCA_AC_CFG(aci), 1880 ic->ic_edca_ac[aci].ac_ecwmax << 16 | 1881 ic->ic_edca_ac[aci].ac_ecwmin << 12 | 1882 ic->ic_edca_ac[aci].ac_aifsn << 8 | 1883 ic->ic_edca_ac[aci].ac_txoplimit); 1884 } 1885 1886 /* update SCH/DMA registers too */ 1887 run_write(sc, RT2860_WMM_AIFSN_CFG, 1888 ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | 1889 ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | 1890 ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 | 1891 ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn); 1892 run_write(sc, RT2860_WMM_CWMIN_CFG, 1893 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | 1894 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | 1895 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 | 1896 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin); 1897 run_write(sc, RT2860_WMM_CWMAX_CFG, 1898 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | 1899 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | 1900 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 | 1901 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax); 1902 run_write(sc, RT2860_WMM_TXOP0_CFG, 1903 ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | 1904 ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit); 1905 run_write(sc, RT2860_WMM_TXOP1_CFG, 1906 ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | 1907 ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit); 1908 splx(s); 1909 } 1910 1911 int 1912 run_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1913 struct ieee80211_key *k) 1914 { 1915 struct run_softc *sc = ic->ic_softc; 1916 struct run_cmd_key cmd; 1917 1918 /* defer setting of WEP keys until interface is brought up */ 1919 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1920 (IFF_UP | IFF_RUNNING)) 1921 return 0; 1922 1923 /* do it in a process context */ 1924 cmd.key = *k; 1925 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 1926 run_do_async(sc, run_set_key_cb, &cmd, sizeof cmd); 1927 return 0; 1928 } 1929 1930 void 1931 run_set_key_cb(struct run_softc *sc, void *arg) 1932 { 1933 struct run_cmd_key *cmd = arg; 1934 struct ieee80211_key *k = &cmd->key; 1935 uint32_t attr; 1936 uint16_t base; 1937 uint8_t mode, wcid, iv[8]; 1938 1939 /* map net80211 cipher to RT2860 security mode */ 1940 switch (k->k_cipher) { 1941 case IEEE80211_CIPHER_WEP40: 1942 mode = RT2860_MODE_WEP40; 1943 break; 1944 case IEEE80211_CIPHER_WEP104: 1945 mode = RT2860_MODE_WEP104; 1946 break; 1947 case IEEE80211_CIPHER_TKIP: 1948 mode = RT2860_MODE_TKIP; 1949 break; 1950 case IEEE80211_CIPHER_CCMP: 1951 mode = RT2860_MODE_AES_CCMP; 1952 break; 1953 default: 1954 return; 1955 } 1956 1957 if (k->k_flags & IEEE80211_KEY_GROUP) { 1958 wcid = 0; /* NB: update WCID0 for group keys */ 1959 base = RT2860_SKEY(0, k->k_id); 1960 } else { 1961 wcid = RUN_AID2WCID(cmd->associd); 1962 base = RT2860_PKEY(wcid); 1963 } 1964 1965 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 1966 run_write_region_1(sc, base, k->k_key, 16); 1967 run_write_region_1(sc, base + 16, &k->k_key[24], 8); 1968 run_write_region_1(sc, base + 24, &k->k_key[16], 8); 1969 } else { 1970 /* roundup len to 16-bit: XXX fix write_region_1() instead */ 1971 run_write_region_1(sc, base, k->k_key, (k->k_len + 1) & ~1); 1972 } 1973 1974 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 1975 (k->k_flags & IEEE80211_KEY_TX)) { 1976 /* set initial packet number in IV+EIV */ 1977 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 1978 k->k_cipher == IEEE80211_CIPHER_WEP104) { 1979 memset(iv, 0, sizeof iv); 1980 iv[3] = sc->sc_ic.ic_def_txkey << 6; 1981 } else { 1982 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 1983 iv[0] = k->k_tsc >> 8; 1984 iv[1] = (iv[0] | 0x20) & 0x7f; 1985 iv[2] = k->k_tsc; 1986 } else /* CCMP */ { 1987 iv[0] = k->k_tsc; 1988 iv[1] = k->k_tsc >> 8; 1989 iv[2] = 0; 1990 } 1991 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 1992 iv[4] = k->k_tsc >> 16; 1993 iv[5] = k->k_tsc >> 24; 1994 iv[6] = k->k_tsc >> 32; 1995 iv[7] = k->k_tsc >> 40; 1996 } 1997 run_write_region_1(sc, RT2860_IVEIV(wcid), iv, 8); 1998 } 1999 2000 if (k->k_flags & IEEE80211_KEY_GROUP) { 2001 /* install group key */ 2002 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2003 attr &= ~(0xf << (k->k_id * 4)); 2004 attr |= mode << (k->k_id * 4); 2005 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2006 } else { 2007 /* install pairwise key */ 2008 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2009 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2010 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2011 } 2012 } 2013 2014 void 2015 run_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2016 struct ieee80211_key *k) 2017 { 2018 struct run_softc *sc = ic->ic_softc; 2019 struct run_cmd_key cmd; 2020 2021 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 2022 ic->ic_state != IEEE80211_S_RUN) 2023 return; /* nothing to do */ 2024 2025 /* do it in a process context */ 2026 cmd.key = *k; 2027 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2028 run_do_async(sc, run_delete_key_cb, &cmd, sizeof cmd); 2029 } 2030 2031 void 2032 run_delete_key_cb(struct run_softc *sc, void *arg) 2033 { 2034 struct run_cmd_key *cmd = arg; 2035 struct ieee80211_key *k = &cmd->key; 2036 uint32_t attr; 2037 uint8_t wcid; 2038 2039 if (k->k_flags & IEEE80211_KEY_GROUP) { 2040 /* remove group key */ 2041 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2042 attr &= ~(0xf << (k->k_id * 4)); 2043 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2044 2045 } else { 2046 /* remove pairwise key */ 2047 wcid = RUN_AID2WCID(cmd->associd); 2048 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2049 attr &= ~0xf; 2050 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2051 } 2052 } 2053 2054 void 2055 run_calibrate_to(void *arg) 2056 { 2057 /* do it in a process context */ 2058 run_do_async(arg, run_calibrate_cb, NULL, 0); 2059 /* next timeout will be rescheduled in the calibration task */ 2060 } 2061 2062 /* ARGSUSED */ 2063 void 2064 run_calibrate_cb(struct run_softc *sc, void *arg) 2065 { 2066 struct ifnet *ifp = &sc->sc_ic.ic_if; 2067 uint32_t sta[3]; 2068 int s, error; 2069 2070 /* read statistic counters (clear on read) and update AMRR state */ 2071 error = run_read_region_1(sc, RT2860_TX_STA_CNT0, (uint8_t *)sta, 2072 sizeof sta); 2073 if (error != 0) 2074 goto skip; 2075 2076 DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n", 2077 letoh32(sta[1]) >> 16, letoh32(sta[1]) & 0xffff, 2078 letoh32(sta[0]) & 0xffff)); 2079 2080 s = splnet(); 2081 /* count failed TX as errors */ 2082 ifp->if_oerrors += letoh32(sta[0]) & 0xffff; 2083 2084 sc->amn.amn_retrycnt = 2085 (letoh32(sta[0]) & 0xffff) + /* failed TX count */ 2086 (letoh32(sta[1]) >> 16); /* TX retransmission count */ 2087 2088 sc->amn.amn_txcnt = 2089 sc->amn.amn_retrycnt + 2090 (letoh32(sta[1]) & 0xffff); /* successful TX count */ 2091 2092 ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); 2093 splx(s); 2094 2095 skip: 2096 if (!usbd_is_dying(sc->sc_udev)) 2097 timeout_add_sec(&sc->calib_to, 1); 2098 } 2099 2100 void 2101 run_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 2102 { 2103 struct run_softc *sc = ic->ic_softc; 2104 struct run_node *rn = (void *)ni; 2105 struct ieee80211_rateset *rs = &ni->ni_rates; 2106 uint8_t rate; 2107 int ridx, i, j; 2108 2109 DPRINTF(("new assoc isnew=%d addr=%s\n", 2110 isnew, ether_sprintf(ni->ni_macaddr))); 2111 2112 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2113 /* start at lowest available bit-rate, AMRR will raise */ 2114 ni->ni_txrate = 0; 2115 2116 for (i = 0; i < rs->rs_nrates; i++) { 2117 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2118 /* convert 802.11 rate to hardware rate index */ 2119 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 2120 if (rt2860_rates[ridx].rate == rate) 2121 break; 2122 rn->ridx[i] = ridx; 2123 /* determine rate of control response frames */ 2124 for (j = i; j >= 0; j--) { 2125 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 2126 rt2860_rates[rn->ridx[i]].phy == 2127 rt2860_rates[rn->ridx[j]].phy) 2128 break; 2129 } 2130 if (j >= 0) { 2131 rn->ctl_ridx[i] = rn->ridx[j]; 2132 } else { 2133 /* no basic rate found, use mandatory one */ 2134 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 2135 } 2136 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 2137 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 2138 } 2139 } 2140 2141 /* 2142 * Return the Rx chain with the highest RSSI for a given frame. 2143 */ 2144 static __inline uint8_t 2145 run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi) 2146 { 2147 uint8_t rxchain = 0; 2148 2149 if (sc->nrxchains > 1) { 2150 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 2151 rxchain = 1; 2152 if (sc->nrxchains > 2) 2153 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 2154 rxchain = 2; 2155 } 2156 return rxchain; 2157 } 2158 2159 void 2160 run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen) 2161 { 2162 struct ieee80211com *ic = &sc->sc_ic; 2163 struct ifnet *ifp = &ic->ic_if; 2164 struct ieee80211_frame *wh; 2165 struct ieee80211_rxinfo rxi; 2166 struct ieee80211_node *ni; 2167 struct rt2870_rxd *rxd; 2168 struct rt2860_rxwi *rxwi; 2169 struct mbuf *m; 2170 uint32_t flags; 2171 uint16_t len; 2172 #if NBPFILTER > 0 2173 uint16_t phy; 2174 #endif 2175 uint16_t rxwisize; 2176 uint8_t ant, rssi; 2177 int s; 2178 2179 rxwi = (struct rt2860_rxwi *)buf; 2180 rxwisize = sizeof(struct rt2860_rxwi); 2181 if (sc->mac_ver == 0x5592) 2182 rxwisize += sizeof(uint64_t); 2183 else if (sc->mac_ver == 0x3593) 2184 rxwisize += sizeof(uint32_t); 2185 len = letoh16(rxwi->len) & 0xfff; 2186 if (__predict_false(len > dmalen)) { 2187 DPRINTF(("bad RXWI length %u > %u\n", len, dmalen)); 2188 return; 2189 } 2190 if (len > MCLBYTES) { 2191 DPRINTF(("frame too large (length=%d)\n", len)); 2192 ifp->if_ierrors++; 2193 return; 2194 } 2195 /* Rx descriptor is located at the end */ 2196 rxd = (struct rt2870_rxd *)(buf + dmalen); 2197 flags = letoh32(rxd->flags); 2198 2199 if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 2200 ifp->if_ierrors++; 2201 return; 2202 } 2203 2204 if (__predict_false((flags & RT2860_RX_MICERR))) { 2205 /* report MIC failures to net80211 for TKIP */ 2206 ic->ic_stats.is_rx_locmicfail++; 2207 ieee80211_michael_mic_failure(ic, 0/* XXX */); 2208 ifp->if_ierrors++; 2209 return; 2210 } 2211 2212 wh = (struct ieee80211_frame *)(buf + rxwisize); 2213 rxi.rxi_flags = 0; 2214 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2215 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 2216 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 2217 } 2218 2219 if (flags & RT2860_RX_L2PAD) { 2220 u_int hdrlen = ieee80211_get_hdrlen(wh); 2221 memmove((caddr_t)wh + 2, wh, hdrlen); 2222 wh = (struct ieee80211_frame *)((caddr_t)wh + 2); 2223 } 2224 2225 /* could use m_devget but net80211 wants contig mgmt frames */ 2226 MGETHDR(m, M_DONTWAIT, MT_DATA); 2227 if (__predict_false(m == NULL)) { 2228 ifp->if_ierrors++; 2229 return; 2230 } 2231 if (len > MHLEN) { 2232 MCLGET(m, M_DONTWAIT); 2233 if (__predict_false(!(m->m_flags & M_EXT))) { 2234 ifp->if_ierrors++; 2235 m_freem(m); 2236 return; 2237 } 2238 } 2239 /* finalize mbuf */ 2240 memcpy(mtod(m, caddr_t), wh, len); 2241 m->m_pkthdr.len = m->m_len = len; 2242 2243 ant = run_maxrssi_chain(sc, rxwi); 2244 rssi = rxwi->rssi[ant]; 2245 2246 #if NBPFILTER > 0 2247 if (__predict_false(sc->sc_drvbpf != NULL)) { 2248 struct run_rx_radiotap_header *tap = &sc->sc_rxtap; 2249 struct mbuf mb; 2250 2251 tap->wr_flags = 0; 2252 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 2253 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 2254 tap->wr_antsignal = rssi; 2255 tap->wr_antenna = ant; 2256 tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); 2257 tap->wr_rate = 2; /* in case it can't be found below */ 2258 phy = letoh16(rxwi->phy); 2259 switch (phy & RT2860_PHY_MODE) { 2260 case RT2860_PHY_CCK: 2261 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 2262 case 0: tap->wr_rate = 2; break; 2263 case 1: tap->wr_rate = 4; break; 2264 case 2: tap->wr_rate = 11; break; 2265 case 3: tap->wr_rate = 22; break; 2266 } 2267 if (phy & RT2860_PHY_SHPRE) 2268 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2269 break; 2270 case RT2860_PHY_OFDM: 2271 switch (phy & RT2860_PHY_MCS) { 2272 case 0: tap->wr_rate = 12; break; 2273 case 1: tap->wr_rate = 18; break; 2274 case 2: tap->wr_rate = 24; break; 2275 case 3: tap->wr_rate = 36; break; 2276 case 4: tap->wr_rate = 48; break; 2277 case 5: tap->wr_rate = 72; break; 2278 case 6: tap->wr_rate = 96; break; 2279 case 7: tap->wr_rate = 108; break; 2280 } 2281 break; 2282 } 2283 mb.m_data = (caddr_t)tap; 2284 mb.m_len = sc->sc_rxtap_len; 2285 mb.m_next = m; 2286 mb.m_nextpkt = NULL; 2287 mb.m_type = 0; 2288 mb.m_flags = 0; 2289 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 2290 } 2291 #endif 2292 2293 s = splnet(); 2294 ni = ieee80211_find_rxnode(ic, wh); 2295 rxi.rxi_rssi = rssi; 2296 rxi.rxi_tstamp = 0; /* unused */ 2297 ieee80211_input(ifp, m, ni, &rxi); 2298 2299 /* node is no longer needed */ 2300 ieee80211_release_node(ic, ni); 2301 splx(s); 2302 } 2303 2304 void 2305 run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2306 { 2307 struct run_rx_data *data = priv; 2308 struct run_softc *sc = data->sc; 2309 uint8_t *buf; 2310 uint32_t dmalen; 2311 int xferlen; 2312 uint16_t rxwisize; 2313 2314 rxwisize = sizeof(struct rt2860_rxwi); 2315 if (sc->mac_ver == 0x5592) 2316 rxwisize += sizeof(uint64_t); 2317 else if (sc->mac_ver == 0x3593) 2318 rxwisize += sizeof(uint32_t); 2319 2320 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2321 DPRINTF(("RX status=%d\n", status)); 2322 if (status == USBD_STALLED) 2323 usbd_clear_endpoint_stall_async(sc->rxq.pipeh); 2324 if (status != USBD_CANCELLED) 2325 goto skip; 2326 return; 2327 } 2328 usbd_get_xfer_status(xfer, NULL, NULL, &xferlen, NULL); 2329 2330 if (__predict_false(xferlen < sizeof (uint32_t) + rxwisize + 2331 sizeof(struct rt2870_rxd))) { 2332 DPRINTF(("xfer too short %d\n", xferlen)); 2333 goto skip; 2334 } 2335 2336 /* HW can aggregate multiple 802.11 frames in a single USB xfer */ 2337 buf = data->buf; 2338 while (xferlen > 8) { 2339 dmalen = letoh32(*(uint32_t *)buf) & 0xffff; 2340 2341 if (__predict_false(dmalen == 0 || (dmalen & 3) != 0)) { 2342 DPRINTF(("bad DMA length %u\n", dmalen)); 2343 break; 2344 } 2345 if (__predict_false(dmalen + 8 > xferlen)) { 2346 DPRINTF(("bad DMA length %u > %d\n", 2347 dmalen + 8, xferlen)); 2348 break; 2349 } 2350 run_rx_frame(sc, buf + sizeof (uint32_t), dmalen); 2351 buf += dmalen + 8; 2352 xferlen -= dmalen + 8; 2353 } 2354 2355 skip: /* setup a new transfer */ 2356 usbd_setup_xfer(xfer, sc->rxq.pipeh, data, data->buf, RUN_MAX_RXSZ, 2357 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, run_rxeof); 2358 (void)usbd_transfer(data->xfer); 2359 } 2360 2361 void 2362 run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2363 { 2364 struct run_tx_data *data = priv; 2365 struct run_softc *sc = data->sc; 2366 struct run_tx_ring *txq = &sc->txq[data->qid]; 2367 struct ifnet *ifp = &sc->sc_ic.ic_if; 2368 int s; 2369 2370 s = splnet(); 2371 txq->queued--; 2372 sc->qfullmsk &= ~(1 << data->qid); 2373 2374 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2375 DPRINTF(("TX status=%d\n", status)); 2376 if (status == USBD_STALLED) 2377 usbd_clear_endpoint_stall_async(txq->pipeh); 2378 ifp->if_oerrors++; 2379 splx(s); 2380 return; 2381 } 2382 2383 sc->sc_tx_timer = 0; 2384 ifq_clr_oactive(&ifp->if_snd); 2385 run_start(ifp); 2386 splx(s); 2387 } 2388 2389 int 2390 run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2391 { 2392 struct ieee80211com *ic = &sc->sc_ic; 2393 struct run_node *rn = (void *)ni; 2394 struct ieee80211_frame *wh; 2395 struct run_tx_ring *ring; 2396 struct run_tx_data *data; 2397 struct rt2870_txd *txd; 2398 struct rt2860_txwi *txwi; 2399 uint16_t qos, dur; 2400 uint16_t txwisize; 2401 uint8_t type, mcs, tid, qid; 2402 int error, hasqos, ridx, ctl_ridx, xferlen; 2403 2404 wh = mtod(m, struct ieee80211_frame *); 2405 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2406 2407 if ((hasqos = ieee80211_has_qos(wh))) { 2408 qos = ieee80211_get_qos(wh); 2409 tid = qos & IEEE80211_QOS_TID; 2410 qid = ieee80211_up_to_ac(ic, tid); 2411 } else { 2412 qos = 0; 2413 tid = 0; 2414 qid = EDCA_AC_BE; 2415 } 2416 ring = &sc->txq[qid]; 2417 data = &ring->data[ring->cur]; 2418 2419 /* pickup a rate index */ 2420 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2421 type != IEEE80211_FC0_TYPE_DATA) { 2422 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2423 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 2424 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2425 } else if (ic->ic_fixed_rate != -1) { 2426 ridx = sc->fixed_ridx; 2427 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2428 } else { 2429 ridx = rn->ridx[ni->ni_txrate]; 2430 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 2431 } 2432 2433 /* get MCS code from rate index */ 2434 mcs = rt2860_rates[ridx].mcs; 2435 2436 txwisize = sizeof(struct rt2860_txwi); 2437 if (sc->mac_ver == 0x5592) 2438 txwisize += sizeof(uint32_t); 2439 xferlen = txwisize + m->m_pkthdr.len; 2440 2441 /* roundup to 32-bit alignment */ 2442 xferlen = (xferlen + 3) & ~3; 2443 2444 txd = (struct rt2870_txd *)data->buf; 2445 txd->flags = RT2860_TX_QSEL_EDCA; 2446 txd->len = htole16(xferlen); 2447 2448 /* setup TX Wireless Information */ 2449 txwi = (struct rt2860_txwi *)(txd + 1); 2450 txwi->flags = 0; 2451 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 2452 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? 2453 RUN_AID2WCID(ni->ni_associd) : 0xff; 2454 txwi->len = htole16(m->m_pkthdr.len); 2455 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 2456 txwi->phy = htole16(RT2860_PHY_CCK); 2457 if (ridx != RT2860_RIDX_CCK1 && 2458 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 2459 mcs |= RT2860_PHY_SHPRE; 2460 } else 2461 txwi->phy = htole16(RT2860_PHY_OFDM); 2462 txwi->phy |= htole16(mcs); 2463 2464 txwi->txop = RT2860_TX_TXOP_BACKOFF; 2465 2466 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2467 (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 2468 IEEE80211_QOS_ACK_POLICY_NOACK)) { 2469 txwi->xflags |= RT2860_TX_ACK; 2470 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2471 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 2472 else 2473 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 2474 *(uint16_t *)wh->i_dur = htole16(dur); 2475 } 2476 2477 #if NBPFILTER > 0 2478 if (__predict_false(sc->sc_drvbpf != NULL)) { 2479 struct run_tx_radiotap_header *tap = &sc->sc_txtap; 2480 struct mbuf mb; 2481 2482 tap->wt_flags = 0; 2483 tap->wt_rate = rt2860_rates[ridx].rate; 2484 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2485 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2486 tap->wt_hwqueue = qid; 2487 if (mcs & RT2860_PHY_SHPRE) 2488 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2489 2490 mb.m_data = (caddr_t)tap; 2491 mb.m_len = sc->sc_txtap_len; 2492 mb.m_next = m; 2493 mb.m_nextpkt = NULL; 2494 mb.m_type = 0; 2495 mb.m_flags = 0; 2496 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 2497 } 2498 #endif 2499 2500 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)txwi + txwisize); 2501 m_freem(m); 2502 2503 xferlen += sizeof (*txd) + 4; 2504 2505 usbd_setup_xfer(data->xfer, ring->pipeh, data, data->buf, xferlen, 2506 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, RUN_TX_TIMEOUT, run_txeof); 2507 error = usbd_transfer(data->xfer); 2508 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) 2509 return error; 2510 2511 ieee80211_release_node(ic, ni); 2512 2513 ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT; 2514 if (++ring->queued >= RUN_TX_RING_COUNT) 2515 sc->qfullmsk |= 1 << qid; 2516 2517 return 0; 2518 } 2519 2520 void 2521 run_start(struct ifnet *ifp) 2522 { 2523 struct run_softc *sc = ifp->if_softc; 2524 struct ieee80211com *ic = &sc->sc_ic; 2525 struct ieee80211_node *ni; 2526 struct mbuf *m; 2527 2528 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 2529 return; 2530 2531 for (;;) { 2532 if (sc->qfullmsk != 0) { 2533 ifq_set_oactive(&ifp->if_snd); 2534 break; 2535 } 2536 /* send pending management frames first */ 2537 m = mq_dequeue(&ic->ic_mgtq); 2538 if (m != NULL) { 2539 ni = m->m_pkthdr.ph_cookie; 2540 goto sendit; 2541 } 2542 if (ic->ic_state != IEEE80211_S_RUN) 2543 break; 2544 2545 /* encapsulate and send data frames */ 2546 IFQ_DEQUEUE(&ifp->if_snd, m); 2547 if (m == NULL) 2548 break; 2549 #if NBPFILTER > 0 2550 if (ifp->if_bpf != NULL) 2551 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 2552 #endif 2553 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 2554 continue; 2555 sendit: 2556 #if NBPFILTER > 0 2557 if (ic->ic_rawbpf != NULL) 2558 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 2559 #endif 2560 if (run_tx(sc, m, ni) != 0) { 2561 ieee80211_release_node(ic, ni); 2562 ifp->if_oerrors++; 2563 continue; 2564 } 2565 2566 sc->sc_tx_timer = 5; 2567 ifp->if_timer = 1; 2568 } 2569 } 2570 2571 void 2572 run_watchdog(struct ifnet *ifp) 2573 { 2574 struct run_softc *sc = ifp->if_softc; 2575 2576 ifp->if_timer = 0; 2577 2578 if (sc->sc_tx_timer > 0) { 2579 if (--sc->sc_tx_timer == 0) { 2580 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2581 /* run_init(ifp); XXX needs a process context! */ 2582 ifp->if_oerrors++; 2583 return; 2584 } 2585 ifp->if_timer = 1; 2586 } 2587 2588 ieee80211_watchdog(ifp); 2589 } 2590 2591 int 2592 run_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2593 { 2594 struct run_softc *sc = ifp->if_softc; 2595 struct ieee80211com *ic = &sc->sc_ic; 2596 int s, error = 0; 2597 2598 if (usbd_is_dying(sc->sc_udev)) 2599 return ENXIO; 2600 2601 usbd_ref_incr(sc->sc_udev); 2602 2603 s = splnet(); 2604 2605 switch (cmd) { 2606 case SIOCSIFADDR: 2607 ifp->if_flags |= IFF_UP; 2608 /* FALLTHROUGH */ 2609 case SIOCSIFFLAGS: 2610 if (ifp->if_flags & IFF_UP) { 2611 if (!(ifp->if_flags & IFF_RUNNING)) 2612 run_init(ifp); 2613 } else { 2614 if (ifp->if_flags & IFF_RUNNING) 2615 run_stop(ifp, 1); 2616 } 2617 break; 2618 2619 case SIOCS80211CHANNEL: 2620 /* 2621 * This allows for fast channel switching in monitor mode 2622 * (used by kismet). 2623 */ 2624 error = ieee80211_ioctl(ifp, cmd, data); 2625 if (error == ENETRESET && 2626 ic->ic_opmode == IEEE80211_M_MONITOR) { 2627 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2628 (IFF_UP | IFF_RUNNING)) 2629 run_set_chan(sc, ic->ic_ibss_chan); 2630 error = 0; 2631 } 2632 break; 2633 2634 default: 2635 error = ieee80211_ioctl(ifp, cmd, data); 2636 } 2637 2638 if (error == ENETRESET) { 2639 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2640 (IFF_UP | IFF_RUNNING)) { 2641 run_stop(ifp, 0); 2642 run_init(ifp); 2643 } 2644 error = 0; 2645 } 2646 2647 splx(s); 2648 2649 usbd_ref_decr(sc->sc_udev); 2650 2651 return error; 2652 } 2653 2654 void 2655 run_iq_calib(struct run_softc *sc, u_int chan) 2656 { 2657 uint16_t val; 2658 2659 /* Tx0 IQ gain. */ 2660 run_bbp_write(sc, 158, 0x2c); 2661 if (chan <= 14) 2662 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val); 2663 else if (chan <= 64) { 2664 run_efuse_read(sc, 2665 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, &val); 2666 } else if (chan <= 138) { 2667 run_efuse_read(sc, 2668 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, &val); 2669 } else if (chan <= 165) { 2670 run_efuse_read(sc, 2671 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, 2672 &val); 2673 } else 2674 val = 0; 2675 run_bbp_write(sc, 159, val); 2676 2677 /* Tx0 IQ phase. */ 2678 run_bbp_write(sc, 158, 0x2d); 2679 if (chan <= 14) { 2680 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, &val); 2681 } else if (chan <= 64) { 2682 run_efuse_read(sc, 2683 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, &val); 2684 } else if (chan <= 138) { 2685 run_efuse_read(sc, 2686 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, &val); 2687 } else if (chan <= 165) { 2688 run_efuse_read(sc, 2689 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, &val); 2690 } else 2691 val = 0; 2692 run_bbp_write(sc, 159, val); 2693 2694 /* Tx1 IQ gain. */ 2695 run_bbp_write(sc, 158, 0x4a); 2696 if (chan <= 14) { 2697 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, &val); 2698 } else if (chan <= 64) { 2699 run_efuse_read(sc, 2700 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, &val); 2701 } else if (chan <= 138) { 2702 run_efuse_read(sc, 2703 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, &val); 2704 } else if (chan <= 165) { 2705 run_efuse_read(sc, 2706 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, &val); 2707 } else 2708 val = 0; 2709 run_bbp_write(sc, 159, val); 2710 2711 /* Tx1 IQ phase. */ 2712 run_bbp_write(sc, 158, 0x4b); 2713 if (chan <= 14) { 2714 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, &val); 2715 } else if (chan <= 64) { 2716 run_efuse_read(sc, 2717 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, &val); 2718 } else if (chan <= 138) { 2719 run_efuse_read(sc, 2720 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, &val); 2721 } else if (chan <= 165) { 2722 run_efuse_read(sc, 2723 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, &val); 2724 } else 2725 val = 0; 2726 run_bbp_write(sc, 159, val); 2727 2728 /* RF IQ compensation control. */ 2729 run_bbp_write(sc, 158, 0x04); 2730 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, &val); 2731 run_bbp_write(sc, 159, val); 2732 2733 /* RF IQ imbalance compensation control. */ 2734 run_bbp_write(sc, 158, 0x03); 2735 run_efuse_read(sc, 2736 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val); 2737 run_bbp_write(sc, 159, val); 2738 } 2739 2740 void 2741 run_select_chan_group(struct run_softc *sc, int group) 2742 { 2743 uint32_t tmp; 2744 uint8_t agc; 2745 2746 run_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2747 run_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2748 run_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2749 if (sc->mac_ver < 0x3572) 2750 run_bbp_write(sc, 86, 0x00); 2751 2752 if (sc->mac_ver == 0x3593) { 2753 run_bbp_write(sc, 77, 0x98); 2754 run_bbp_write(sc, 83, (group == 0) ? 0x8a : 0x9a); 2755 } 2756 2757 if (group == 0) { 2758 if (sc->ext_2ghz_lna) { 2759 if (sc->mac_ver >= 0x5390) 2760 run_bbp_write(sc, 75, 0x52); 2761 else { 2762 run_bbp_write(sc, 82, 0x62); 2763 run_bbp_write(sc, 75, 0x46); 2764 } 2765 } else { 2766 if (sc->mac_ver == 0x5592) { 2767 run_bbp_write(sc, 79, 0x1c); 2768 run_bbp_write(sc, 80, 0x0e); 2769 run_bbp_write(sc, 81, 0x3a); 2770 run_bbp_write(sc, 82, 0x62); 2771 2772 run_bbp_write(sc, 195, 0x80); 2773 run_bbp_write(sc, 196, 0xe0); 2774 run_bbp_write(sc, 195, 0x81); 2775 run_bbp_write(sc, 196, 0x1f); 2776 run_bbp_write(sc, 195, 0x82); 2777 run_bbp_write(sc, 196, 0x38); 2778 run_bbp_write(sc, 195, 0x83); 2779 run_bbp_write(sc, 196, 0x32); 2780 run_bbp_write(sc, 195, 0x85); 2781 run_bbp_write(sc, 196, 0x28); 2782 run_bbp_write(sc, 195, 0x86); 2783 run_bbp_write(sc, 196, 0x19); 2784 } else if (sc->mac_ver >= 0x5390) 2785 run_bbp_write(sc, 75, 0x50); 2786 else { 2787 run_bbp_write(sc, 82, 2788 (sc->mac_ver == 0x3593) ? 0x62 : 0x84); 2789 run_bbp_write(sc, 75, 0x50); 2790 } 2791 } 2792 } else { 2793 if (sc->mac_ver == 0x5592) { 2794 run_bbp_write(sc, 79, 0x18); 2795 run_bbp_write(sc, 80, 0x08); 2796 run_bbp_write(sc, 81, 0x38); 2797 run_bbp_write(sc, 82, 0x92); 2798 2799 run_bbp_write(sc, 195, 0x80); 2800 run_bbp_write(sc, 196, 0xf0); 2801 run_bbp_write(sc, 195, 0x81); 2802 run_bbp_write(sc, 196, 0x1e); 2803 run_bbp_write(sc, 195, 0x82); 2804 run_bbp_write(sc, 196, 0x28); 2805 run_bbp_write(sc, 195, 0x83); 2806 run_bbp_write(sc, 196, 0x20); 2807 run_bbp_write(sc, 195, 0x85); 2808 run_bbp_write(sc, 196, 0x7f); 2809 run_bbp_write(sc, 195, 0x86); 2810 run_bbp_write(sc, 196, 0x7f); 2811 } else if (sc->mac_ver == 0x3572) 2812 run_bbp_write(sc, 82, 0x94); 2813 else 2814 run_bbp_write(sc, 82, 2815 (sc->mac_ver == 0x3593) ? 0x82 : 0xf2); 2816 if (sc->ext_5ghz_lna) 2817 run_bbp_write(sc, 75, 0x46); 2818 else 2819 run_bbp_write(sc, 75, 0x50); 2820 } 2821 2822 run_read(sc, RT2860_TX_BAND_CFG, &tmp); 2823 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2824 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2825 run_write(sc, RT2860_TX_BAND_CFG, tmp); 2826 2827 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2828 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2829 if (sc->mac_ver == 0x3593) 2830 tmp |= 1 << 29 | 1 << 28; 2831 if (sc->nrxchains > 1) 2832 tmp |= RT2860_LNA_PE1_EN; 2833 if (group == 0) { /* 2GHz */ 2834 tmp |= RT2860_PA_PE_G0_EN; 2835 if (sc->ntxchains > 1) 2836 tmp |= RT2860_PA_PE_G1_EN; 2837 if (sc->mac_ver == 0x3593) { 2838 if (sc->ntxchains > 2) 2839 tmp |= 1 << 25; 2840 } 2841 } else { /* 5GHz */ 2842 tmp |= RT2860_PA_PE_A0_EN; 2843 if (sc->ntxchains > 1) 2844 tmp |= RT2860_PA_PE_A1_EN; 2845 } 2846 if (sc->mac_ver == 0x3572) { 2847 run_rt3070_rf_write(sc, 8, 0x00); 2848 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2849 run_rt3070_rf_write(sc, 8, 0x80); 2850 } else 2851 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2852 2853 if (sc->mac_ver == 0x5592) { 2854 run_bbp_write(sc, 195, 0x8d); 2855 run_bbp_write(sc, 196, 0x1a); 2856 } 2857 2858 if (sc->mac_ver == 0x3593) { 2859 run_read(sc, RT2860_GPIO_CTRL, &tmp); 2860 tmp &= ~0x01010000; 2861 if (group == 0) 2862 tmp |= 0x00010000; 2863 tmp = (tmp & ~0x00009090) | 0x00000090; 2864 run_write(sc, RT2860_GPIO_CTRL, tmp); 2865 } 2866 2867 /* set initial AGC value */ 2868 if (group == 0) { /* 2GHz band */ 2869 if (sc->mac_ver >= 0x3070) 2870 agc = 0x1c + sc->lna[0] * 2; 2871 else 2872 agc = 0x2e + sc->lna[0]; 2873 } else { /* 5GHz band */ 2874 if (sc->mac_ver == 0x5592) 2875 agc = 0x24 + sc->lna[group] * 2; 2876 else if (sc->mac_ver == 0x3572 || sc->mac_ver == 0x3593) 2877 agc = 0x22 + (sc->lna[group] * 5) / 3; 2878 else 2879 agc = 0x32 + (sc->lna[group] * 5) / 3; 2880 } 2881 run_set_agc(sc, agc); 2882 } 2883 2884 void 2885 run_rt2870_set_chan(struct run_softc *sc, u_int chan) 2886 { 2887 const struct rfprog *rfprog = rt2860_rf2850; 2888 uint32_t r2, r3, r4; 2889 int8_t txpow1, txpow2; 2890 int i; 2891 2892 /* find the settings for this channel (we know it exists) */ 2893 for (i = 0; rfprog[i].chan != chan; i++); 2894 2895 r2 = rfprog[i].r2; 2896 if (sc->ntxchains == 1) 2897 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2898 if (sc->nrxchains == 1) 2899 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2900 else if (sc->nrxchains == 2) 2901 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2902 2903 /* use Tx power values from EEPROM */ 2904 txpow1 = sc->txpow1[i]; 2905 txpow2 = sc->txpow2[i]; 2906 if (chan > 14) { 2907 if (txpow1 >= 0) 2908 txpow1 = txpow1 << 1 | 1; 2909 else 2910 txpow1 = (7 + txpow1) << 1; 2911 if (txpow2 >= 0) 2912 txpow2 = txpow2 << 1 | 1; 2913 else 2914 txpow2 = (7 + txpow2) << 1; 2915 } 2916 r3 = rfprog[i].r3 | txpow1 << 7; 2917 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2918 2919 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2920 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2921 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2922 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2923 2924 DELAY(200); 2925 2926 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2927 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2928 run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1); 2929 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2930 2931 DELAY(200); 2932 2933 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2934 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2935 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2936 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2937 } 2938 2939 void 2940 run_rt3070_set_chan(struct run_softc *sc, u_int chan) 2941 { 2942 int8_t txpow1, txpow2; 2943 uint8_t rf; 2944 int i; 2945 2946 /* find the settings for this channel (we know it exists) */ 2947 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2948 2949 /* use Tx power values from EEPROM */ 2950 txpow1 = sc->txpow1[i]; 2951 txpow2 = sc->txpow2[i]; 2952 2953 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2954 2955 /* RT3370/RT3390: RF R3 [7:4] is not reserved bits. */ 2956 run_rt3070_rf_read(sc, 3, &rf); 2957 rf = (rf & ~0x0f) | rt3070_freqs[i].k; 2958 run_rt3070_rf_write(sc, 3, rf); 2959 2960 run_rt3070_rf_read(sc, 6, &rf); 2961 rf = (rf & ~0x03) | rt3070_freqs[i].r; 2962 run_rt3070_rf_write(sc, 6, rf); 2963 2964 /* set Tx0 power */ 2965 run_rt3070_rf_read(sc, 12, &rf); 2966 rf = (rf & ~0x1f) | txpow1; 2967 run_rt3070_rf_write(sc, 12, rf); 2968 2969 /* set Tx1 power */ 2970 run_rt3070_rf_read(sc, 13, &rf); 2971 rf = (rf & ~0x1f) | txpow2; 2972 run_rt3070_rf_write(sc, 13, rf); 2973 2974 run_rt3070_rf_read(sc, 1, &rf); 2975 rf &= ~0xfc; 2976 if (sc->ntxchains == 1) 2977 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 2978 else if (sc->ntxchains == 2) 2979 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 2980 if (sc->nrxchains == 1) 2981 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2982 else if (sc->nrxchains == 2) 2983 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 2984 run_rt3070_rf_write(sc, 1, rf); 2985 2986 /* set RF offset */ 2987 run_rt3070_rf_read(sc, 23, &rf); 2988 rf = (rf & ~0x7f) | sc->freq; 2989 run_rt3070_rf_write(sc, 23, rf); 2990 2991 /* program RF filter */ 2992 run_rt3070_rf_read(sc, 24, &rf); /* Tx */ 2993 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2994 run_rt3070_rf_write(sc, 24, rf); 2995 run_rt3070_rf_read(sc, 31, &rf); /* Rx */ 2996 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2997 run_rt3070_rf_write(sc, 31, rf); 2998 2999 /* enable RF tuning */ 3000 run_rt3070_rf_read(sc, 7, &rf); 3001 run_rt3070_rf_write(sc, 7, rf | 0x01); 3002 } 3003 3004 void 3005 run_rt3572_set_chan(struct run_softc *sc, u_int chan) 3006 { 3007 int8_t txpow1, txpow2; 3008 uint32_t tmp; 3009 uint8_t rf; 3010 int i; 3011 3012 /* find the settings for this channel (we know it exists) */ 3013 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3014 3015 /* use Tx power values from EEPROM */ 3016 txpow1 = sc->txpow1[i]; 3017 txpow2 = sc->txpow2[i]; 3018 3019 if (chan <= 14) { 3020 run_bbp_write(sc, 25, sc->bbp25); 3021 run_bbp_write(sc, 26, sc->bbp26); 3022 } else { 3023 /* enable IQ phase correction */ 3024 run_bbp_write(sc, 25, 0x09); 3025 run_bbp_write(sc, 26, 0xff); 3026 } 3027 3028 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 3029 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 3030 run_rt3070_rf_read(sc, 6, &rf); 3031 rf = (rf & ~0x0f) | rt3070_freqs[i].r; 3032 rf |= (chan <= 14) ? 0x08 : 0x04; 3033 run_rt3070_rf_write(sc, 6, rf); 3034 3035 /* set PLL mode */ 3036 run_rt3070_rf_read(sc, 5, &rf); 3037 rf &= ~(0x08 | 0x04); 3038 rf |= (chan <= 14) ? 0x04 : 0x08; 3039 run_rt3070_rf_write(sc, 5, rf); 3040 3041 /* set Tx power for chain 0 */ 3042 if (chan <= 14) 3043 rf = 0x60 | txpow1; 3044 else 3045 rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); 3046 run_rt3070_rf_write(sc, 12, rf); 3047 3048 /* set Tx power for chain 1 */ 3049 if (chan <= 14) 3050 rf = 0x60 | txpow2; 3051 else 3052 rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); 3053 run_rt3070_rf_write(sc, 13, rf); 3054 3055 /* set Tx/Rx streams */ 3056 run_rt3070_rf_read(sc, 1, &rf); 3057 rf &= ~0xfc; 3058 if (sc->ntxchains == 1) 3059 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 3060 else if (sc->ntxchains == 2) 3061 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 3062 if (sc->nrxchains == 1) 3063 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 3064 else if (sc->nrxchains == 2) 3065 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 3066 run_rt3070_rf_write(sc, 1, rf); 3067 3068 /* set RF offset */ 3069 run_rt3070_rf_read(sc, 23, &rf); 3070 rf = (rf & ~0x7f) | sc->freq; 3071 run_rt3070_rf_write(sc, 23, rf); 3072 3073 /* program RF filter */ 3074 rf = sc->rf24_20mhz; 3075 run_rt3070_rf_write(sc, 24, rf); /* Tx */ 3076 run_rt3070_rf_write(sc, 31, rf); /* Rx */ 3077 3078 /* enable RF tuning */ 3079 run_rt3070_rf_read(sc, 7, &rf); 3080 rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); 3081 run_rt3070_rf_write(sc, 7, rf); 3082 3083 /* TSSI */ 3084 rf = (chan <= 14) ? 0xc3 : 0xc0; 3085 run_rt3070_rf_write(sc, 9, rf); 3086 3087 /* set loop filter 1 */ 3088 run_rt3070_rf_write(sc, 10, 0xf1); 3089 /* set loop filter 2 */ 3090 run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); 3091 3092 /* set tx_mx2_ic */ 3093 run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); 3094 /* set tx_mx1_ic */ 3095 if (chan <= 14) 3096 rf = 0x48 | sc->txmixgain_2ghz; 3097 else 3098 rf = 0x78 | sc->txmixgain_5ghz; 3099 run_rt3070_rf_write(sc, 16, rf); 3100 3101 /* set tx_lo1 */ 3102 run_rt3070_rf_write(sc, 17, 0x23); 3103 /* set tx_lo2 */ 3104 if (chan <= 14) 3105 rf = 0x93; 3106 else if (chan <= 64) 3107 rf = 0xb7; 3108 else if (chan <= 128) 3109 rf = 0x74; 3110 else 3111 rf = 0x72; 3112 run_rt3070_rf_write(sc, 19, rf); 3113 3114 /* set rx_lo1 */ 3115 if (chan <= 14) 3116 rf = 0xb3; 3117 else if (chan <= 64) 3118 rf = 0xf6; 3119 else if (chan <= 128) 3120 rf = 0xf4; 3121 else 3122 rf = 0xf3; 3123 run_rt3070_rf_write(sc, 20, rf); 3124 3125 /* set pfd_delay */ 3126 if (chan <= 14) 3127 rf = 0x15; 3128 else if (chan <= 64) 3129 rf = 0x3d; 3130 else 3131 rf = 0x01; 3132 run_rt3070_rf_write(sc, 25, rf); 3133 3134 /* set rx_lo2 */ 3135 run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); 3136 /* set ldo_rf_vc */ 3137 run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); 3138 /* set drv_cc */ 3139 run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); 3140 3141 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3142 tmp &= ~0x8080; 3143 if (chan <= 14) 3144 tmp |= 0x80; 3145 run_write(sc, RT2860_GPIO_CTRL, tmp); 3146 3147 /* enable RF tuning */ 3148 run_rt3070_rf_read(sc, 7, &rf); 3149 run_rt3070_rf_write(sc, 7, rf | 0x01); 3150 3151 DELAY(2000); 3152 } 3153 3154 void 3155 run_rt3593_set_chan(struct run_softc *sc, u_int chan) 3156 { 3157 int8_t txpow1, txpow2, txpow3; 3158 uint8_t h20mhz, rf; 3159 int i; 3160 3161 /* find the settings for this channel (we know it exists) */ 3162 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3163 3164 /* use Tx power values from EEPROM */ 3165 txpow1 = sc->txpow1[i]; 3166 txpow2 = sc->txpow2[i]; 3167 txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; 3168 3169 if (chan <= 14) { 3170 run_bbp_write(sc, 25, sc->bbp25); 3171 run_bbp_write(sc, 26, sc->bbp26); 3172 } else { 3173 /* Enable IQ phase correction. */ 3174 run_bbp_write(sc, 25, 0x09); 3175 run_bbp_write(sc, 26, 0xff); 3176 } 3177 3178 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3179 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3180 run_rt3070_rf_read(sc, 11, &rf); 3181 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3182 run_rt3070_rf_write(sc, 11, rf); 3183 3184 /* Set pll_idoh. */ 3185 run_rt3070_rf_read(sc, 11, &rf); 3186 rf &= ~0x4c; 3187 rf |= (chan <= 14) ? 0x44 : 0x48; 3188 run_rt3070_rf_write(sc, 11, rf); 3189 3190 if (chan <= 14) 3191 rf = txpow1 & 0x1f; 3192 else 3193 rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); 3194 run_rt3070_rf_write(sc, 53, rf); 3195 3196 if (chan <= 14) 3197 rf = txpow2 & 0x1f; 3198 else 3199 rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); 3200 run_rt3070_rf_write(sc, 55, rf); 3201 3202 if (chan <= 14) 3203 rf = txpow3 & 0x1f; 3204 else 3205 rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); 3206 run_rt3070_rf_write(sc, 54, rf); 3207 3208 rf = RT3070_RF_BLOCK | RT3070_PLL_PD; 3209 if (sc->ntxchains == 3) 3210 rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; 3211 else 3212 rf |= RT3070_TX0_PD | RT3070_TX1_PD; 3213 rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; 3214 run_rt3070_rf_write(sc, 1, rf); 3215 3216 run_adjust_freq_offset(sc); 3217 3218 run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); 3219 3220 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 3221 run_rt3070_rf_read(sc, 30, &rf); 3222 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 3223 run_rt3070_rf_write(sc, 30, rf); 3224 3225 run_rt3070_rf_read(sc, 36, &rf); 3226 if (chan <= 14) 3227 rf |= 0x80; 3228 else 3229 rf &= ~0x80; 3230 run_rt3070_rf_write(sc, 36, rf); 3231 3232 /* Set vcolo_bs. */ 3233 run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); 3234 /* Set pfd_delay. */ 3235 run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); 3236 3237 /* Set vco bias current control. */ 3238 run_rt3070_rf_read(sc, 6, &rf); 3239 rf &= ~0xc0; 3240 if (chan <= 14) 3241 rf |= 0x40; 3242 else if (chan <= 128) 3243 rf |= 0x80; 3244 else 3245 rf |= 0x40; 3246 run_rt3070_rf_write(sc, 6, rf); 3247 3248 run_rt3070_rf_read(sc, 30, &rf); 3249 rf = (rf & ~0x18) | 0x10; 3250 run_rt3070_rf_write(sc, 30, rf); 3251 3252 run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); 3253 run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); 3254 3255 run_rt3070_rf_read(sc, 51, &rf); 3256 rf = (rf & ~0x03) | 0x01; 3257 run_rt3070_rf_write(sc, 51, rf); 3258 /* Set tx_mx1_cc. */ 3259 run_rt3070_rf_read(sc, 51, &rf); 3260 rf &= ~0x1c; 3261 rf |= (chan <= 14) ? 0x14 : 0x10; 3262 run_rt3070_rf_write(sc, 51, rf); 3263 /* Set tx_mx1_ic. */ 3264 run_rt3070_rf_read(sc, 51, &rf); 3265 rf &= ~0xe0; 3266 rf |= (chan <= 14) ? 0x60 : 0x40; 3267 run_rt3070_rf_write(sc, 51, rf); 3268 /* Set tx_lo1_ic. */ 3269 run_rt3070_rf_read(sc, 49, &rf); 3270 rf &= ~0x1c; 3271 rf |= (chan <= 14) ? 0x0c : 0x08; 3272 run_rt3070_rf_write(sc, 49, rf); 3273 /* Set tx_lo1_en. */ 3274 run_rt3070_rf_read(sc, 50, &rf); 3275 run_rt3070_rf_write(sc, 50, rf & ~0x20); 3276 /* Set drv_cc. */ 3277 run_rt3070_rf_read(sc, 57, &rf); 3278 rf &= ~0xfc; 3279 rf |= (chan <= 14) ? 0x6c : 0x3c; 3280 run_rt3070_rf_write(sc, 57, rf); 3281 /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ 3282 run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); 3283 /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ 3284 run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); 3285 /* Enable VCO calibration. */ 3286 run_rt3070_rf_read(sc, 3, &rf); 3287 rf &= ~RT3593_VCOCAL; 3288 rf |= (chan <= 14) ? RT3593_VCOCAL : 0xbe; 3289 run_rt3070_rf_write(sc, 3, rf); 3290 3291 if (chan <= 14) 3292 rf = 0x23; 3293 else if (chan <= 64) 3294 rf = 0x36; 3295 else if (chan <= 128) 3296 rf = 0x32; 3297 else 3298 rf = 0x30; 3299 run_rt3070_rf_write(sc, 39, rf); 3300 if (chan <= 14) 3301 rf = 0xbb; 3302 else if (chan <= 64) 3303 rf = 0xeb; 3304 else if (chan <= 128) 3305 rf = 0xb3; 3306 else 3307 rf = 0x9b; 3308 run_rt3070_rf_write(sc, 45, rf); 3309 3310 /* Set FEQ/AEQ control. */ 3311 run_bbp_write(sc, 105, 0x34); 3312 } 3313 3314 void 3315 run_rt5390_set_chan(struct run_softc *sc, u_int chan) 3316 { 3317 int8_t txpow1, txpow2; 3318 uint8_t rf; 3319 int i; 3320 3321 /* find the settings for this channel (we know it exists) */ 3322 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3323 3324 /* use Tx power values from EEPROM */ 3325 txpow1 = sc->txpow1[i]; 3326 txpow2 = sc->txpow2[i]; 3327 3328 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3329 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3330 run_rt3070_rf_read(sc, 11, &rf); 3331 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3332 run_rt3070_rf_write(sc, 11, rf); 3333 3334 run_rt3070_rf_read(sc, 49, &rf); 3335 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3336 /* The valid range of the RF R49 is 0x00 to 0x27. */ 3337 if ((rf & 0x3f) > 0x27) 3338 rf = (rf & ~0x3f) | 0x27; 3339 run_rt3070_rf_write(sc, 49, rf); 3340 3341 if (sc->mac_ver == 0x5392) { 3342 run_rt3070_rf_read(sc, 50, &rf); 3343 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3344 /* The valid range of the RF R50 is 0x00 to 0x27. */ 3345 if ((rf & 0x3f) > 0x27) 3346 rf = (rf & ~0x3f) | 0x27; 3347 run_rt3070_rf_write(sc, 50, rf); 3348 } 3349 3350 run_rt3070_rf_read(sc, 1, &rf); 3351 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 3352 if (sc->mac_ver == 0x5392) 3353 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 3354 run_rt3070_rf_write(sc, 1, rf); 3355 3356 if (sc->mac_ver != 0x5392) { 3357 run_rt3070_rf_read(sc, 2, &rf); 3358 rf |= 0x80; 3359 run_rt3070_rf_write(sc, 2, rf); 3360 DELAY(10); 3361 rf &= 0x7f; 3362 run_rt3070_rf_write(sc, 2, rf); 3363 } 3364 3365 run_adjust_freq_offset(sc); 3366 3367 if (sc->mac_ver == 0x5392) { 3368 /* Fix for RT5392C. */ 3369 if (sc->mac_rev >= 0x0223) { 3370 if (chan <= 4) 3371 rf = 0x0f; 3372 else if (chan >= 5 && chan <= 7) 3373 rf = 0x0e; 3374 else 3375 rf = 0x0d; 3376 run_rt3070_rf_write(sc, 23, rf); 3377 3378 if (chan <= 4) 3379 rf = 0x0c; 3380 else if (chan == 5) 3381 rf = 0x0b; 3382 else if (chan >= 6 && chan <= 7) 3383 rf = 0x0a; 3384 else if (chan >= 8 && chan <= 10) 3385 rf = 0x09; 3386 else 3387 rf = 0x08; 3388 run_rt3070_rf_write(sc, 59, rf); 3389 } else { 3390 if (chan <= 11) 3391 rf = 0x0f; 3392 else 3393 rf = 0x0b; 3394 run_rt3070_rf_write(sc, 59, rf); 3395 } 3396 } else { 3397 /* Fix for RT5390F. */ 3398 if (sc->mac_rev >= 0x0502) { 3399 if (chan <= 11) 3400 rf = 0x43; 3401 else 3402 rf = 0x23; 3403 run_rt3070_rf_write(sc, 55, rf); 3404 3405 if (chan <= 11) 3406 rf = 0x0f; 3407 else if (chan == 12) 3408 rf = 0x0d; 3409 else 3410 rf = 0x0b; 3411 run_rt3070_rf_write(sc, 59, rf); 3412 } else { 3413 run_rt3070_rf_write(sc, 55, 0x44); 3414 run_rt3070_rf_write(sc, 59, 0x8f); 3415 } 3416 } 3417 3418 /* Enable VCO calibration. */ 3419 run_rt3070_rf_read(sc, 3, &rf); 3420 rf |= RT3593_VCOCAL; 3421 run_rt3070_rf_write(sc, 3, rf); 3422 } 3423 3424 void 3425 run_rt5592_set_chan(struct run_softc *sc, u_int chan) 3426 { 3427 const struct rt5592_freqs *freqs; 3428 uint32_t tmp; 3429 uint8_t reg, rf, txpow_bound; 3430 int8_t txpow1, txpow2; 3431 int i; 3432 3433 run_read(sc, RT5592_DEBUG_INDEX, &tmp); 3434 freqs = (tmp & RT5592_SEL_XTAL) ? 3435 rt5592_freqs_40mhz : rt5592_freqs_20mhz; 3436 3437 /* find the settings for this channel (we know it exists) */ 3438 for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); 3439 3440 /* use Tx power values from EEPROM */ 3441 txpow1 = sc->txpow1[i]; 3442 txpow2 = sc->txpow2[i]; 3443 3444 run_read(sc, RT3070_LDO_CFG0, &tmp); 3445 tmp &= ~0x1c000000; 3446 if (chan > 14) 3447 tmp |= 0x14000000; 3448 run_write(sc, RT3070_LDO_CFG0, tmp); 3449 3450 /* N setting. */ 3451 run_rt3070_rf_write(sc, 8, freqs->n & 0xff); 3452 run_rt3070_rf_read(sc, 9, &rf); 3453 rf &= ~(1 << 4); 3454 rf |= ((freqs->n & 0x0100) >> 8) << 4; 3455 run_rt3070_rf_write(sc, 9, rf); 3456 3457 /* K setting. */ 3458 run_rt3070_rf_read(sc, 9, &rf); 3459 rf &= ~0x0f; 3460 rf |= (freqs->k & 0x0f); 3461 run_rt3070_rf_write(sc, 9, rf); 3462 3463 /* Mode setting. */ 3464 run_rt3070_rf_read(sc, 11, &rf); 3465 rf &= ~0x0c; 3466 rf |= ((freqs->m - 0x8) & 0x3) << 2; 3467 run_rt3070_rf_write(sc, 11, rf); 3468 run_rt3070_rf_read(sc, 9, &rf); 3469 rf &= ~(1 << 7); 3470 rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; 3471 run_rt3070_rf_write(sc, 9, rf); 3472 3473 /* R setting. */ 3474 run_rt3070_rf_read(sc, 11, &rf); 3475 rf &= ~0x03; 3476 rf |= (freqs->r - 0x1); 3477 run_rt3070_rf_write(sc, 11, rf); 3478 3479 if (chan <= 14) { 3480 /* Initialize RF registers for 2GHZ. */ 3481 for (i = 0; i < nitems(rt5592_2ghz_def_rf); i++) { 3482 run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, 3483 rt5592_2ghz_def_rf[i].val); 3484 } 3485 3486 rf = (chan <= 10) ? 0x07 : 0x06; 3487 run_rt3070_rf_write(sc, 23, rf); 3488 run_rt3070_rf_write(sc, 59, rf); 3489 3490 run_rt3070_rf_write(sc, 55, 0x43); 3491 3492 /* 3493 * RF R49/R50 Tx power ALC code. 3494 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. 3495 */ 3496 reg = 2; 3497 txpow_bound = 0x27; 3498 } else { 3499 /* Initialize RF registers for 5GHZ. */ 3500 for (i = 0; i < nitems(rt5592_5ghz_def_rf); i++) { 3501 run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, 3502 rt5592_5ghz_def_rf[i].val); 3503 } 3504 for (i = 0; i < nitems(rt5592_chan_5ghz); i++) { 3505 if (chan >= rt5592_chan_5ghz[i].firstchan && 3506 chan <= rt5592_chan_5ghz[i].lastchan) { 3507 run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, 3508 rt5592_chan_5ghz[i].val); 3509 } 3510 } 3511 3512 /* 3513 * RF R49/R50 Tx power ALC code. 3514 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. 3515 */ 3516 reg = 3; 3517 txpow_bound = 0x2b; 3518 } 3519 3520 /* RF R49 ch0 Tx power ALC code. */ 3521 run_rt3070_rf_read(sc, 49, &rf); 3522 rf &= ~0xc0; 3523 rf |= (reg << 6); 3524 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3525 if ((rf & 0x3f) > txpow_bound) 3526 rf = (rf & ~0x3f) | txpow_bound; 3527 run_rt3070_rf_write(sc, 49, rf); 3528 3529 /* RF R50 ch1 Tx power ALC code. */ 3530 run_rt3070_rf_read(sc, 50, &rf); 3531 rf &= ~(1 << 7 | 1 << 6); 3532 rf |= (reg << 6); 3533 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3534 if ((rf & 0x3f) > txpow_bound) 3535 rf = (rf & ~0x3f) | txpow_bound; 3536 run_rt3070_rf_write(sc, 50, rf); 3537 3538 /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ 3539 run_rt3070_rf_read(sc, 1, &rf); 3540 rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD); 3541 if (sc->ntxchains > 1) 3542 rf |= RT3070_TX1_PD; 3543 if (sc->nrxchains > 1) 3544 rf |= RT3070_RX1_PD; 3545 run_rt3070_rf_write(sc, 1, rf); 3546 3547 run_rt3070_rf_write(sc, 6, 0xe4); 3548 3549 run_rt3070_rf_write(sc, 30, 0x10); 3550 run_rt3070_rf_write(sc, 31, 0x80); 3551 run_rt3070_rf_write(sc, 32, 0x80); 3552 3553 run_adjust_freq_offset(sc); 3554 3555 /* Enable VCO calibration. */ 3556 run_rt3070_rf_read(sc, 3, &rf); 3557 rf |= RT3593_VCOCAL; 3558 run_rt3070_rf_write(sc, 3, rf); 3559 } 3560 3561 void 3562 run_set_agc(struct run_softc *sc, uint8_t agc) 3563 { 3564 uint8_t bbp; 3565 3566 if (sc->mac_ver == 0x3572) { 3567 run_bbp_read(sc, 27, &bbp); 3568 bbp &= ~(0x3 << 5); 3569 run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ 3570 run_bbp_write(sc, 66, agc); 3571 run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ 3572 run_bbp_write(sc, 66, agc); 3573 } else 3574 run_bbp_write(sc, 66, agc); 3575 } 3576 3577 void 3578 run_set_rx_antenna(struct run_softc *sc, int aux) 3579 { 3580 uint32_t tmp; 3581 uint8_t bbp152; 3582 3583 if (aux) { 3584 if (sc->rf_rev == RT5390_RF_5370) { 3585 run_bbp_read(sc, 152, &bbp152); 3586 run_bbp_write(sc, 152, bbp152 & ~0x80); 3587 } else { 3588 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 0); 3589 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3590 run_write(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 3591 } 3592 } else { 3593 if (sc->rf_rev == RT5390_RF_5370) { 3594 run_bbp_read(sc, 152, &bbp152); 3595 run_bbp_write(sc, 152, bbp152 | 0x80); 3596 } else { 3597 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 1); 3598 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3599 run_write(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 3600 } 3601 } 3602 } 3603 3604 int 3605 run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) 3606 { 3607 struct ieee80211com *ic = &sc->sc_ic; 3608 u_int chan, group; 3609 3610 chan = ieee80211_chan2ieee(ic, c); 3611 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3612 return EINVAL; 3613 3614 if (sc->mac_ver == 0x5592) 3615 run_rt5592_set_chan(sc, chan); 3616 else if (sc->mac_ver >= 0x5390) 3617 run_rt5390_set_chan(sc, chan); 3618 else if (sc->mac_ver == 0x3593) 3619 run_rt3593_set_chan(sc, chan); 3620 else if (sc->mac_ver == 0x3572) 3621 run_rt3572_set_chan(sc, chan); 3622 else if (sc->mac_ver >= 0x3070) 3623 run_rt3070_set_chan(sc, chan); 3624 else 3625 run_rt2870_set_chan(sc, chan); 3626 3627 /* determine channel group */ 3628 if (chan <= 14) 3629 group = 0; 3630 else if (chan <= 64) 3631 group = 1; 3632 else if (chan <= 128) 3633 group = 2; 3634 else 3635 group = 3; 3636 3637 /* XXX necessary only when group has changed! */ 3638 run_select_chan_group(sc, group); 3639 3640 DELAY(1000); 3641 3642 /* Perform IQ calibration. */ 3643 if (sc->mac_ver >= 0x5392) 3644 run_iq_calib(sc, chan); 3645 3646 return 0; 3647 } 3648 3649 void 3650 run_enable_tsf_sync(struct run_softc *sc) 3651 { 3652 struct ieee80211com *ic = &sc->sc_ic; 3653 uint32_t tmp; 3654 3655 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 3656 tmp &= ~0x1fffff; 3657 tmp |= ic->ic_bss->ni_intval * 16; 3658 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3659 /* local TSF is always updated with remote TSF on beacon reception */ 3660 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3661 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 3662 } 3663 3664 void 3665 run_enable_mrr(struct run_softc *sc) 3666 { 3667 #define CCK(mcs) (mcs) 3668 #define OFDM(mcs) (1 << 3 | (mcs)) 3669 run_write(sc, RT2860_LG_FBK_CFG0, 3670 OFDM(6) << 28 | /* 54->48 */ 3671 OFDM(5) << 24 | /* 48->36 */ 3672 OFDM(4) << 20 | /* 36->24 */ 3673 OFDM(3) << 16 | /* 24->18 */ 3674 OFDM(2) << 12 | /* 18->12 */ 3675 OFDM(1) << 8 | /* 12-> 9 */ 3676 OFDM(0) << 4 | /* 9-> 6 */ 3677 OFDM(0)); /* 6-> 6 */ 3678 3679 run_write(sc, RT2860_LG_FBK_CFG1, 3680 CCK(2) << 12 | /* 11->5.5 */ 3681 CCK(1) << 8 | /* 5.5-> 2 */ 3682 CCK(0) << 4 | /* 2-> 1 */ 3683 CCK(0)); /* 1-> 1 */ 3684 #undef OFDM 3685 #undef CCK 3686 } 3687 3688 void 3689 run_set_txpreamble(struct run_softc *sc) 3690 { 3691 uint32_t tmp; 3692 3693 run_read(sc, RT2860_AUTO_RSP_CFG, &tmp); 3694 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 3695 tmp |= RT2860_CCK_SHORT_EN; 3696 else 3697 tmp &= ~RT2860_CCK_SHORT_EN; 3698 run_write(sc, RT2860_AUTO_RSP_CFG, tmp); 3699 } 3700 3701 void 3702 run_set_basicrates(struct run_softc *sc) 3703 { 3704 struct ieee80211com *ic = &sc->sc_ic; 3705 3706 /* set basic rates mask */ 3707 if (ic->ic_curmode == IEEE80211_MODE_11B) 3708 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 3709 else if (ic->ic_curmode == IEEE80211_MODE_11A) 3710 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 3711 else /* 11g */ 3712 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 3713 } 3714 3715 void 3716 run_set_leds(struct run_softc *sc, uint16_t which) 3717 { 3718 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3719 which | (sc->leds & 0x7f)); 3720 } 3721 3722 void 3723 run_set_bssid(struct run_softc *sc, const uint8_t *bssid) 3724 { 3725 run_write(sc, RT2860_MAC_BSSID_DW0, 3726 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3727 run_write(sc, RT2860_MAC_BSSID_DW1, 3728 bssid[4] | bssid[5] << 8); 3729 } 3730 3731 void 3732 run_set_macaddr(struct run_softc *sc, const uint8_t *addr) 3733 { 3734 run_write(sc, RT2860_MAC_ADDR_DW0, 3735 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3736 run_write(sc, RT2860_MAC_ADDR_DW1, 3737 addr[4] | addr[5] << 8 | 0xff << 16); 3738 } 3739 3740 void 3741 run_updateslot(struct ieee80211com *ic) 3742 { 3743 /* do it in a process context */ 3744 run_do_async(ic->ic_softc, run_updateslot_cb, NULL, 0); 3745 } 3746 3747 /* ARGSUSED */ 3748 void 3749 run_updateslot_cb(struct run_softc *sc, void *arg) 3750 { 3751 uint32_t tmp; 3752 3753 run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp); 3754 tmp &= ~0xff; 3755 tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 3756 IEEE80211_DUR_DS_SHSLOT : IEEE80211_DUR_DS_SLOT; 3757 run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3758 } 3759 3760 #if NBPFILTER > 0 3761 int8_t 3762 run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain) 3763 { 3764 struct ieee80211com *ic = &sc->sc_ic; 3765 struct ieee80211_channel *c = ic->ic_ibss_chan; 3766 int delta; 3767 3768 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3769 u_int chan = ieee80211_chan2ieee(ic, c); 3770 delta = sc->rssi_5ghz[rxchain]; 3771 3772 /* determine channel group */ 3773 if (chan <= 64) 3774 delta -= sc->lna[1]; 3775 else if (chan <= 128) 3776 delta -= sc->lna[2]; 3777 else 3778 delta -= sc->lna[3]; 3779 } else 3780 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3781 3782 return -12 - delta - rssi; 3783 } 3784 #endif 3785 3786 void 3787 run_rt5390_bbp_init(struct run_softc *sc) 3788 { 3789 int i; 3790 uint8_t bbp; 3791 3792 /* Apply maximum likelihood detection for 2 stream case. */ 3793 run_bbp_read(sc, 105, &bbp); 3794 if (sc->nrxchains > 1) 3795 run_bbp_write(sc, 105, bbp | RT5390_MLD); 3796 3797 /* Avoid data lost and CRC error. */ 3798 run_bbp_read(sc, 4, &bbp); 3799 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3800 3801 if (sc->mac_ver == 0x5592) { 3802 for (i = 0; i < nitems(rt5592_def_bbp); i++) { 3803 run_bbp_write(sc, rt5592_def_bbp[i].reg, 3804 rt5592_def_bbp[i].val); 3805 } 3806 for (i = 0; i < nitems(rt5592_bbp_r196); i++) { 3807 run_bbp_write(sc, 195, i + 0x80); 3808 run_bbp_write(sc, 196, rt5592_bbp_r196[i]); 3809 } 3810 } else { 3811 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3812 run_bbp_write(sc, rt5390_def_bbp[i].reg, 3813 rt5390_def_bbp[i].val); 3814 } 3815 } 3816 if (sc->mac_ver == 0x5392) { 3817 run_bbp_write(sc, 88, 0x90); 3818 run_bbp_write(sc, 95, 0x9a); 3819 run_bbp_write(sc, 98, 0x12); 3820 run_bbp_write(sc, 106, 0x12); 3821 run_bbp_write(sc, 134, 0xd0); 3822 run_bbp_write(sc, 135, 0xf6); 3823 run_bbp_write(sc, 148, 0x84); 3824 } 3825 3826 run_bbp_read(sc, 152, &bbp); 3827 run_bbp_write(sc, 152, bbp | 0x80); 3828 3829 /* Fix BBP254 for RT5592C. */ 3830 if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { 3831 run_bbp_read(sc, 254, &bbp); 3832 run_bbp_write(sc, 254, bbp | 0x80); 3833 } 3834 3835 /* Disable hardware antenna diversity. */ 3836 if (sc->mac_ver == 0x5390) 3837 run_bbp_write(sc, 154, 0); 3838 3839 /* Initialize Rx CCK/OFDM frequency offset report. */ 3840 run_bbp_write(sc, 142, 1); 3841 run_bbp_write(sc, 143, 57); 3842 } 3843 3844 int 3845 run_bbp_init(struct run_softc *sc) 3846 { 3847 int i, error, ntries; 3848 uint8_t bbp0; 3849 3850 /* wait for BBP to wake up */ 3851 for (ntries = 0; ntries < 20; ntries++) { 3852 if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) 3853 return error; 3854 if (bbp0 != 0 && bbp0 != 0xff) 3855 break; 3856 } 3857 if (ntries == 20) 3858 return ETIMEDOUT; 3859 3860 /* initialize BBP registers to default values */ 3861 if (sc->mac_ver >= 0x5390) 3862 run_rt5390_bbp_init(sc); 3863 else { 3864 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3865 run_bbp_write(sc, rt2860_def_bbp[i].reg, 3866 rt2860_def_bbp[i].val); 3867 } 3868 } 3869 3870 if (sc->mac_ver == 0x3593) { 3871 run_bbp_write(sc, 79, 0x13); 3872 run_bbp_write(sc, 80, 0x05); 3873 run_bbp_write(sc, 81, 0x33); 3874 run_bbp_write(sc, 86, 0x46); 3875 run_bbp_write(sc, 137, 0x0f); 3876 } 3877 3878 /* fix BBP84 for RT2860E */ 3879 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3880 run_bbp_write(sc, 84, 0x19); 3881 3882 if (sc->mac_ver >= 0x3070 && (sc->mac_ver != 0x3593 && 3883 sc->mac_ver != 0x5592)) { 3884 run_bbp_write(sc, 79, 0x13); 3885 run_bbp_write(sc, 80, 0x05); 3886 run_bbp_write(sc, 81, 0x33); 3887 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3888 run_bbp_write(sc, 69, 0x16); 3889 run_bbp_write(sc, 73, 0x12); 3890 } 3891 return 0; 3892 } 3893 3894 int 3895 run_rt3070_rf_init(struct run_softc *sc) 3896 { 3897 uint32_t tmp; 3898 uint8_t bbp4, mingain, rf, target; 3899 int i; 3900 3901 run_rt3070_rf_read(sc, 30, &rf); 3902 /* toggle RF R30 bit 7 */ 3903 run_rt3070_rf_write(sc, 30, rf | 0x80); 3904 DELAY(1000); 3905 run_rt3070_rf_write(sc, 30, rf & ~0x80); 3906 3907 /* initialize RF registers to default value */ 3908 if (sc->mac_ver == 0x3572) { 3909 for (i = 0; i < nitems(rt3572_def_rf); i++) { 3910 run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, 3911 rt3572_def_rf[i].val); 3912 } 3913 } else { 3914 for (i = 0; i < nitems(rt3070_def_rf); i++) { 3915 run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, 3916 rt3070_def_rf[i].val); 3917 } 3918 } 3919 if (sc->mac_ver == 0x3070 && sc->mac_rev < 0x0201) { 3920 /* 3921 * Change voltage from 1.2V to 1.35V for RT3070. 3922 * The DAC issue (RT3070_LDO_CFG0) has been fixed 3923 * in RT3070(F). 3924 */ 3925 run_read(sc, RT3070_LDO_CFG0, &tmp); 3926 tmp = (tmp & ~0x0f000000) | 0x0d000000; 3927 run_write(sc, RT3070_LDO_CFG0, tmp); 3928 3929 } else if (sc->mac_ver == 0x3071) { 3930 run_rt3070_rf_read(sc, 6, &rf); 3931 run_rt3070_rf_write(sc, 6, rf | 0x40); 3932 run_rt3070_rf_write(sc, 31, 0x14); 3933 3934 run_read(sc, RT3070_LDO_CFG0, &tmp); 3935 tmp &= ~0x1f000000; 3936 if (sc->mac_rev < 0x0211) 3937 tmp |= 0x0d000000; /* 1.35V */ 3938 else 3939 tmp |= 0x01000000; /* 1.2V */ 3940 run_write(sc, RT3070_LDO_CFG0, tmp); 3941 3942 /* patch LNA_PE_G1 */ 3943 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 3944 run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 3945 3946 } else if (sc->mac_ver == 0x3572) { 3947 run_rt3070_rf_read(sc, 6, &rf); 3948 run_rt3070_rf_write(sc, 6, rf | 0x40); 3949 /* increase voltage from 1.2V to 1.35V */ 3950 run_read(sc, RT3070_LDO_CFG0, &tmp); 3951 tmp = (tmp & ~0x1f000000) | 0x0d000000; 3952 run_write(sc, RT3070_LDO_CFG0, tmp); 3953 3954 if (sc->mac_rev < 0x0211 || !sc->patch_dac) { 3955 DELAY(1); /* wait for 1msec */ 3956 /* decrease voltage back to 1.2V */ 3957 tmp = (tmp & ~0x1f000000) | 0x01000000; 3958 run_write(sc, RT3070_LDO_CFG0, tmp); 3959 } 3960 } 3961 3962 /* select 20MHz bandwidth */ 3963 run_rt3070_rf_read(sc, 31, &rf); 3964 run_rt3070_rf_write(sc, 31, rf & ~0x20); 3965 3966 /* calibrate filter for 20MHz bandwidth */ 3967 sc->rf24_20mhz = 0x1f; /* default value */ 3968 target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; 3969 run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); 3970 3971 /* select 40MHz bandwidth */ 3972 run_bbp_read(sc, 4, &bbp4); 3973 run_bbp_write(sc, 4, (bbp4 & ~0x18) | 0x10); 3974 run_rt3070_rf_read(sc, 31, &rf); 3975 run_rt3070_rf_write(sc, 31, rf | 0x20); 3976 3977 /* calibrate filter for 40MHz bandwidth */ 3978 sc->rf24_40mhz = 0x2f; /* default value */ 3979 target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; 3980 run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); 3981 3982 /* go back to 20MHz bandwidth */ 3983 run_bbp_read(sc, 4, &bbp4); 3984 run_bbp_write(sc, 4, bbp4 & ~0x18); 3985 3986 if (sc->mac_ver == 0x3572) { 3987 /* save default BBP registers 25 and 26 values */ 3988 run_bbp_read(sc, 25, &sc->bbp25); 3989 run_bbp_read(sc, 26, &sc->bbp26); 3990 3991 } else if (sc->mac_rev < 0x0201 || sc->mac_rev < 0x0211) 3992 run_rt3070_rf_write(sc, 27, 0x03); 3993 3994 run_read(sc, RT3070_OPT_14, &tmp); 3995 run_write(sc, RT3070_OPT_14, tmp | 1); 3996 3997 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 3998 run_rt3070_rf_read(sc, 17, &rf); 3999 rf &= ~RT3070_TX_LO1; 4000 if ((sc->mac_ver == 0x3070 || 4001 (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && 4002 !sc->ext_2ghz_lna) 4003 rf |= 0x20; /* fix for long range Rx issue */ 4004 mingain = (sc->mac_ver == 0x3070) ? 1 : 2; 4005 if (sc->txmixgain_2ghz >= mingain) 4006 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 4007 run_rt3070_rf_write(sc, 17, rf); 4008 } 4009 if (sc->mac_ver == 0x3071) { 4010 run_rt3070_rf_read(sc, 1, &rf); 4011 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 4012 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 4013 run_rt3070_rf_write(sc, 1, rf); 4014 4015 run_rt3070_rf_read(sc, 15, &rf); 4016 run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 4017 4018 run_rt3070_rf_read(sc, 20, &rf); 4019 run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 4020 4021 run_rt3070_rf_read(sc, 21, &rf); 4022 run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 4023 } 4024 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4025 /* fix Tx to Rx IQ glitch by raising RF voltage */ 4026 run_rt3070_rf_read(sc, 27, &rf); 4027 rf &= ~0x77; 4028 if (sc->mac_rev < 0x0211) 4029 rf |= 0x03; 4030 run_rt3070_rf_write(sc, 27, rf); 4031 } 4032 return 0; 4033 } 4034 4035 void 4036 run_rt3593_rf_init(struct run_softc *sc) 4037 { 4038 uint32_t tmp; 4039 uint8_t rf; 4040 int i; 4041 4042 /* Disable the GPIO bits 4 and 7 for LNA PE control. */ 4043 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4044 tmp &= ~(1 << 4 | 1 << 7); 4045 run_write(sc, RT3070_GPIO_SWITCH, tmp); 4046 4047 /* Initialize RF registers to default value. */ 4048 for (i = 0; i < nitems(rt3593_def_rf); i++) { 4049 run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, 4050 rt3593_def_rf[i].val); 4051 } 4052 4053 /* Toggle RF R2 to initiate calibration. */ 4054 run_rt3070_rf_write(sc, 2, RT3593_RESCAL); 4055 4056 /* Initialize RF frequency offset. */ 4057 run_adjust_freq_offset(sc); 4058 4059 run_rt3070_rf_read(sc, 18, &rf); 4060 run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); 4061 4062 /* 4063 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to 4064 * decrease voltage back to 1.2V. 4065 */ 4066 run_read(sc, RT3070_LDO_CFG0, &tmp); 4067 tmp = (tmp & ~0x1f000000) | 0x0d000000; 4068 run_write(sc, RT3070_LDO_CFG0, tmp); 4069 DELAY(1); 4070 tmp = (tmp & ~0x1f000000) | 0x01000000; 4071 run_write(sc, RT3070_LDO_CFG0, tmp); 4072 4073 sc->rf24_20mhz = 0x1f; 4074 sc->rf24_40mhz = 0x2f; 4075 4076 /* Save default BBP registers 25 and 26 values. */ 4077 run_bbp_read(sc, 25, &sc->bbp25); 4078 run_bbp_read(sc, 26, &sc->bbp26); 4079 4080 run_read(sc, RT3070_OPT_14, &tmp); 4081 run_write(sc, RT3070_OPT_14, tmp | 1); 4082 } 4083 4084 void 4085 run_rt5390_rf_init(struct run_softc *sc) 4086 { 4087 uint32_t tmp; 4088 uint8_t rf; 4089 int i; 4090 4091 /* Toggle RF R2 to initiate calibration. */ 4092 if (sc->mac_ver == 0x5390) { 4093 run_rt3070_rf_read(sc, 2, &rf); 4094 run_rt3070_rf_write(sc, 2, rf | RT3593_RESCAL); 4095 DELAY(10); 4096 run_rt3070_rf_write(sc, 2, rf & ~RT3593_RESCAL); 4097 } else { 4098 run_rt3070_rf_write(sc, 2, RT3593_RESCAL); 4099 DELAY(10); 4100 } 4101 4102 /* Initialize RF registers to default value. */ 4103 if (sc->mac_ver == 0x5592) { 4104 for (i = 0; i < nitems(rt5592_def_rf); i++) { 4105 run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, 4106 rt5592_def_rf[i].val); 4107 } 4108 /* Initialize RF frequency offset. */ 4109 run_adjust_freq_offset(sc); 4110 } else if (sc->mac_ver == 0x5392) { 4111 for (i = 0; i < nitems(rt5392_def_rf); i++) { 4112 run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, 4113 rt5392_def_rf[i].val); 4114 } 4115 if (sc->mac_rev >= 0x0223) { 4116 run_rt3070_rf_write(sc, 23, 0x0f); 4117 run_rt3070_rf_write(sc, 24, 0x3e); 4118 run_rt3070_rf_write(sc, 51, 0x32); 4119 run_rt3070_rf_write(sc, 53, 0x22); 4120 run_rt3070_rf_write(sc, 56, 0xc1); 4121 run_rt3070_rf_write(sc, 59, 0x0f); 4122 } 4123 } else { 4124 for (i = 0; i < nitems(rt5390_def_rf); i++) { 4125 run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, 4126 rt5390_def_rf[i].val); 4127 } 4128 if (sc->mac_rev >= 0x0502) { 4129 run_rt3070_rf_write(sc, 6, 0xe0); 4130 run_rt3070_rf_write(sc, 25, 0x80); 4131 run_rt3070_rf_write(sc, 46, 0x73); 4132 run_rt3070_rf_write(sc, 53, 0x00); 4133 run_rt3070_rf_write(sc, 56, 0x42); 4134 run_rt3070_rf_write(sc, 61, 0xd1); 4135 } 4136 } 4137 4138 sc->rf24_20mhz = 0x1f; /* default value */ 4139 sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; 4140 4141 if (sc->mac_rev < 0x0211) 4142 run_rt3070_rf_write(sc, 27, 0x3); 4143 4144 run_read(sc, RT3070_OPT_14, &tmp); 4145 run_write(sc, RT3070_OPT_14, tmp | 1); 4146 } 4147 4148 int 4149 run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, 4150 uint8_t *val) 4151 { 4152 uint8_t rf22, rf24; 4153 uint8_t bbp55_pb, bbp55_sb, delta; 4154 int ntries; 4155 4156 /* program filter */ 4157 run_rt3070_rf_read(sc, 24, &rf24); 4158 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 4159 run_rt3070_rf_write(sc, 24, rf24); 4160 4161 /* enable baseband loopback mode */ 4162 run_rt3070_rf_read(sc, 22, &rf22); 4163 run_rt3070_rf_write(sc, 22, rf22 | 0x01); 4164 4165 /* set power and frequency of passband test tone */ 4166 run_bbp_write(sc, 24, 0x00); 4167 for (ntries = 0; ntries < 100; ntries++) { 4168 /* transmit test tone */ 4169 run_bbp_write(sc, 25, 0x90); 4170 DELAY(1000); 4171 /* read received power */ 4172 run_bbp_read(sc, 55, &bbp55_pb); 4173 if (bbp55_pb != 0) 4174 break; 4175 } 4176 if (ntries == 100) 4177 return ETIMEDOUT; 4178 4179 /* set power and frequency of stopband test tone */ 4180 run_bbp_write(sc, 24, 0x06); 4181 for (ntries = 0; ntries < 100; ntries++) { 4182 /* transmit test tone */ 4183 run_bbp_write(sc, 25, 0x90); 4184 DELAY(1000); 4185 /* read received power */ 4186 run_bbp_read(sc, 55, &bbp55_sb); 4187 4188 delta = bbp55_pb - bbp55_sb; 4189 if (delta > target) 4190 break; 4191 4192 /* reprogram filter */ 4193 rf24++; 4194 run_rt3070_rf_write(sc, 24, rf24); 4195 } 4196 if (ntries < 100) { 4197 if (rf24 != init) 4198 rf24--; /* backtrack */ 4199 *val = rf24; 4200 run_rt3070_rf_write(sc, 24, rf24); 4201 } 4202 4203 /* restore initial state */ 4204 run_bbp_write(sc, 24, 0x00); 4205 4206 /* disable baseband loopback mode */ 4207 run_rt3070_rf_read(sc, 22, &rf22); 4208 run_rt3070_rf_write(sc, 22, rf22 & ~0x01); 4209 4210 return 0; 4211 } 4212 4213 void 4214 run_rt3070_rf_setup(struct run_softc *sc) 4215 { 4216 uint8_t bbp, rf; 4217 int i; 4218 4219 if (sc->mac_ver == 0x3572) { 4220 /* enable DC filter */ 4221 if (sc->mac_rev >= 0x0201) 4222 run_bbp_write(sc, 103, 0xc0); 4223 4224 run_bbp_read(sc, 138, &bbp); 4225 if (sc->ntxchains == 1) 4226 bbp |= 0x20; /* turn off DAC1 */ 4227 if (sc->nrxchains == 1) 4228 bbp &= ~0x02; /* turn off ADC1 */ 4229 run_bbp_write(sc, 138, bbp); 4230 4231 if (sc->mac_rev >= 0x0211) { 4232 /* improve power consumption */ 4233 run_bbp_read(sc, 31, &bbp); 4234 run_bbp_write(sc, 31, bbp & ~0x03); 4235 } 4236 4237 run_rt3070_rf_read(sc, 16, &rf); 4238 rf = (rf & ~0x07) | sc->txmixgain_2ghz; 4239 run_rt3070_rf_write(sc, 16, rf); 4240 4241 } else if (sc->mac_ver == 0x3071) { 4242 /* enable DC filter */ 4243 if (sc->mac_rev >= 0x0211) { 4244 run_bbp_write(sc, 103, 0xc0); 4245 4246 /* improve power consumption */ 4247 run_bbp_read(sc, 31, &bbp); 4248 run_bbp_write(sc, 31, bbp & ~0x03); 4249 } 4250 4251 run_bbp_read(sc, 138, &bbp); 4252 if (sc->ntxchains == 1) 4253 bbp |= 0x20; /* turn off DAC1 */ 4254 if (sc->nrxchains == 1) 4255 bbp &= ~0x02; /* turn off ADC1 */ 4256 run_bbp_write(sc, 138, bbp); 4257 4258 run_write(sc, RT2860_TX_SW_CFG1, 0); 4259 if (sc->mac_rev < 0x0211) { 4260 run_write(sc, RT2860_TX_SW_CFG2, 4261 sc->patch_dac ? 0x2c : 0x0f); 4262 } else 4263 run_write(sc, RT2860_TX_SW_CFG2, 0); 4264 4265 } else if (sc->mac_ver == 0x3070) { 4266 if (sc->mac_rev >= 0x0201) { 4267 /* enable DC filter */ 4268 run_bbp_write(sc, 103, 0xc0); 4269 4270 /* improve power consumption */ 4271 run_bbp_read(sc, 31, &bbp); 4272 run_bbp_write(sc, 31, bbp & ~0x03); 4273 } 4274 4275 if (sc->mac_rev < 0x0201) { 4276 run_write(sc, RT2860_TX_SW_CFG1, 0); 4277 run_write(sc, RT2860_TX_SW_CFG2, 0x2c); 4278 } else 4279 run_write(sc, RT2860_TX_SW_CFG2, 0); 4280 } 4281 4282 /* initialize RF registers from ROM for >=RT3071*/ 4283 if (sc->mac_ver >= 0x3071) { 4284 for (i = 0; i < 10; i++) { 4285 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 4286 continue; 4287 run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 4288 } 4289 } 4290 } 4291 4292 void 4293 run_rt3593_rf_setup(struct run_softc *sc) 4294 { 4295 uint8_t bbp, rf; 4296 4297 if (sc->mac_rev >= 0x0211) { 4298 /* Enable DC filter. */ 4299 run_bbp_write(sc, 103, 0xc0); 4300 } 4301 run_write(sc, RT2860_TX_SW_CFG1, 0); 4302 if (sc->mac_rev < 0x0211) { 4303 run_write(sc, RT2860_TX_SW_CFG2, 4304 sc->patch_dac ? 0x2c : 0x0f); 4305 } else 4306 run_write(sc, RT2860_TX_SW_CFG2, 0); 4307 4308 run_rt3070_rf_read(sc, 50, &rf); 4309 run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); 4310 4311 run_rt3070_rf_read(sc, 51, &rf); 4312 rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | 4313 ((sc->txmixgain_2ghz & 0x07) << 2); 4314 run_rt3070_rf_write(sc, 51, rf); 4315 4316 run_rt3070_rf_read(sc, 38, &rf); 4317 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4318 4319 run_rt3070_rf_read(sc, 39, &rf); 4320 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4321 4322 run_rt3070_rf_read(sc, 1, &rf); 4323 run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); 4324 4325 run_rt3070_rf_read(sc, 30, &rf); 4326 rf = (rf & ~0x18) | 0x10; 4327 run_rt3070_rf_write(sc, 30, rf); 4328 4329 /* Apply maximum likelihood detection for 2 stream case. */ 4330 run_bbp_read(sc, 105, &bbp); 4331 if (sc->nrxchains > 1) 4332 run_bbp_write(sc, 105, bbp | RT5390_MLD); 4333 4334 /* Avoid data lost and CRC error. */ 4335 run_bbp_read(sc, 4, &bbp); 4336 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4337 4338 run_bbp_write(sc, 92, 0x02); 4339 run_bbp_write(sc, 82, 0x82); 4340 run_bbp_write(sc, 106, 0x05); 4341 run_bbp_write(sc, 104, 0x92); 4342 run_bbp_write(sc, 88, 0x90); 4343 run_bbp_write(sc, 148, 0xc8); 4344 run_bbp_write(sc, 47, 0x48); 4345 run_bbp_write(sc, 120, 0x50); 4346 4347 run_bbp_write(sc, 163, 0x9d); 4348 4349 /* SNR mapping. */ 4350 run_bbp_write(sc, 142, 0x06); 4351 run_bbp_write(sc, 143, 0xa0); 4352 run_bbp_write(sc, 142, 0x07); 4353 run_bbp_write(sc, 143, 0xa1); 4354 run_bbp_write(sc, 142, 0x08); 4355 run_bbp_write(sc, 143, 0xa2); 4356 4357 run_bbp_write(sc, 31, 0x08); 4358 run_bbp_write(sc, 68, 0x0b); 4359 run_bbp_write(sc, 105, 0x04); 4360 } 4361 4362 void 4363 run_rt5390_rf_setup(struct run_softc *sc) 4364 { 4365 uint8_t bbp, rf; 4366 4367 if (sc->mac_rev >= 0x0211) { 4368 /* Enable DC filter. */ 4369 run_bbp_write(sc, 103, 0xc0); 4370 4371 if (sc->mac_ver != 0x5592) { 4372 /* Improve power consumption. */ 4373 run_bbp_read(sc, 31, &bbp); 4374 run_bbp_write(sc, 31, bbp & ~0x03); 4375 } 4376 } 4377 4378 run_bbp_read(sc, 138, &bbp); 4379 if (sc->ntxchains == 1) 4380 bbp |= 0x20; /* turn off DAC1 */ 4381 if (sc->nrxchains == 1) 4382 bbp &= ~0x02; /* turn off ADC1 */ 4383 run_bbp_write(sc, 138, bbp); 4384 4385 run_rt3070_rf_read(sc, 38, &rf); 4386 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4387 4388 run_rt3070_rf_read(sc, 39, &rf); 4389 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4390 4391 /* Avoid data lost and CRC error. */ 4392 run_bbp_read(sc, 4, &bbp); 4393 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4394 4395 run_rt3070_rf_read(sc, 30, &rf); 4396 rf = (rf & ~0x18) | 0x10; 4397 run_rt3070_rf_write(sc, 30, rf); 4398 4399 if (sc->mac_ver != 0x5592) { 4400 run_write(sc, RT2860_TX_SW_CFG1, 0); 4401 if (sc->mac_rev < 0x0211) { 4402 run_write(sc, RT2860_TX_SW_CFG2, 4403 sc->patch_dac ? 0x2c : 0x0f); 4404 } else 4405 run_write(sc, RT2860_TX_SW_CFG2, 0); 4406 } 4407 } 4408 4409 int 4410 run_txrx_enable(struct run_softc *sc) 4411 { 4412 uint32_t tmp; 4413 int error, ntries; 4414 4415 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 4416 for (ntries = 0; ntries < 200; ntries++) { 4417 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4418 return error; 4419 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4420 break; 4421 DELAY(1000); 4422 } 4423 if (ntries == 200) 4424 return ETIMEDOUT; 4425 4426 DELAY(50); 4427 4428 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE; 4429 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4430 4431 /* enable Rx bulk aggregation (set timeout and limit) */ 4432 tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN | 4433 RT2860_USB_RX_AGG_TO(128) | RT2860_USB_RX_AGG_LMT(2); 4434 run_write(sc, RT2860_USB_DMA_CFG, tmp); 4435 4436 /* set Rx filter */ 4437 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 4438 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 4439 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 4440 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 4441 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 4442 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 4443 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 4444 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 4445 } 4446 run_write(sc, RT2860_RX_FILTR_CFG, tmp); 4447 4448 run_write(sc, RT2860_MAC_SYS_CTRL, 4449 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4450 4451 return 0; 4452 } 4453 4454 void 4455 run_adjust_freq_offset(struct run_softc *sc) 4456 { 4457 uint8_t rf, tmp; 4458 4459 run_rt3070_rf_read(sc, 17, &rf); 4460 tmp = rf; 4461 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 4462 rf = MIN(rf, 0x5f); 4463 4464 if (tmp != rf) 4465 run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); 4466 } 4467 4468 int 4469 run_init(struct ifnet *ifp) 4470 { 4471 struct run_softc *sc = ifp->if_softc; 4472 struct ieee80211com *ic = &sc->sc_ic; 4473 uint32_t tmp; 4474 uint8_t bbp1, bbp3; 4475 int i, error, qid, ridx, ntries; 4476 4477 if (usbd_is_dying(sc->sc_udev)) 4478 return ENXIO; 4479 4480 for (ntries = 0; ntries < 100; ntries++) { 4481 if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0) 4482 goto fail; 4483 if (tmp != 0 && tmp != 0xffffffff) 4484 break; 4485 DELAY(10); 4486 } 4487 if (ntries == 100) { 4488 error = ETIMEDOUT; 4489 goto fail; 4490 } 4491 4492 if ((error = run_load_microcode(sc)) != 0) { 4493 printf("%s: could not load 8051 microcode\n", 4494 sc->sc_dev.dv_xname); 4495 goto fail; 4496 } 4497 4498 /* init host command ring */ 4499 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4500 4501 /* init Tx rings (4 EDCAs) */ 4502 for (qid = 0; qid < 4; qid++) { 4503 if ((error = run_alloc_tx_ring(sc, qid)) != 0) 4504 goto fail; 4505 } 4506 /* init Rx ring */ 4507 if ((error = run_alloc_rx_ring(sc)) != 0) 4508 goto fail; 4509 4510 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 4511 run_set_macaddr(sc, ic->ic_myaddr); 4512 4513 for (ntries = 0; ntries < 100; ntries++) { 4514 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4515 goto fail; 4516 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4517 break; 4518 DELAY(1000); 4519 } 4520 if (ntries == 100) { 4521 printf("%s: timeout waiting for DMA engine\n", 4522 sc->sc_dev.dv_xname); 4523 error = ETIMEDOUT; 4524 goto fail; 4525 } 4526 tmp &= 0xff0; 4527 tmp |= RT2860_TX_WB_DDONE; 4528 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4529 4530 /* turn off PME_OEN to solve high-current issue */ 4531 run_read(sc, RT2860_SYS_CTRL, &tmp); 4532 run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN); 4533 4534 run_write(sc, RT2860_MAC_SYS_CTRL, 4535 RT2860_BBP_HRST | RT2860_MAC_SRST); 4536 run_write(sc, RT2860_USB_DMA_CFG, 0); 4537 4538 if ((error = run_reset(sc)) != 0) { 4539 printf("%s: could not reset chipset\n", sc->sc_dev.dv_xname); 4540 goto fail; 4541 } 4542 4543 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4544 4545 /* init Tx power for all Tx rates (from EEPROM) */ 4546 for (ridx = 0; ridx < 5; ridx++) { 4547 if (sc->txpow20mhz[ridx] == 0xffffffff) 4548 continue; 4549 run_write(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 4550 } 4551 4552 for (i = 0; i < nitems(rt2870_def_mac); i++) 4553 run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); 4554 run_write(sc, RT2860_WMM_AIFSN_CFG, 0x00002273); 4555 run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344); 4556 run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa); 4557 4558 if (sc->mac_ver >= 0x5390) { 4559 run_write(sc, RT2860_TX_SW_CFG0, 4560 4 << RT2860_DLY_PAPE_EN_SHIFT | 4); 4561 if (sc->mac_ver >= 0x5392) { 4562 run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff); 4563 if (sc->mac_ver == 0x5592) { 4564 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980); 4565 run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082); 4566 } else { 4567 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980); 4568 run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); 4569 } 4570 } 4571 } else if (sc->mac_ver == 0x3593) { 4572 run_write(sc, RT2860_TX_SW_CFG0, 4573 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); 4574 } else if (sc->mac_ver >= 0x3070) { 4575 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 4576 run_write(sc, RT2860_TX_SW_CFG0, 4577 4 << RT2860_DLY_PAPE_EN_SHIFT); 4578 } 4579 4580 /* wait while MAC is busy */ 4581 for (ntries = 0; ntries < 100; ntries++) { 4582 if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0) 4583 goto fail; 4584 if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 4585 break; 4586 DELAY(1000); 4587 } 4588 if (ntries == 100) { 4589 error = ETIMEDOUT; 4590 goto fail; 4591 } 4592 4593 /* clear Host to MCU mailbox */ 4594 run_write(sc, RT2860_H2M_BBPAGENT, 0); 4595 run_write(sc, RT2860_H2M_MAILBOX, 0); 4596 DELAY(1000); 4597 4598 if ((error = run_bbp_init(sc)) != 0) { 4599 printf("%s: could not initialize BBP\n", sc->sc_dev.dv_xname); 4600 goto fail; 4601 } 4602 4603 /* abort TSF synchronization */ 4604 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 4605 tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 4606 RT2860_TBTT_TIMER_EN); 4607 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 4608 4609 /* clear RX WCID search table */ 4610 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4611 /* clear WCID attribute table */ 4612 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4613 /* clear shared key table */ 4614 run_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 4615 /* clear shared key mode */ 4616 run_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 4617 4618 run_read(sc, RT2860_US_CYC_CNT, &tmp); 4619 tmp = (tmp & ~0xff) | 0x1e; 4620 run_write(sc, RT2860_US_CYC_CNT, tmp); 4621 4622 if (sc->mac_rev != 0x0101) 4623 run_write(sc, RT2860_TXOP_CTRL_CFG, 0x0000583f); 4624 4625 run_write(sc, RT2860_WMM_TXOP0_CFG, 0); 4626 run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); 4627 4628 /* write vendor-specific BBP values (from EEPROM) */ 4629 if (sc->mac_ver < 0x3593) { 4630 for (i = 0; i < 8; i++) { 4631 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4632 continue; 4633 run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4634 } 4635 } 4636 4637 /* select Main antenna for 1T1R devices */ 4638 if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370) 4639 run_set_rx_antenna(sc, 0); 4640 4641 /* send LEDs operating mode to microcontroller */ 4642 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); 4643 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); 4644 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); 4645 4646 if (sc->mac_ver >= 0x5390) 4647 run_rt5390_rf_init(sc); 4648 else if (sc->mac_ver == 0x3593) 4649 run_rt3593_rf_init(sc); 4650 else if (sc->mac_ver >= 0x3070) 4651 run_rt3070_rf_init(sc); 4652 4653 /* disable non-existing Rx chains */ 4654 run_bbp_read(sc, 3, &bbp3); 4655 bbp3 &= ~(1 << 3 | 1 << 4); 4656 if (sc->nrxchains == 2) 4657 bbp3 |= 1 << 3; 4658 else if (sc->nrxchains == 3) 4659 bbp3 |= 1 << 4; 4660 run_bbp_write(sc, 3, bbp3); 4661 4662 /* disable non-existing Tx chains */ 4663 run_bbp_read(sc, 1, &bbp1); 4664 if (sc->ntxchains == 1) 4665 bbp1 &= ~(1 << 3 | 1 << 4); 4666 run_bbp_write(sc, 1, bbp1); 4667 4668 if (sc->mac_ver >= 0x5390) 4669 run_rt5390_rf_setup(sc); 4670 else if (sc->mac_ver == 0x3593) 4671 run_rt3593_rf_setup(sc); 4672 else if (sc->mac_ver >= 0x3070) 4673 run_rt3070_rf_setup(sc); 4674 4675 /* select default channel */ 4676 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 4677 run_set_chan(sc, ic->ic_ibss_chan); 4678 4679 /* turn radio LED on */ 4680 run_set_leds(sc, RT2860_LED_RADIO); 4681 4682 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 4683 struct run_rx_data *data = &sc->rxq.data[i]; 4684 4685 usbd_setup_xfer(data->xfer, sc->rxq.pipeh, data, data->buf, 4686 RUN_MAX_RXSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 4687 USBD_NO_TIMEOUT, run_rxeof); 4688 error = usbd_transfer(data->xfer); 4689 if (error != 0 && error != USBD_IN_PROGRESS) 4690 goto fail; 4691 } 4692 4693 if ((error = run_txrx_enable(sc)) != 0) 4694 goto fail; 4695 4696 ifp->if_flags |= IFF_RUNNING; 4697 ifq_clr_oactive(&ifp->if_snd); 4698 4699 if (ic->ic_flags & IEEE80211_F_WEPON) { 4700 /* install WEP keys */ 4701 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4702 (void)run_set_key(ic, NULL, &ic->ic_nw_keys[i]); 4703 } 4704 4705 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4706 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4707 else 4708 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4709 4710 if (error != 0) 4711 fail: run_stop(ifp, 1); 4712 return error; 4713 } 4714 4715 void 4716 run_stop(struct ifnet *ifp, int disable) 4717 { 4718 struct run_softc *sc = ifp->if_softc; 4719 struct ieee80211com *ic = &sc->sc_ic; 4720 uint32_t tmp; 4721 int s, ntries, qid; 4722 4723 if (ifp->if_flags & IFF_RUNNING) 4724 run_set_leds(sc, 0); /* turn all LEDs off */ 4725 4726 sc->sc_tx_timer = 0; 4727 ifp->if_timer = 0; 4728 ifp->if_flags &= ~IFF_RUNNING; 4729 ifq_clr_oactive(&ifp->if_snd); 4730 4731 timeout_del(&sc->scan_to); 4732 timeout_del(&sc->calib_to); 4733 4734 s = splusb(); 4735 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4736 /* wait for all queued asynchronous commands to complete */ 4737 usb_wait_task(sc->sc_udev, &sc->sc_task); 4738 splx(s); 4739 4740 /* Disable Tx/Rx DMA. */ 4741 run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp); 4742 tmp &= ~(RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 4743 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4744 4745 for (ntries = 0; ntries < 100; ntries++) { 4746 if (run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp) != 0) 4747 break; 4748 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4749 break; 4750 DELAY(10); 4751 } 4752 if (ntries == 100) { 4753 printf("%s: timeout waiting for DMA engine\n", 4754 sc->sc_dev.dv_xname); 4755 } 4756 4757 /* disable Tx/Rx */ 4758 run_read(sc, RT2860_MAC_SYS_CTRL, &tmp); 4759 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4760 run_write(sc, RT2860_MAC_SYS_CTRL, tmp); 4761 4762 /* wait for pending Tx to complete */ 4763 for (ntries = 0; ntries < 100; ntries++) { 4764 if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) 4765 break; 4766 if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) 4767 break; 4768 } 4769 DELAY(1000); 4770 run_write(sc, RT2860_USB_DMA_CFG, 0); 4771 4772 /* reset adapter */ 4773 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4774 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4775 4776 /* reset Tx and Rx rings */ 4777 sc->qfullmsk = 0; 4778 for (qid = 0; qid < 4; qid++) 4779 run_free_tx_ring(sc, qid); 4780 run_free_rx_ring(sc); 4781 } 4782