1 /* $OpenBSD: if_rsu.c,v 1.51 2022/04/21 21:03:03 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for Realtek RTL8188SU/RTL8191SU/RTL8192SU. 21 */ 22 23 #include "bpfilter.h" 24 25 #include <sys/param.h> 26 #include <sys/sockio.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/timeout.h> 32 #include <sys/conf.h> 33 #include <sys/device.h> 34 #include <sys/endian.h> 35 36 #include <machine/intr.h> 37 38 #if NBPFILTER > 0 39 #include <net/bpf.h> 40 #endif 41 #include <net/if.h> 42 #include <net/if_dl.h> 43 #include <net/if_media.h> 44 45 #include <netinet/in.h> 46 #include <netinet/if_ether.h> 47 48 #include <net80211/ieee80211_var.h> 49 #include <net80211/ieee80211_radiotap.h> 50 51 #include <dev/usb/usb.h> 52 #include <dev/usb/usbdi.h> 53 #include <dev/usb/usbdi_util.h> 54 #include <dev/usb/usbdevs.h> 55 56 #include <dev/usb/if_rsureg.h> 57 58 #ifdef RSU_DEBUG 59 #define DPRINTF(x) do { if (rsu_debug) printf x; } while (0) 60 #define DPRINTFN(n, x) do { if (rsu_debug >= (n)) printf x; } while (0) 61 int rsu_debug = 4; 62 #else 63 #define DPRINTF(x) 64 #define DPRINTFN(n, x) 65 #endif 66 67 /* 68 * NB: When updating this list of devices, beware to also update the list 69 * of devices that have HT support disabled below, if applicable. 70 */ 71 static const struct usb_devno rsu_devs[] = { 72 { USB_VENDOR_ACCTON, USB_PRODUCT_ACCTON_RTL8192SU }, 73 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_USBN10 }, 74 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8192SU_1 }, 75 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_1 }, 76 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_2 }, 77 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_3 }, 78 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_4 }, 79 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_5 }, 80 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192SU_1 }, 81 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192SU_2 }, 82 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192SU_3 }, 83 { USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_RTL8192SU_1 }, 84 { USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_RTL8192SU_2 }, 85 { USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_RTL8192SU_3 }, 86 { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_RTL8192SU }, 87 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA131A1 }, 88 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_RTL8192SU_1 }, 89 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_RTL8192SU_2 }, 90 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192SU_1 }, 91 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192SU_2 }, 92 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192SU_3 }, 93 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWGUN54 }, 94 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWNUM300 }, 95 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192SU_1 }, 96 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192SU_2 }, 97 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_GWUSNANO }, 98 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8171 }, 99 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8172 }, 100 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8173 }, 101 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8174 }, 102 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192SU }, 103 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8712 }, 104 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8713 }, 105 { USB_VENDOR_SENAO, USB_PRODUCT_SENAO_RTL8192SU_1 }, 106 { USB_VENDOR_SENAO, USB_PRODUCT_SENAO_RTL8192SU_2 }, 107 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_WL349V1 }, 108 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_WL353 }, 109 { USB_VENDOR_SWEEX2, USB_PRODUCT_SWEEX2_LW154 } 110 }; 111 112 /* List of devices that have HT support disabled. */ 113 static const struct usb_devno rsu_devs_noht[] = { 114 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8192SU_1 }, 115 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_4 } 116 }; 117 118 int rsu_match(struct device *, void *, void *); 119 void rsu_attach(struct device *, struct device *, void *); 120 int rsu_detach(struct device *, int); 121 int rsu_open_pipes(struct rsu_softc *); 122 void rsu_close_pipes(struct rsu_softc *); 123 int rsu_alloc_rx_list(struct rsu_softc *); 124 void rsu_free_rx_list(struct rsu_softc *); 125 int rsu_alloc_tx_list(struct rsu_softc *); 126 void rsu_free_tx_list(struct rsu_softc *); 127 void rsu_task(void *); 128 void rsu_do_async(struct rsu_softc *, 129 void (*)(struct rsu_softc *, void *), void *, int); 130 void rsu_wait_async(struct rsu_softc *); 131 int rsu_write_region_1(struct rsu_softc *, uint16_t, uint8_t *, 132 int); 133 void rsu_write_1(struct rsu_softc *, uint16_t, uint8_t); 134 void rsu_write_2(struct rsu_softc *, uint16_t, uint16_t); 135 void rsu_write_4(struct rsu_softc *, uint16_t, uint32_t); 136 int rsu_read_region_1(struct rsu_softc *, uint16_t, uint8_t *, 137 int); 138 uint8_t rsu_read_1(struct rsu_softc *, uint16_t); 139 uint16_t rsu_read_2(struct rsu_softc *, uint16_t); 140 uint32_t rsu_read_4(struct rsu_softc *, uint16_t); 141 int rsu_fw_iocmd(struct rsu_softc *, uint32_t); 142 uint8_t rsu_efuse_read_1(struct rsu_softc *, uint16_t); 143 int rsu_read_rom(struct rsu_softc *); 144 int rsu_fw_cmd(struct rsu_softc *, uint8_t, void *, int); 145 int rsu_media_change(struct ifnet *); 146 void rsu_calib_to(void *); 147 void rsu_calib_cb(struct rsu_softc *, void *); 148 int rsu_newstate(struct ieee80211com *, enum ieee80211_state, int); 149 void rsu_newstate_cb(struct rsu_softc *, void *); 150 int rsu_set_key(struct ieee80211com *, struct ieee80211_node *, 151 struct ieee80211_key *); 152 void rsu_set_key_cb(struct rsu_softc *, void *); 153 void rsu_delete_key(struct ieee80211com *, struct ieee80211_node *, 154 struct ieee80211_key *); 155 void rsu_delete_key_cb(struct rsu_softc *, void *); 156 int rsu_site_survey(struct rsu_softc *); 157 int rsu_join_bss(struct rsu_softc *, struct ieee80211_node *); 158 int rsu_disconnect(struct rsu_softc *); 159 void rsu_event_survey(struct rsu_softc *, uint8_t *, int); 160 void rsu_event_join_bss(struct rsu_softc *, uint8_t *, int); 161 void rsu_rx_event(struct rsu_softc *, uint8_t, uint8_t *, int); 162 void rsu_rx_multi_event(struct rsu_softc *, uint8_t *, int); 163 int8_t rsu_get_rssi(struct rsu_softc *, int, void *); 164 void rsu_rx_frame(struct rsu_softc *, uint8_t *, int, 165 struct mbuf_list *); 166 void rsu_rx_multi_frame(struct rsu_softc *, uint8_t *, int); 167 void rsu_rxeof(struct usbd_xfer *, void *, usbd_status); 168 void rsu_txeof(struct usbd_xfer *, void *, usbd_status); 169 int rsu_tx(struct rsu_softc *, struct mbuf *, 170 struct ieee80211_node *); 171 int rsu_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 172 int, int, int); 173 void rsu_start(struct ifnet *); 174 void rsu_watchdog(struct ifnet *); 175 int rsu_ioctl(struct ifnet *, u_long, caddr_t); 176 void rsu_power_on_acut(struct rsu_softc *); 177 void rsu_power_on_bcut(struct rsu_softc *); 178 void rsu_power_off(struct rsu_softc *); 179 int rsu_fw_loadsection(struct rsu_softc *, uint8_t *, int); 180 int rsu_load_firmware(struct rsu_softc *); 181 int rsu_init(struct ifnet *); 182 void rsu_stop(struct ifnet *); 183 184 struct cfdriver rsu_cd = { 185 NULL, "rsu", DV_IFNET 186 }; 187 188 const struct cfattach rsu_ca = { 189 sizeof(struct rsu_softc), rsu_match, rsu_attach, rsu_detach, 190 }; 191 192 int 193 rsu_match(struct device *parent, void *match, void *aux) 194 { 195 struct usb_attach_arg *uaa = aux; 196 197 if (uaa->iface == NULL || uaa->configno != 1) 198 return (UMATCH_NONE); 199 200 return ((usb_lookup(rsu_devs, uaa->vendor, uaa->product) != NULL) ? 201 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 202 } 203 204 void 205 rsu_attach(struct device *parent, struct device *self, void *aux) 206 { 207 struct rsu_softc *sc = (struct rsu_softc *)self; 208 struct usb_attach_arg *uaa = aux; 209 struct ieee80211com *ic = &sc->sc_ic; 210 struct ifnet *ifp = &ic->ic_if; 211 int i, error; 212 213 sc->sc_udev = uaa->device; 214 sc->sc_iface = uaa->iface; 215 216 usb_init_task(&sc->sc_task, rsu_task, sc, USB_TASK_TYPE_GENERIC); 217 timeout_set(&sc->calib_to, rsu_calib_to, sc); 218 219 /* Read chip revision. */ 220 sc->cut = MS(rsu_read_4(sc, R92S_PMC_FSM), R92S_PMC_FSM_CUT); 221 if (sc->cut != 3) 222 sc->cut = (sc->cut >> 1) + 1; 223 224 error = rsu_read_rom(sc); 225 if (error != 0) { 226 printf("%s: could not read ROM\n", sc->sc_dev.dv_xname); 227 return; 228 } 229 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->rom[0x12]); 230 231 printf("%s: MAC/BB RTL8712 cut %d, address %s\n", 232 sc->sc_dev.dv_xname, sc->cut, ether_sprintf(ic->ic_myaddr)); 233 234 if (rsu_open_pipes(sc) != 0) 235 return; 236 237 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 238 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 239 ic->ic_state = IEEE80211_S_INIT; 240 241 /* Set device capabilities. */ 242 ic->ic_caps = 243 IEEE80211_C_SCANALL | /* Hardware scan. */ 244 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 245 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 246 IEEE80211_C_WEP | /* WEP. */ 247 IEEE80211_C_RSN; /* WPA/RSN. */ 248 /* Check if HT support is present. */ 249 if (usb_lookup(rsu_devs_noht, uaa->vendor, uaa->product) == NULL) { 250 #ifdef notyet 251 /* Set HT capabilities. */ 252 ic->ic_htcaps = 253 IEEE80211_HTCAP_CBW20_40 | 254 IEEE80211_HTCAP_DSSSCCK40; 255 /* Set supported HT rates. */ 256 for (i = 0; i < 2; i++) 257 ic->ic_sup_mcs[i] = 0xff; 258 #endif 259 } 260 261 /* Set supported .11b and .11g rates. */ 262 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 263 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 264 265 /* Set supported .11b and .11g channels (1 through 14). */ 266 for (i = 1; i <= 14; i++) { 267 ic->ic_channels[i].ic_freq = 268 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 269 ic->ic_channels[i].ic_flags = 270 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 271 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 272 } 273 274 ifp->if_softc = sc; 275 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 276 ifp->if_ioctl = rsu_ioctl; 277 ifp->if_start = rsu_start; 278 ifp->if_watchdog = rsu_watchdog; 279 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 280 281 if_attach(ifp); 282 ieee80211_ifattach(ifp); 283 #ifdef notyet 284 ic->ic_set_key = rsu_set_key; 285 ic->ic_delete_key = rsu_delete_key; 286 #endif 287 /* Override state transition machine. */ 288 sc->sc_newstate = ic->ic_newstate; 289 ic->ic_newstate = rsu_newstate; 290 ic->ic_send_mgmt = rsu_send_mgmt; 291 ieee80211_media_init(ifp, rsu_media_change, ieee80211_media_status); 292 293 #if NBPFILTER > 0 294 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 295 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 296 297 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 298 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 299 sc->sc_rxtap.wr_ihdr.it_present = htole32(RSU_RX_RADIOTAP_PRESENT); 300 301 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 302 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 303 sc->sc_txtap.wt_ihdr.it_present = htole32(RSU_TX_RADIOTAP_PRESENT); 304 #endif 305 } 306 307 int 308 rsu_detach(struct device *self, int flags) 309 { 310 struct rsu_softc *sc = (struct rsu_softc *)self; 311 struct ifnet *ifp = &sc->sc_ic.ic_if; 312 int s; 313 314 s = splusb(); 315 316 if (timeout_initialized(&sc->calib_to)) 317 timeout_del(&sc->calib_to); 318 319 /* Wait for all async commands to complete. */ 320 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 321 322 usbd_ref_wait(sc->sc_udev); 323 324 if (ifp->if_softc != NULL) { 325 ieee80211_ifdetach(ifp); 326 if_detach(ifp); 327 } 328 329 /* Abort and close Tx/Rx pipes. */ 330 rsu_close_pipes(sc); 331 332 /* Free Tx/Rx buffers. */ 333 rsu_free_tx_list(sc); 334 rsu_free_rx_list(sc); 335 splx(s); 336 337 return (0); 338 } 339 340 int 341 rsu_open_pipes(struct rsu_softc *sc) 342 { 343 usb_interface_descriptor_t *id; 344 int i, error; 345 346 /* 347 * Determine the number of Tx/Rx endpoints (there are chips with 348 * 4, 6 or 11 endpoints). 349 */ 350 id = usbd_get_interface_descriptor(sc->sc_iface); 351 sc->npipes = id->bNumEndpoints; 352 if (sc->npipes == 4) 353 sc->qid2idx = rsu_qid2idx_4ep; 354 else if (sc->npipes == 6) 355 sc->qid2idx = rsu_qid2idx_6ep; 356 else /* Assume npipes==11; will fail below otherwise. */ 357 sc->qid2idx = rsu_qid2idx_11ep; 358 DPRINTF(("%d endpoints configuration\n", sc->npipes)); 359 360 /* Open all pipes. */ 361 for (i = 0; i < MIN(sc->npipes, nitems(r92s_epaddr)); i++) { 362 error = usbd_open_pipe(sc->sc_iface, r92s_epaddr[i], 0, 363 &sc->pipe[i]); 364 if (error != 0) { 365 printf("%s: could not open bulk pipe 0x%02x\n", 366 sc->sc_dev.dv_xname, r92s_epaddr[i]); 367 break; 368 } 369 } 370 if (error != 0) 371 rsu_close_pipes(sc); 372 return (error); 373 } 374 375 void 376 rsu_close_pipes(struct rsu_softc *sc) 377 { 378 int i; 379 380 /* Close all pipes. */ 381 for (i = 0; i < sc->npipes; i++) { 382 if (sc->pipe[i] == NULL) 383 continue; 384 usbd_close_pipe(sc->pipe[i]); 385 } 386 } 387 388 int 389 rsu_alloc_rx_list(struct rsu_softc *sc) 390 { 391 struct rsu_rx_data *data; 392 int i, error = 0; 393 394 for (i = 0; i < RSU_RX_LIST_COUNT; i++) { 395 data = &sc->rx_data[i]; 396 397 data->sc = sc; /* Backpointer for callbacks. */ 398 399 data->xfer = usbd_alloc_xfer(sc->sc_udev); 400 if (data->xfer == NULL) { 401 printf("%s: could not allocate xfer\n", 402 sc->sc_dev.dv_xname); 403 error = ENOMEM; 404 break; 405 } 406 data->buf = usbd_alloc_buffer(data->xfer, RSU_RXBUFSZ); 407 if (data->buf == NULL) { 408 printf("%s: could not allocate xfer buffer\n", 409 sc->sc_dev.dv_xname); 410 error = ENOMEM; 411 break; 412 } 413 } 414 if (error != 0) 415 rsu_free_rx_list(sc); 416 return (error); 417 } 418 419 void 420 rsu_free_rx_list(struct rsu_softc *sc) 421 { 422 int i; 423 424 /* NB: Caller must abort pipe first. */ 425 for (i = 0; i < RSU_RX_LIST_COUNT; i++) { 426 if (sc->rx_data[i].xfer != NULL) 427 usbd_free_xfer(sc->rx_data[i].xfer); 428 sc->rx_data[i].xfer = NULL; 429 } 430 } 431 432 int 433 rsu_alloc_tx_list(struct rsu_softc *sc) 434 { 435 struct rsu_tx_data *data; 436 int i, error = 0; 437 438 TAILQ_INIT(&sc->tx_free_list); 439 for (i = 0; i < RSU_TX_LIST_COUNT; i++) { 440 data = &sc->tx_data[i]; 441 442 data->sc = sc; /* Backpointer for callbacks. */ 443 444 data->xfer = usbd_alloc_xfer(sc->sc_udev); 445 if (data->xfer == NULL) { 446 printf("%s: could not allocate xfer\n", 447 sc->sc_dev.dv_xname); 448 error = ENOMEM; 449 break; 450 } 451 data->buf = usbd_alloc_buffer(data->xfer, RSU_TXBUFSZ); 452 if (data->buf == NULL) { 453 printf("%s: could not allocate xfer buffer\n", 454 sc->sc_dev.dv_xname); 455 error = ENOMEM; 456 break; 457 } 458 /* Append this Tx buffer to our free list. */ 459 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 460 } 461 if (error != 0) 462 rsu_free_tx_list(sc); 463 return (error); 464 } 465 466 void 467 rsu_free_tx_list(struct rsu_softc *sc) 468 { 469 int i; 470 471 /* NB: Caller must abort pipe first. */ 472 for (i = 0; i < RSU_TX_LIST_COUNT; i++) { 473 if (sc->tx_data[i].xfer != NULL) 474 usbd_free_xfer(sc->tx_data[i].xfer); 475 sc->tx_data[i].xfer = NULL; 476 } 477 } 478 479 void 480 rsu_task(void *arg) 481 { 482 struct rsu_softc *sc = arg; 483 struct rsu_host_cmd_ring *ring = &sc->cmdq; 484 struct rsu_host_cmd *cmd; 485 int s; 486 487 /* Process host commands. */ 488 s = splusb(); 489 while (ring->next != ring->cur) { 490 cmd = &ring->cmd[ring->next]; 491 splx(s); 492 /* Invoke callback. */ 493 cmd->cb(sc, cmd->data); 494 s = splusb(); 495 ring->queued--; 496 ring->next = (ring->next + 1) % RSU_HOST_CMD_RING_COUNT; 497 } 498 splx(s); 499 } 500 501 void 502 rsu_do_async(struct rsu_softc *sc, 503 void (*cb)(struct rsu_softc *, void *), void *arg, int len) 504 { 505 struct rsu_host_cmd_ring *ring = &sc->cmdq; 506 struct rsu_host_cmd *cmd; 507 int s; 508 509 s = splusb(); 510 cmd = &ring->cmd[ring->cur]; 511 cmd->cb = cb; 512 KASSERT(len <= sizeof(cmd->data)); 513 memcpy(cmd->data, arg, len); 514 ring->cur = (ring->cur + 1) % RSU_HOST_CMD_RING_COUNT; 515 516 /* If there is no pending command already, schedule a task. */ 517 if (++ring->queued == 1) 518 usb_add_task(sc->sc_udev, &sc->sc_task); 519 splx(s); 520 } 521 522 void 523 rsu_wait_async(struct rsu_softc *sc) 524 { 525 /* Wait for all queued asynchronous commands to complete. */ 526 usb_wait_task(sc->sc_udev, &sc->sc_task); 527 } 528 529 int 530 rsu_write_region_1(struct rsu_softc *sc, uint16_t addr, uint8_t *buf, 531 int len) 532 { 533 usb_device_request_t req; 534 535 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 536 req.bRequest = R92S_REQ_REGS; 537 USETW(req.wValue, addr); 538 USETW(req.wIndex, 0); 539 USETW(req.wLength, len); 540 return (usbd_do_request(sc->sc_udev, &req, buf)); 541 } 542 543 void 544 rsu_write_1(struct rsu_softc *sc, uint16_t addr, uint8_t val) 545 { 546 rsu_write_region_1(sc, addr, &val, 1); 547 } 548 549 void 550 rsu_write_2(struct rsu_softc *sc, uint16_t addr, uint16_t val) 551 { 552 val = htole16(val); 553 rsu_write_region_1(sc, addr, (uint8_t *)&val, 2); 554 } 555 556 void 557 rsu_write_4(struct rsu_softc *sc, uint16_t addr, uint32_t val) 558 { 559 val = htole32(val); 560 rsu_write_region_1(sc, addr, (uint8_t *)&val, 4); 561 } 562 563 int 564 rsu_read_region_1(struct rsu_softc *sc, uint16_t addr, uint8_t *buf, 565 int len) 566 { 567 usb_device_request_t req; 568 569 req.bmRequestType = UT_READ_VENDOR_DEVICE; 570 req.bRequest = R92S_REQ_REGS; 571 USETW(req.wValue, addr); 572 USETW(req.wIndex, 0); 573 USETW(req.wLength, len); 574 return (usbd_do_request(sc->sc_udev, &req, buf)); 575 } 576 577 uint8_t 578 rsu_read_1(struct rsu_softc *sc, uint16_t addr) 579 { 580 uint8_t val; 581 582 if (rsu_read_region_1(sc, addr, &val, 1) != 0) 583 return (0xff); 584 return (val); 585 } 586 587 uint16_t 588 rsu_read_2(struct rsu_softc *sc, uint16_t addr) 589 { 590 uint16_t val; 591 592 if (rsu_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 593 return (0xffff); 594 return (letoh16(val)); 595 } 596 597 uint32_t 598 rsu_read_4(struct rsu_softc *sc, uint16_t addr) 599 { 600 uint32_t val; 601 602 if (rsu_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 603 return (0xffffffff); 604 return (letoh32(val)); 605 } 606 607 int 608 rsu_fw_iocmd(struct rsu_softc *sc, uint32_t iocmd) 609 { 610 int ntries; 611 612 rsu_write_4(sc, R92S_IOCMD_CTRL, iocmd); 613 DELAY(100); 614 for (ntries = 0; ntries < 50; ntries++) { 615 if (rsu_read_4(sc, R92S_IOCMD_CTRL) == 0) 616 return (0); 617 DELAY(10); 618 } 619 return (ETIMEDOUT); 620 } 621 622 uint8_t 623 rsu_efuse_read_1(struct rsu_softc *sc, uint16_t addr) 624 { 625 uint32_t reg; 626 int ntries; 627 628 reg = rsu_read_4(sc, R92S_EFUSE_CTRL); 629 reg = RW(reg, R92S_EFUSE_CTRL_ADDR, addr); 630 reg &= ~R92S_EFUSE_CTRL_VALID; 631 rsu_write_4(sc, R92S_EFUSE_CTRL, reg); 632 /* Wait for read operation to complete. */ 633 for (ntries = 0; ntries < 100; ntries++) { 634 reg = rsu_read_4(sc, R92S_EFUSE_CTRL); 635 if (reg & R92S_EFUSE_CTRL_VALID) 636 return (MS(reg, R92S_EFUSE_CTRL_DATA)); 637 DELAY(5); 638 } 639 printf("%s: could not read efuse byte at address 0x%x\n", 640 sc->sc_dev.dv_xname, addr); 641 return (0xff); 642 } 643 644 int 645 rsu_read_rom(struct rsu_softc *sc) 646 { 647 uint8_t *rom = sc->rom; 648 uint16_t addr = 0; 649 uint32_t reg; 650 uint8_t off, msk; 651 int i; 652 653 /* Make sure that ROM type is eFuse and that autoload succeeded. */ 654 reg = rsu_read_1(sc, R92S_EE_9346CR); 655 if ((reg & (R92S_9356SEL | R92S_EEPROM_EN)) != R92S_EEPROM_EN) 656 return (EIO); 657 658 /* Turn on 2.5V to prevent eFuse leakage. */ 659 reg = rsu_read_1(sc, R92S_EFUSE_TEST + 3); 660 rsu_write_1(sc, R92S_EFUSE_TEST + 3, reg | 0x80); 661 DELAY(1000); 662 rsu_write_1(sc, R92S_EFUSE_TEST + 3, reg & ~0x80); 663 664 /* Read full ROM image. */ 665 memset(&sc->rom, 0xff, sizeof(sc->rom)); 666 while (addr < 512) { 667 reg = rsu_efuse_read_1(sc, addr); 668 if (reg == 0xff) 669 break; 670 addr++; 671 off = reg >> 4; 672 msk = reg & 0xf; 673 for (i = 0; i < 4; i++) { 674 if (msk & (1 << i)) 675 continue; 676 rom[off * 8 + i * 2 + 0] = 677 rsu_efuse_read_1(sc, addr); 678 addr++; 679 rom[off * 8 + i * 2 + 1] = 680 rsu_efuse_read_1(sc, addr); 681 addr++; 682 } 683 } 684 #ifdef RSU_DEBUG 685 if (rsu_debug >= 5) { 686 /* Dump ROM content. */ 687 printf("\n"); 688 for (i = 0; i < sizeof(sc->rom); i++) 689 printf("%02x:", rom[i]); 690 printf("\n"); 691 } 692 #endif 693 return (0); 694 } 695 696 int 697 rsu_fw_cmd(struct rsu_softc *sc, uint8_t code, void *buf, int len) 698 { 699 struct rsu_tx_data *data; 700 struct r92s_tx_desc *txd; 701 struct r92s_fw_cmd_hdr *cmd; 702 struct usbd_pipe *pipe; 703 int cmdsz, xferlen; 704 705 data = sc->fwcmd_data; 706 707 /* Round-up command length to a multiple of 8 bytes. */ 708 cmdsz = (len + 7) & ~7; 709 710 xferlen = sizeof(*txd) + sizeof(*cmd) + cmdsz; 711 KASSERT(xferlen <= RSU_TXBUFSZ); 712 memset(data->buf, 0, xferlen); 713 714 /* Setup Tx descriptor. */ 715 txd = (struct r92s_tx_desc *)data->buf; 716 txd->txdw0 = htole32( 717 SM(R92S_TXDW0_OFFSET, sizeof(*txd)) | 718 SM(R92S_TXDW0_PKTLEN, sizeof(*cmd) + cmdsz) | 719 R92S_TXDW0_OWN | R92S_TXDW0_FSG | R92S_TXDW0_LSG); 720 txd->txdw1 = htole32(SM(R92S_TXDW1_QSEL, R92S_TXDW1_QSEL_H2C)); 721 722 /* Setup command header. */ 723 cmd = (struct r92s_fw_cmd_hdr *)&txd[1]; 724 cmd->len = htole16(cmdsz); 725 cmd->code = code; 726 cmd->seq = sc->cmd_seq; 727 sc->cmd_seq = (sc->cmd_seq + 1) & 0x7f; 728 729 /* Copy command payload. */ 730 memcpy(&cmd[1], buf, len); 731 732 DPRINTFN(2, ("Tx cmd code=%d len=%d\n", code, cmdsz)); 733 pipe = sc->pipe[sc->qid2idx[RSU_QID_H2C]]; 734 usbd_setup_xfer(data->xfer, pipe, NULL, data->buf, xferlen, 735 USBD_SHORT_XFER_OK | USBD_NO_COPY | USBD_SYNCHRONOUS, 736 RSU_CMD_TIMEOUT, NULL); 737 return (usbd_transfer(data->xfer)); 738 } 739 740 int 741 rsu_media_change(struct ifnet *ifp) 742 { 743 int error; 744 745 error = ieee80211_media_change(ifp); 746 if (error != ENETRESET) 747 return (error); 748 749 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 750 (IFF_UP | IFF_RUNNING)) { 751 rsu_stop(ifp); 752 error = rsu_init(ifp); 753 } 754 return (error); 755 } 756 757 void 758 rsu_calib_to(void *arg) 759 { 760 struct rsu_softc *sc = arg; 761 762 if (usbd_is_dying(sc->sc_udev)) 763 return; 764 765 usbd_ref_incr(sc->sc_udev); 766 767 /* Do it in a process context. */ 768 rsu_do_async(sc, rsu_calib_cb, NULL, 0); 769 770 usbd_ref_decr(sc->sc_udev); 771 } 772 773 /* ARGSUSED */ 774 void 775 rsu_calib_cb(struct rsu_softc *sc, void *arg) 776 { 777 uint32_t reg; 778 779 #ifdef notyet 780 /* Read WPS PBC status. */ 781 rsu_write_1(sc, R92S_MAC_PINMUX_CTRL, 782 R92S_GPIOMUX_EN | SM(R92S_GPIOSEL_GPIO, R92S_GPIOSEL_GPIO_JTAG)); 783 rsu_write_1(sc, R92S_GPIO_IO_SEL, 784 rsu_read_1(sc, R92S_GPIO_IO_SEL) & ~R92S_GPIO_WPS); 785 reg = rsu_read_1(sc, R92S_GPIO_CTRL); 786 if (reg != 0xff && (reg & R92S_GPIO_WPS)) 787 DPRINTF(("WPS PBC is pushed\n")); 788 #endif 789 /* Read current signal level. */ 790 if (rsu_fw_iocmd(sc, 0xf4000001) == 0) { 791 reg = rsu_read_4(sc, R92S_IOCMD_DATA); 792 DPRINTFN(8, ("RSSI=%d%%\n", reg >> 4)); 793 } 794 795 if (!usbd_is_dying(sc->sc_udev)) 796 timeout_add_sec(&sc->calib_to, 2); 797 } 798 799 int 800 rsu_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 801 { 802 struct rsu_softc *sc = ic->ic_softc; 803 struct rsu_cmd_newstate cmd; 804 805 /* Do it in a process context. */ 806 cmd.state = nstate; 807 cmd.arg = arg; 808 rsu_do_async(sc, rsu_newstate_cb, &cmd, sizeof(cmd)); 809 return (0); 810 } 811 812 void 813 rsu_newstate_cb(struct rsu_softc *sc, void *arg) 814 { 815 struct rsu_cmd_newstate *cmd = arg; 816 struct ieee80211com *ic = &sc->sc_ic; 817 struct ifnet *ifp = &ic->ic_if; 818 enum ieee80211_state ostate; 819 int error, s; 820 821 s = splnet(); 822 ostate = ic->ic_state; 823 824 if (ostate == IEEE80211_S_RUN) { 825 /* Stop calibration. */ 826 timeout_del(&sc->calib_to); 827 /* Disassociate from our current BSS. */ 828 (void)rsu_disconnect(sc); 829 } 830 switch (cmd->state) { 831 case IEEE80211_S_INIT: 832 break; 833 case IEEE80211_S_SCAN: 834 error = rsu_site_survey(sc); 835 if (error != 0) { 836 printf("%s: could not send site survey command\n", 837 sc->sc_dev.dv_xname); 838 } 839 if (ifp->if_flags & IFF_DEBUG) 840 printf("%s: %s -> %s\n", ifp->if_xname, 841 ieee80211_state_name[ic->ic_state], 842 ieee80211_state_name[cmd->state]); 843 ic->ic_state = cmd->state; 844 splx(s); 845 return; 846 case IEEE80211_S_AUTH: 847 ic->ic_bss->ni_rsn_supp_state = RSNA_SUPP_INITIALIZE; 848 error = rsu_join_bss(sc, ic->ic_bss); 849 if (error != 0) { 850 printf("%s: could not send join command\n", 851 sc->sc_dev.dv_xname); 852 ieee80211_begin_scan(&ic->ic_if); 853 splx(s); 854 return; 855 } 856 if (ifp->if_flags & IFF_DEBUG) 857 printf("%s: %s -> %s\n", ifp->if_xname, 858 ieee80211_state_name[ic->ic_state], 859 ieee80211_state_name[cmd->state]); 860 ic->ic_state = cmd->state; 861 if (ic->ic_flags & IEEE80211_F_RSNON) 862 ic->ic_bss->ni_rsn_supp_state = RSNA_SUPP_PTKSTART; 863 splx(s); 864 return; 865 case IEEE80211_S_ASSOC: 866 /* No-op for this driver. See rsu_event_join_bss(). */ 867 if (ifp->if_flags & IFF_DEBUG) 868 printf("%s: %s -> %s\n", ifp->if_xname, 869 ieee80211_state_name[ic->ic_state], 870 ieee80211_state_name[cmd->state]); 871 ic->ic_state = cmd->state; 872 splx(s); 873 return; 874 case IEEE80211_S_RUN: 875 /* Indicate highest supported rate. */ 876 ic->ic_bss->ni_txrate = ic->ic_bss->ni_rates.rs_nrates - 1; 877 878 /* Start periodic calibration. */ 879 if (!usbd_is_dying(sc->sc_udev)) 880 timeout_add_sec(&sc->calib_to, 2); 881 break; 882 } 883 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 884 splx(s); 885 } 886 887 int 888 rsu_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 889 struct ieee80211_key *k) 890 { 891 struct rsu_softc *sc = ic->ic_softc; 892 struct rsu_cmd_key cmd; 893 894 /* Defer setting of WEP keys until interface is brought up. */ 895 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 896 (IFF_UP | IFF_RUNNING)) 897 return (0); 898 899 /* Do it in a process context. */ 900 cmd.key = *k; 901 cmd.ni = ni; 902 rsu_do_async(sc, rsu_set_key_cb, &cmd, sizeof(cmd)); 903 sc->sc_key_tasks++; 904 return EBUSY; 905 } 906 907 void 908 rsu_set_key_cb(struct rsu_softc *sc, void *arg) 909 { 910 struct rsu_cmd_key *cmd = arg; 911 struct ieee80211com *ic = &sc->sc_ic; 912 struct ieee80211_key *k = &cmd->key; 913 struct r92s_fw_cmd_set_key key; 914 915 sc->sc_key_tasks--; 916 917 memset(&key, 0, sizeof(key)); 918 /* Map net80211 cipher to HW crypto algorithm. */ 919 switch (k->k_cipher) { 920 case IEEE80211_CIPHER_WEP40: 921 key.algo = R92S_KEY_ALGO_WEP40; 922 break; 923 case IEEE80211_CIPHER_WEP104: 924 key.algo = R92S_KEY_ALGO_WEP104; 925 break; 926 case IEEE80211_CIPHER_TKIP: 927 key.algo = R92S_KEY_ALGO_TKIP; 928 break; 929 case IEEE80211_CIPHER_CCMP: 930 key.algo = R92S_KEY_ALGO_AES; 931 break; 932 default: 933 IEEE80211_SEND_MGMT(ic, cmd->ni, IEEE80211_FC0_SUBTYPE_DEAUTH, 934 IEEE80211_REASON_AUTH_LEAVE); 935 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 936 return; 937 } 938 key.id = k->k_id; 939 key.grpkey = (k->k_flags & IEEE80211_KEY_GROUP) != 0; 940 memcpy(key.key, k->k_key, MIN(k->k_len, sizeof(key.key))); 941 (void)rsu_fw_cmd(sc, R92S_CMD_SET_KEY, &key, sizeof(key)); 942 943 if (sc->sc_key_tasks == 0) { 944 DPRINTF(("marking port %s valid\n", 945 ether_sprintf(cmd->ni->ni_macaddr))); 946 cmd->ni->ni_port_valid = 1; 947 ieee80211_set_link_state(ic, LINK_STATE_UP); 948 } 949 } 950 951 /* ARGSUSED */ 952 void 953 rsu_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 954 struct ieee80211_key *k) 955 { 956 struct rsu_softc *sc = ic->ic_softc; 957 struct rsu_cmd_key cmd; 958 959 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 960 ic->ic_state != IEEE80211_S_RUN) 961 return; /* Nothing to do. */ 962 963 /* Do it in a process context. */ 964 cmd.key = *k; 965 rsu_do_async(sc, rsu_delete_key_cb, &cmd, sizeof(cmd)); 966 } 967 968 void 969 rsu_delete_key_cb(struct rsu_softc *sc, void *arg) 970 { 971 struct rsu_cmd_key *cmd = arg; 972 struct ieee80211_key *k = &cmd->key; 973 struct r92s_fw_cmd_set_key key; 974 975 memset(&key, 0, sizeof(key)); 976 key.id = k->k_id; 977 (void)rsu_fw_cmd(sc, R92S_CMD_SET_KEY, &key, sizeof(key)); 978 } 979 980 int 981 rsu_site_survey(struct rsu_softc *sc) 982 { 983 struct ieee80211com *ic = &sc->sc_ic; 984 struct r92s_fw_cmd_sitesurvey cmd; 985 986 memset(&cmd, 0, sizeof(cmd)); 987 if ((ic->ic_flags & IEEE80211_F_ASCAN) || sc->scan_pass == 1) 988 cmd.active = htole32(1); 989 cmd.limit = htole32(48); 990 if (sc->scan_pass == 1) { 991 /* Do a directed scan for second pass. */ 992 cmd.ssidlen = htole32(ic->ic_des_esslen); 993 memcpy(cmd.ssid, ic->ic_des_essid, ic->ic_des_esslen); 994 } 995 DPRINTF(("sending site survey command, pass=%d\n", sc->scan_pass)); 996 return (rsu_fw_cmd(sc, R92S_CMD_SITE_SURVEY, &cmd, sizeof(cmd))); 997 } 998 999 int 1000 rsu_join_bss(struct rsu_softc *sc, struct ieee80211_node *ni) 1001 { 1002 struct ieee80211com *ic = &sc->sc_ic; 1003 struct ndis_wlan_bssid_ex *bss; 1004 struct ndis_802_11_fixed_ies *fixed; 1005 struct r92s_fw_cmd_auth auth; 1006 uint8_t buf[sizeof(*bss) + 128], *frm; 1007 uint8_t opmode; 1008 int error; 1009 1010 /* Let the FW decide the opmode based on the capinfo field. */ 1011 opmode = NDIS802_11AUTOUNKNOWN; 1012 DPRINTF(("setting operating mode to %d\n", opmode)); 1013 error = rsu_fw_cmd(sc, R92S_CMD_SET_OPMODE, &opmode, sizeof(opmode)); 1014 if (error != 0) 1015 return (error); 1016 1017 memset(&auth, 0, sizeof(auth)); 1018 if (ic->ic_flags & IEEE80211_F_RSNON) { 1019 auth.mode = R92S_AUTHMODE_WPA; 1020 auth.dot1x = ieee80211_is_8021x_akm(ni->ni_rsnakms); 1021 } else 1022 auth.mode = R92S_AUTHMODE_OPEN; 1023 DPRINTF(("setting auth mode to %d\n", auth.mode)); 1024 error = rsu_fw_cmd(sc, R92S_CMD_SET_AUTH, &auth, sizeof(auth)); 1025 if (error != 0) 1026 return (error); 1027 1028 memset(buf, 0, sizeof(buf)); 1029 bss = (struct ndis_wlan_bssid_ex *)buf; 1030 IEEE80211_ADDR_COPY(bss->macaddr, ni->ni_bssid); 1031 bss->ssid.ssidlen = htole32(ni->ni_esslen); 1032 memcpy(bss->ssid.ssid, ni->ni_essid, ni->ni_esslen); 1033 if (ic->ic_flags & (IEEE80211_F_WEPON | IEEE80211_F_RSNON)) 1034 bss->privacy = htole32(1); 1035 bss->rssi = htole32(ni->ni_rssi); 1036 if (ic->ic_curmode == IEEE80211_MODE_11B) 1037 bss->networktype = htole32(NDIS802_11DS); 1038 else 1039 bss->networktype = htole32(NDIS802_11OFDM24); 1040 bss->config.len = htole32(sizeof(bss->config)); 1041 bss->config.bintval = htole32(ni->ni_intval); 1042 bss->config.dsconfig = htole32(ieee80211_chan2ieee(ic, ni->ni_chan)); 1043 bss->inframode = htole32(NDIS802_11INFRASTRUCTURE); 1044 memcpy(bss->supprates, ni->ni_rates.rs_rates, 1045 ni->ni_rates.rs_nrates); 1046 /* Write the fixed fields of the beacon frame. */ 1047 fixed = (struct ndis_802_11_fixed_ies *)&bss[1]; 1048 memcpy(&fixed->tstamp, ni->ni_tstamp, 8); 1049 fixed->bintval = htole16(ni->ni_intval); 1050 fixed->capabilities = htole16(ni->ni_capinfo); 1051 /* Write IEs to be included in the association request. */ 1052 frm = (uint8_t *)&fixed[1]; 1053 if ((ic->ic_flags & IEEE80211_F_RSNON) && 1054 (ni->ni_rsnprotos & IEEE80211_PROTO_RSN)) 1055 frm = ieee80211_add_rsn(frm, ic, ni); 1056 if (ni->ni_flags & IEEE80211_NODE_QOS) 1057 frm = ieee80211_add_qos_capability(frm, ic); 1058 if (ni->ni_flags & IEEE80211_NODE_HT) 1059 frm = ieee80211_add_htcaps(frm, ic); 1060 if ((ic->ic_flags & IEEE80211_F_RSNON) && 1061 (ni->ni_rsnprotos & IEEE80211_PROTO_WPA)) 1062 frm = ieee80211_add_wpa(frm, ic, ni); 1063 bss->ieslen = htole32(frm - (uint8_t *)fixed); 1064 bss->len = htole32(((frm - buf) + 3) & ~3); 1065 DPRINTF(("sending join bss command to %s chan %d\n", 1066 ether_sprintf(bss->macaddr), letoh32(bss->config.dsconfig))); 1067 return (rsu_fw_cmd(sc, R92S_CMD_JOIN_BSS, buf, sizeof(buf))); 1068 } 1069 1070 int 1071 rsu_disconnect(struct rsu_softc *sc) 1072 { 1073 uint32_t zero = 0; /* :-) */ 1074 1075 /* Disassociate from our current BSS. */ 1076 DPRINTF(("sending disconnect command\n")); 1077 return (rsu_fw_cmd(sc, R92S_CMD_DISCONNECT, &zero, sizeof(zero))); 1078 } 1079 1080 void 1081 rsu_event_survey(struct rsu_softc *sc, uint8_t *buf, int len) 1082 { 1083 struct ieee80211com *ic = &sc->sc_ic; 1084 struct ifnet *ifp = &ic->ic_if; 1085 struct ieee80211_rxinfo rxi; 1086 struct ieee80211_node *ni; 1087 struct ieee80211_frame *wh; 1088 struct ndis_wlan_bssid_ex *bss; 1089 struct mbuf *m; 1090 uint32_t pktlen, ieslen; 1091 1092 if (__predict_false(len < sizeof(*bss))) 1093 return; 1094 bss = (struct ndis_wlan_bssid_ex *)buf; 1095 ieslen = letoh32(bss->ieslen); 1096 if (ieslen > len - sizeof(*bss)) 1097 return; 1098 1099 DPRINTFN(2, ("found BSS %s: len=%d chan=%d inframode=%d " 1100 "networktype=%d privacy=%d\n", 1101 ether_sprintf(bss->macaddr), letoh32(bss->len), 1102 letoh32(bss->config.dsconfig), letoh32(bss->inframode), 1103 letoh32(bss->networktype), letoh32(bss->privacy))); 1104 1105 /* Build a fake beacon frame to let net80211 do all the parsing. */ 1106 pktlen = sizeof(*wh) + ieslen; 1107 if (__predict_false(pktlen > MCLBYTES)) 1108 return; 1109 MGETHDR(m, M_DONTWAIT, MT_DATA); 1110 if (__predict_false(m == NULL)) 1111 return; 1112 if (pktlen > MHLEN) { 1113 MCLGET(m, M_DONTWAIT); 1114 if (!(m->m_flags & M_EXT)) { 1115 m_free(m); 1116 return; 1117 } 1118 } 1119 wh = mtod(m, struct ieee80211_frame *); 1120 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 1121 IEEE80211_FC0_SUBTYPE_BEACON; 1122 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1123 *(uint16_t *)wh->i_dur = 0; 1124 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 1125 IEEE80211_ADDR_COPY(wh->i_addr2, bss->macaddr); 1126 IEEE80211_ADDR_COPY(wh->i_addr3, bss->macaddr); 1127 *(uint16_t *)wh->i_seq = 0; 1128 memcpy(&wh[1], (uint8_t *)&bss[1], ieslen); 1129 1130 /* Finalize mbuf. */ 1131 m->m_pkthdr.len = m->m_len = pktlen; 1132 1133 ni = ieee80211_find_rxnode(ic, wh); 1134 memset(&rxi, 0, sizeof(rxi)); 1135 rxi.rxi_rssi = letoh32(bss->rssi); 1136 ieee80211_input(ifp, m, ni, &rxi); 1137 /* Node is no longer needed. */ 1138 ieee80211_release_node(ic, ni); 1139 } 1140 1141 void 1142 rsu_event_join_bss(struct rsu_softc *sc, uint8_t *buf, int len) 1143 { 1144 struct ieee80211com *ic = &sc->sc_ic; 1145 struct ieee80211_node *ni = ic->ic_bss; 1146 struct r92s_event_join_bss *rsp; 1147 int res; 1148 1149 if (__predict_false(len < sizeof(*rsp))) 1150 return; 1151 rsp = (struct r92s_event_join_bss *)buf; 1152 res = (int)letoh32(rsp->join_res); 1153 1154 DPRINTF(("Rx join BSS event len=%d res=%d\n", len, res)); 1155 if (res <= 0) { 1156 ic->ic_stats.is_rx_auth_fail++; 1157 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1158 return; 1159 } 1160 DPRINTF(("associated with %s associd=%d\n", 1161 ether_sprintf(rsp->bss.macaddr), letoh32(rsp->associd))); 1162 1163 ni->ni_associd = letoh32(rsp->associd) | 0xc000; 1164 if (ic->ic_flags & IEEE80211_F_WEPON) 1165 ni->ni_flags |= IEEE80211_NODE_TXRXPROT; 1166 1167 /* Force an ASSOC->RUN transition. AUTH->RUN is invalid. */ 1168 ic->ic_state = IEEE80211_S_ASSOC; 1169 ieee80211_new_state(ic, IEEE80211_S_RUN, 1170 IEEE80211_FC0_SUBTYPE_ASSOC_RESP); 1171 } 1172 1173 void 1174 rsu_rx_event(struct rsu_softc *sc, uint8_t code, uint8_t *buf, int len) 1175 { 1176 struct ieee80211com *ic = &sc->sc_ic; 1177 struct ifnet *ifp = &ic->ic_if; 1178 1179 DPRINTFN(4, ("Rx event code=%d len=%d\n", code, len)); 1180 switch (code) { 1181 case R92S_EVT_SURVEY: 1182 if (ic->ic_state == IEEE80211_S_SCAN) 1183 rsu_event_survey(sc, buf, len); 1184 break; 1185 case R92S_EVT_SURVEY_DONE: 1186 DPRINTF(("site survey pass %d done, found %d BSS\n", 1187 sc->scan_pass, letoh32(*(uint32_t *)buf))); 1188 if (ic->ic_state != IEEE80211_S_SCAN) 1189 break; /* Ignore if not scanning. */ 1190 if (sc->scan_pass == 0 && ic->ic_des_esslen != 0) { 1191 /* Schedule a directed scan for hidden APs. */ 1192 sc->scan_pass = 1; 1193 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1194 break; 1195 } 1196 ieee80211_end_scan(ifp); 1197 sc->scan_pass = 0; 1198 break; 1199 case R92S_EVT_JOIN_BSS: 1200 if (ic->ic_state == IEEE80211_S_AUTH) 1201 rsu_event_join_bss(sc, buf, len); 1202 break; 1203 case R92S_EVT_DEL_STA: 1204 DPRINTF(("disassociated from %s\n", ether_sprintf(buf))); 1205 if (ic->ic_state == IEEE80211_S_RUN && 1206 IEEE80211_ADDR_EQ(ic->ic_bss->ni_bssid, buf)) 1207 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1208 break; 1209 case R92S_EVT_WPS_PBC: 1210 DPRINTF(("WPS PBC pushed.\n")); 1211 break; 1212 case R92S_EVT_FWDBG: 1213 if (ifp->if_flags & IFF_DEBUG) { 1214 buf[60] = '\0'; 1215 printf("FWDBG: %s\n", (char *)buf); 1216 } 1217 break; 1218 } 1219 } 1220 1221 void 1222 rsu_rx_multi_event(struct rsu_softc *sc, uint8_t *buf, int len) 1223 { 1224 struct r92s_fw_cmd_hdr *cmd; 1225 int cmdsz; 1226 1227 DPRINTFN(6, ("Rx events len=%d\n", len)); 1228 1229 /* Skip Rx status. */ 1230 buf += sizeof(struct r92s_rx_stat); 1231 len -= sizeof(struct r92s_rx_stat); 1232 1233 /* Process all events. */ 1234 for (;;) { 1235 /* Check that command header fits. */ 1236 if (__predict_false(len < sizeof(*cmd))) 1237 break; 1238 cmd = (struct r92s_fw_cmd_hdr *)buf; 1239 /* Check that command payload fits. */ 1240 cmdsz = letoh16(cmd->len); 1241 if (__predict_false(len < sizeof(*cmd) + cmdsz)) 1242 break; 1243 if (cmdsz > len) 1244 break; 1245 1246 /* Process firmware event. */ 1247 rsu_rx_event(sc, cmd->code, (uint8_t *)&cmd[1], cmdsz); 1248 1249 if (!(cmd->seq & R92S_FW_CMD_MORE)) 1250 break; 1251 buf += sizeof(*cmd) + cmdsz; 1252 len -= sizeof(*cmd) + cmdsz; 1253 } 1254 } 1255 1256 int8_t 1257 rsu_get_rssi(struct rsu_softc *sc, int rate, void *physt) 1258 { 1259 static const int8_t cckoff[] = { 14, -2, -20, -40 }; 1260 struct r92s_rx_phystat *phy; 1261 struct r92s_rx_cck *cck; 1262 uint8_t rpt; 1263 int8_t rssi; 1264 1265 if (rate <= 3) { 1266 cck = (struct r92s_rx_cck *)physt; 1267 rpt = (cck->agc_rpt >> 6) & 0x3; 1268 rssi = cck->agc_rpt & 0x3e; 1269 rssi = cckoff[rpt] - rssi; 1270 } else { /* OFDM/HT. */ 1271 phy = (struct r92s_rx_phystat *)physt; 1272 rssi = ((letoh32(phy->phydw1) >> 1) & 0x7f) - 106; 1273 } 1274 return (rssi); 1275 } 1276 1277 void 1278 rsu_rx_frame(struct rsu_softc *sc, uint8_t *buf, int pktlen, 1279 struct mbuf_list *ml) 1280 { 1281 struct ieee80211com *ic = &sc->sc_ic; 1282 struct ifnet *ifp = &ic->ic_if; 1283 struct ieee80211_rxinfo rxi; 1284 struct ieee80211_frame *wh; 1285 struct ieee80211_node *ni; 1286 struct r92s_rx_stat *stat; 1287 uint32_t rxdw0, rxdw3; 1288 struct mbuf *m; 1289 uint8_t rate; 1290 int8_t rssi = 0; 1291 int s, infosz; 1292 1293 stat = (struct r92s_rx_stat *)buf; 1294 rxdw0 = letoh32(stat->rxdw0); 1295 rxdw3 = letoh32(stat->rxdw3); 1296 1297 if (__predict_false(rxdw0 & R92S_RXDW0_CRCERR)) { 1298 ifp->if_ierrors++; 1299 return; 1300 } 1301 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1302 ifp->if_ierrors++; 1303 return; 1304 } 1305 1306 rate = MS(rxdw3, R92S_RXDW3_RATE); 1307 infosz = MS(rxdw0, R92S_RXDW0_INFOSZ) * 8; 1308 1309 /* Get RSSI from PHY status descriptor if present. */ 1310 if (infosz != 0) 1311 rssi = rsu_get_rssi(sc, rate, &stat[1]); 1312 1313 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1314 pktlen, rate, infosz, rssi)); 1315 1316 MGETHDR(m, M_DONTWAIT, MT_DATA); 1317 if (__predict_false(m == NULL)) { 1318 ifp->if_ierrors++; 1319 return; 1320 } 1321 if (pktlen > MHLEN) { 1322 MCLGET(m, M_DONTWAIT); 1323 if (__predict_false(!(m->m_flags & M_EXT))) { 1324 ifp->if_ierrors++; 1325 m_freem(m); 1326 return; 1327 } 1328 } 1329 /* Finalize mbuf. */ 1330 /* Hardware does Rx TCP checksum offload. */ 1331 if (rxdw3 & R92S_RXDW3_TCPCHKVALID) { 1332 if (__predict_true(rxdw3 & R92S_RXDW3_TCPCHKRPT)) 1333 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 1334 else 1335 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_BAD; 1336 } 1337 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 1338 memcpy(mtod(m, uint8_t *), wh, pktlen); 1339 m->m_pkthdr.len = m->m_len = pktlen; 1340 1341 s = splnet(); 1342 #if NBPFILTER > 0 1343 if (__predict_false(sc->sc_drvbpf != NULL)) { 1344 struct rsu_rx_radiotap_header *tap = &sc->sc_rxtap; 1345 struct mbuf mb; 1346 1347 tap->wr_flags = 0; 1348 /* Map HW rate index to 802.11 rate. */ 1349 tap->wr_flags = 2; 1350 if (!(rxdw3 & R92S_RXDW3_HTC)) { 1351 switch (rate) { 1352 /* CCK. */ 1353 case 0: tap->wr_rate = 2; break; 1354 case 1: tap->wr_rate = 4; break; 1355 case 2: tap->wr_rate = 11; break; 1356 case 3: tap->wr_rate = 22; break; 1357 /* OFDM. */ 1358 case 4: tap->wr_rate = 12; break; 1359 case 5: tap->wr_rate = 18; break; 1360 case 6: tap->wr_rate = 24; break; 1361 case 7: tap->wr_rate = 36; break; 1362 case 8: tap->wr_rate = 48; break; 1363 case 9: tap->wr_rate = 72; break; 1364 case 10: tap->wr_rate = 96; break; 1365 case 11: tap->wr_rate = 108; break; 1366 } 1367 } else if (rate >= 12) { /* MCS0~15. */ 1368 /* Bit 7 set means HT MCS instead of rate. */ 1369 tap->wr_rate = 0x80 | (rate - 12); 1370 } 1371 tap->wr_dbm_antsignal = rssi; 1372 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1373 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1374 1375 mb.m_data = (caddr_t)tap; 1376 mb.m_len = sc->sc_rxtap_len; 1377 mb.m_next = m; 1378 mb.m_nextpkt = NULL; 1379 mb.m_type = 0; 1380 mb.m_flags = 0; 1381 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1382 } 1383 #endif 1384 1385 ni = ieee80211_find_rxnode(ic, wh); 1386 memset(&rxi, 0, sizeof(rxi)); 1387 rxi.rxi_rssi = rssi; 1388 ieee80211_inputm(ifp, m, ni, &rxi, ml); 1389 /* Node is no longer needed. */ 1390 ieee80211_release_node(ic, ni); 1391 splx(s); 1392 } 1393 1394 void 1395 rsu_rx_multi_frame(struct rsu_softc *sc, uint8_t *buf, int len) 1396 { 1397 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1398 struct r92s_rx_stat *stat; 1399 uint32_t rxdw0; 1400 int totlen, pktlen, infosz, npkts; 1401 1402 /* Get the number of encapsulated frames. */ 1403 stat = (struct r92s_rx_stat *)buf; 1404 npkts = MS(letoh32(stat->rxdw2), R92S_RXDW2_PKTCNT); 1405 DPRINTFN(6, ("Rx %d frames in one chunk\n", npkts)); 1406 1407 /* Process all of them. */ 1408 while (npkts-- > 0) { 1409 if (__predict_false(len < sizeof(*stat))) 1410 break; 1411 stat = (struct r92s_rx_stat *)buf; 1412 rxdw0 = letoh32(stat->rxdw0); 1413 1414 pktlen = MS(rxdw0, R92S_RXDW0_PKTLEN); 1415 if (__predict_false(pktlen == 0)) 1416 break; 1417 1418 infosz = MS(rxdw0, R92S_RXDW0_INFOSZ) * 8; 1419 1420 /* Make sure everything fits in xfer. */ 1421 totlen = sizeof(*stat) + infosz + pktlen; 1422 if (__predict_false(totlen > len)) 1423 break; 1424 1425 /* Process 802.11 frame. */ 1426 rsu_rx_frame(sc, buf, pktlen, &ml); 1427 1428 /* Next chunk is 128-byte aligned. */ 1429 totlen = (totlen + 127) & ~127; 1430 buf += totlen; 1431 len -= totlen; 1432 } 1433 if_input(&sc->sc_ic.ic_if, &ml); 1434 } 1435 1436 void 1437 rsu_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1438 { 1439 struct rsu_rx_data *data = priv; 1440 struct rsu_softc *sc = data->sc; 1441 struct r92s_rx_stat *stat; 1442 struct ifnet *ifp = &sc->sc_ic.ic_if; 1443 int len; 1444 1445 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1446 DPRINTF(("RX status=%d\n", status)); 1447 if (status == USBD_STALLED) 1448 usbd_clear_endpoint_stall_async(data->pipe); 1449 if (status != USBD_CANCELLED) 1450 goto resubmit; 1451 return; 1452 } 1453 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1454 1455 if (__predict_false(len < sizeof(*stat))) { 1456 DPRINTF(("xfer too short %d\n", len)); 1457 ifp->if_ierrors++; 1458 goto resubmit; 1459 } 1460 if (len > RSU_RXBUFSZ) { 1461 DPRINTF(("xfer too large %d\n", len)); 1462 ifp->if_ierrors++; 1463 goto resubmit; 1464 } 1465 1466 /* Determine if it is a firmware C2H event or an 802.11 frame. */ 1467 stat = (struct r92s_rx_stat *)data->buf; 1468 if ((letoh32(stat->rxdw1) & 0x1ff) == 0x1ff) 1469 rsu_rx_multi_event(sc, data->buf, len); 1470 else 1471 rsu_rx_multi_frame(sc, data->buf, len); 1472 1473 resubmit: 1474 /* Setup a new transfer. */ 1475 usbd_setup_xfer(xfer, data->pipe, data, data->buf, RSU_RXBUFSZ, 1476 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, rsu_rxeof); 1477 (void)usbd_transfer(xfer); 1478 } 1479 1480 void 1481 rsu_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1482 { 1483 struct rsu_tx_data *data = priv; 1484 struct rsu_softc *sc = data->sc; 1485 struct ifnet *ifp = &sc->sc_ic.ic_if; 1486 int s; 1487 1488 s = splnet(); 1489 /* Put this Tx buffer back to our free list. */ 1490 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1491 1492 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1493 DPRINTF(("TX status=%d\n", status)); 1494 if (status == USBD_STALLED) 1495 usbd_clear_endpoint_stall_async(data->pipe); 1496 ifp->if_oerrors++; 1497 splx(s); 1498 return; 1499 } 1500 sc->sc_tx_timer = 0; 1501 1502 /* We just released a Tx buffer, notify Tx. */ 1503 if (ifq_is_oactive(&ifp->if_snd)) { 1504 ifq_clr_oactive(&ifp->if_snd); 1505 rsu_start(ifp); 1506 } 1507 splx(s); 1508 } 1509 1510 int 1511 rsu_tx(struct rsu_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1512 { 1513 struct ieee80211com *ic = &sc->sc_ic; 1514 struct ieee80211_frame *wh; 1515 struct ieee80211_key *k = NULL; 1516 struct rsu_tx_data *data; 1517 struct r92s_tx_desc *txd; 1518 struct usbd_pipe *pipe; 1519 uint16_t qos; 1520 uint8_t type, qid, tid = 0; 1521 int hasqos, xferlen, error; 1522 1523 wh = mtod(m, struct ieee80211_frame *); 1524 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1525 1526 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1527 k = ieee80211_get_txkey(ic, wh, ni); 1528 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1529 return (ENOBUFS); 1530 wh = mtod(m, struct ieee80211_frame *); 1531 } 1532 if ((hasqos = ieee80211_has_qos(wh))) { 1533 qos = ieee80211_get_qos(wh); 1534 tid = qos & IEEE80211_QOS_TID; 1535 qid = rsu_ac2qid[ieee80211_up_to_ac(ic, tid)]; 1536 } else 1537 qid = RSU_QID_BE; 1538 1539 /* Get the USB pipe to use for this queue id. */ 1540 pipe = sc->pipe[sc->qid2idx[qid]]; 1541 1542 /* Grab a Tx buffer from our free list. */ 1543 data = TAILQ_FIRST(&sc->tx_free_list); 1544 TAILQ_REMOVE(&sc->tx_free_list, data, next); 1545 1546 /* Fill Tx descriptor. */ 1547 txd = (struct r92s_tx_desc *)data->buf; 1548 memset(txd, 0, sizeof(*txd)); 1549 1550 txd->txdw0 |= htole32( 1551 SM(R92S_TXDW0_PKTLEN, m->m_pkthdr.len) | 1552 SM(R92S_TXDW0_OFFSET, sizeof(*txd)) | 1553 R92S_TXDW0_OWN | R92S_TXDW0_FSG | R92S_TXDW0_LSG); 1554 1555 txd->txdw1 |= htole32( 1556 SM(R92S_TXDW1_MACID, R92S_MACID_BSS) | 1557 SM(R92S_TXDW1_QSEL, R92S_TXDW1_QSEL_BE)); 1558 if (!hasqos) 1559 txd->txdw1 |= htole32(R92S_TXDW1_NONQOS); 1560 #ifdef notyet 1561 if (k != NULL) { 1562 switch (k->k_cipher) { 1563 case IEEE80211_CIPHER_WEP40: 1564 case IEEE80211_CIPHER_WEP104: 1565 cipher = R92S_TXDW1_CIPHER_WEP; 1566 break; 1567 case IEEE80211_CIPHER_TKIP: 1568 cipher = R92S_TXDW1_CIPHER_TKIP; 1569 break; 1570 case IEEE80211_CIPHER_CCMP: 1571 cipher = R92S_TXDW1_CIPHER_AES; 1572 break; 1573 default: 1574 cipher = R92S_TXDW1_CIPHER_NONE; 1575 } 1576 txd->txdw1 |= htole32( 1577 SM(R92S_TXDW1_CIPHER, cipher) | 1578 SM(R92S_TXDW1_KEYIDX, k->k_id)); 1579 } 1580 #endif 1581 txd->txdw2 |= htole32(R92S_TXDW2_BK); 1582 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1583 txd->txdw2 |= htole32(R92S_TXDW2_BMCAST); 1584 /* 1585 * Firmware will use and increment the sequence number for the 1586 * specified TID. 1587 */ 1588 txd->txdw3 |= htole32(SM(R92S_TXDW3_SEQ, tid)); 1589 1590 #if NBPFILTER > 0 1591 if (__predict_false(sc->sc_drvbpf != NULL)) { 1592 struct rsu_tx_radiotap_header *tap = &sc->sc_txtap; 1593 struct mbuf mb; 1594 1595 tap->wt_flags = 0; 1596 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1597 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1598 1599 mb.m_data = (caddr_t)tap; 1600 mb.m_len = sc->sc_txtap_len; 1601 mb.m_next = m; 1602 mb.m_nextpkt = NULL; 1603 mb.m_type = 0; 1604 mb.m_flags = 0; 1605 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1606 } 1607 #endif 1608 1609 xferlen = sizeof(*txd) + m->m_pkthdr.len; 1610 m_copydata(m, 0, m->m_pkthdr.len, &txd[1]); 1611 m_freem(m); 1612 1613 data->pipe = pipe; 1614 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 1615 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, RSU_TX_TIMEOUT, 1616 rsu_txeof); 1617 error = usbd_transfer(data->xfer); 1618 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) { 1619 /* Put this Tx buffer back to our free list. */ 1620 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1621 return (error); 1622 } 1623 ieee80211_release_node(ic, ni); 1624 return (0); 1625 } 1626 1627 /* ARGSUSED */ 1628 int 1629 rsu_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1630 int arg1, int arg2) 1631 { 1632 return (EOPNOTSUPP); 1633 } 1634 1635 void 1636 rsu_start(struct ifnet *ifp) 1637 { 1638 struct rsu_softc *sc = ifp->if_softc; 1639 struct ieee80211com *ic = &sc->sc_ic; 1640 struct ieee80211_node *ni; 1641 struct mbuf *m; 1642 1643 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1644 return; 1645 1646 for (;;) { 1647 if (TAILQ_EMPTY(&sc->tx_free_list)) { 1648 ifq_set_oactive(&ifp->if_snd); 1649 break; 1650 } 1651 if (ic->ic_state != IEEE80211_S_RUN) 1652 break; 1653 1654 /* Encapsulate and send data frames. */ 1655 m = ifq_dequeue(&ifp->if_snd); 1656 if (m == NULL) 1657 break; 1658 #if NBPFILTER > 0 1659 if (ifp->if_bpf != NULL) 1660 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1661 #endif 1662 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1663 continue; 1664 1665 #if NBPFILTER > 0 1666 if (ic->ic_rawbpf != NULL) 1667 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1668 #endif 1669 if (rsu_tx(sc, m, ni) != 0) { 1670 ieee80211_release_node(ic, ni); 1671 ifp->if_oerrors++; 1672 continue; 1673 } 1674 1675 sc->sc_tx_timer = 5; 1676 ifp->if_timer = 1; 1677 } 1678 } 1679 1680 void 1681 rsu_watchdog(struct ifnet *ifp) 1682 { 1683 struct rsu_softc *sc = ifp->if_softc; 1684 1685 ifp->if_timer = 0; 1686 1687 if (sc->sc_tx_timer > 0) { 1688 if (--sc->sc_tx_timer == 0) { 1689 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1690 /* rsu_init(ifp); XXX needs a process context! */ 1691 ifp->if_oerrors++; 1692 return; 1693 } 1694 ifp->if_timer = 1; 1695 } 1696 ieee80211_watchdog(ifp); 1697 } 1698 1699 int 1700 rsu_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1701 { 1702 struct rsu_softc *sc = ifp->if_softc; 1703 int s, error = 0; 1704 1705 if (usbd_is_dying(sc->sc_udev)) 1706 return ENXIO; 1707 1708 usbd_ref_incr(sc->sc_udev); 1709 1710 s = splnet(); 1711 1712 switch (cmd) { 1713 case SIOCSIFADDR: 1714 ifp->if_flags |= IFF_UP; 1715 /* FALLTHROUGH */ 1716 case SIOCSIFFLAGS: 1717 if (ifp->if_flags & IFF_UP) { 1718 if (!(ifp->if_flags & IFF_RUNNING)) 1719 rsu_init(ifp); 1720 } else { 1721 if (ifp->if_flags & IFF_RUNNING) 1722 rsu_stop(ifp); 1723 } 1724 break; 1725 default: 1726 error = ieee80211_ioctl(ifp, cmd, data); 1727 } 1728 1729 if (error == ENETRESET) { 1730 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1731 (IFF_UP | IFF_RUNNING)) { 1732 rsu_stop(ifp); 1733 rsu_init(ifp); 1734 } 1735 error = 0; 1736 } 1737 splx(s); 1738 1739 usbd_ref_decr(sc->sc_udev); 1740 1741 return (error); 1742 } 1743 1744 /* 1745 * Power on sequence for A-cut adapters. 1746 */ 1747 void 1748 rsu_power_on_acut(struct rsu_softc *sc) 1749 { 1750 uint32_t reg; 1751 1752 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x53); 1753 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x57); 1754 1755 /* Enable AFE macro block's bandgap and Mbias. */ 1756 rsu_write_1(sc, R92S_AFE_MISC, 1757 rsu_read_1(sc, R92S_AFE_MISC) | 1758 R92S_AFE_MISC_BGEN | R92S_AFE_MISC_MBEN); 1759 /* Enable LDOA15 block. */ 1760 rsu_write_1(sc, R92S_LDOA15_CTRL, 1761 rsu_read_1(sc, R92S_LDOA15_CTRL) | R92S_LDA15_EN); 1762 1763 rsu_write_1(sc, R92S_SPS1_CTRL, 1764 rsu_read_1(sc, R92S_SPS1_CTRL) | R92S_SPS1_LDEN); 1765 usbd_delay_ms(sc->sc_udev, 2); 1766 /* Enable switch regulator block. */ 1767 rsu_write_1(sc, R92S_SPS1_CTRL, 1768 rsu_read_1(sc, R92S_SPS1_CTRL) | R92S_SPS1_SWEN); 1769 1770 rsu_write_4(sc, R92S_SPS1_CTRL, 0x00a7b267); 1771 1772 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 1773 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) | 0x08); 1774 1775 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1776 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x20); 1777 1778 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 1779 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) & ~0x90); 1780 1781 /* Enable AFE clock. */ 1782 rsu_write_1(sc, R92S_AFE_XTAL_CTRL + 1, 1783 rsu_read_1(sc, R92S_AFE_XTAL_CTRL + 1) & ~0x04); 1784 /* Enable AFE PLL macro block. */ 1785 rsu_write_1(sc, R92S_AFE_PLL_CTRL, 1786 rsu_read_1(sc, R92S_AFE_PLL_CTRL) | 0x11); 1787 /* Attach AFE PLL to MACTOP/BB. */ 1788 rsu_write_1(sc, R92S_SYS_ISO_CTRL, 1789 rsu_read_1(sc, R92S_SYS_ISO_CTRL) & ~0x11); 1790 1791 /* Switch to 40MHz clock instead of 80MHz. */ 1792 rsu_write_2(sc, R92S_SYS_CLKR, 1793 rsu_read_2(sc, R92S_SYS_CLKR) & ~R92S_SYS_CLKSEL); 1794 1795 /* Enable MAC clock. */ 1796 rsu_write_2(sc, R92S_SYS_CLKR, 1797 rsu_read_2(sc, R92S_SYS_CLKR) | 1798 R92S_MAC_CLK_EN | R92S_SYS_CLK_EN); 1799 1800 rsu_write_1(sc, R92S_PMC_FSM, 0x02); 1801 1802 /* Enable digital core and IOREG R/W. */ 1803 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1804 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x08); 1805 1806 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1807 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x80); 1808 1809 /* Switch the control path to firmware. */ 1810 reg = rsu_read_2(sc, R92S_SYS_CLKR); 1811 reg = (reg & ~R92S_SWHW_SEL) | R92S_FWHW_SEL; 1812 rsu_write_2(sc, R92S_SYS_CLKR, reg); 1813 1814 rsu_write_2(sc, R92S_CR, 0x37fc); 1815 1816 /* Fix USB RX FIFO issue. */ 1817 rsu_write_1(sc, 0xfe5c, 1818 rsu_read_1(sc, 0xfe5c) | 0x80); 1819 rsu_write_1(sc, 0x00ab, 1820 rsu_read_1(sc, 0x00ab) | 0xc0); 1821 1822 rsu_write_1(sc, R92S_SYS_CLKR, 1823 rsu_read_1(sc, R92S_SYS_CLKR) & ~R92S_SYS_CPU_CLKSEL); 1824 } 1825 1826 /* 1827 * Power on sequence for B-cut and C-cut adapters. 1828 */ 1829 void 1830 rsu_power_on_bcut(struct rsu_softc *sc) 1831 { 1832 uint32_t reg; 1833 int ntries; 1834 1835 /* Prevent eFuse leakage. */ 1836 rsu_write_1(sc, 0x37, 0xb0); 1837 usbd_delay_ms(sc->sc_udev, 10); 1838 rsu_write_1(sc, 0x37, 0x30); 1839 1840 /* Switch the control path to hardware. */ 1841 reg = rsu_read_2(sc, R92S_SYS_CLKR); 1842 if (reg & R92S_FWHW_SEL) { 1843 rsu_write_2(sc, R92S_SYS_CLKR, 1844 reg & ~(R92S_SWHW_SEL | R92S_FWHW_SEL)); 1845 } 1846 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1847 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) & ~0x8c); 1848 DELAY(1000); 1849 1850 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x53); 1851 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x57); 1852 1853 reg = rsu_read_1(sc, R92S_AFE_MISC); 1854 rsu_write_1(sc, R92S_AFE_MISC, reg | R92S_AFE_MISC_BGEN); 1855 rsu_write_1(sc, R92S_AFE_MISC, reg | R92S_AFE_MISC_BGEN | 1856 R92S_AFE_MISC_MBEN | R92S_AFE_MISC_I32_EN); 1857 1858 /* Enable PLL. */ 1859 rsu_write_1(sc, R92S_LDOA15_CTRL, 1860 rsu_read_1(sc, R92S_LDOA15_CTRL) | R92S_LDA15_EN); 1861 1862 rsu_write_1(sc, R92S_LDOV12D_CTRL, 1863 rsu_read_1(sc, R92S_LDOV12D_CTRL) | R92S_LDV12_EN); 1864 1865 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 1866 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) | 0x08); 1867 1868 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1869 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x20); 1870 1871 /* Support 64KB IMEM. */ 1872 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 1873 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) & ~0x97); 1874 1875 /* Enable AFE clock. */ 1876 rsu_write_1(sc, R92S_AFE_XTAL_CTRL + 1, 1877 rsu_read_1(sc, R92S_AFE_XTAL_CTRL + 1) & ~0x04); 1878 /* Enable AFE PLL macro block. */ 1879 reg = rsu_read_1(sc, R92S_AFE_PLL_CTRL); 1880 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x11); 1881 DELAY(500); 1882 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x51); 1883 DELAY(500); 1884 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x11); 1885 DELAY(500); 1886 1887 /* Attach AFE PLL to MACTOP/BB. */ 1888 rsu_write_1(sc, R92S_SYS_ISO_CTRL, 1889 rsu_read_1(sc, R92S_SYS_ISO_CTRL) & ~0x11); 1890 1891 /* Switch to 40MHz clock. */ 1892 rsu_write_1(sc, R92S_SYS_CLKR, 0x00); 1893 /* Disable CPU clock and 80MHz SSC. */ 1894 rsu_write_1(sc, R92S_SYS_CLKR, 1895 rsu_read_1(sc, R92S_SYS_CLKR) | 0xa0); 1896 /* Enable MAC clock. */ 1897 rsu_write_2(sc, R92S_SYS_CLKR, 1898 rsu_read_2(sc, R92S_SYS_CLKR) | 1899 R92S_MAC_CLK_EN | R92S_SYS_CLK_EN); 1900 1901 rsu_write_1(sc, R92S_PMC_FSM, 0x02); 1902 1903 /* Enable digital core and IOREG R/W. */ 1904 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1905 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x08); 1906 1907 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1908 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x80); 1909 1910 /* Switch the control path to firmware. */ 1911 reg = rsu_read_2(sc, R92S_SYS_CLKR); 1912 reg = (reg & ~R92S_SWHW_SEL) | R92S_FWHW_SEL; 1913 rsu_write_2(sc, R92S_SYS_CLKR, reg); 1914 1915 rsu_write_2(sc, R92S_CR, 0x37fc); 1916 1917 /* Fix USB RX FIFO issue. */ 1918 rsu_write_1(sc, 0xfe5c, 1919 rsu_read_1(sc, 0xfe5c) | 0x80); 1920 1921 rsu_write_1(sc, R92S_SYS_CLKR, 1922 rsu_read_1(sc, R92S_SYS_CLKR) & ~R92S_SYS_CPU_CLKSEL); 1923 1924 rsu_write_1(sc, 0xfe1c, 0x80); 1925 1926 /* Make sure TxDMA is ready to download firmware. */ 1927 for (ntries = 0; ntries < 20; ntries++) { 1928 reg = rsu_read_1(sc, R92S_TCR); 1929 if ((reg & (R92S_TCR_IMEM_CHK_RPT | R92S_TCR_EMEM_CHK_RPT)) == 1930 (R92S_TCR_IMEM_CHK_RPT | R92S_TCR_EMEM_CHK_RPT)) 1931 break; 1932 DELAY(5); 1933 } 1934 if (ntries == 20) { 1935 /* Reset TxDMA. */ 1936 reg = rsu_read_1(sc, R92S_CR); 1937 rsu_write_1(sc, R92S_CR, reg & ~R92S_CR_TXDMA_EN); 1938 DELAY(2); 1939 rsu_write_1(sc, R92S_CR, reg | R92S_CR_TXDMA_EN); 1940 } 1941 } 1942 1943 void 1944 rsu_power_off(struct rsu_softc *sc) 1945 { 1946 /* Turn RF off. */ 1947 rsu_write_1(sc, R92S_RF_CTRL, 0x00); 1948 usbd_delay_ms(sc->sc_udev, 5); 1949 1950 /* Turn MAC off. */ 1951 /* Switch control path. */ 1952 rsu_write_1(sc, R92S_SYS_CLKR + 1, 0x38); 1953 /* Reset MACTOP. */ 1954 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 0x70); 1955 rsu_write_1(sc, R92S_PMC_FSM, 0x06); 1956 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 0, 0xf9); 1957 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 0xe8); 1958 1959 /* Disable AFE PLL. */ 1960 rsu_write_1(sc, R92S_AFE_PLL_CTRL, 0x00); 1961 /* Disable A15V. */ 1962 rsu_write_1(sc, R92S_LDOA15_CTRL, 0x54); 1963 /* Disable eFuse 1.2V. */ 1964 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 0x50); 1965 rsu_write_1(sc, R92S_LDOV12D_CTRL, 0x24); 1966 /* Enable AFE macro block's bandgap and Mbias. */ 1967 rsu_write_1(sc, R92S_AFE_MISC, 0x30); 1968 /* Disable 1.6V LDO. */ 1969 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x56); 1970 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x43); 1971 } 1972 1973 int 1974 rsu_fw_loadsection(struct rsu_softc *sc, uint8_t *buf, int len) 1975 { 1976 struct rsu_tx_data *data; 1977 struct r92s_tx_desc *txd; 1978 struct usbd_pipe *pipe; 1979 int mlen, error; 1980 1981 data = sc->fwcmd_data; 1982 pipe = sc->pipe[sc->qid2idx[RSU_QID_VO]]; 1983 txd = (struct r92s_tx_desc *)data->buf; 1984 while (len > 0) { 1985 memset(txd, 0, sizeof(*txd)); 1986 if (len <= RSU_TXBUFSZ - sizeof(*txd)) { 1987 /* Last chunk. */ 1988 txd->txdw0 |= htole32(R92S_TXDW0_LINIP); 1989 mlen = len; 1990 } else 1991 mlen = RSU_TXBUFSZ - sizeof(*txd); 1992 txd->txdw0 |= htole32(SM(R92S_TXDW0_PKTLEN, mlen)); 1993 memcpy(&txd[1], buf, mlen); 1994 1995 usbd_setup_xfer(data->xfer, pipe, NULL, data->buf, 1996 sizeof(*txd) + mlen, 1997 USBD_SHORT_XFER_OK | USBD_NO_COPY | USBD_SYNCHRONOUS, 1998 RSU_TX_TIMEOUT, NULL); 1999 error = usbd_transfer(data->xfer); 2000 if (error != 0) 2001 return (error); 2002 buf += mlen; 2003 len -= mlen; 2004 } 2005 return (0); 2006 } 2007 2008 int 2009 rsu_load_firmware(struct rsu_softc *sc) 2010 { 2011 struct ieee80211com *ic = &sc->sc_ic; 2012 struct r92s_fw_hdr *hdr; 2013 struct r92s_fw_priv *dmem; 2014 uint8_t *imem, *emem; 2015 int imemsz, ememsz; 2016 u_char *fw; 2017 size_t size; 2018 uint32_t reg; 2019 int ntries, error; 2020 2021 /* Read firmware image from the filesystem. */ 2022 if ((error = loadfirmware("rsu-rtl8712", &fw, &size)) != 0) { 2023 printf("%s: failed loadfirmware of file %s (error %d)\n", 2024 sc->sc_dev.dv_xname, "rsu-rtl8712", error); 2025 return (error); 2026 } 2027 if (size < sizeof(*hdr)) { 2028 printf("%s: firmware too short\n", sc->sc_dev.dv_xname); 2029 error = EINVAL; 2030 goto fail; 2031 } 2032 hdr = (struct r92s_fw_hdr *)fw; 2033 if (hdr->signature != htole16(0x8712) && 2034 hdr->signature != htole16(0x8192)) { 2035 printf("%s: invalid firmware signature 0x%x\n", 2036 sc->sc_dev.dv_xname, letoh16(hdr->signature)); 2037 error = EINVAL; 2038 goto fail; 2039 } 2040 DPRINTF(("FW V%d %02x-%02x %02x:%02x\n", letoh16(hdr->version), 2041 hdr->month, hdr->day, hdr->hour, hdr->minute)); 2042 2043 /* Make sure that driver and firmware are in sync. */ 2044 if (hdr->privsz != htole32(sizeof(*dmem))) { 2045 printf("%s: unsupported firmware image\n", 2046 sc->sc_dev.dv_xname); 2047 error = EINVAL; 2048 goto fail; 2049 } 2050 /* Get FW sections sizes. */ 2051 imemsz = letoh32(hdr->imemsz); 2052 ememsz = letoh32(hdr->sramsz); 2053 /* Check that all FW sections fit in image. */ 2054 if (size < sizeof(*hdr) + imemsz + ememsz) { 2055 printf("%s: firmware too short\n", sc->sc_dev.dv_xname); 2056 error = EINVAL; 2057 goto fail; 2058 } 2059 imem = (uint8_t *)&hdr[1]; 2060 emem = imem + imemsz; 2061 2062 /* Load IMEM section. */ 2063 error = rsu_fw_loadsection(sc, imem, imemsz); 2064 if (error != 0) { 2065 printf("%s: could not load firmware section %s\n", 2066 sc->sc_dev.dv_xname, "IMEM"); 2067 goto fail; 2068 } 2069 /* Wait for load to complete. */ 2070 for (ntries = 0; ntries < 10; ntries++) { 2071 reg = rsu_read_2(sc, R92S_TCR); 2072 if (reg & R92S_TCR_IMEM_CODE_DONE) 2073 break; 2074 DELAY(10); 2075 } 2076 if (ntries == 10 || !(reg & R92S_TCR_IMEM_CHK_RPT)) { 2077 printf("%s: timeout waiting for %s transfer\n", 2078 sc->sc_dev.dv_xname, "IMEM"); 2079 error = ETIMEDOUT; 2080 goto fail; 2081 } 2082 2083 /* Load EMEM section. */ 2084 error = rsu_fw_loadsection(sc, emem, ememsz); 2085 if (error != 0) { 2086 printf("%s: could not load firmware section %s\n", 2087 sc->sc_dev.dv_xname, "EMEM"); 2088 goto fail; 2089 } 2090 /* Wait for load to complete. */ 2091 for (ntries = 0; ntries < 10; ntries++) { 2092 reg = rsu_read_2(sc, R92S_TCR); 2093 if (reg & R92S_TCR_EMEM_CODE_DONE) 2094 break; 2095 DELAY(10); 2096 } 2097 if (ntries == 10 || !(reg & R92S_TCR_EMEM_CHK_RPT)) { 2098 printf("%s: timeout waiting for %s transfer\n", 2099 sc->sc_dev.dv_xname, "EMEM"); 2100 error = ETIMEDOUT; 2101 goto fail; 2102 } 2103 2104 /* Enable CPU. */ 2105 rsu_write_1(sc, R92S_SYS_CLKR, 2106 rsu_read_1(sc, R92S_SYS_CLKR) | R92S_SYS_CPU_CLKSEL); 2107 if (!(rsu_read_1(sc, R92S_SYS_CLKR) & R92S_SYS_CPU_CLKSEL)) { 2108 printf("%s: could not enable system clock\n", 2109 sc->sc_dev.dv_xname); 2110 error = EIO; 2111 goto fail; 2112 } 2113 rsu_write_2(sc, R92S_SYS_FUNC_EN, 2114 rsu_read_2(sc, R92S_SYS_FUNC_EN) | R92S_FEN_CPUEN); 2115 if (!(rsu_read_2(sc, R92S_SYS_FUNC_EN) & R92S_FEN_CPUEN)) { 2116 printf("%s: could not enable microcontroller\n", 2117 sc->sc_dev.dv_xname); 2118 error = EIO; 2119 goto fail; 2120 } 2121 /* Wait for CPU to initialize. */ 2122 for (ntries = 0; ntries < 100; ntries++) { 2123 if (rsu_read_2(sc, R92S_TCR) & R92S_TCR_IMEM_RDY) 2124 break; 2125 DELAY(1000); 2126 } 2127 if (ntries == 100) { 2128 printf("%s: timeout waiting for microcontroller\n", 2129 sc->sc_dev.dv_xname); 2130 error = ETIMEDOUT; 2131 goto fail; 2132 } 2133 2134 /* Update DMEM section before loading. */ 2135 dmem = &hdr->priv; 2136 memset(dmem, 0, sizeof(*dmem)); 2137 dmem->hci_sel = R92S_HCI_SEL_USB | R92S_HCI_SEL_8172; 2138 dmem->nendpoints = sc->npipes; 2139 dmem->rf_config = 0x12; /* 1T2R */ 2140 dmem->vcs_type = R92S_VCS_TYPE_AUTO; 2141 dmem->vcs_mode = R92S_VCS_MODE_RTS_CTS; 2142 dmem->bw40_en = (ic->ic_htcaps & IEEE80211_HTCAP_CBW20_40) != 0; 2143 dmem->turbo_mode = 1; 2144 /* Load DMEM section. */ 2145 error = rsu_fw_loadsection(sc, (uint8_t *)dmem, sizeof(*dmem)); 2146 if (error != 0) { 2147 printf("%s: could not load firmware section %s\n", 2148 sc->sc_dev.dv_xname, "DMEM"); 2149 goto fail; 2150 } 2151 /* Wait for load to complete. */ 2152 for (ntries = 0; ntries < 100; ntries++) { 2153 if (rsu_read_2(sc, R92S_TCR) & R92S_TCR_DMEM_CODE_DONE) 2154 break; 2155 DELAY(1000); 2156 } 2157 if (ntries == 100) { 2158 printf("%s: timeout waiting for %s transfer\n", 2159 sc->sc_dev.dv_xname, "DMEM"); 2160 error = ETIMEDOUT; 2161 goto fail; 2162 } 2163 /* Wait for firmware readiness. */ 2164 for (ntries = 0; ntries < 60; ntries++) { 2165 if (!(rsu_read_2(sc, R92S_TCR) & R92S_TCR_FWRDY)) 2166 break; 2167 DELAY(1000); 2168 } 2169 if (ntries == 60) { 2170 printf("%s: timeout waiting for firmware readiness\n", 2171 sc->sc_dev.dv_xname); 2172 error = ETIMEDOUT; 2173 goto fail; 2174 } 2175 fail: 2176 free(fw, M_DEVBUF, size); 2177 return (error); 2178 } 2179 2180 int 2181 rsu_init(struct ifnet *ifp) 2182 { 2183 struct rsu_softc *sc = ifp->if_softc; 2184 struct ieee80211com *ic = &sc->sc_ic; 2185 struct r92s_set_pwr_mode cmd; 2186 struct rsu_rx_data *data; 2187 int i, error; 2188 2189 /* Init host async commands ring. */ 2190 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2191 2192 /* Allocate Tx/Rx buffers. */ 2193 error = rsu_alloc_rx_list(sc); 2194 if (error != 0) { 2195 printf("%s: could not allocate Rx buffers\n", 2196 sc->sc_dev.dv_xname); 2197 goto fail; 2198 } 2199 error = rsu_alloc_tx_list(sc); 2200 if (error != 0) { 2201 printf("%s: could not allocate Tx buffers\n", 2202 sc->sc_dev.dv_xname); 2203 goto fail; 2204 } 2205 /* Reserve one Tx buffer for firmware commands. */ 2206 sc->fwcmd_data = TAILQ_FIRST(&sc->tx_free_list); 2207 TAILQ_REMOVE(&sc->tx_free_list, sc->fwcmd_data, next); 2208 2209 /* Power on adapter. */ 2210 if (sc->cut == 1) 2211 rsu_power_on_acut(sc); 2212 else 2213 rsu_power_on_bcut(sc); 2214 /* Load firmware. */ 2215 error = rsu_load_firmware(sc); 2216 if (error != 0) 2217 goto fail; 2218 2219 /* Enable Rx TCP checksum offload. */ 2220 rsu_write_4(sc, R92S_RCR, 2221 rsu_read_4(sc, R92S_RCR) | 0x04000000); 2222 /* Append PHY status. */ 2223 rsu_write_4(sc, R92S_RCR, 2224 rsu_read_4(sc, R92S_RCR) | 0x02000000); 2225 2226 rsu_write_4(sc, R92S_CR, 2227 rsu_read_4(sc, R92S_CR) & ~0xff000000); 2228 2229 /* Use 128 bytes pages. */ 2230 rsu_write_1(sc, 0x00b5, 2231 rsu_read_1(sc, 0x00b5) | 0x01); 2232 /* Enable USB Rx aggregation. */ 2233 rsu_write_1(sc, 0x00bd, 2234 rsu_read_1(sc, 0x00bd) | 0x80); 2235 /* Set USB Rx aggregation threshold. */ 2236 rsu_write_1(sc, 0x00d9, 0x01); 2237 /* Set USB Rx aggregation timeout (1.7ms/4). */ 2238 rsu_write_1(sc, 0xfe5b, 0x04); 2239 /* Fix USB Rx FIFO issue. */ 2240 rsu_write_1(sc, 0xfe5c, 2241 rsu_read_1(sc, 0xfe5c) | 0x80); 2242 2243 /* Set MAC address. */ 2244 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2245 rsu_write_region_1(sc, R92S_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 2246 2247 /* Queue Rx xfers (XXX C2H pipe for 11-pipe configurations?) */ 2248 for (i = 0; i < RSU_RX_LIST_COUNT; i++) { 2249 data = &sc->rx_data[i]; 2250 2251 data->pipe = sc->pipe[sc->qid2idx[RSU_QID_RXOFF]]; 2252 usbd_setup_xfer(data->xfer, data->pipe, data, data->buf, 2253 RSU_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2254 USBD_NO_TIMEOUT, rsu_rxeof); 2255 error = usbd_transfer(data->xfer); 2256 if (error != 0 && error != USBD_IN_PROGRESS) 2257 goto fail; 2258 } 2259 2260 /* NB: it really takes that long for firmware to boot. */ 2261 usbd_delay_ms(sc->sc_udev, 1500); 2262 2263 DPRINTF(("setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 2264 error = rsu_fw_cmd(sc, R92S_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2265 IEEE80211_ADDR_LEN); 2266 if (error != 0) { 2267 printf("%s: could not set MAC address\n", sc->sc_dev.dv_xname); 2268 goto fail; 2269 } 2270 2271 rsu_write_1(sc, R92S_USB_HRPWM, 2272 R92S_USB_HRPWM_PS_ST_ACTIVE | R92S_USB_HRPWM_PS_ALL_ON); 2273 2274 memset(&cmd, 0, sizeof(cmd)); 2275 cmd.mode = R92S_PS_MODE_ACTIVE; 2276 DPRINTF(("setting ps mode to %d\n", cmd.mode)); 2277 error = rsu_fw_cmd(sc, R92S_CMD_SET_PWR_MODE, &cmd, sizeof(cmd)); 2278 if (error != 0) { 2279 printf("%s: could not set PS mode\n", sc->sc_dev.dv_xname); 2280 goto fail; 2281 } 2282 2283 if (ic->ic_htcaps & IEEE80211_HTCAP_CBW20_40) { 2284 /* Enable 40MHz mode. */ 2285 error = rsu_fw_iocmd(sc, 2286 SM(R92S_IOCMD_CLASS, 0xf4) | 2287 SM(R92S_IOCMD_INDEX, 0x00) | 2288 SM(R92S_IOCMD_VALUE, 0x0007)); 2289 if (error != 0) { 2290 printf("%s: could not enable 40MHz mode\n", 2291 sc->sc_dev.dv_xname); 2292 goto fail; 2293 } 2294 } 2295 2296 /* Set default channel. */ 2297 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2298 2299 /* We're ready to go. */ 2300 ifp->if_flags |= IFF_RUNNING; 2301 ifq_clr_oactive(&ifp->if_snd); 2302 2303 #ifdef notyet 2304 if (ic->ic_flags & IEEE80211_F_WEPON) { 2305 /* Install WEP keys. */ 2306 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2307 rsu_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2308 rsu_wait_async(sc); 2309 } 2310 #endif 2311 2312 sc->scan_pass = 0; 2313 ieee80211_begin_scan(ifp); 2314 return (0); 2315 fail: 2316 rsu_stop(ifp); 2317 return (error); 2318 } 2319 2320 void 2321 rsu_stop(struct ifnet *ifp) 2322 { 2323 struct rsu_softc *sc = ifp->if_softc; 2324 struct ieee80211com *ic = &sc->sc_ic; 2325 int i, s; 2326 2327 sc->sc_tx_timer = 0; 2328 ifp->if_timer = 0; 2329 ifp->if_flags &= ~IFF_RUNNING; 2330 ifq_clr_oactive(&ifp->if_snd); 2331 2332 s = splusb(); 2333 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2334 /* Wait for all async commands to complete. */ 2335 rsu_wait_async(sc); 2336 splx(s); 2337 2338 timeout_del(&sc->calib_to); 2339 2340 /* Power off adapter. */ 2341 rsu_power_off(sc); 2342 2343 /* Abort Tx/Rx. */ 2344 for (i = 0; i < sc->npipes; i++) 2345 usbd_abort_pipe(sc->pipe[i]); 2346 2347 /* Free Tx/Rx buffers. */ 2348 rsu_free_tx_list(sc); 2349 rsu_free_rx_list(sc); 2350 } 2351