1 /* $OpenBSD: if_rsu.c,v 1.45 2019/09/12 12:55:07 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for Realtek RTL8188SU/RTL8191SU/RTL8192SU. 21 */ 22 23 #include "bpfilter.h" 24 25 #include <sys/param.h> 26 #include <sys/sockio.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/timeout.h> 32 #include <sys/conf.h> 33 #include <sys/device.h> 34 #include <sys/endian.h> 35 36 #include <machine/intr.h> 37 38 #if NBPFILTER > 0 39 #include <net/bpf.h> 40 #endif 41 #include <net/if.h> 42 #include <net/if_dl.h> 43 #include <net/if_media.h> 44 45 #include <netinet/in.h> 46 #include <netinet/if_ether.h> 47 48 #include <net80211/ieee80211_var.h> 49 #include <net80211/ieee80211_radiotap.h> 50 51 #include <dev/usb/usb.h> 52 #include <dev/usb/usbdi.h> 53 #include <dev/usb/usbdi_util.h> 54 #include <dev/usb/usbdevs.h> 55 56 #include <dev/usb/if_rsureg.h> 57 58 #ifdef RSU_DEBUG 59 #define DPRINTF(x) do { if (rsu_debug) printf x; } while (0) 60 #define DPRINTFN(n, x) do { if (rsu_debug >= (n)) printf x; } while (0) 61 int rsu_debug = 4; 62 #else 63 #define DPRINTF(x) 64 #define DPRINTFN(n, x) 65 #endif 66 67 /* 68 * NB: When updating this list of devices, beware to also update the list 69 * of devices that have HT support disabled below, if applicable. 70 */ 71 static const struct usb_devno rsu_devs[] = { 72 { USB_VENDOR_ACCTON, USB_PRODUCT_ACCTON_RTL8192SU }, 73 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_USBN10 }, 74 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8192SU_1 }, 75 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_1 }, 76 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_2 }, 77 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_3 }, 78 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_4 }, 79 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_5 }, 80 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192SU_1 }, 81 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192SU_2 }, 82 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192SU_3 }, 83 { USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_RTL8192SU_1 }, 84 { USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_RTL8192SU_2 }, 85 { USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_RTL8192SU_3 }, 86 { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_RTL8192SU }, 87 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA131A1 }, 88 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_RTL8192SU_1 }, 89 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_RTL8192SU_2 }, 90 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192SU_1 }, 91 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192SU_2 }, 92 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192SU_3 }, 93 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWGUN54 }, 94 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWNUM300 }, 95 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192SU_1 }, 96 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192SU_2 }, 97 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_GWUSNANO }, 98 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8171 }, 99 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8172 }, 100 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8173 }, 101 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8174 }, 102 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192SU }, 103 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8712 }, 104 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8713 }, 105 { USB_VENDOR_SENAO, USB_PRODUCT_SENAO_RTL8192SU_1 }, 106 { USB_VENDOR_SENAO, USB_PRODUCT_SENAO_RTL8192SU_2 }, 107 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_WL349V1 }, 108 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_WL353 }, 109 { USB_VENDOR_SWEEX2, USB_PRODUCT_SWEEX2_LW154 } 110 }; 111 112 /* List of devices that have HT support disabled. */ 113 static const struct usb_devno rsu_devs_noht[] = { 114 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8192SU_1 }, 115 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_4 } 116 }; 117 118 int rsu_match(struct device *, void *, void *); 119 void rsu_attach(struct device *, struct device *, void *); 120 int rsu_detach(struct device *, int); 121 int rsu_open_pipes(struct rsu_softc *); 122 void rsu_close_pipes(struct rsu_softc *); 123 int rsu_alloc_rx_list(struct rsu_softc *); 124 void rsu_free_rx_list(struct rsu_softc *); 125 int rsu_alloc_tx_list(struct rsu_softc *); 126 void rsu_free_tx_list(struct rsu_softc *); 127 void rsu_task(void *); 128 void rsu_do_async(struct rsu_softc *, 129 void (*)(struct rsu_softc *, void *), void *, int); 130 void rsu_wait_async(struct rsu_softc *); 131 int rsu_write_region_1(struct rsu_softc *, uint16_t, uint8_t *, 132 int); 133 void rsu_write_1(struct rsu_softc *, uint16_t, uint8_t); 134 void rsu_write_2(struct rsu_softc *, uint16_t, uint16_t); 135 void rsu_write_4(struct rsu_softc *, uint16_t, uint32_t); 136 int rsu_read_region_1(struct rsu_softc *, uint16_t, uint8_t *, 137 int); 138 uint8_t rsu_read_1(struct rsu_softc *, uint16_t); 139 uint16_t rsu_read_2(struct rsu_softc *, uint16_t); 140 uint32_t rsu_read_4(struct rsu_softc *, uint16_t); 141 int rsu_fw_iocmd(struct rsu_softc *, uint32_t); 142 uint8_t rsu_efuse_read_1(struct rsu_softc *, uint16_t); 143 int rsu_read_rom(struct rsu_softc *); 144 int rsu_fw_cmd(struct rsu_softc *, uint8_t, void *, int); 145 int rsu_media_change(struct ifnet *); 146 void rsu_calib_to(void *); 147 void rsu_calib_cb(struct rsu_softc *, void *); 148 int rsu_newstate(struct ieee80211com *, enum ieee80211_state, int); 149 void rsu_newstate_cb(struct rsu_softc *, void *); 150 int rsu_set_key(struct ieee80211com *, struct ieee80211_node *, 151 struct ieee80211_key *); 152 void rsu_set_key_cb(struct rsu_softc *, void *); 153 void rsu_delete_key(struct ieee80211com *, struct ieee80211_node *, 154 struct ieee80211_key *); 155 void rsu_delete_key_cb(struct rsu_softc *, void *); 156 int rsu_site_survey(struct rsu_softc *); 157 int rsu_join_bss(struct rsu_softc *, struct ieee80211_node *); 158 int rsu_disconnect(struct rsu_softc *); 159 void rsu_event_survey(struct rsu_softc *, uint8_t *, int); 160 void rsu_event_join_bss(struct rsu_softc *, uint8_t *, int); 161 void rsu_rx_event(struct rsu_softc *, uint8_t, uint8_t *, int); 162 void rsu_rx_multi_event(struct rsu_softc *, uint8_t *, int); 163 int8_t rsu_get_rssi(struct rsu_softc *, int, void *); 164 void rsu_rx_frame(struct rsu_softc *, uint8_t *, int, 165 struct mbuf_list *); 166 void rsu_rx_multi_frame(struct rsu_softc *, uint8_t *, int); 167 void rsu_rxeof(struct usbd_xfer *, void *, usbd_status); 168 void rsu_txeof(struct usbd_xfer *, void *, usbd_status); 169 int rsu_tx(struct rsu_softc *, struct mbuf *, 170 struct ieee80211_node *); 171 int rsu_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 172 int, int, int); 173 void rsu_start(struct ifnet *); 174 void rsu_watchdog(struct ifnet *); 175 int rsu_ioctl(struct ifnet *, u_long, caddr_t); 176 void rsu_power_on_acut(struct rsu_softc *); 177 void rsu_power_on_bcut(struct rsu_softc *); 178 void rsu_power_off(struct rsu_softc *); 179 int rsu_fw_loadsection(struct rsu_softc *, uint8_t *, int); 180 int rsu_load_firmware(struct rsu_softc *); 181 int rsu_init(struct ifnet *); 182 void rsu_stop(struct ifnet *); 183 184 struct cfdriver rsu_cd = { 185 NULL, "rsu", DV_IFNET 186 }; 187 188 const struct cfattach rsu_ca = { 189 sizeof(struct rsu_softc), rsu_match, rsu_attach, rsu_detach, 190 }; 191 192 int 193 rsu_match(struct device *parent, void *match, void *aux) 194 { 195 struct usb_attach_arg *uaa = aux; 196 197 if (uaa->iface == NULL || uaa->configno != 1) 198 return (UMATCH_NONE); 199 200 return ((usb_lookup(rsu_devs, uaa->vendor, uaa->product) != NULL) ? 201 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 202 } 203 204 void 205 rsu_attach(struct device *parent, struct device *self, void *aux) 206 { 207 struct rsu_softc *sc = (struct rsu_softc *)self; 208 struct usb_attach_arg *uaa = aux; 209 struct ieee80211com *ic = &sc->sc_ic; 210 struct ifnet *ifp = &ic->ic_if; 211 int i, error; 212 213 sc->sc_udev = uaa->device; 214 sc->sc_iface = uaa->iface; 215 216 usb_init_task(&sc->sc_task, rsu_task, sc, USB_TASK_TYPE_GENERIC); 217 timeout_set(&sc->calib_to, rsu_calib_to, sc); 218 219 /* Read chip revision. */ 220 sc->cut = MS(rsu_read_4(sc, R92S_PMC_FSM), R92S_PMC_FSM_CUT); 221 if (sc->cut != 3) 222 sc->cut = (sc->cut >> 1) + 1; 223 224 error = rsu_read_rom(sc); 225 if (error != 0) { 226 printf("%s: could not read ROM\n", sc->sc_dev.dv_xname); 227 return; 228 } 229 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->rom[0x12]); 230 231 printf("%s: MAC/BB RTL8712 cut %d, address %s\n", 232 sc->sc_dev.dv_xname, sc->cut, ether_sprintf(ic->ic_myaddr)); 233 234 if (rsu_open_pipes(sc) != 0) 235 return; 236 237 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 238 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 239 ic->ic_state = IEEE80211_S_INIT; 240 241 /* Set device capabilities. */ 242 ic->ic_caps = 243 IEEE80211_C_SCANALL | /* Hardware scan. */ 244 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 245 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 246 IEEE80211_C_WEP | /* WEP. */ 247 IEEE80211_C_RSN; /* WPA/RSN. */ 248 /* Check if HT support is present. */ 249 if (usb_lookup(rsu_devs_noht, uaa->vendor, uaa->product) == NULL) { 250 #ifdef notyet 251 /* Set HT capabilities. */ 252 ic->ic_htcaps = 253 IEEE80211_HTCAP_CBW20_40 | 254 IEEE80211_HTCAP_DSSSCCK40; 255 /* Set supported HT rates. */ 256 for (i = 0; i < 2; i++) 257 ic->ic_sup_mcs[i] = 0xff; 258 #endif 259 } 260 261 /* Set supported .11b and .11g rates. */ 262 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 263 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 264 265 /* Set supported .11b and .11g channels (1 through 14). */ 266 for (i = 1; i <= 14; i++) { 267 ic->ic_channels[i].ic_freq = 268 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 269 ic->ic_channels[i].ic_flags = 270 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 271 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 272 } 273 274 ifp->if_softc = sc; 275 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 276 ifp->if_ioctl = rsu_ioctl; 277 ifp->if_start = rsu_start; 278 ifp->if_watchdog = rsu_watchdog; 279 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 280 281 if_attach(ifp); 282 ieee80211_ifattach(ifp); 283 #ifdef notyet 284 ic->ic_set_key = rsu_set_key; 285 ic->ic_delete_key = rsu_delete_key; 286 #endif 287 /* Override state transition machine. */ 288 sc->sc_newstate = ic->ic_newstate; 289 ic->ic_newstate = rsu_newstate; 290 ic->ic_send_mgmt = rsu_send_mgmt; 291 ieee80211_media_init(ifp, rsu_media_change, ieee80211_media_status); 292 293 #if NBPFILTER > 0 294 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 295 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 296 297 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 298 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 299 sc->sc_rxtap.wr_ihdr.it_present = htole32(RSU_RX_RADIOTAP_PRESENT); 300 301 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 302 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 303 sc->sc_txtap.wt_ihdr.it_present = htole32(RSU_TX_RADIOTAP_PRESENT); 304 #endif 305 } 306 307 int 308 rsu_detach(struct device *self, int flags) 309 { 310 struct rsu_softc *sc = (struct rsu_softc *)self; 311 struct ifnet *ifp = &sc->sc_ic.ic_if; 312 int s; 313 314 s = splusb(); 315 316 if (timeout_initialized(&sc->calib_to)) 317 timeout_del(&sc->calib_to); 318 319 /* Wait for all async commands to complete. */ 320 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 321 322 usbd_ref_wait(sc->sc_udev); 323 324 if (ifp->if_softc != NULL) { 325 ieee80211_ifdetach(ifp); 326 if_detach(ifp); 327 } 328 329 /* Abort and close Tx/Rx pipes. */ 330 rsu_close_pipes(sc); 331 332 /* Free Tx/Rx buffers. */ 333 rsu_free_tx_list(sc); 334 rsu_free_rx_list(sc); 335 splx(s); 336 337 return (0); 338 } 339 340 int 341 rsu_open_pipes(struct rsu_softc *sc) 342 { 343 usb_interface_descriptor_t *id; 344 int i, error; 345 346 /* 347 * Determine the number of Tx/Rx endpoints (there are chips with 348 * 4, 6 or 11 endpoints). 349 */ 350 id = usbd_get_interface_descriptor(sc->sc_iface); 351 sc->npipes = id->bNumEndpoints; 352 if (sc->npipes == 4) 353 sc->qid2idx = rsu_qid2idx_4ep; 354 else if (sc->npipes == 6) 355 sc->qid2idx = rsu_qid2idx_6ep; 356 else /* Assume npipes==11; will fail below otherwise. */ 357 sc->qid2idx = rsu_qid2idx_11ep; 358 DPRINTF(("%d endpoints configuration\n", sc->npipes)); 359 360 /* Open all pipes. */ 361 for (i = 0; i < MIN(sc->npipes, nitems(r92s_epaddr)); i++) { 362 error = usbd_open_pipe(sc->sc_iface, r92s_epaddr[i], 0, 363 &sc->pipe[i]); 364 if (error != 0) { 365 printf("%s: could not open bulk pipe 0x%02x\n", 366 sc->sc_dev.dv_xname, r92s_epaddr[i]); 367 break; 368 } 369 } 370 if (error != 0) 371 rsu_close_pipes(sc); 372 return (error); 373 } 374 375 void 376 rsu_close_pipes(struct rsu_softc *sc) 377 { 378 int i; 379 380 /* Close all pipes. */ 381 for (i = 0; i < sc->npipes; i++) { 382 if (sc->pipe[i] == NULL) 383 continue; 384 usbd_abort_pipe(sc->pipe[i]); 385 usbd_close_pipe(sc->pipe[i]); 386 } 387 } 388 389 int 390 rsu_alloc_rx_list(struct rsu_softc *sc) 391 { 392 struct rsu_rx_data *data; 393 int i, error = 0; 394 395 for (i = 0; i < RSU_RX_LIST_COUNT; i++) { 396 data = &sc->rx_data[i]; 397 398 data->sc = sc; /* Backpointer for callbacks. */ 399 400 data->xfer = usbd_alloc_xfer(sc->sc_udev); 401 if (data->xfer == NULL) { 402 printf("%s: could not allocate xfer\n", 403 sc->sc_dev.dv_xname); 404 error = ENOMEM; 405 break; 406 } 407 data->buf = usbd_alloc_buffer(data->xfer, RSU_RXBUFSZ); 408 if (data->buf == NULL) { 409 printf("%s: could not allocate xfer buffer\n", 410 sc->sc_dev.dv_xname); 411 error = ENOMEM; 412 break; 413 } 414 } 415 if (error != 0) 416 rsu_free_rx_list(sc); 417 return (error); 418 } 419 420 void 421 rsu_free_rx_list(struct rsu_softc *sc) 422 { 423 int i; 424 425 /* NB: Caller must abort pipe first. */ 426 for (i = 0; i < RSU_RX_LIST_COUNT; i++) { 427 if (sc->rx_data[i].xfer != NULL) 428 usbd_free_xfer(sc->rx_data[i].xfer); 429 sc->rx_data[i].xfer = NULL; 430 } 431 } 432 433 int 434 rsu_alloc_tx_list(struct rsu_softc *sc) 435 { 436 struct rsu_tx_data *data; 437 int i, error = 0; 438 439 TAILQ_INIT(&sc->tx_free_list); 440 for (i = 0; i < RSU_TX_LIST_COUNT; i++) { 441 data = &sc->tx_data[i]; 442 443 data->sc = sc; /* Backpointer for callbacks. */ 444 445 data->xfer = usbd_alloc_xfer(sc->sc_udev); 446 if (data->xfer == NULL) { 447 printf("%s: could not allocate xfer\n", 448 sc->sc_dev.dv_xname); 449 error = ENOMEM; 450 break; 451 } 452 data->buf = usbd_alloc_buffer(data->xfer, RSU_TXBUFSZ); 453 if (data->buf == NULL) { 454 printf("%s: could not allocate xfer buffer\n", 455 sc->sc_dev.dv_xname); 456 error = ENOMEM; 457 break; 458 } 459 /* Append this Tx buffer to our free list. */ 460 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 461 } 462 if (error != 0) 463 rsu_free_tx_list(sc); 464 return (error); 465 } 466 467 void 468 rsu_free_tx_list(struct rsu_softc *sc) 469 { 470 int i; 471 472 /* NB: Caller must abort pipe first. */ 473 for (i = 0; i < RSU_TX_LIST_COUNT; i++) { 474 if (sc->tx_data[i].xfer != NULL) 475 usbd_free_xfer(sc->tx_data[i].xfer); 476 sc->tx_data[i].xfer = NULL; 477 } 478 } 479 480 void 481 rsu_task(void *arg) 482 { 483 struct rsu_softc *sc = arg; 484 struct rsu_host_cmd_ring *ring = &sc->cmdq; 485 struct rsu_host_cmd *cmd; 486 int s; 487 488 /* Process host commands. */ 489 s = splusb(); 490 while (ring->next != ring->cur) { 491 cmd = &ring->cmd[ring->next]; 492 splx(s); 493 /* Invoke callback. */ 494 cmd->cb(sc, cmd->data); 495 s = splusb(); 496 ring->queued--; 497 ring->next = (ring->next + 1) % RSU_HOST_CMD_RING_COUNT; 498 } 499 splx(s); 500 } 501 502 void 503 rsu_do_async(struct rsu_softc *sc, 504 void (*cb)(struct rsu_softc *, void *), void *arg, int len) 505 { 506 struct rsu_host_cmd_ring *ring = &sc->cmdq; 507 struct rsu_host_cmd *cmd; 508 int s; 509 510 s = splusb(); 511 cmd = &ring->cmd[ring->cur]; 512 cmd->cb = cb; 513 KASSERT(len <= sizeof(cmd->data)); 514 memcpy(cmd->data, arg, len); 515 ring->cur = (ring->cur + 1) % RSU_HOST_CMD_RING_COUNT; 516 517 /* If there is no pending command already, schedule a task. */ 518 if (++ring->queued == 1) 519 usb_add_task(sc->sc_udev, &sc->sc_task); 520 splx(s); 521 } 522 523 void 524 rsu_wait_async(struct rsu_softc *sc) 525 { 526 /* Wait for all queued asynchronous commands to complete. */ 527 usb_wait_task(sc->sc_udev, &sc->sc_task); 528 } 529 530 int 531 rsu_write_region_1(struct rsu_softc *sc, uint16_t addr, uint8_t *buf, 532 int len) 533 { 534 usb_device_request_t req; 535 536 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 537 req.bRequest = R92S_REQ_REGS; 538 USETW(req.wValue, addr); 539 USETW(req.wIndex, 0); 540 USETW(req.wLength, len); 541 return (usbd_do_request(sc->sc_udev, &req, buf)); 542 } 543 544 void 545 rsu_write_1(struct rsu_softc *sc, uint16_t addr, uint8_t val) 546 { 547 rsu_write_region_1(sc, addr, &val, 1); 548 } 549 550 void 551 rsu_write_2(struct rsu_softc *sc, uint16_t addr, uint16_t val) 552 { 553 val = htole16(val); 554 rsu_write_region_1(sc, addr, (uint8_t *)&val, 2); 555 } 556 557 void 558 rsu_write_4(struct rsu_softc *sc, uint16_t addr, uint32_t val) 559 { 560 val = htole32(val); 561 rsu_write_region_1(sc, addr, (uint8_t *)&val, 4); 562 } 563 564 int 565 rsu_read_region_1(struct rsu_softc *sc, uint16_t addr, uint8_t *buf, 566 int len) 567 { 568 usb_device_request_t req; 569 570 req.bmRequestType = UT_READ_VENDOR_DEVICE; 571 req.bRequest = R92S_REQ_REGS; 572 USETW(req.wValue, addr); 573 USETW(req.wIndex, 0); 574 USETW(req.wLength, len); 575 return (usbd_do_request(sc->sc_udev, &req, buf)); 576 } 577 578 uint8_t 579 rsu_read_1(struct rsu_softc *sc, uint16_t addr) 580 { 581 uint8_t val; 582 583 if (rsu_read_region_1(sc, addr, &val, 1) != 0) 584 return (0xff); 585 return (val); 586 } 587 588 uint16_t 589 rsu_read_2(struct rsu_softc *sc, uint16_t addr) 590 { 591 uint16_t val; 592 593 if (rsu_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 594 return (0xffff); 595 return (letoh16(val)); 596 } 597 598 uint32_t 599 rsu_read_4(struct rsu_softc *sc, uint16_t addr) 600 { 601 uint32_t val; 602 603 if (rsu_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 604 return (0xffffffff); 605 return (letoh32(val)); 606 } 607 608 int 609 rsu_fw_iocmd(struct rsu_softc *sc, uint32_t iocmd) 610 { 611 int ntries; 612 613 rsu_write_4(sc, R92S_IOCMD_CTRL, iocmd); 614 DELAY(100); 615 for (ntries = 0; ntries < 50; ntries++) { 616 if (rsu_read_4(sc, R92S_IOCMD_CTRL) == 0) 617 return (0); 618 DELAY(10); 619 } 620 return (ETIMEDOUT); 621 } 622 623 uint8_t 624 rsu_efuse_read_1(struct rsu_softc *sc, uint16_t addr) 625 { 626 uint32_t reg; 627 int ntries; 628 629 reg = rsu_read_4(sc, R92S_EFUSE_CTRL); 630 reg = RW(reg, R92S_EFUSE_CTRL_ADDR, addr); 631 reg &= ~R92S_EFUSE_CTRL_VALID; 632 rsu_write_4(sc, R92S_EFUSE_CTRL, reg); 633 /* Wait for read operation to complete. */ 634 for (ntries = 0; ntries < 100; ntries++) { 635 reg = rsu_read_4(sc, R92S_EFUSE_CTRL); 636 if (reg & R92S_EFUSE_CTRL_VALID) 637 return (MS(reg, R92S_EFUSE_CTRL_DATA)); 638 DELAY(5); 639 } 640 printf("%s: could not read efuse byte at address 0x%x\n", 641 sc->sc_dev.dv_xname, addr); 642 return (0xff); 643 } 644 645 int 646 rsu_read_rom(struct rsu_softc *sc) 647 { 648 uint8_t *rom = sc->rom; 649 uint16_t addr = 0; 650 uint32_t reg; 651 uint8_t off, msk; 652 int i; 653 654 /* Make sure that ROM type is eFuse and that autoload succeeded. */ 655 reg = rsu_read_1(sc, R92S_EE_9346CR); 656 if ((reg & (R92S_9356SEL | R92S_EEPROM_EN)) != R92S_EEPROM_EN) 657 return (EIO); 658 659 /* Turn on 2.5V to prevent eFuse leakage. */ 660 reg = rsu_read_1(sc, R92S_EFUSE_TEST + 3); 661 rsu_write_1(sc, R92S_EFUSE_TEST + 3, reg | 0x80); 662 DELAY(1000); 663 rsu_write_1(sc, R92S_EFUSE_TEST + 3, reg & ~0x80); 664 665 /* Read full ROM image. */ 666 memset(&sc->rom, 0xff, sizeof(sc->rom)); 667 while (addr < 512) { 668 reg = rsu_efuse_read_1(sc, addr); 669 if (reg == 0xff) 670 break; 671 addr++; 672 off = reg >> 4; 673 msk = reg & 0xf; 674 for (i = 0; i < 4; i++) { 675 if (msk & (1 << i)) 676 continue; 677 rom[off * 8 + i * 2 + 0] = 678 rsu_efuse_read_1(sc, addr); 679 addr++; 680 rom[off * 8 + i * 2 + 1] = 681 rsu_efuse_read_1(sc, addr); 682 addr++; 683 } 684 } 685 #ifdef RSU_DEBUG 686 if (rsu_debug >= 5) { 687 /* Dump ROM content. */ 688 printf("\n"); 689 for (i = 0; i < sizeof(sc->rom); i++) 690 printf("%02x:", rom[i]); 691 printf("\n"); 692 } 693 #endif 694 return (0); 695 } 696 697 int 698 rsu_fw_cmd(struct rsu_softc *sc, uint8_t code, void *buf, int len) 699 { 700 struct rsu_tx_data *data; 701 struct r92s_tx_desc *txd; 702 struct r92s_fw_cmd_hdr *cmd; 703 struct usbd_pipe *pipe; 704 int cmdsz, xferlen; 705 706 data = sc->fwcmd_data; 707 708 /* Round-up command length to a multiple of 8 bytes. */ 709 cmdsz = (len + 7) & ~7; 710 711 xferlen = sizeof(*txd) + sizeof(*cmd) + cmdsz; 712 KASSERT(xferlen <= RSU_TXBUFSZ); 713 memset(data->buf, 0, xferlen); 714 715 /* Setup Tx descriptor. */ 716 txd = (struct r92s_tx_desc *)data->buf; 717 txd->txdw0 = htole32( 718 SM(R92S_TXDW0_OFFSET, sizeof(*txd)) | 719 SM(R92S_TXDW0_PKTLEN, sizeof(*cmd) + cmdsz) | 720 R92S_TXDW0_OWN | R92S_TXDW0_FSG | R92S_TXDW0_LSG); 721 txd->txdw1 = htole32(SM(R92S_TXDW1_QSEL, R92S_TXDW1_QSEL_H2C)); 722 723 /* Setup command header. */ 724 cmd = (struct r92s_fw_cmd_hdr *)&txd[1]; 725 cmd->len = htole16(cmdsz); 726 cmd->code = code; 727 cmd->seq = sc->cmd_seq; 728 sc->cmd_seq = (sc->cmd_seq + 1) & 0x7f; 729 730 /* Copy command payload. */ 731 memcpy(&cmd[1], buf, len); 732 733 DPRINTFN(2, ("Tx cmd code=%d len=%d\n", code, cmdsz)); 734 pipe = sc->pipe[sc->qid2idx[RSU_QID_H2C]]; 735 usbd_setup_xfer(data->xfer, pipe, NULL, data->buf, xferlen, 736 USBD_SHORT_XFER_OK | USBD_NO_COPY | USBD_SYNCHRONOUS, 737 RSU_CMD_TIMEOUT, NULL); 738 return (usbd_transfer(data->xfer)); 739 } 740 741 int 742 rsu_media_change(struct ifnet *ifp) 743 { 744 int error; 745 746 error = ieee80211_media_change(ifp); 747 if (error != ENETRESET) 748 return (error); 749 750 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 751 (IFF_UP | IFF_RUNNING)) { 752 rsu_stop(ifp); 753 error = rsu_init(ifp); 754 } 755 return (error); 756 } 757 758 void 759 rsu_calib_to(void *arg) 760 { 761 struct rsu_softc *sc = arg; 762 763 if (usbd_is_dying(sc->sc_udev)) 764 return; 765 766 usbd_ref_incr(sc->sc_udev); 767 768 /* Do it in a process context. */ 769 rsu_do_async(sc, rsu_calib_cb, NULL, 0); 770 771 usbd_ref_decr(sc->sc_udev); 772 } 773 774 /* ARGSUSED */ 775 void 776 rsu_calib_cb(struct rsu_softc *sc, void *arg) 777 { 778 uint32_t reg; 779 780 #ifdef notyet 781 /* Read WPS PBC status. */ 782 rsu_write_1(sc, R92S_MAC_PINMUX_CTRL, 783 R92S_GPIOMUX_EN | SM(R92S_GPIOSEL_GPIO, R92S_GPIOSEL_GPIO_JTAG)); 784 rsu_write_1(sc, R92S_GPIO_IO_SEL, 785 rsu_read_1(sc, R92S_GPIO_IO_SEL) & ~R92S_GPIO_WPS); 786 reg = rsu_read_1(sc, R92S_GPIO_CTRL); 787 if (reg != 0xff && (reg & R92S_GPIO_WPS)) 788 DPRINTF(("WPS PBC is pushed\n")); 789 #endif 790 /* Read current signal level. */ 791 if (rsu_fw_iocmd(sc, 0xf4000001) == 0) { 792 reg = rsu_read_4(sc, R92S_IOCMD_DATA); 793 DPRINTFN(8, ("RSSI=%d%%\n", reg >> 4)); 794 } 795 796 if (!usbd_is_dying(sc->sc_udev)) 797 timeout_add_sec(&sc->calib_to, 2); 798 } 799 800 int 801 rsu_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 802 { 803 struct rsu_softc *sc = ic->ic_softc; 804 struct rsu_cmd_newstate cmd; 805 806 /* Do it in a process context. */ 807 cmd.state = nstate; 808 cmd.arg = arg; 809 rsu_do_async(sc, rsu_newstate_cb, &cmd, sizeof(cmd)); 810 return (0); 811 } 812 813 void 814 rsu_newstate_cb(struct rsu_softc *sc, void *arg) 815 { 816 struct rsu_cmd_newstate *cmd = arg; 817 struct ieee80211com *ic = &sc->sc_ic; 818 struct ifnet *ifp = &ic->ic_if; 819 enum ieee80211_state ostate; 820 int error, s; 821 822 s = splnet(); 823 ostate = ic->ic_state; 824 825 if (ostate == IEEE80211_S_RUN) { 826 /* Stop calibration. */ 827 timeout_del(&sc->calib_to); 828 /* Disassociate from our current BSS. */ 829 (void)rsu_disconnect(sc); 830 } 831 switch (cmd->state) { 832 case IEEE80211_S_INIT: 833 break; 834 case IEEE80211_S_SCAN: 835 error = rsu_site_survey(sc); 836 if (error != 0) { 837 printf("%s: could not send site survey command\n", 838 sc->sc_dev.dv_xname); 839 } 840 if (ifp->if_flags & IFF_DEBUG) 841 printf("%s: %s -> %s\n", ifp->if_xname, 842 ieee80211_state_name[ic->ic_state], 843 ieee80211_state_name[cmd->state]); 844 ic->ic_state = cmd->state; 845 splx(s); 846 return; 847 case IEEE80211_S_AUTH: 848 ic->ic_bss->ni_rsn_supp_state = RSNA_SUPP_INITIALIZE; 849 error = rsu_join_bss(sc, ic->ic_bss); 850 if (error != 0) { 851 printf("%s: could not send join command\n", 852 sc->sc_dev.dv_xname); 853 ieee80211_begin_scan(&ic->ic_if); 854 splx(s); 855 return; 856 } 857 if (ifp->if_flags & IFF_DEBUG) 858 printf("%s: %s -> %s\n", ifp->if_xname, 859 ieee80211_state_name[ic->ic_state], 860 ieee80211_state_name[cmd->state]); 861 ic->ic_state = cmd->state; 862 if (ic->ic_flags & IEEE80211_F_RSNON) 863 ic->ic_bss->ni_rsn_supp_state = RSNA_SUPP_PTKSTART; 864 splx(s); 865 return; 866 case IEEE80211_S_ASSOC: 867 /* No-op for this driver. See rsu_event_join_bss(). */ 868 if (ifp->if_flags & IFF_DEBUG) 869 printf("%s: %s -> %s\n", ifp->if_xname, 870 ieee80211_state_name[ic->ic_state], 871 ieee80211_state_name[cmd->state]); 872 ic->ic_state = cmd->state; 873 splx(s); 874 return; 875 case IEEE80211_S_RUN: 876 /* Indicate highest supported rate. */ 877 ic->ic_bss->ni_txrate = ic->ic_bss->ni_rates.rs_nrates - 1; 878 879 /* Start periodic calibration. */ 880 if (!usbd_is_dying(sc->sc_udev)) 881 timeout_add_sec(&sc->calib_to, 2); 882 break; 883 } 884 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 885 splx(s); 886 } 887 888 int 889 rsu_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 890 struct ieee80211_key *k) 891 { 892 struct rsu_softc *sc = ic->ic_softc; 893 struct rsu_cmd_key cmd; 894 895 /* Defer setting of WEP keys until interface is brought up. */ 896 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 897 (IFF_UP | IFF_RUNNING)) 898 return (0); 899 900 /* Do it in a process context. */ 901 cmd.key = *k; 902 rsu_do_async(sc, rsu_set_key_cb, &cmd, sizeof(cmd)); 903 return (0); 904 } 905 906 void 907 rsu_set_key_cb(struct rsu_softc *sc, void *arg) 908 { 909 struct rsu_cmd_key *cmd = arg; 910 struct ieee80211_key *k = &cmd->key; 911 struct r92s_fw_cmd_set_key key; 912 913 memset(&key, 0, sizeof(key)); 914 /* Map net80211 cipher to HW crypto algorithm. */ 915 switch (k->k_cipher) { 916 case IEEE80211_CIPHER_WEP40: 917 key.algo = R92S_KEY_ALGO_WEP40; 918 break; 919 case IEEE80211_CIPHER_WEP104: 920 key.algo = R92S_KEY_ALGO_WEP104; 921 break; 922 case IEEE80211_CIPHER_TKIP: 923 key.algo = R92S_KEY_ALGO_TKIP; 924 break; 925 case IEEE80211_CIPHER_CCMP: 926 key.algo = R92S_KEY_ALGO_AES; 927 break; 928 default: 929 return; 930 } 931 key.id = k->k_id; 932 key.grpkey = (k->k_flags & IEEE80211_KEY_GROUP) != 0; 933 memcpy(key.key, k->k_key, MIN(k->k_len, sizeof(key.key))); 934 (void)rsu_fw_cmd(sc, R92S_CMD_SET_KEY, &key, sizeof(key)); 935 } 936 937 /* ARGSUSED */ 938 void 939 rsu_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 940 struct ieee80211_key *k) 941 { 942 struct rsu_softc *sc = ic->ic_softc; 943 struct rsu_cmd_key cmd; 944 945 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 946 ic->ic_state != IEEE80211_S_RUN) 947 return; /* Nothing to do. */ 948 949 /* Do it in a process context. */ 950 cmd.key = *k; 951 rsu_do_async(sc, rsu_delete_key_cb, &cmd, sizeof(cmd)); 952 } 953 954 void 955 rsu_delete_key_cb(struct rsu_softc *sc, void *arg) 956 { 957 struct rsu_cmd_key *cmd = arg; 958 struct ieee80211_key *k = &cmd->key; 959 struct r92s_fw_cmd_set_key key; 960 961 memset(&key, 0, sizeof(key)); 962 key.id = k->k_id; 963 (void)rsu_fw_cmd(sc, R92S_CMD_SET_KEY, &key, sizeof(key)); 964 } 965 966 int 967 rsu_site_survey(struct rsu_softc *sc) 968 { 969 struct ieee80211com *ic = &sc->sc_ic; 970 struct r92s_fw_cmd_sitesurvey cmd; 971 972 memset(&cmd, 0, sizeof(cmd)); 973 if ((ic->ic_flags & IEEE80211_F_ASCAN) || sc->scan_pass == 1) 974 cmd.active = htole32(1); 975 cmd.limit = htole32(48); 976 if (sc->scan_pass == 1) { 977 /* Do a directed scan for second pass. */ 978 cmd.ssidlen = htole32(ic->ic_des_esslen); 979 memcpy(cmd.ssid, ic->ic_des_essid, ic->ic_des_esslen); 980 } 981 DPRINTF(("sending site survey command, pass=%d\n", sc->scan_pass)); 982 return (rsu_fw_cmd(sc, R92S_CMD_SITE_SURVEY, &cmd, sizeof(cmd))); 983 } 984 985 int 986 rsu_join_bss(struct rsu_softc *sc, struct ieee80211_node *ni) 987 { 988 struct ieee80211com *ic = &sc->sc_ic; 989 struct ndis_wlan_bssid_ex *bss; 990 struct ndis_802_11_fixed_ies *fixed; 991 struct r92s_fw_cmd_auth auth; 992 uint8_t buf[sizeof(*bss) + 128], *frm; 993 uint8_t opmode; 994 int error; 995 996 /* Let the FW decide the opmode based on the capinfo field. */ 997 opmode = NDIS802_11AUTOUNKNOWN; 998 DPRINTF(("setting operating mode to %d\n", opmode)); 999 error = rsu_fw_cmd(sc, R92S_CMD_SET_OPMODE, &opmode, sizeof(opmode)); 1000 if (error != 0) 1001 return (error); 1002 1003 memset(&auth, 0, sizeof(auth)); 1004 if (ic->ic_flags & IEEE80211_F_RSNON) { 1005 auth.mode = R92S_AUTHMODE_WPA; 1006 auth.dot1x = ieee80211_is_8021x_akm(ni->ni_rsnakms); 1007 } else 1008 auth.mode = R92S_AUTHMODE_OPEN; 1009 DPRINTF(("setting auth mode to %d\n", auth.mode)); 1010 error = rsu_fw_cmd(sc, R92S_CMD_SET_AUTH, &auth, sizeof(auth)); 1011 if (error != 0) 1012 return (error); 1013 1014 memset(buf, 0, sizeof(buf)); 1015 bss = (struct ndis_wlan_bssid_ex *)buf; 1016 IEEE80211_ADDR_COPY(bss->macaddr, ni->ni_bssid); 1017 bss->ssid.ssidlen = htole32(ni->ni_esslen); 1018 memcpy(bss->ssid.ssid, ni->ni_essid, ni->ni_esslen); 1019 if (ic->ic_flags & (IEEE80211_F_WEPON | IEEE80211_F_RSNON)) 1020 bss->privacy = htole32(1); 1021 bss->rssi = htole32(ni->ni_rssi); 1022 if (ic->ic_curmode == IEEE80211_MODE_11B) 1023 bss->networktype = htole32(NDIS802_11DS); 1024 else 1025 bss->networktype = htole32(NDIS802_11OFDM24); 1026 bss->config.len = htole32(sizeof(bss->config)); 1027 bss->config.bintval = htole32(ni->ni_intval); 1028 bss->config.dsconfig = htole32(ieee80211_chan2ieee(ic, ni->ni_chan)); 1029 bss->inframode = htole32(NDIS802_11INFRASTRUCTURE); 1030 memcpy(bss->supprates, ni->ni_rates.rs_rates, 1031 ni->ni_rates.rs_nrates); 1032 /* Write the fixed fields of the beacon frame. */ 1033 fixed = (struct ndis_802_11_fixed_ies *)&bss[1]; 1034 memcpy(&fixed->tstamp, ni->ni_tstamp, 8); 1035 fixed->bintval = htole16(ni->ni_intval); 1036 fixed->capabilities = htole16(ni->ni_capinfo); 1037 /* Write IEs to be included in the association request. */ 1038 frm = (uint8_t *)&fixed[1]; 1039 if ((ic->ic_flags & IEEE80211_F_RSNON) && 1040 (ni->ni_rsnprotos & IEEE80211_PROTO_RSN)) 1041 frm = ieee80211_add_rsn(frm, ic, ni); 1042 if (ni->ni_flags & IEEE80211_NODE_QOS) 1043 frm = ieee80211_add_qos_capability(frm, ic); 1044 if (ni->ni_flags & IEEE80211_NODE_HT) 1045 frm = ieee80211_add_htcaps(frm, ic); 1046 if ((ic->ic_flags & IEEE80211_F_RSNON) && 1047 (ni->ni_rsnprotos & IEEE80211_PROTO_WPA)) 1048 frm = ieee80211_add_wpa(frm, ic, ni); 1049 bss->ieslen = htole32(frm - (uint8_t *)fixed); 1050 bss->len = htole32(((frm - buf) + 3) & ~3); 1051 DPRINTF(("sending join bss command to %s chan %d\n", 1052 ether_sprintf(bss->macaddr), letoh32(bss->config.dsconfig))); 1053 return (rsu_fw_cmd(sc, R92S_CMD_JOIN_BSS, buf, sizeof(buf))); 1054 } 1055 1056 int 1057 rsu_disconnect(struct rsu_softc *sc) 1058 { 1059 uint32_t zero = 0; /* :-) */ 1060 1061 /* Disassociate from our current BSS. */ 1062 DPRINTF(("sending disconnect command\n")); 1063 return (rsu_fw_cmd(sc, R92S_CMD_DISCONNECT, &zero, sizeof(zero))); 1064 } 1065 1066 void 1067 rsu_event_survey(struct rsu_softc *sc, uint8_t *buf, int len) 1068 { 1069 struct ieee80211com *ic = &sc->sc_ic; 1070 struct ifnet *ifp = &ic->ic_if; 1071 struct ieee80211_rxinfo rxi; 1072 struct ieee80211_node *ni; 1073 struct ieee80211_frame *wh; 1074 struct ndis_wlan_bssid_ex *bss; 1075 struct mbuf *m; 1076 uint32_t pktlen, ieslen; 1077 1078 if (__predict_false(len < sizeof(*bss))) 1079 return; 1080 bss = (struct ndis_wlan_bssid_ex *)buf; 1081 ieslen = letoh32(bss->ieslen); 1082 if (ieslen > len - sizeof(*bss)) 1083 return; 1084 1085 DPRINTFN(2, ("found BSS %s: len=%d chan=%d inframode=%d " 1086 "networktype=%d privacy=%d\n", 1087 ether_sprintf(bss->macaddr), letoh32(bss->len), 1088 letoh32(bss->config.dsconfig), letoh32(bss->inframode), 1089 letoh32(bss->networktype), letoh32(bss->privacy))); 1090 1091 /* Build a fake beacon frame to let net80211 do all the parsing. */ 1092 pktlen = sizeof(*wh) + ieslen; 1093 if (__predict_false(pktlen > MCLBYTES)) 1094 return; 1095 MGETHDR(m, M_DONTWAIT, MT_DATA); 1096 if (__predict_false(m == NULL)) 1097 return; 1098 if (pktlen > MHLEN) { 1099 MCLGET(m, M_DONTWAIT); 1100 if (!(m->m_flags & M_EXT)) { 1101 m_free(m); 1102 return; 1103 } 1104 } 1105 wh = mtod(m, struct ieee80211_frame *); 1106 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 1107 IEEE80211_FC0_SUBTYPE_BEACON; 1108 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1109 *(uint16_t *)wh->i_dur = 0; 1110 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 1111 IEEE80211_ADDR_COPY(wh->i_addr2, bss->macaddr); 1112 IEEE80211_ADDR_COPY(wh->i_addr3, bss->macaddr); 1113 *(uint16_t *)wh->i_seq = 0; 1114 memcpy(&wh[1], (uint8_t *)&bss[1], ieslen); 1115 1116 /* Finalize mbuf. */ 1117 m->m_pkthdr.len = m->m_len = pktlen; 1118 1119 ni = ieee80211_find_rxnode(ic, wh); 1120 rxi.rxi_flags = 0; 1121 rxi.rxi_rssi = letoh32(bss->rssi); 1122 rxi.rxi_tstamp = 0; 1123 ieee80211_input(ifp, m, ni, &rxi); 1124 /* Node is no longer needed. */ 1125 ieee80211_release_node(ic, ni); 1126 } 1127 1128 void 1129 rsu_event_join_bss(struct rsu_softc *sc, uint8_t *buf, int len) 1130 { 1131 struct ieee80211com *ic = &sc->sc_ic; 1132 struct ieee80211_node *ni = ic->ic_bss; 1133 struct r92s_event_join_bss *rsp; 1134 int res; 1135 1136 if (__predict_false(len < sizeof(*rsp))) 1137 return; 1138 rsp = (struct r92s_event_join_bss *)buf; 1139 res = (int)letoh32(rsp->join_res); 1140 1141 DPRINTF(("Rx join BSS event len=%d res=%d\n", len, res)); 1142 if (res <= 0) { 1143 ic->ic_stats.is_rx_auth_fail++; 1144 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1145 return; 1146 } 1147 DPRINTF(("associated with %s associd=%d\n", 1148 ether_sprintf(rsp->bss.macaddr), letoh32(rsp->associd))); 1149 1150 ni->ni_associd = letoh32(rsp->associd) | 0xc000; 1151 if (ic->ic_flags & IEEE80211_F_WEPON) 1152 ni->ni_flags |= IEEE80211_NODE_TXRXPROT; 1153 1154 /* Force an ASSOC->RUN transition. AUTH->RUN is invalid. */ 1155 ic->ic_state = IEEE80211_S_ASSOC; 1156 ieee80211_new_state(ic, IEEE80211_S_RUN, 1157 IEEE80211_FC0_SUBTYPE_ASSOC_RESP); 1158 } 1159 1160 void 1161 rsu_rx_event(struct rsu_softc *sc, uint8_t code, uint8_t *buf, int len) 1162 { 1163 struct ieee80211com *ic = &sc->sc_ic; 1164 struct ifnet *ifp = &ic->ic_if; 1165 1166 DPRINTFN(4, ("Rx event code=%d len=%d\n", code, len)); 1167 switch (code) { 1168 case R92S_EVT_SURVEY: 1169 if (ic->ic_state == IEEE80211_S_SCAN) 1170 rsu_event_survey(sc, buf, len); 1171 break; 1172 case R92S_EVT_SURVEY_DONE: 1173 DPRINTF(("site survey pass %d done, found %d BSS\n", 1174 sc->scan_pass, letoh32(*(uint32_t *)buf))); 1175 if (ic->ic_state != IEEE80211_S_SCAN) 1176 break; /* Ignore if not scanning. */ 1177 if (sc->scan_pass == 0 && ic->ic_des_esslen != 0) { 1178 /* Schedule a directed scan for hidden APs. */ 1179 sc->scan_pass = 1; 1180 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1181 break; 1182 } 1183 ieee80211_end_scan(ifp); 1184 sc->scan_pass = 0; 1185 break; 1186 case R92S_EVT_JOIN_BSS: 1187 if (ic->ic_state == IEEE80211_S_AUTH) 1188 rsu_event_join_bss(sc, buf, len); 1189 break; 1190 case R92S_EVT_DEL_STA: 1191 DPRINTF(("disassociated from %s\n", ether_sprintf(buf))); 1192 if (ic->ic_state == IEEE80211_S_RUN && 1193 IEEE80211_ADDR_EQ(ic->ic_bss->ni_bssid, buf)) 1194 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1195 break; 1196 case R92S_EVT_WPS_PBC: 1197 DPRINTF(("WPS PBC pushed.\n")); 1198 break; 1199 case R92S_EVT_FWDBG: 1200 if (ifp->if_flags & IFF_DEBUG) { 1201 buf[60] = '\0'; 1202 printf("FWDBG: %s\n", (char *)buf); 1203 } 1204 break; 1205 } 1206 } 1207 1208 void 1209 rsu_rx_multi_event(struct rsu_softc *sc, uint8_t *buf, int len) 1210 { 1211 struct r92s_fw_cmd_hdr *cmd; 1212 int cmdsz; 1213 1214 DPRINTFN(6, ("Rx events len=%d\n", len)); 1215 1216 /* Skip Rx status. */ 1217 buf += sizeof(struct r92s_rx_stat); 1218 len -= sizeof(struct r92s_rx_stat); 1219 1220 /* Process all events. */ 1221 for (;;) { 1222 /* Check that command header fits. */ 1223 if (__predict_false(len < sizeof(*cmd))) 1224 break; 1225 cmd = (struct r92s_fw_cmd_hdr *)buf; 1226 /* Check that command payload fits. */ 1227 cmdsz = letoh16(cmd->len); 1228 if (__predict_false(len < sizeof(*cmd) + cmdsz)) 1229 break; 1230 if (cmdsz > len) 1231 break; 1232 1233 /* Process firmware event. */ 1234 rsu_rx_event(sc, cmd->code, (uint8_t *)&cmd[1], cmdsz); 1235 1236 if (!(cmd->seq & R92S_FW_CMD_MORE)) 1237 break; 1238 buf += sizeof(*cmd) + cmdsz; 1239 len -= sizeof(*cmd) + cmdsz; 1240 } 1241 } 1242 1243 int8_t 1244 rsu_get_rssi(struct rsu_softc *sc, int rate, void *physt) 1245 { 1246 static const int8_t cckoff[] = { 14, -2, -20, -40 }; 1247 struct r92s_rx_phystat *phy; 1248 struct r92s_rx_cck *cck; 1249 uint8_t rpt; 1250 int8_t rssi; 1251 1252 if (rate <= 3) { 1253 cck = (struct r92s_rx_cck *)physt; 1254 rpt = (cck->agc_rpt >> 6) & 0x3; 1255 rssi = cck->agc_rpt & 0x3e; 1256 rssi = cckoff[rpt] - rssi; 1257 } else { /* OFDM/HT. */ 1258 phy = (struct r92s_rx_phystat *)physt; 1259 rssi = ((letoh32(phy->phydw1) >> 1) & 0x7f) - 106; 1260 } 1261 return (rssi); 1262 } 1263 1264 void 1265 rsu_rx_frame(struct rsu_softc *sc, uint8_t *buf, int pktlen, 1266 struct mbuf_list *ml) 1267 { 1268 struct ieee80211com *ic = &sc->sc_ic; 1269 struct ifnet *ifp = &ic->ic_if; 1270 struct ieee80211_rxinfo rxi; 1271 struct ieee80211_frame *wh; 1272 struct ieee80211_node *ni; 1273 struct r92s_rx_stat *stat; 1274 uint32_t rxdw0, rxdw3; 1275 struct mbuf *m; 1276 uint8_t rate; 1277 int8_t rssi = 0; 1278 int s, infosz; 1279 1280 stat = (struct r92s_rx_stat *)buf; 1281 rxdw0 = letoh32(stat->rxdw0); 1282 rxdw3 = letoh32(stat->rxdw3); 1283 1284 if (__predict_false(rxdw0 & R92S_RXDW0_CRCERR)) { 1285 ifp->if_ierrors++; 1286 return; 1287 } 1288 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1289 ifp->if_ierrors++; 1290 return; 1291 } 1292 1293 rate = MS(rxdw3, R92S_RXDW3_RATE); 1294 infosz = MS(rxdw0, R92S_RXDW0_INFOSZ) * 8; 1295 1296 /* Get RSSI from PHY status descriptor if present. */ 1297 if (infosz != 0) 1298 rssi = rsu_get_rssi(sc, rate, &stat[1]); 1299 1300 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1301 pktlen, rate, infosz, rssi)); 1302 1303 MGETHDR(m, M_DONTWAIT, MT_DATA); 1304 if (__predict_false(m == NULL)) { 1305 ifp->if_ierrors++; 1306 return; 1307 } 1308 if (pktlen > MHLEN) { 1309 MCLGET(m, M_DONTWAIT); 1310 if (__predict_false(!(m->m_flags & M_EXT))) { 1311 ifp->if_ierrors++; 1312 m_freem(m); 1313 return; 1314 } 1315 } 1316 /* Finalize mbuf. */ 1317 /* Hardware does Rx TCP checksum offload. */ 1318 if (rxdw3 & R92S_RXDW3_TCPCHKVALID) { 1319 if (__predict_true(rxdw3 & R92S_RXDW3_TCPCHKRPT)) 1320 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 1321 else 1322 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_BAD; 1323 } 1324 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 1325 memcpy(mtod(m, uint8_t *), wh, pktlen); 1326 m->m_pkthdr.len = m->m_len = pktlen; 1327 1328 s = splnet(); 1329 #if NBPFILTER > 0 1330 if (__predict_false(sc->sc_drvbpf != NULL)) { 1331 struct rsu_rx_radiotap_header *tap = &sc->sc_rxtap; 1332 struct mbuf mb; 1333 1334 tap->wr_flags = 0; 1335 /* Map HW rate index to 802.11 rate. */ 1336 tap->wr_flags = 2; 1337 if (!(rxdw3 & R92S_RXDW3_HTC)) { 1338 switch (rate) { 1339 /* CCK. */ 1340 case 0: tap->wr_rate = 2; break; 1341 case 1: tap->wr_rate = 4; break; 1342 case 2: tap->wr_rate = 11; break; 1343 case 3: tap->wr_rate = 22; break; 1344 /* OFDM. */ 1345 case 4: tap->wr_rate = 12; break; 1346 case 5: tap->wr_rate = 18; break; 1347 case 6: tap->wr_rate = 24; break; 1348 case 7: tap->wr_rate = 36; break; 1349 case 8: tap->wr_rate = 48; break; 1350 case 9: tap->wr_rate = 72; break; 1351 case 10: tap->wr_rate = 96; break; 1352 case 11: tap->wr_rate = 108; break; 1353 } 1354 } else if (rate >= 12) { /* MCS0~15. */ 1355 /* Bit 7 set means HT MCS instead of rate. */ 1356 tap->wr_rate = 0x80 | (rate - 12); 1357 } 1358 tap->wr_dbm_antsignal = rssi; 1359 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1360 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1361 1362 mb.m_data = (caddr_t)tap; 1363 mb.m_len = sc->sc_rxtap_len; 1364 mb.m_next = m; 1365 mb.m_nextpkt = NULL; 1366 mb.m_type = 0; 1367 mb.m_flags = 0; 1368 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1369 } 1370 #endif 1371 1372 ni = ieee80211_find_rxnode(ic, wh); 1373 rxi.rxi_flags = 0; 1374 rxi.rxi_rssi = rssi; 1375 rxi.rxi_tstamp = 0; /* Unused. */ 1376 ieee80211_inputm(ifp, m, ni, &rxi, ml); 1377 /* Node is no longer needed. */ 1378 ieee80211_release_node(ic, ni); 1379 splx(s); 1380 } 1381 1382 void 1383 rsu_rx_multi_frame(struct rsu_softc *sc, uint8_t *buf, int len) 1384 { 1385 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1386 struct r92s_rx_stat *stat; 1387 uint32_t rxdw0; 1388 int totlen, pktlen, infosz, npkts; 1389 1390 /* Get the number of encapsulated frames. */ 1391 stat = (struct r92s_rx_stat *)buf; 1392 npkts = MS(letoh32(stat->rxdw2), R92S_RXDW2_PKTCNT); 1393 DPRINTFN(6, ("Rx %d frames in one chunk\n", npkts)); 1394 1395 /* Process all of them. */ 1396 while (npkts-- > 0) { 1397 if (__predict_false(len < sizeof(*stat))) 1398 break; 1399 stat = (struct r92s_rx_stat *)buf; 1400 rxdw0 = letoh32(stat->rxdw0); 1401 1402 pktlen = MS(rxdw0, R92S_RXDW0_PKTLEN); 1403 if (__predict_false(pktlen == 0)) 1404 break; 1405 1406 infosz = MS(rxdw0, R92S_RXDW0_INFOSZ) * 8; 1407 1408 /* Make sure everything fits in xfer. */ 1409 totlen = sizeof(*stat) + infosz + pktlen; 1410 if (__predict_false(totlen > len)) 1411 break; 1412 1413 /* Process 802.11 frame. */ 1414 rsu_rx_frame(sc, buf, pktlen, &ml); 1415 1416 /* Next chunk is 128-byte aligned. */ 1417 totlen = (totlen + 127) & ~127; 1418 buf += totlen; 1419 len -= totlen; 1420 } 1421 if_input(&sc->sc_ic.ic_if, &ml); 1422 } 1423 1424 void 1425 rsu_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1426 { 1427 struct rsu_rx_data *data = priv; 1428 struct rsu_softc *sc = data->sc; 1429 struct r92s_rx_stat *stat; 1430 struct ifnet *ifp = &sc->sc_ic.ic_if; 1431 int len; 1432 1433 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1434 DPRINTF(("RX status=%d\n", status)); 1435 if (status == USBD_STALLED) 1436 usbd_clear_endpoint_stall_async(data->pipe); 1437 if (status != USBD_CANCELLED) 1438 goto resubmit; 1439 return; 1440 } 1441 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1442 1443 if (__predict_false(len < sizeof(*stat))) { 1444 DPRINTF(("xfer too short %d\n", len)); 1445 ifp->if_ierrors++; 1446 goto resubmit; 1447 } 1448 if (len > RSU_RXBUFSZ) { 1449 DPRINTF(("xfer too large %d\n", len)); 1450 ifp->if_ierrors++; 1451 goto resubmit; 1452 } 1453 1454 /* Determine if it is a firmware C2H event or an 802.11 frame. */ 1455 stat = (struct r92s_rx_stat *)data->buf; 1456 if ((letoh32(stat->rxdw1) & 0x1ff) == 0x1ff) 1457 rsu_rx_multi_event(sc, data->buf, len); 1458 else 1459 rsu_rx_multi_frame(sc, data->buf, len); 1460 1461 resubmit: 1462 /* Setup a new transfer. */ 1463 usbd_setup_xfer(xfer, data->pipe, data, data->buf, RSU_RXBUFSZ, 1464 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, rsu_rxeof); 1465 (void)usbd_transfer(xfer); 1466 } 1467 1468 void 1469 rsu_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1470 { 1471 struct rsu_tx_data *data = priv; 1472 struct rsu_softc *sc = data->sc; 1473 struct ifnet *ifp = &sc->sc_ic.ic_if; 1474 int s; 1475 1476 s = splnet(); 1477 /* Put this Tx buffer back to our free list. */ 1478 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1479 1480 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1481 DPRINTF(("TX status=%d\n", status)); 1482 if (status == USBD_STALLED) 1483 usbd_clear_endpoint_stall_async(data->pipe); 1484 ifp->if_oerrors++; 1485 splx(s); 1486 return; 1487 } 1488 sc->sc_tx_timer = 0; 1489 1490 /* We just released a Tx buffer, notify Tx. */ 1491 if (ifq_is_oactive(&ifp->if_snd)) { 1492 ifq_clr_oactive(&ifp->if_snd); 1493 rsu_start(ifp); 1494 } 1495 splx(s); 1496 } 1497 1498 int 1499 rsu_tx(struct rsu_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1500 { 1501 struct ieee80211com *ic = &sc->sc_ic; 1502 struct ieee80211_frame *wh; 1503 struct ieee80211_key *k = NULL; 1504 struct rsu_tx_data *data; 1505 struct r92s_tx_desc *txd; 1506 struct usbd_pipe *pipe; 1507 uint16_t qos; 1508 uint8_t type, qid, tid = 0; 1509 int hasqos, xferlen, error; 1510 1511 wh = mtod(m, struct ieee80211_frame *); 1512 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1513 1514 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1515 k = ieee80211_get_txkey(ic, wh, ni); 1516 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1517 return (ENOBUFS); 1518 wh = mtod(m, struct ieee80211_frame *); 1519 } 1520 if ((hasqos = ieee80211_has_qos(wh))) { 1521 qos = ieee80211_get_qos(wh); 1522 tid = qos & IEEE80211_QOS_TID; 1523 qid = rsu_ac2qid[ieee80211_up_to_ac(ic, tid)]; 1524 } else 1525 qid = RSU_QID_BE; 1526 1527 /* Get the USB pipe to use for this queue id. */ 1528 pipe = sc->pipe[sc->qid2idx[qid]]; 1529 1530 /* Grab a Tx buffer from our free list. */ 1531 data = TAILQ_FIRST(&sc->tx_free_list); 1532 TAILQ_REMOVE(&sc->tx_free_list, data, next); 1533 1534 /* Fill Tx descriptor. */ 1535 txd = (struct r92s_tx_desc *)data->buf; 1536 memset(txd, 0, sizeof(*txd)); 1537 1538 txd->txdw0 |= htole32( 1539 SM(R92S_TXDW0_PKTLEN, m->m_pkthdr.len) | 1540 SM(R92S_TXDW0_OFFSET, sizeof(*txd)) | 1541 R92S_TXDW0_OWN | R92S_TXDW0_FSG | R92S_TXDW0_LSG); 1542 1543 txd->txdw1 |= htole32( 1544 SM(R92S_TXDW1_MACID, R92S_MACID_BSS) | 1545 SM(R92S_TXDW1_QSEL, R92S_TXDW1_QSEL_BE)); 1546 if (!hasqos) 1547 txd->txdw1 |= htole32(R92S_TXDW1_NONQOS); 1548 #ifdef notyet 1549 if (k != NULL) { 1550 switch (k->k_cipher) { 1551 case IEEE80211_CIPHER_WEP40: 1552 case IEEE80211_CIPHER_WEP104: 1553 cipher = R92S_TXDW1_CIPHER_WEP; 1554 break; 1555 case IEEE80211_CIPHER_TKIP: 1556 cipher = R92S_TXDW1_CIPHER_TKIP; 1557 break; 1558 case IEEE80211_CIPHER_CCMP: 1559 cipher = R92S_TXDW1_CIPHER_AES; 1560 break; 1561 default: 1562 cipher = R92S_TXDW1_CIPHER_NONE; 1563 } 1564 txd->txdw1 |= htole32( 1565 SM(R92S_TXDW1_CIPHER, cipher) | 1566 SM(R92S_TXDW1_KEYIDX, k->k_id)); 1567 } 1568 #endif 1569 txd->txdw2 |= htole32(R92S_TXDW2_BK); 1570 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1571 txd->txdw2 |= htole32(R92S_TXDW2_BMCAST); 1572 /* 1573 * Firmware will use and increment the sequence number for the 1574 * specified TID. 1575 */ 1576 txd->txdw3 |= htole32(SM(R92S_TXDW3_SEQ, tid)); 1577 1578 #if NBPFILTER > 0 1579 if (__predict_false(sc->sc_drvbpf != NULL)) { 1580 struct rsu_tx_radiotap_header *tap = &sc->sc_txtap; 1581 struct mbuf mb; 1582 1583 tap->wt_flags = 0; 1584 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1585 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1586 1587 mb.m_data = (caddr_t)tap; 1588 mb.m_len = sc->sc_txtap_len; 1589 mb.m_next = m; 1590 mb.m_nextpkt = NULL; 1591 mb.m_type = 0; 1592 mb.m_flags = 0; 1593 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1594 } 1595 #endif 1596 1597 xferlen = sizeof(*txd) + m->m_pkthdr.len; 1598 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 1599 m_freem(m); 1600 1601 data->pipe = pipe; 1602 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 1603 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, RSU_TX_TIMEOUT, 1604 rsu_txeof); 1605 error = usbd_transfer(data->xfer); 1606 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) { 1607 /* Put this Tx buffer back to our free list. */ 1608 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1609 return (error); 1610 } 1611 ieee80211_release_node(ic, ni); 1612 return (0); 1613 } 1614 1615 /* ARGSUSED */ 1616 int 1617 rsu_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1618 int arg1, int arg2) 1619 { 1620 return (EOPNOTSUPP); 1621 } 1622 1623 void 1624 rsu_start(struct ifnet *ifp) 1625 { 1626 struct rsu_softc *sc = ifp->if_softc; 1627 struct ieee80211com *ic = &sc->sc_ic; 1628 struct ieee80211_node *ni; 1629 struct mbuf *m; 1630 1631 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1632 return; 1633 1634 for (;;) { 1635 if (TAILQ_EMPTY(&sc->tx_free_list)) { 1636 ifq_set_oactive(&ifp->if_snd); 1637 break; 1638 } 1639 if (ic->ic_state != IEEE80211_S_RUN) 1640 break; 1641 1642 /* Encapsulate and send data frames. */ 1643 IFQ_DEQUEUE(&ifp->if_snd, m); 1644 if (m == NULL) 1645 break; 1646 #if NBPFILTER > 0 1647 if (ifp->if_bpf != NULL) 1648 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1649 #endif 1650 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1651 continue; 1652 1653 #if NBPFILTER > 0 1654 if (ic->ic_rawbpf != NULL) 1655 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1656 #endif 1657 if (rsu_tx(sc, m, ni) != 0) { 1658 ieee80211_release_node(ic, ni); 1659 ifp->if_oerrors++; 1660 continue; 1661 } 1662 1663 sc->sc_tx_timer = 5; 1664 ifp->if_timer = 1; 1665 } 1666 } 1667 1668 void 1669 rsu_watchdog(struct ifnet *ifp) 1670 { 1671 struct rsu_softc *sc = ifp->if_softc; 1672 1673 ifp->if_timer = 0; 1674 1675 if (sc->sc_tx_timer > 0) { 1676 if (--sc->sc_tx_timer == 0) { 1677 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1678 /* rsu_init(ifp); XXX needs a process context! */ 1679 ifp->if_oerrors++; 1680 return; 1681 } 1682 ifp->if_timer = 1; 1683 } 1684 ieee80211_watchdog(ifp); 1685 } 1686 1687 int 1688 rsu_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1689 { 1690 struct rsu_softc *sc = ifp->if_softc; 1691 int s, error = 0; 1692 1693 if (usbd_is_dying(sc->sc_udev)) 1694 return ENXIO; 1695 1696 usbd_ref_incr(sc->sc_udev); 1697 1698 s = splnet(); 1699 1700 switch (cmd) { 1701 case SIOCSIFADDR: 1702 ifp->if_flags |= IFF_UP; 1703 /* FALLTHROUGH */ 1704 case SIOCSIFFLAGS: 1705 if (ifp->if_flags & IFF_UP) { 1706 if (!(ifp->if_flags & IFF_RUNNING)) 1707 rsu_init(ifp); 1708 } else { 1709 if (ifp->if_flags & IFF_RUNNING) 1710 rsu_stop(ifp); 1711 } 1712 break; 1713 default: 1714 error = ieee80211_ioctl(ifp, cmd, data); 1715 } 1716 1717 if (error == ENETRESET) { 1718 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1719 (IFF_UP | IFF_RUNNING)) { 1720 rsu_stop(ifp); 1721 rsu_init(ifp); 1722 } 1723 error = 0; 1724 } 1725 splx(s); 1726 1727 usbd_ref_decr(sc->sc_udev); 1728 1729 return (error); 1730 } 1731 1732 /* 1733 * Power on sequence for A-cut adapters. 1734 */ 1735 void 1736 rsu_power_on_acut(struct rsu_softc *sc) 1737 { 1738 uint32_t reg; 1739 1740 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x53); 1741 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x57); 1742 1743 /* Enable AFE macro block's bandgap and Mbias. */ 1744 rsu_write_1(sc, R92S_AFE_MISC, 1745 rsu_read_1(sc, R92S_AFE_MISC) | 1746 R92S_AFE_MISC_BGEN | R92S_AFE_MISC_MBEN); 1747 /* Enable LDOA15 block. */ 1748 rsu_write_1(sc, R92S_LDOA15_CTRL, 1749 rsu_read_1(sc, R92S_LDOA15_CTRL) | R92S_LDA15_EN); 1750 1751 rsu_write_1(sc, R92S_SPS1_CTRL, 1752 rsu_read_1(sc, R92S_SPS1_CTRL) | R92S_SPS1_LDEN); 1753 usbd_delay_ms(sc->sc_udev, 2); 1754 /* Enable switch regulator block. */ 1755 rsu_write_1(sc, R92S_SPS1_CTRL, 1756 rsu_read_1(sc, R92S_SPS1_CTRL) | R92S_SPS1_SWEN); 1757 1758 rsu_write_4(sc, R92S_SPS1_CTRL, 0x00a7b267); 1759 1760 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 1761 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) | 0x08); 1762 1763 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1764 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x20); 1765 1766 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 1767 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) & ~0x90); 1768 1769 /* Enable AFE clock. */ 1770 rsu_write_1(sc, R92S_AFE_XTAL_CTRL + 1, 1771 rsu_read_1(sc, R92S_AFE_XTAL_CTRL + 1) & ~0x04); 1772 /* Enable AFE PLL macro block. */ 1773 rsu_write_1(sc, R92S_AFE_PLL_CTRL, 1774 rsu_read_1(sc, R92S_AFE_PLL_CTRL) | 0x11); 1775 /* Attach AFE PLL to MACTOP/BB. */ 1776 rsu_write_1(sc, R92S_SYS_ISO_CTRL, 1777 rsu_read_1(sc, R92S_SYS_ISO_CTRL) & ~0x11); 1778 1779 /* Switch to 40MHz clock instead of 80MHz. */ 1780 rsu_write_2(sc, R92S_SYS_CLKR, 1781 rsu_read_2(sc, R92S_SYS_CLKR) & ~R92S_SYS_CLKSEL); 1782 1783 /* Enable MAC clock. */ 1784 rsu_write_2(sc, R92S_SYS_CLKR, 1785 rsu_read_2(sc, R92S_SYS_CLKR) | 1786 R92S_MAC_CLK_EN | R92S_SYS_CLK_EN); 1787 1788 rsu_write_1(sc, R92S_PMC_FSM, 0x02); 1789 1790 /* Enable digital core and IOREG R/W. */ 1791 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1792 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x08); 1793 1794 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1795 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x80); 1796 1797 /* Switch the control path to firmware. */ 1798 reg = rsu_read_2(sc, R92S_SYS_CLKR); 1799 reg = (reg & ~R92S_SWHW_SEL) | R92S_FWHW_SEL; 1800 rsu_write_2(sc, R92S_SYS_CLKR, reg); 1801 1802 rsu_write_2(sc, R92S_CR, 0x37fc); 1803 1804 /* Fix USB RX FIFO issue. */ 1805 rsu_write_1(sc, 0xfe5c, 1806 rsu_read_1(sc, 0xfe5c) | 0x80); 1807 rsu_write_1(sc, 0x00ab, 1808 rsu_read_1(sc, 0x00ab) | 0xc0); 1809 1810 rsu_write_1(sc, R92S_SYS_CLKR, 1811 rsu_read_1(sc, R92S_SYS_CLKR) & ~R92S_SYS_CPU_CLKSEL); 1812 } 1813 1814 /* 1815 * Power on sequence for B-cut and C-cut adapters. 1816 */ 1817 void 1818 rsu_power_on_bcut(struct rsu_softc *sc) 1819 { 1820 uint32_t reg; 1821 int ntries; 1822 1823 /* Prevent eFuse leakage. */ 1824 rsu_write_1(sc, 0x37, 0xb0); 1825 usbd_delay_ms(sc->sc_udev, 10); 1826 rsu_write_1(sc, 0x37, 0x30); 1827 1828 /* Switch the control path to hardware. */ 1829 reg = rsu_read_2(sc, R92S_SYS_CLKR); 1830 if (reg & R92S_FWHW_SEL) { 1831 rsu_write_2(sc, R92S_SYS_CLKR, 1832 reg & ~(R92S_SWHW_SEL | R92S_FWHW_SEL)); 1833 } 1834 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1835 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) & ~0x8c); 1836 DELAY(1000); 1837 1838 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x53); 1839 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x57); 1840 1841 reg = rsu_read_1(sc, R92S_AFE_MISC); 1842 rsu_write_1(sc, R92S_AFE_MISC, reg | R92S_AFE_MISC_BGEN); 1843 rsu_write_1(sc, R92S_AFE_MISC, reg | R92S_AFE_MISC_BGEN | 1844 R92S_AFE_MISC_MBEN | R92S_AFE_MISC_I32_EN); 1845 1846 /* Enable PLL. */ 1847 rsu_write_1(sc, R92S_LDOA15_CTRL, 1848 rsu_read_1(sc, R92S_LDOA15_CTRL) | R92S_LDA15_EN); 1849 1850 rsu_write_1(sc, R92S_LDOV12D_CTRL, 1851 rsu_read_1(sc, R92S_LDOV12D_CTRL) | R92S_LDV12_EN); 1852 1853 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 1854 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) | 0x08); 1855 1856 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1857 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x20); 1858 1859 /* Support 64KB IMEM. */ 1860 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 1861 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) & ~0x97); 1862 1863 /* Enable AFE clock. */ 1864 rsu_write_1(sc, R92S_AFE_XTAL_CTRL + 1, 1865 rsu_read_1(sc, R92S_AFE_XTAL_CTRL + 1) & ~0x04); 1866 /* Enable AFE PLL macro block. */ 1867 reg = rsu_read_1(sc, R92S_AFE_PLL_CTRL); 1868 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x11); 1869 DELAY(500); 1870 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x51); 1871 DELAY(500); 1872 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x11); 1873 DELAY(500); 1874 1875 /* Attach AFE PLL to MACTOP/BB. */ 1876 rsu_write_1(sc, R92S_SYS_ISO_CTRL, 1877 rsu_read_1(sc, R92S_SYS_ISO_CTRL) & ~0x11); 1878 1879 /* Switch to 40MHz clock. */ 1880 rsu_write_1(sc, R92S_SYS_CLKR, 0x00); 1881 /* Disable CPU clock and 80MHz SSC. */ 1882 rsu_write_1(sc, R92S_SYS_CLKR, 1883 rsu_read_1(sc, R92S_SYS_CLKR) | 0xa0); 1884 /* Enable MAC clock. */ 1885 rsu_write_2(sc, R92S_SYS_CLKR, 1886 rsu_read_2(sc, R92S_SYS_CLKR) | 1887 R92S_MAC_CLK_EN | R92S_SYS_CLK_EN); 1888 1889 rsu_write_1(sc, R92S_PMC_FSM, 0x02); 1890 1891 /* Enable digital core and IOREG R/W. */ 1892 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1893 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x08); 1894 1895 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 1896 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x80); 1897 1898 /* Switch the control path to firmware. */ 1899 reg = rsu_read_2(sc, R92S_SYS_CLKR); 1900 reg = (reg & ~R92S_SWHW_SEL) | R92S_FWHW_SEL; 1901 rsu_write_2(sc, R92S_SYS_CLKR, reg); 1902 1903 rsu_write_2(sc, R92S_CR, 0x37fc); 1904 1905 /* Fix USB RX FIFO issue. */ 1906 rsu_write_1(sc, 0xfe5c, 1907 rsu_read_1(sc, 0xfe5c) | 0x80); 1908 1909 rsu_write_1(sc, R92S_SYS_CLKR, 1910 rsu_read_1(sc, R92S_SYS_CLKR) & ~R92S_SYS_CPU_CLKSEL); 1911 1912 rsu_write_1(sc, 0xfe1c, 0x80); 1913 1914 /* Make sure TxDMA is ready to download firmware. */ 1915 for (ntries = 0; ntries < 20; ntries++) { 1916 reg = rsu_read_1(sc, R92S_TCR); 1917 if ((reg & (R92S_TCR_IMEM_CHK_RPT | R92S_TCR_EMEM_CHK_RPT)) == 1918 (R92S_TCR_IMEM_CHK_RPT | R92S_TCR_EMEM_CHK_RPT)) 1919 break; 1920 DELAY(5); 1921 } 1922 if (ntries == 20) { 1923 /* Reset TxDMA. */ 1924 reg = rsu_read_1(sc, R92S_CR); 1925 rsu_write_1(sc, R92S_CR, reg & ~R92S_CR_TXDMA_EN); 1926 DELAY(2); 1927 rsu_write_1(sc, R92S_CR, reg | R92S_CR_TXDMA_EN); 1928 } 1929 } 1930 1931 void 1932 rsu_power_off(struct rsu_softc *sc) 1933 { 1934 /* Turn RF off. */ 1935 rsu_write_1(sc, R92S_RF_CTRL, 0x00); 1936 usbd_delay_ms(sc->sc_udev, 5); 1937 1938 /* Turn MAC off. */ 1939 /* Switch control path. */ 1940 rsu_write_1(sc, R92S_SYS_CLKR + 1, 0x38); 1941 /* Reset MACTOP. */ 1942 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 0x70); 1943 rsu_write_1(sc, R92S_PMC_FSM, 0x06); 1944 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 0, 0xf9); 1945 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 0xe8); 1946 1947 /* Disable AFE PLL. */ 1948 rsu_write_1(sc, R92S_AFE_PLL_CTRL, 0x00); 1949 /* Disable A15V. */ 1950 rsu_write_1(sc, R92S_LDOA15_CTRL, 0x54); 1951 /* Disable eFuse 1.2V. */ 1952 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 0x50); 1953 rsu_write_1(sc, R92S_LDOV12D_CTRL, 0x24); 1954 /* Enable AFE macro block's bandgap and Mbias. */ 1955 rsu_write_1(sc, R92S_AFE_MISC, 0x30); 1956 /* Disable 1.6V LDO. */ 1957 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x56); 1958 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x43); 1959 } 1960 1961 int 1962 rsu_fw_loadsection(struct rsu_softc *sc, uint8_t *buf, int len) 1963 { 1964 struct rsu_tx_data *data; 1965 struct r92s_tx_desc *txd; 1966 struct usbd_pipe *pipe; 1967 int mlen, error; 1968 1969 data = sc->fwcmd_data; 1970 pipe = sc->pipe[sc->qid2idx[RSU_QID_VO]]; 1971 txd = (struct r92s_tx_desc *)data->buf; 1972 while (len > 0) { 1973 memset(txd, 0, sizeof(*txd)); 1974 if (len <= RSU_TXBUFSZ - sizeof(*txd)) { 1975 /* Last chunk. */ 1976 txd->txdw0 |= htole32(R92S_TXDW0_LINIP); 1977 mlen = len; 1978 } else 1979 mlen = RSU_TXBUFSZ - sizeof(*txd); 1980 txd->txdw0 |= htole32(SM(R92S_TXDW0_PKTLEN, mlen)); 1981 memcpy(&txd[1], buf, mlen); 1982 1983 usbd_setup_xfer(data->xfer, pipe, NULL, data->buf, 1984 sizeof(*txd) + mlen, 1985 USBD_SHORT_XFER_OK | USBD_NO_COPY | USBD_SYNCHRONOUS, 1986 RSU_TX_TIMEOUT, NULL); 1987 error = usbd_transfer(data->xfer); 1988 if (error != 0) 1989 return (error); 1990 buf += mlen; 1991 len -= mlen; 1992 } 1993 return (0); 1994 } 1995 1996 int 1997 rsu_load_firmware(struct rsu_softc *sc) 1998 { 1999 struct ieee80211com *ic = &sc->sc_ic; 2000 struct r92s_fw_hdr *hdr; 2001 struct r92s_fw_priv *dmem; 2002 uint8_t *imem, *emem; 2003 int imemsz, ememsz; 2004 u_char *fw; 2005 size_t size; 2006 uint32_t reg; 2007 int ntries, error; 2008 2009 /* Read firmware image from the filesystem. */ 2010 if ((error = loadfirmware("rsu-rtl8712fw", &fw, &size)) != 0) { 2011 printf("%s: failed loadfirmware of file %s (error %d)\n", 2012 sc->sc_dev.dv_xname, "rsu-rtl8712fw", error); 2013 return (error); 2014 } 2015 if (size < sizeof(*hdr)) { 2016 printf("%s: firmware too short\n", sc->sc_dev.dv_xname); 2017 error = EINVAL; 2018 goto fail; 2019 } 2020 hdr = (struct r92s_fw_hdr *)fw; 2021 if (hdr->signature != htole16(0x8712) && 2022 hdr->signature != htole16(0x8192)) { 2023 printf("%s: invalid firmware signature 0x%x\n", 2024 sc->sc_dev.dv_xname, letoh16(hdr->signature)); 2025 error = EINVAL; 2026 goto fail; 2027 } 2028 DPRINTF(("FW V%d %02x-%02x %02x:%02x\n", letoh16(hdr->version), 2029 hdr->month, hdr->day, hdr->hour, hdr->minute)); 2030 2031 /* Make sure that driver and firmware are in sync. */ 2032 if (hdr->privsz != htole32(sizeof(*dmem))) { 2033 printf("%s: unsupported firmware image\n", 2034 sc->sc_dev.dv_xname); 2035 error = EINVAL; 2036 goto fail; 2037 } 2038 /* Get FW sections sizes. */ 2039 imemsz = letoh32(hdr->imemsz); 2040 ememsz = letoh32(hdr->sramsz); 2041 /* Check that all FW sections fit in image. */ 2042 if (size < sizeof(*hdr) + imemsz + ememsz) { 2043 printf("%s: firmware too short\n", sc->sc_dev.dv_xname); 2044 error = EINVAL; 2045 goto fail; 2046 } 2047 imem = (uint8_t *)&hdr[1]; 2048 emem = imem + imemsz; 2049 2050 /* Load IMEM section. */ 2051 error = rsu_fw_loadsection(sc, imem, imemsz); 2052 if (error != 0) { 2053 printf("%s: could not load firmware section %s\n", 2054 sc->sc_dev.dv_xname, "IMEM"); 2055 goto fail; 2056 } 2057 /* Wait for load to complete. */ 2058 for (ntries = 0; ntries < 10; ntries++) { 2059 reg = rsu_read_2(sc, R92S_TCR); 2060 if (reg & R92S_TCR_IMEM_CODE_DONE) 2061 break; 2062 DELAY(10); 2063 } 2064 if (ntries == 10 || !(reg & R92S_TCR_IMEM_CHK_RPT)) { 2065 printf("%s: timeout waiting for %s transfer\n", 2066 sc->sc_dev.dv_xname, "IMEM"); 2067 error = ETIMEDOUT; 2068 goto fail; 2069 } 2070 2071 /* Load EMEM section. */ 2072 error = rsu_fw_loadsection(sc, emem, ememsz); 2073 if (error != 0) { 2074 printf("%s: could not load firmware section %s\n", 2075 sc->sc_dev.dv_xname, "EMEM"); 2076 goto fail; 2077 } 2078 /* Wait for load to complete. */ 2079 for (ntries = 0; ntries < 10; ntries++) { 2080 reg = rsu_read_2(sc, R92S_TCR); 2081 if (reg & R92S_TCR_EMEM_CODE_DONE) 2082 break; 2083 DELAY(10); 2084 } 2085 if (ntries == 10 || !(reg & R92S_TCR_EMEM_CHK_RPT)) { 2086 printf("%s: timeout waiting for %s transfer\n", 2087 sc->sc_dev.dv_xname, "EMEM"); 2088 error = ETIMEDOUT; 2089 goto fail; 2090 } 2091 2092 /* Enable CPU. */ 2093 rsu_write_1(sc, R92S_SYS_CLKR, 2094 rsu_read_1(sc, R92S_SYS_CLKR) | R92S_SYS_CPU_CLKSEL); 2095 if (!(rsu_read_1(sc, R92S_SYS_CLKR) & R92S_SYS_CPU_CLKSEL)) { 2096 printf("%s: could not enable system clock\n", 2097 sc->sc_dev.dv_xname); 2098 error = EIO; 2099 goto fail; 2100 } 2101 rsu_write_2(sc, R92S_SYS_FUNC_EN, 2102 rsu_read_2(sc, R92S_SYS_FUNC_EN) | R92S_FEN_CPUEN); 2103 if (!(rsu_read_2(sc, R92S_SYS_FUNC_EN) & R92S_FEN_CPUEN)) { 2104 printf("%s: could not enable microcontroller\n", 2105 sc->sc_dev.dv_xname); 2106 error = EIO; 2107 goto fail; 2108 } 2109 /* Wait for CPU to initialize. */ 2110 for (ntries = 0; ntries < 100; ntries++) { 2111 if (rsu_read_2(sc, R92S_TCR) & R92S_TCR_IMEM_RDY) 2112 break; 2113 DELAY(1000); 2114 } 2115 if (ntries == 100) { 2116 printf("%s: timeout waiting for microcontroller\n", 2117 sc->sc_dev.dv_xname); 2118 error = ETIMEDOUT; 2119 goto fail; 2120 } 2121 2122 /* Update DMEM section before loading. */ 2123 dmem = &hdr->priv; 2124 memset(dmem, 0, sizeof(*dmem)); 2125 dmem->hci_sel = R92S_HCI_SEL_USB | R92S_HCI_SEL_8172; 2126 dmem->nendpoints = sc->npipes; 2127 dmem->rf_config = 0x12; /* 1T2R */ 2128 dmem->vcs_type = R92S_VCS_TYPE_AUTO; 2129 dmem->vcs_mode = R92S_VCS_MODE_RTS_CTS; 2130 dmem->bw40_en = (ic->ic_htcaps & IEEE80211_HTCAP_CBW20_40) != 0; 2131 dmem->turbo_mode = 1; 2132 /* Load DMEM section. */ 2133 error = rsu_fw_loadsection(sc, (uint8_t *)dmem, sizeof(*dmem)); 2134 if (error != 0) { 2135 printf("%s: could not load firmware section %s\n", 2136 sc->sc_dev.dv_xname, "DMEM"); 2137 goto fail; 2138 } 2139 /* Wait for load to complete. */ 2140 for (ntries = 0; ntries < 100; ntries++) { 2141 if (rsu_read_2(sc, R92S_TCR) & R92S_TCR_DMEM_CODE_DONE) 2142 break; 2143 DELAY(1000); 2144 } 2145 if (ntries == 100) { 2146 printf("%s: timeout waiting for %s transfer\n", 2147 sc->sc_dev.dv_xname, "DMEM"); 2148 error = ETIMEDOUT; 2149 goto fail; 2150 } 2151 /* Wait for firmware readiness. */ 2152 for (ntries = 0; ntries < 60; ntries++) { 2153 if (!(rsu_read_2(sc, R92S_TCR) & R92S_TCR_FWRDY)) 2154 break; 2155 DELAY(1000); 2156 } 2157 if (ntries == 60) { 2158 printf("%s: timeout waiting for firmware readiness\n", 2159 sc->sc_dev.dv_xname); 2160 error = ETIMEDOUT; 2161 goto fail; 2162 } 2163 fail: 2164 free(fw, M_DEVBUF, size); 2165 return (error); 2166 } 2167 2168 int 2169 rsu_init(struct ifnet *ifp) 2170 { 2171 struct rsu_softc *sc = ifp->if_softc; 2172 struct ieee80211com *ic = &sc->sc_ic; 2173 struct r92s_set_pwr_mode cmd; 2174 struct rsu_rx_data *data; 2175 int i, error; 2176 2177 /* Init host async commands ring. */ 2178 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2179 2180 /* Allocate Tx/Rx buffers. */ 2181 error = rsu_alloc_rx_list(sc); 2182 if (error != 0) { 2183 printf("%s: could not allocate Rx buffers\n", 2184 sc->sc_dev.dv_xname); 2185 goto fail; 2186 } 2187 error = rsu_alloc_tx_list(sc); 2188 if (error != 0) { 2189 printf("%s: could not allocate Tx buffers\n", 2190 sc->sc_dev.dv_xname); 2191 goto fail; 2192 } 2193 /* Reserve one Tx buffer for firmware commands. */ 2194 sc->fwcmd_data = TAILQ_FIRST(&sc->tx_free_list); 2195 TAILQ_REMOVE(&sc->tx_free_list, sc->fwcmd_data, next); 2196 2197 /* Power on adapter. */ 2198 if (sc->cut == 1) 2199 rsu_power_on_acut(sc); 2200 else 2201 rsu_power_on_bcut(sc); 2202 /* Load firmware. */ 2203 error = rsu_load_firmware(sc); 2204 if (error != 0) 2205 goto fail; 2206 2207 /* Enable Rx TCP checksum offload. */ 2208 rsu_write_4(sc, R92S_RCR, 2209 rsu_read_4(sc, R92S_RCR) | 0x04000000); 2210 /* Append PHY status. */ 2211 rsu_write_4(sc, R92S_RCR, 2212 rsu_read_4(sc, R92S_RCR) | 0x02000000); 2213 2214 rsu_write_4(sc, R92S_CR, 2215 rsu_read_4(sc, R92S_CR) & ~0xff000000); 2216 2217 /* Use 128 bytes pages. */ 2218 rsu_write_1(sc, 0x00b5, 2219 rsu_read_1(sc, 0x00b5) | 0x01); 2220 /* Enable USB Rx aggregation. */ 2221 rsu_write_1(sc, 0x00bd, 2222 rsu_read_1(sc, 0x00bd) | 0x80); 2223 /* Set USB Rx aggregation threshold. */ 2224 rsu_write_1(sc, 0x00d9, 0x01); 2225 /* Set USB Rx aggregation timeout (1.7ms/4). */ 2226 rsu_write_1(sc, 0xfe5b, 0x04); 2227 /* Fix USB Rx FIFO issue. */ 2228 rsu_write_1(sc, 0xfe5c, 2229 rsu_read_1(sc, 0xfe5c) | 0x80); 2230 2231 /* Set MAC address. */ 2232 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2233 rsu_write_region_1(sc, R92S_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 2234 2235 /* Queue Rx xfers (XXX C2H pipe for 11-pipe configurations?) */ 2236 for (i = 0; i < RSU_RX_LIST_COUNT; i++) { 2237 data = &sc->rx_data[i]; 2238 2239 data->pipe = sc->pipe[sc->qid2idx[RSU_QID_RXOFF]]; 2240 usbd_setup_xfer(data->xfer, data->pipe, data, data->buf, 2241 RSU_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2242 USBD_NO_TIMEOUT, rsu_rxeof); 2243 error = usbd_transfer(data->xfer); 2244 if (error != 0 && error != USBD_IN_PROGRESS) 2245 goto fail; 2246 } 2247 2248 /* NB: it really takes that long for firmware to boot. */ 2249 usbd_delay_ms(sc->sc_udev, 1500); 2250 2251 DPRINTF(("setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 2252 error = rsu_fw_cmd(sc, R92S_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2253 IEEE80211_ADDR_LEN); 2254 if (error != 0) { 2255 printf("%s: could not set MAC address\n", sc->sc_dev.dv_xname); 2256 goto fail; 2257 } 2258 2259 rsu_write_1(sc, R92S_USB_HRPWM, 2260 R92S_USB_HRPWM_PS_ST_ACTIVE | R92S_USB_HRPWM_PS_ALL_ON); 2261 2262 memset(&cmd, 0, sizeof(cmd)); 2263 cmd.mode = R92S_PS_MODE_ACTIVE; 2264 DPRINTF(("setting ps mode to %d\n", cmd.mode)); 2265 error = rsu_fw_cmd(sc, R92S_CMD_SET_PWR_MODE, &cmd, sizeof(cmd)); 2266 if (error != 0) { 2267 printf("%s: could not set PS mode\n", sc->sc_dev.dv_xname); 2268 goto fail; 2269 } 2270 2271 if (ic->ic_htcaps & IEEE80211_HTCAP_CBW20_40) { 2272 /* Enable 40MHz mode. */ 2273 error = rsu_fw_iocmd(sc, 2274 SM(R92S_IOCMD_CLASS, 0xf4) | 2275 SM(R92S_IOCMD_INDEX, 0x00) | 2276 SM(R92S_IOCMD_VALUE, 0x0007)); 2277 if (error != 0) { 2278 printf("%s: could not enable 40MHz mode\n", 2279 sc->sc_dev.dv_xname); 2280 goto fail; 2281 } 2282 } 2283 2284 /* Set default channel. */ 2285 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2286 2287 /* We're ready to go. */ 2288 ifp->if_flags |= IFF_RUNNING; 2289 ifq_clr_oactive(&ifp->if_snd); 2290 2291 #ifdef notyet 2292 if (ic->ic_flags & IEEE80211_F_WEPON) { 2293 /* Install WEP keys. */ 2294 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2295 rsu_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2296 rsu_wait_async(sc); 2297 } 2298 #endif 2299 2300 sc->scan_pass = 0; 2301 ieee80211_begin_scan(ifp); 2302 return (0); 2303 fail: 2304 rsu_stop(ifp); 2305 return (error); 2306 } 2307 2308 void 2309 rsu_stop(struct ifnet *ifp) 2310 { 2311 struct rsu_softc *sc = ifp->if_softc; 2312 struct ieee80211com *ic = &sc->sc_ic; 2313 int i, s; 2314 2315 sc->sc_tx_timer = 0; 2316 ifp->if_timer = 0; 2317 ifp->if_flags &= ~IFF_RUNNING; 2318 ifq_clr_oactive(&ifp->if_snd); 2319 2320 s = splusb(); 2321 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2322 /* Wait for all async commands to complete. */ 2323 rsu_wait_async(sc); 2324 splx(s); 2325 2326 timeout_del(&sc->calib_to); 2327 2328 /* Power off adapter. */ 2329 rsu_power_off(sc); 2330 2331 /* Abort Tx/Rx. */ 2332 for (i = 0; i < sc->npipes; i++) 2333 usbd_abort_pipe(sc->pipe[i]); 2334 2335 /* Free Tx/Rx buffers. */ 2336 rsu_free_tx_list(sc); 2337 rsu_free_rx_list(sc); 2338 } 2339