1 /* $OpenBSD: if_otus.c,v 1.42 2014/07/13 15:52:49 mpi Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for Atheros AR9001U chipset. 21 */ 22 23 #include "bpfilter.h" 24 25 #include <sys/param.h> 26 #include <sys/sockio.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/timeout.h> 32 #include <sys/conf.h> 33 #include <sys/device.h> 34 35 #include <machine/bus.h> 36 #include <machine/endian.h> 37 #include <machine/intr.h> 38 39 #if NBPFILTER > 0 40 #include <net/bpf.h> 41 #endif 42 #include <net/if.h> 43 #include <net/if_arp.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 #include <net/if_types.h> 47 48 #include <netinet/in.h> 49 #include <netinet/if_ether.h> 50 51 #include <net80211/ieee80211_var.h> 52 #include <net80211/ieee80211_amrr.h> 53 #include <net80211/ieee80211_radiotap.h> 54 55 #include <dev/usb/usb.h> 56 #include <dev/usb/usbdi.h> 57 #include <dev/usb/usbdi_util.h> 58 #include <dev/usb/usbdevs.h> 59 60 #include <dev/usb/if_otusreg.h> 61 62 #ifdef OTUS_DEBUG 63 #define DPRINTF(x) do { if (otus_debug) printf x; } while (0) 64 #define DPRINTFN(n, x) do { if (otus_debug >= (n)) printf x; } while (0) 65 int otus_debug = 1; 66 #else 67 #define DPRINTF(x) 68 #define DPRINTFN(n, x) 69 #endif 70 71 static const struct usb_devno otus_devs[] = { 72 { USB_VENDOR_ACCTON, USB_PRODUCT_ACCTON_WN7512 }, 73 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_3CRUSBN275 }, 74 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_TG121N }, 75 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_AR9170 }, 76 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN612 }, 77 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN821NV2 }, 78 { USB_VENDOR_AVM, USB_PRODUCT_AVM_FRITZWLAN }, 79 { USB_VENDOR_CACE, USB_PRODUCT_CACE_AIRPCAPNX }, 80 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA130D1 }, 81 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A1 }, 82 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A2 }, 83 { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_WNGDNUS2 }, 84 { USB_VENDOR_NEC, USB_PRODUCT_NEC_WL300NUG }, 85 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WN111V2 }, 86 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000 }, 87 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNDA3100 }, 88 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_GW_US300 }, 89 { USB_VENDOR_WISTRONNEWEB, USB_PRODUCT_WISTRONNEWEB_O8494 }, 90 { USB_VENDOR_WISTRONNEWEB, USB_PRODUCT_WISTRONNEWEB_WNC0600 }, 91 { USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB81 }, 92 { USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB82 }, 93 { USB_VENDOR_ZYDAS, USB_PRODUCT_ZYDAS_ZD1221 }, 94 { USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_NWD271N } 95 }; 96 97 int otus_match(struct device *, void *, void *); 98 void otus_attach(struct device *, struct device *, void *); 99 int otus_detach(struct device *, int); 100 void otus_attachhook(void *); 101 void otus_get_chanlist(struct otus_softc *); 102 int otus_load_firmware(struct otus_softc *, const char *, 103 uint32_t); 104 int otus_open_pipes(struct otus_softc *); 105 void otus_close_pipes(struct otus_softc *); 106 int otus_alloc_tx_cmd(struct otus_softc *); 107 void otus_free_tx_cmd(struct otus_softc *); 108 int otus_alloc_tx_data_list(struct otus_softc *); 109 void otus_free_tx_data_list(struct otus_softc *); 110 int otus_alloc_rx_data_list(struct otus_softc *); 111 void otus_free_rx_data_list(struct otus_softc *); 112 void otus_next_scan(void *); 113 void otus_task(void *); 114 void otus_do_async(struct otus_softc *, 115 void (*)(struct otus_softc *, void *), void *, int); 116 int otus_newstate(struct ieee80211com *, enum ieee80211_state, 117 int); 118 void otus_newstate_cb(struct otus_softc *, void *); 119 int otus_cmd(struct otus_softc *, uint8_t, const void *, int, 120 void *); 121 void otus_write(struct otus_softc *, uint32_t, uint32_t); 122 int otus_write_barrier(struct otus_softc *); 123 struct ieee80211_node *otus_node_alloc(struct ieee80211com *); 124 int otus_media_change(struct ifnet *); 125 int otus_read_eeprom(struct otus_softc *); 126 void otus_newassoc(struct ieee80211com *, struct ieee80211_node *, 127 int); 128 void otus_intr(struct usbd_xfer *, void *, usbd_status); 129 void otus_cmd_rxeof(struct otus_softc *, uint8_t *, int); 130 void otus_sub_rxeof(struct otus_softc *, uint8_t *, int); 131 void otus_rxeof(struct usbd_xfer *, void *, usbd_status); 132 void otus_txeof(struct usbd_xfer *, void *, usbd_status); 133 int otus_tx(struct otus_softc *, struct mbuf *, 134 struct ieee80211_node *); 135 void otus_start(struct ifnet *); 136 void otus_watchdog(struct ifnet *); 137 int otus_ioctl(struct ifnet *, u_long, caddr_t); 138 int otus_set_multi(struct otus_softc *); 139 void otus_updateedca(struct ieee80211com *); 140 void otus_updateedca_cb(struct otus_softc *, void *); 141 void otus_updateslot(struct ieee80211com *); 142 void otus_updateslot_cb(struct otus_softc *, void *); 143 int otus_init_mac(struct otus_softc *); 144 uint32_t otus_phy_get_def(struct otus_softc *, uint32_t); 145 int otus_set_board_values(struct otus_softc *, 146 struct ieee80211_channel *); 147 int otus_program_phy(struct otus_softc *, 148 struct ieee80211_channel *); 149 int otus_set_rf_bank4(struct otus_softc *, 150 struct ieee80211_channel *); 151 void otus_get_delta_slope(uint32_t, uint32_t *, uint32_t *); 152 int otus_set_chan(struct otus_softc *, struct ieee80211_channel *, 153 int); 154 int otus_set_key(struct ieee80211com *, struct ieee80211_node *, 155 struct ieee80211_key *); 156 void otus_set_key_cb(struct otus_softc *, void *); 157 void otus_delete_key(struct ieee80211com *, struct ieee80211_node *, 158 struct ieee80211_key *); 159 void otus_delete_key_cb(struct otus_softc *, void *); 160 void otus_calibrate_to(void *); 161 int otus_set_bssid(struct otus_softc *, const uint8_t *); 162 int otus_set_macaddr(struct otus_softc *, const uint8_t *); 163 void otus_led_newstate_type1(struct otus_softc *); 164 void otus_led_newstate_type2(struct otus_softc *); 165 void otus_led_newstate_type3(struct otus_softc *); 166 int otus_init(struct ifnet *); 167 void otus_stop(struct ifnet *); 168 169 struct cfdriver otus_cd = { 170 NULL, "otus", DV_IFNET 171 }; 172 173 const struct cfattach otus_ca = { 174 sizeof (struct otus_softc), otus_match, otus_attach, otus_detach 175 }; 176 177 int 178 otus_match(struct device *parent, void *match, void *aux) 179 { 180 struct usb_attach_arg *uaa = aux; 181 182 if (uaa->iface != NULL) 183 return UMATCH_NONE; 184 185 return (usb_lookup(otus_devs, uaa->vendor, uaa->product) != NULL) ? 186 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 187 } 188 189 void 190 otus_attach(struct device *parent, struct device *self, void *aux) 191 { 192 struct otus_softc *sc = (struct otus_softc *)self; 193 struct usb_attach_arg *uaa = aux; 194 int error; 195 196 sc->sc_udev = uaa->device; 197 198 usb_init_task(&sc->sc_task, otus_task, sc, USB_TASK_TYPE_GENERIC); 199 timeout_set(&sc->scan_to, otus_next_scan, sc); 200 timeout_set(&sc->calib_to, otus_calibrate_to, sc); 201 202 sc->amrr.amrr_min_success_threshold = 1; 203 sc->amrr.amrr_max_success_threshold = 10; 204 205 if (usbd_set_config_no(sc->sc_udev, 1, 0) != 0) { 206 printf("%s: could not set configuration no\n", 207 sc->sc_dev.dv_xname); 208 return; 209 } 210 211 /* Get the first interface handle. */ 212 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 213 if (error != 0) { 214 printf("%s: could not get interface handle\n", 215 sc->sc_dev.dv_xname); 216 return; 217 } 218 219 if ((error = otus_open_pipes(sc)) != 0) { 220 printf("%s: could not open pipes\n", sc->sc_dev.dv_xname); 221 return; 222 } 223 224 if (rootvp == NULL) 225 mountroothook_establish(otus_attachhook, sc); 226 else 227 otus_attachhook(sc); 228 } 229 230 int 231 otus_detach(struct device *self, int flags) 232 { 233 struct otus_softc *sc = (struct otus_softc *)self; 234 struct ifnet *ifp = &sc->sc_ic.ic_if; 235 int s; 236 237 s = splusb(); 238 239 if (timeout_initialized(&sc->scan_to)) 240 timeout_del(&sc->scan_to); 241 if (timeout_initialized(&sc->calib_to)) 242 timeout_del(&sc->calib_to); 243 244 /* Wait for all queued asynchronous commands to complete. */ 245 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 246 247 usbd_ref_wait(sc->sc_udev); 248 249 if (ifp->if_softc != NULL) { 250 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 251 ieee80211_ifdetach(ifp); 252 if_detach(ifp); 253 } 254 255 otus_close_pipes(sc); 256 257 splx(s); 258 259 return 0; 260 } 261 262 void 263 otus_attachhook(void *xsc) 264 { 265 struct otus_softc *sc = xsc; 266 struct ieee80211com *ic = &sc->sc_ic; 267 struct ifnet *ifp = &ic->ic_if; 268 usb_device_request_t req; 269 uint32_t in, out; 270 int error; 271 272 error = otus_load_firmware(sc, "otus-init", AR_FW_INIT_ADDR); 273 if (error != 0) { 274 printf("%s: could not load %s firmware\n", 275 sc->sc_dev.dv_xname, "init"); 276 return; 277 } 278 279 usbd_delay_ms(sc->sc_udev, 1000); 280 281 error = otus_load_firmware(sc, "otus-main", AR_FW_MAIN_ADDR); 282 if (error != 0) { 283 printf("%s: could not load %s firmware\n", 284 sc->sc_dev.dv_xname, "main"); 285 return; 286 } 287 288 /* Tell device that firmware transfer is complete. */ 289 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 290 req.bRequest = AR_FW_DOWNLOAD_COMPLETE; 291 USETW(req.wValue, 0); 292 USETW(req.wIndex, 0); 293 USETW(req.wLength, 0); 294 if (usbd_do_request(sc->sc_udev, &req, NULL) != 0) { 295 printf("%s: firmware initialization failed\n", 296 sc->sc_dev.dv_xname); 297 return; 298 } 299 300 /* Send an ECHO command to check that everything is settled. */ 301 in = 0xbadc0ffe; 302 if (otus_cmd(sc, AR_CMD_ECHO, &in, sizeof in, &out) != 0) { 303 printf("%s: echo command failed\n", sc->sc_dev.dv_xname); 304 return; 305 } 306 if (in != out) { 307 printf("%s: echo reply mismatch: 0x%08x!=0x%08x\n", 308 sc->sc_dev.dv_xname, in, out); 309 return; 310 } 311 312 /* Read entire EEPROM. */ 313 if (otus_read_eeprom(sc) != 0) { 314 printf("%s: could not read EEPROM\n", sc->sc_dev.dv_xname); 315 return; 316 } 317 318 sc->txmask = sc->eeprom.baseEepHeader.txMask; 319 sc->rxmask = sc->eeprom.baseEepHeader.rxMask; 320 sc->capflags = sc->eeprom.baseEepHeader.opCapFlags; 321 IEEE80211_ADDR_COPY(ic->ic_myaddr, sc->eeprom.baseEepHeader.macAddr); 322 sc->sc_led_newstate = otus_led_newstate_type3; /* XXX */ 323 324 printf("%s: MAC/BBP AR9170, RF AR%X, MIMO %dT%dR, address %s\n", 325 sc->sc_dev.dv_xname, (sc->capflags & AR5416_OPFLAGS_11A) ? 326 0x9104 : ((sc->txmask == 0x5) ? 0x9102 : 0x9101), 327 (sc->txmask == 0x5) ? 2 : 1, (sc->rxmask == 0x5) ? 2 : 1, 328 ether_sprintf(ic->ic_myaddr)); 329 330 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 331 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 332 ic->ic_state = IEEE80211_S_INIT; 333 334 /* Set device capabilities. */ 335 ic->ic_caps = 336 IEEE80211_C_MONITOR | /* monitor mode supported */ 337 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 338 IEEE80211_C_SHSLOT | /* short slot time supported */ 339 IEEE80211_C_WEP | /* WEP */ 340 IEEE80211_C_RSN; /* WPA/RSN */ 341 342 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { 343 /* Set supported .11b and .11g rates. */ 344 ic->ic_sup_rates[IEEE80211_MODE_11B] = 345 ieee80211_std_rateset_11b; 346 ic->ic_sup_rates[IEEE80211_MODE_11G] = 347 ieee80211_std_rateset_11g; 348 } 349 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { 350 /* Set supported .11a rates. */ 351 ic->ic_sup_rates[IEEE80211_MODE_11A] = 352 ieee80211_std_rateset_11a; 353 } 354 355 /* Build the list of supported channels. */ 356 otus_get_chanlist(sc); 357 358 ifp->if_softc = sc; 359 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 360 ifp->if_ioctl = otus_ioctl; 361 ifp->if_start = otus_start; 362 ifp->if_watchdog = otus_watchdog; 363 IFQ_SET_READY(&ifp->if_snd); 364 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 365 366 if_attach(ifp); 367 ieee80211_ifattach(ifp); 368 ic->ic_node_alloc = otus_node_alloc; 369 ic->ic_newassoc = otus_newassoc; 370 ic->ic_updateslot = otus_updateslot; 371 ic->ic_updateedca = otus_updateedca; 372 #ifdef notyet 373 ic->ic_set_key = otus_set_key; 374 ic->ic_delete_key = otus_delete_key; 375 #endif 376 /* Override state transition machine. */ 377 sc->sc_newstate = ic->ic_newstate; 378 ic->ic_newstate = otus_newstate; 379 ieee80211_media_init(ifp, otus_media_change, ieee80211_media_status); 380 381 #if NBPFILTER > 0 382 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 383 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 384 385 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 386 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 387 sc->sc_rxtap.wr_ihdr.it_present = htole32(OTUS_RX_RADIOTAP_PRESENT); 388 389 sc->sc_txtap_len = sizeof sc->sc_txtapu; 390 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 391 sc->sc_txtap.wt_ihdr.it_present = htole32(OTUS_TX_RADIOTAP_PRESENT); 392 #endif 393 } 394 395 void 396 otus_get_chanlist(struct otus_softc *sc) 397 { 398 struct ieee80211com *ic = &sc->sc_ic; 399 uint16_t domain; 400 uint8_t chan; 401 int i; 402 403 /* XXX regulatory domain. */ 404 domain = letoh16(sc->eeprom.baseEepHeader.regDmn[0]); 405 DPRINTF(("regdomain=0x%04x\n", domain)); 406 407 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { 408 for (i = 0; i < 14; i++) { 409 chan = ar_chans[i]; 410 ic->ic_channels[chan].ic_freq = 411 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 412 ic->ic_channels[chan].ic_flags = 413 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 414 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 415 } 416 } 417 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { 418 for (i = 14; i < nitems(ar_chans); i++) { 419 chan = ar_chans[i]; 420 ic->ic_channels[chan].ic_freq = 421 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 422 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 423 } 424 } 425 } 426 427 int 428 otus_load_firmware(struct otus_softc *sc, const char *name, uint32_t addr) 429 { 430 usb_device_request_t req; 431 size_t size; 432 u_char *fw, *ptr; 433 int mlen, error; 434 435 /* Read firmware image from the filesystem. */ 436 if ((error = loadfirmware(name, &fw, &size)) != 0) { 437 printf("%s: failed loadfirmware of file %s (error %d)\n", 438 sc->sc_dev.dv_xname, name, error); 439 return error; 440 } 441 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 442 req.bRequest = AR_FW_DOWNLOAD; 443 USETW(req.wIndex, 0); 444 445 ptr = fw; 446 addr >>= 8; 447 while (size > 0) { 448 mlen = MIN(size, 4096); 449 450 USETW(req.wValue, addr); 451 USETW(req.wLength, mlen); 452 if (usbd_do_request(sc->sc_udev, &req, ptr) != 0) { 453 error = EIO; 454 break; 455 } 456 addr += mlen >> 8; 457 ptr += mlen; 458 size -= mlen; 459 } 460 free(fw, M_DEVBUF, 0); 461 return error; 462 } 463 464 int 465 otus_open_pipes(struct otus_softc *sc) 466 { 467 usb_endpoint_descriptor_t *ed; 468 int i, isize, error; 469 470 error = usbd_open_pipe(sc->sc_iface, AR_EPT_BULK_RX_NO, 0, 471 &sc->data_rx_pipe); 472 if (error != 0) { 473 printf("%s: could not open Rx bulk pipe\n", 474 sc->sc_dev.dv_xname); 475 goto fail; 476 } 477 478 ed = usbd_get_endpoint_descriptor(sc->sc_iface, AR_EPT_INTR_RX_NO); 479 if (ed == NULL) { 480 printf("%s: could not retrieve Rx intr pipe descriptor\n", 481 sc->sc_dev.dv_xname); 482 goto fail; 483 } 484 isize = UGETW(ed->wMaxPacketSize); 485 if (isize == 0) { 486 printf("%s: invalid Rx intr pipe descriptor\n", 487 sc->sc_dev.dv_xname); 488 goto fail; 489 } 490 sc->ibuf = malloc(isize, M_USBDEV, M_NOWAIT); 491 if (sc->ibuf == NULL) { 492 printf("%s: could not allocate Rx intr buffer\n", 493 sc->sc_dev.dv_xname); 494 goto fail; 495 } 496 error = usbd_open_pipe_intr(sc->sc_iface, AR_EPT_INTR_RX_NO, 497 USBD_SHORT_XFER_OK, &sc->cmd_rx_pipe, sc, sc->ibuf, isize, 498 otus_intr, USBD_DEFAULT_INTERVAL); 499 if (error != 0) { 500 printf("%s: could not open Rx intr pipe\n", 501 sc->sc_dev.dv_xname); 502 goto fail; 503 } 504 505 error = usbd_open_pipe(sc->sc_iface, AR_EPT_BULK_TX_NO, 0, 506 &sc->data_tx_pipe); 507 if (error != 0) { 508 printf("%s: could not open Tx bulk pipe\n", 509 sc->sc_dev.dv_xname); 510 goto fail; 511 } 512 513 error = usbd_open_pipe(sc->sc_iface, AR_EPT_INTR_TX_NO, 0, 514 &sc->cmd_tx_pipe); 515 if (error != 0) { 516 printf("%s: could not open Tx intr pipe\n", 517 sc->sc_dev.dv_xname); 518 goto fail; 519 } 520 521 if (otus_alloc_tx_cmd(sc) != 0) { 522 printf("%s: could not allocate command xfer\n", 523 sc->sc_dev.dv_xname); 524 goto fail; 525 } 526 527 if (otus_alloc_tx_data_list(sc) != 0) { 528 printf("%s: could not allocate Tx xfers\n", 529 sc->sc_dev.dv_xname); 530 goto fail; 531 } 532 533 if (otus_alloc_rx_data_list(sc) != 0) { 534 printf("%s: could not allocate Rx xfers\n", 535 sc->sc_dev.dv_xname); 536 goto fail; 537 } 538 539 for (i = 0; i < OTUS_RX_DATA_LIST_COUNT; i++) { 540 struct otus_rx_data *data = &sc->rx_data[i]; 541 542 usbd_setup_xfer(data->xfer, sc->data_rx_pipe, data, data->buf, 543 OTUS_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 544 USBD_NO_TIMEOUT, otus_rxeof); 545 error = usbd_transfer(data->xfer); 546 if (error != USBD_IN_PROGRESS && error != 0) { 547 printf("%s: could not queue Rx xfer\n", 548 sc->sc_dev.dv_xname); 549 goto fail; 550 } 551 } 552 return 0; 553 554 fail: otus_close_pipes(sc); 555 return error; 556 } 557 558 void 559 otus_close_pipes(struct otus_softc *sc) 560 { 561 otus_free_tx_cmd(sc); 562 otus_free_tx_data_list(sc); 563 otus_free_rx_data_list(sc); 564 565 if (sc->data_rx_pipe != NULL) 566 usbd_close_pipe(sc->data_rx_pipe); 567 if (sc->cmd_rx_pipe != NULL) { 568 usbd_abort_pipe(sc->cmd_rx_pipe); 569 usbd_close_pipe(sc->cmd_rx_pipe); 570 } 571 if (sc->ibuf != NULL) 572 free(sc->ibuf, M_USBDEV, 0); 573 if (sc->data_tx_pipe != NULL) 574 usbd_close_pipe(sc->data_tx_pipe); 575 if (sc->cmd_tx_pipe != NULL) 576 usbd_close_pipe(sc->cmd_tx_pipe); 577 } 578 579 int 580 otus_alloc_tx_cmd(struct otus_softc *sc) 581 { 582 struct otus_tx_cmd *cmd = &sc->tx_cmd; 583 584 cmd->xfer = usbd_alloc_xfer(sc->sc_udev); 585 if (cmd->xfer == NULL) { 586 printf("%s: could not allocate xfer\n", 587 sc->sc_dev.dv_xname); 588 return ENOMEM; 589 } 590 cmd->buf = usbd_alloc_buffer(cmd->xfer, OTUS_MAX_TXCMDSZ); 591 if (cmd->buf == NULL) { 592 printf("%s: could not allocate xfer buffer\n", 593 sc->sc_dev.dv_xname); 594 usbd_free_xfer(cmd->xfer); 595 return ENOMEM; 596 } 597 return 0; 598 } 599 600 void 601 otus_free_tx_cmd(struct otus_softc *sc) 602 { 603 /* Make sure no transfers are pending. */ 604 usbd_abort_pipe(sc->cmd_tx_pipe); 605 606 if (sc->tx_cmd.xfer != NULL) 607 usbd_free_xfer(sc->tx_cmd.xfer); 608 } 609 610 int 611 otus_alloc_tx_data_list(struct otus_softc *sc) 612 { 613 struct otus_tx_data *data; 614 int i, error; 615 616 for (i = 0; i < OTUS_TX_DATA_LIST_COUNT; i++) { 617 data = &sc->tx_data[i]; 618 619 data->sc = sc; /* Backpointer for callbacks. */ 620 621 data->xfer = usbd_alloc_xfer(sc->sc_udev); 622 if (data->xfer == NULL) { 623 printf("%s: could not allocate xfer\n", 624 sc->sc_dev.dv_xname); 625 error = ENOMEM; 626 goto fail; 627 } 628 data->buf = usbd_alloc_buffer(data->xfer, OTUS_TXBUFSZ); 629 if (data->buf == NULL) { 630 printf("%s: could not allocate xfer buffer\n", 631 sc->sc_dev.dv_xname); 632 error = ENOMEM; 633 goto fail; 634 } 635 } 636 return 0; 637 638 fail: otus_free_tx_data_list(sc); 639 return error; 640 } 641 642 void 643 otus_free_tx_data_list(struct otus_softc *sc) 644 { 645 int i; 646 647 /* Make sure no transfers are pending. */ 648 usbd_abort_pipe(sc->data_tx_pipe); 649 650 for (i = 0; i < OTUS_TX_DATA_LIST_COUNT; i++) 651 if (sc->tx_data[i].xfer != NULL) 652 usbd_free_xfer(sc->tx_data[i].xfer); 653 } 654 655 int 656 otus_alloc_rx_data_list(struct otus_softc *sc) 657 { 658 struct otus_rx_data *data; 659 int i, error; 660 661 for (i = 0; i < OTUS_RX_DATA_LIST_COUNT; i++) { 662 data = &sc->rx_data[i]; 663 664 data->sc = sc; /* Backpointer for callbacks. */ 665 666 data->xfer = usbd_alloc_xfer(sc->sc_udev); 667 if (data->xfer == NULL) { 668 printf("%s: could not allocate xfer\n", 669 sc->sc_dev.dv_xname); 670 error = ENOMEM; 671 goto fail; 672 } 673 data->buf = usbd_alloc_buffer(data->xfer, OTUS_RXBUFSZ); 674 if (data->buf == NULL) { 675 printf("%s: could not allocate xfer buffer\n", 676 sc->sc_dev.dv_xname); 677 error = ENOMEM; 678 goto fail; 679 } 680 } 681 return 0; 682 683 fail: otus_free_rx_data_list(sc); 684 return error; 685 } 686 687 void 688 otus_free_rx_data_list(struct otus_softc *sc) 689 { 690 int i; 691 692 /* Make sure no transfers are pending. */ 693 usbd_abort_pipe(sc->data_rx_pipe); 694 695 for (i = 0; i < OTUS_RX_DATA_LIST_COUNT; i++) 696 if (sc->rx_data[i].xfer != NULL) 697 usbd_free_xfer(sc->rx_data[i].xfer); 698 } 699 700 void 701 otus_next_scan(void *arg) 702 { 703 struct otus_softc *sc = arg; 704 705 if (usbd_is_dying(sc->sc_udev)) 706 return; 707 708 usbd_ref_incr(sc->sc_udev); 709 710 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 711 ieee80211_next_scan(&sc->sc_ic.ic_if); 712 713 usbd_ref_decr(sc->sc_udev); 714 } 715 716 void 717 otus_task(void *arg) 718 { 719 struct otus_softc *sc = arg; 720 struct otus_host_cmd_ring *ring = &sc->cmdq; 721 struct otus_host_cmd *cmd; 722 int s; 723 724 /* Process host commands. */ 725 s = splusb(); 726 while (ring->next != ring->cur) { 727 cmd = &ring->cmd[ring->next]; 728 splx(s); 729 /* Callback. */ 730 cmd->cb(sc, cmd->data); 731 s = splusb(); 732 ring->queued--; 733 ring->next = (ring->next + 1) % OTUS_HOST_CMD_RING_COUNT; 734 } 735 splx(s); 736 } 737 738 void 739 otus_do_async(struct otus_softc *sc, void (*cb)(struct otus_softc *, void *), 740 void *arg, int len) 741 { 742 struct otus_host_cmd_ring *ring = &sc->cmdq; 743 struct otus_host_cmd *cmd; 744 int s; 745 746 s = splusb(); 747 cmd = &ring->cmd[ring->cur]; 748 cmd->cb = cb; 749 KASSERT(len <= sizeof (cmd->data)); 750 memcpy(cmd->data, arg, len); 751 ring->cur = (ring->cur + 1) % OTUS_HOST_CMD_RING_COUNT; 752 753 /* If there is no pending command already, schedule a task. */ 754 if (++ring->queued == 1) 755 usb_add_task(sc->sc_udev, &sc->sc_task); 756 splx(s); 757 } 758 759 int 760 otus_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 761 { 762 struct otus_softc *sc = ic->ic_softc; 763 struct otus_cmd_newstate cmd; 764 765 /* Do it in a process context. */ 766 cmd.state = nstate; 767 cmd.arg = arg; 768 otus_do_async(sc, otus_newstate_cb, &cmd, sizeof cmd); 769 return 0; 770 } 771 772 void 773 otus_newstate_cb(struct otus_softc *sc, void *arg) 774 { 775 struct otus_cmd_newstate *cmd = arg; 776 struct ieee80211com *ic = &sc->sc_ic; 777 struct ieee80211_node *ni; 778 int s; 779 780 s = splnet(); 781 782 switch (cmd->state) { 783 case IEEE80211_S_INIT: 784 break; 785 786 case IEEE80211_S_SCAN: 787 (void)otus_set_chan(sc, ic->ic_bss->ni_chan, 0); 788 if (!usbd_is_dying(sc->sc_udev)) 789 timeout_add_msec(&sc->scan_to, 200); 790 break; 791 792 case IEEE80211_S_AUTH: 793 case IEEE80211_S_ASSOC: 794 (void)otus_set_chan(sc, ic->ic_bss->ni_chan, 0); 795 break; 796 797 case IEEE80211_S_RUN: 798 (void)otus_set_chan(sc, ic->ic_bss->ni_chan, 1); 799 800 ni = ic->ic_bss; 801 802 if (ic->ic_opmode == IEEE80211_M_STA) { 803 otus_updateslot(ic); 804 otus_set_bssid(sc, ni->ni_bssid); 805 806 /* Fake a join to init the Tx rate. */ 807 otus_newassoc(ic, ni, 1); 808 809 /* Start calibration timer. */ 810 if (!usbd_is_dying(sc->sc_udev)) 811 timeout_add_sec(&sc->calib_to, 1); 812 } 813 break; 814 } 815 816 sc->sc_led_newstate(sc); 817 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 818 819 splx(s); 820 } 821 822 int 823 otus_cmd(struct otus_softc *sc, uint8_t code, const void *idata, int ilen, 824 void *odata) 825 { 826 struct otus_tx_cmd *cmd = &sc->tx_cmd; 827 struct ar_cmd_hdr *hdr; 828 int s, xferlen, error; 829 830 /* Always bulk-out a multiple of 4 bytes. */ 831 xferlen = (sizeof (*hdr) + ilen + 3) & ~3; 832 833 hdr = (struct ar_cmd_hdr *)cmd->buf; 834 hdr->code = code; 835 hdr->len = ilen; 836 hdr->token = ++cmd->token; /* Don't care about endianness. */ 837 memcpy((uint8_t *)&hdr[1], idata, ilen); 838 839 DPRINTFN(2, ("sending command code=0x%02x len=%d token=%d\n", 840 code, ilen, hdr->token)); 841 842 s = splusb(); 843 cmd->odata = odata; 844 cmd->done = 0; 845 846 usbd_setup_xfer(cmd->xfer, sc->cmd_tx_pipe, cmd, cmd->buf, xferlen, 847 USBD_FORCE_SHORT_XFER | USBD_NO_COPY | USBD_SYNCHRONOUS, 848 OTUS_CMD_TIMEOUT, NULL); 849 error = usbd_transfer(cmd->xfer); 850 if (error != 0) { 851 splx(s); 852 printf("%s: could not send command 0x%x (error=%s)\n", 853 sc->sc_dev.dv_xname, code, usbd_errstr(error)); 854 return EIO; 855 } 856 if (!cmd->done) 857 error = tsleep(cmd, PCATCH, "otuscmd", hz); 858 cmd->odata = NULL; /* In case answer is received too late. */ 859 splx(s); 860 if (error != 0) { 861 printf("%s: timeout waiting for command 0x%02x reply\n", 862 sc->sc_dev.dv_xname, code); 863 } 864 return error; 865 } 866 867 void 868 otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val) 869 { 870 sc->write_buf[sc->write_idx].reg = htole32(reg); 871 sc->write_buf[sc->write_idx].val = htole32(val); 872 873 if (++sc->write_idx > AR_MAX_WRITE_IDX) 874 (void)otus_write_barrier(sc); 875 } 876 877 int 878 otus_write_barrier(struct otus_softc *sc) 879 { 880 int error; 881 882 if (sc->write_idx == 0) 883 return 0; /* Nothing to flush. */ 884 885 error = otus_cmd(sc, AR_CMD_WREG, sc->write_buf, 886 sizeof (sc->write_buf[0]) * sc->write_idx, NULL); 887 sc->write_idx = 0; 888 return error; 889 } 890 891 struct ieee80211_node * 892 otus_node_alloc(struct ieee80211com *ic) 893 { 894 return malloc(sizeof (struct otus_node), M_DEVBUF, M_NOWAIT | M_ZERO); 895 } 896 897 int 898 otus_media_change(struct ifnet *ifp) 899 { 900 struct otus_softc *sc = ifp->if_softc; 901 struct ieee80211com *ic = &sc->sc_ic; 902 uint8_t rate, ridx; 903 int error; 904 905 error = ieee80211_media_change(ifp); 906 if (error != ENETRESET) 907 return error; 908 909 if (ic->ic_fixed_rate != -1) { 910 rate = ic->ic_sup_rates[ic->ic_curmode]. 911 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 912 for (ridx = 0; ridx <= OTUS_RIDX_MAX; ridx++) 913 if (otus_rates[ridx].rate == rate) 914 break; 915 sc->fixed_ridx = ridx; 916 } 917 918 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 919 error = otus_init(ifp); 920 921 return error; 922 } 923 924 int 925 otus_read_eeprom(struct otus_softc *sc) 926 { 927 uint32_t regs[8], reg; 928 uint8_t *eep; 929 int i, j, error; 930 931 /* Read EEPROM by blocks of 32 bytes. */ 932 eep = (uint8_t *)&sc->eeprom; 933 reg = AR_EEPROM_OFFSET; 934 for (i = 0; i < sizeof (sc->eeprom) / 32; i++) { 935 for (j = 0; j < 8; j++, reg += 4) 936 regs[j] = htole32(reg); 937 error = otus_cmd(sc, AR_CMD_RREG, regs, sizeof regs, eep); 938 if (error != 0) 939 break; 940 eep += 32; 941 } 942 return error; 943 } 944 945 void 946 otus_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 947 { 948 struct otus_softc *sc = ic->ic_softc; 949 struct otus_node *on = (void *)ni; 950 struct ieee80211_rateset *rs = &ni->ni_rates; 951 uint8_t rate; 952 int ridx, i; 953 954 DPRINTF(("new assoc isnew=%d addr=%s\n", 955 isnew, ether_sprintf(ni->ni_macaddr))); 956 957 ieee80211_amrr_node_init(&sc->amrr, &on->amn); 958 /* Start at lowest available bit-rate, AMRR will raise. */ 959 ni->ni_txrate = 0; 960 961 for (i = 0; i < rs->rs_nrates; i++) { 962 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 963 /* Convert 802.11 rate to hardware rate index. */ 964 for (ridx = 0; ridx <= OTUS_RIDX_MAX; ridx++) 965 if (otus_rates[ridx].rate == rate) 966 break; 967 on->ridx[i] = ridx; 968 DPRINTF(("rate=0x%02x ridx=%d\n", 969 rs->rs_rates[i], on->ridx[i])); 970 } 971 } 972 973 /* ARGSUSED */ 974 void 975 otus_intr(struct usbd_xfer *xfer, void *priv, usbd_status status) 976 { 977 #if 0 978 struct otus_softc *sc = priv; 979 int len; 980 981 /* 982 * The Rx intr pipe is unused with current firmware. Notifications 983 * and replies to commands are sent through the Rx bulk pipe instead 984 * (with a magic PLCP header.) 985 */ 986 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 987 DPRINTF(("intr status=%d\n", status)); 988 if (status == USBD_STALLED) 989 usbd_clear_endpoint_stall_async(sc->cmd_rx_pipe); 990 return; 991 } 992 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 993 994 otus_cmd_rxeof(sc, sc->ibuf, len); 995 #endif 996 } 997 998 void 999 otus_cmd_rxeof(struct otus_softc *sc, uint8_t *buf, int len) 1000 { 1001 struct ieee80211com *ic = &sc->sc_ic; 1002 struct otus_tx_cmd *cmd; 1003 struct ar_cmd_hdr *hdr; 1004 int s; 1005 1006 if (__predict_false(len < sizeof (*hdr))) { 1007 DPRINTF(("cmd too small %d\n", len)); 1008 return; 1009 } 1010 hdr = (struct ar_cmd_hdr *)buf; 1011 if (__predict_false(sizeof (*hdr) + hdr->len > len || 1012 sizeof (*hdr) + hdr->len > 64)) { 1013 DPRINTF(("cmd too large %d\n", hdr->len)); 1014 return; 1015 } 1016 1017 if ((hdr->code & 0xc0) != 0xc0) { 1018 DPRINTFN(2, ("received reply code=0x%02x len=%d token=%d\n", 1019 hdr->code, hdr->len, hdr->token)); 1020 cmd = &sc->tx_cmd; 1021 if (__predict_false(hdr->token != cmd->token)) 1022 return; 1023 /* Copy answer into caller's supplied buffer. */ 1024 if (cmd->odata != NULL) 1025 memcpy(cmd->odata, &hdr[1], hdr->len); 1026 cmd->done = 1; 1027 wakeup(cmd); 1028 return; 1029 } 1030 1031 /* Received unsolicited notification. */ 1032 DPRINTF(("received notification code=0x%02x len=%d\n", 1033 hdr->code, hdr->len)); 1034 switch (hdr->code & 0x3f) { 1035 case AR_EVT_BEACON: 1036 break; 1037 case AR_EVT_TX_COMP: 1038 { 1039 struct ar_evt_tx_comp *tx = (struct ar_evt_tx_comp *)&hdr[1]; 1040 struct ieee80211_node *ni; 1041 struct otus_node *on; 1042 1043 DPRINTF(("tx completed %s status=%d phy=0x%x\n", 1044 ether_sprintf(tx->macaddr), letoh16(tx->status), 1045 letoh32(tx->phy))); 1046 s = splnet(); 1047 #ifdef notyet 1048 #ifndef IEEE80211_STA_ONLY 1049 if (ic->ic_opmode != IEEE80211_M_STA) { 1050 ni = ieee80211_find_node(ic, tx->macaddr); 1051 if (__predict_false(ni == NULL)) { 1052 splx(s); 1053 break; 1054 } 1055 } else 1056 #endif 1057 #endif 1058 ni = ic->ic_bss; 1059 /* Update rate control statistics. */ 1060 on = (void *)ni; 1061 /* NB: we do not set the TX_MAC_RATE_PROBING flag. */ 1062 if (__predict_true(tx->status != 0)) 1063 on->amn.amn_retrycnt++; 1064 splx(s); 1065 break; 1066 } 1067 case AR_EVT_TBTT: 1068 break; 1069 } 1070 } 1071 1072 void 1073 otus_sub_rxeof(struct otus_softc *sc, uint8_t *buf, int len) 1074 { 1075 struct ieee80211com *ic = &sc->sc_ic; 1076 struct ifnet *ifp = &ic->ic_if; 1077 struct ieee80211_rxinfo rxi; 1078 struct ieee80211_node *ni; 1079 struct ar_rx_tail *tail; 1080 struct ieee80211_frame *wh; 1081 struct mbuf *m; 1082 uint8_t *plcp; 1083 int s, mlen, align; 1084 1085 if (__predict_false(len < AR_PLCP_HDR_LEN)) { 1086 DPRINTF(("sub-xfer too short %d\n", len)); 1087 return; 1088 } 1089 plcp = buf; 1090 1091 /* All bits in the PLCP header are set to 1 for non-MPDU. */ 1092 if (memcmp(plcp, AR_PLCP_HDR_INTR, AR_PLCP_HDR_LEN) == 0) { 1093 otus_cmd_rxeof(sc, plcp + AR_PLCP_HDR_LEN, 1094 len - AR_PLCP_HDR_LEN); 1095 return; 1096 } 1097 1098 /* Received MPDU. */ 1099 if (__predict_false(len < AR_PLCP_HDR_LEN + sizeof (*tail))) { 1100 DPRINTF(("MPDU too short %d\n", len)); 1101 ifp->if_ierrors++; 1102 return; 1103 } 1104 tail = (struct ar_rx_tail *)(plcp + len - sizeof (*tail)); 1105 1106 /* Discard error frames. */ 1107 if (__predict_false(tail->error != 0)) { 1108 DPRINTF(("error frame 0x%02x\n", tail->error)); 1109 if (tail->error & AR_RX_ERROR_FCS) { 1110 DPRINTFN(3, ("bad FCS\n")); 1111 } else if (tail->error & AR_RX_ERROR_MMIC) { 1112 /* Report Michael MIC failures to net80211. */ 1113 ic->ic_stats.is_rx_locmicfail++; 1114 ieee80211_michael_mic_failure(ic, 0); 1115 } 1116 ifp->if_ierrors++; 1117 return; 1118 } 1119 /* Compute MPDU's length. */ 1120 mlen = len - AR_PLCP_HDR_LEN - sizeof (*tail); 1121 /* Make sure there's room for an 802.11 header + FCS. */ 1122 if (__predict_false(mlen < IEEE80211_MIN_LEN)) { 1123 ifp->if_ierrors++; 1124 return; 1125 } 1126 mlen -= IEEE80211_CRC_LEN; /* strip 802.11 FCS */ 1127 1128 wh = (struct ieee80211_frame *)(plcp + AR_PLCP_HDR_LEN); 1129 /* Provide a 32-bit aligned protocol header to the stack. */ 1130 align = (ieee80211_has_qos(wh) ^ ieee80211_has_addr4(wh)) ? 2 : 0; 1131 1132 MGETHDR(m, M_DONTWAIT, MT_DATA); 1133 if (__predict_false(m == NULL)) { 1134 ifp->if_ierrors++; 1135 return; 1136 } 1137 if (align + mlen > MHLEN) { 1138 MCLGET(m, M_DONTWAIT); 1139 if (__predict_false(!(m->m_flags & M_EXT))) { 1140 ifp->if_ierrors++; 1141 m_freem(m); 1142 return; 1143 } 1144 } 1145 /* Finalize mbuf. */ 1146 m->m_pkthdr.rcvif = ifp; 1147 m->m_data += align; 1148 memcpy(mtod(m, caddr_t), wh, mlen); 1149 m->m_pkthdr.len = m->m_len = mlen; 1150 1151 #if NBPFILTER > 0 1152 if (__predict_false(sc->sc_drvbpf != NULL)) { 1153 struct otus_rx_radiotap_header *tap = &sc->sc_rxtap; 1154 struct mbuf mb; 1155 1156 tap->wr_flags = 0; 1157 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1158 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1159 tap->wr_antsignal = tail->rssi; 1160 tap->wr_rate = 2; /* In case it can't be found below. */ 1161 switch (tail->status & AR_RX_STATUS_MT_MASK) { 1162 case AR_RX_STATUS_MT_CCK: 1163 switch (plcp[0]) { 1164 case 10: tap->wr_rate = 2; break; 1165 case 20: tap->wr_rate = 4; break; 1166 case 55: tap->wr_rate = 11; break; 1167 case 110: tap->wr_rate = 22; break; 1168 } 1169 if (tail->status & AR_RX_STATUS_SHPREAMBLE) 1170 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1171 break; 1172 case AR_RX_STATUS_MT_OFDM: 1173 switch (plcp[0] & 0xf) { 1174 case 0xb: tap->wr_rate = 12; break; 1175 case 0xf: tap->wr_rate = 18; break; 1176 case 0xa: tap->wr_rate = 24; break; 1177 case 0xe: tap->wr_rate = 36; break; 1178 case 0x9: tap->wr_rate = 48; break; 1179 case 0xd: tap->wr_rate = 72; break; 1180 case 0x8: tap->wr_rate = 96; break; 1181 case 0xc: tap->wr_rate = 108; break; 1182 } 1183 break; 1184 } 1185 mb.m_data = (caddr_t)tap; 1186 mb.m_len = sc->sc_rxtap_len; 1187 mb.m_next = m; 1188 mb.m_nextpkt = NULL; 1189 mb.m_type = 0; 1190 mb.m_flags = 0; 1191 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1192 } 1193 #endif 1194 1195 s = splnet(); 1196 ni = ieee80211_find_rxnode(ic, wh); 1197 rxi.rxi_flags = 0; 1198 rxi.rxi_rssi = tail->rssi; 1199 rxi.rxi_tstamp = 0; /* unused */ 1200 ieee80211_input(ifp, m, ni, &rxi); 1201 1202 /* Node is no longer needed. */ 1203 ieee80211_release_node(ic, ni); 1204 splx(s); 1205 } 1206 1207 void 1208 otus_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1209 { 1210 struct otus_rx_data *data = priv; 1211 struct otus_softc *sc = data->sc; 1212 caddr_t buf = data->buf; 1213 struct ar_rx_head *head; 1214 uint16_t hlen; 1215 int len; 1216 1217 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1218 DPRINTF(("RX status=%d\n", status)); 1219 if (status == USBD_STALLED) 1220 usbd_clear_endpoint_stall_async(sc->data_rx_pipe); 1221 if (status != USBD_CANCELLED) 1222 goto resubmit; 1223 return; 1224 } 1225 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1226 1227 while (len >= sizeof (*head)) { 1228 head = (struct ar_rx_head *)buf; 1229 if (__predict_false(head->tag != htole16(AR_RX_HEAD_TAG))) { 1230 DPRINTF(("tag not valid 0x%x\n", letoh16(head->tag))); 1231 break; 1232 } 1233 hlen = letoh16(head->len); 1234 if (__predict_false(sizeof (*head) + hlen > len)) { 1235 DPRINTF(("xfer too short %d/%d\n", len, hlen)); 1236 break; 1237 } 1238 /* Process sub-xfer. */ 1239 otus_sub_rxeof(sc, (uint8_t *)&head[1], hlen); 1240 1241 /* Next sub-xfer is aligned on a 32-bit boundary. */ 1242 hlen = (sizeof (*head) + hlen + 3) & ~3; 1243 buf += hlen; 1244 len -= hlen; 1245 } 1246 1247 resubmit: 1248 usbd_setup_xfer(xfer, sc->data_rx_pipe, data, data->buf, OTUS_RXBUFSZ, 1249 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, otus_rxeof); 1250 (void)usbd_transfer(data->xfer); 1251 } 1252 1253 void 1254 otus_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1255 { 1256 struct otus_tx_data *data = priv; 1257 struct otus_softc *sc = data->sc; 1258 struct ieee80211com *ic = &sc->sc_ic; 1259 struct ifnet *ifp = &ic->ic_if; 1260 int s; 1261 1262 s = splnet(); 1263 sc->tx_queued--; 1264 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1265 DPRINTF(("TX status=%d\n", status)); 1266 if (status == USBD_STALLED) 1267 usbd_clear_endpoint_stall_async(sc->data_tx_pipe); 1268 ifp->if_oerrors++; 1269 splx(s); 1270 return; 1271 } 1272 sc->sc_tx_timer = 0; 1273 ifp->if_opackets++; 1274 ifp->if_flags &= ~IFF_OACTIVE; 1275 otus_start(ifp); 1276 splx(s); 1277 } 1278 1279 int 1280 otus_tx(struct otus_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1281 { 1282 struct ieee80211com *ic = &sc->sc_ic; 1283 struct otus_node *on = (void *)ni; 1284 struct otus_tx_data *data; 1285 struct ieee80211_frame *wh; 1286 struct ieee80211_key *k; 1287 struct ar_tx_head *head; 1288 uint32_t phyctl; 1289 uint16_t macctl, qos; 1290 uint8_t tid, qid; 1291 int error, ridx, hasqos, xferlen; 1292 1293 wh = mtod(m, struct ieee80211_frame *); 1294 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1295 k = ieee80211_get_txkey(ic, wh, ni); 1296 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1297 return ENOBUFS; 1298 wh = mtod(m, struct ieee80211_frame *); 1299 } 1300 1301 if ((hasqos = ieee80211_has_qos(wh))) { 1302 qos = ieee80211_get_qos(wh); 1303 tid = qos & IEEE80211_QOS_TID; 1304 qid = ieee80211_up_to_ac(ic, tid); 1305 } else { 1306 qos = 0; 1307 qid = EDCA_AC_BE; 1308 } 1309 1310 /* Pickup a rate index. */ 1311 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1312 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA) 1313 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1314 OTUS_RIDX_OFDM6 : OTUS_RIDX_CCK1; 1315 else if (ic->ic_fixed_rate != -1) 1316 ridx = sc->fixed_ridx; 1317 else 1318 ridx = on->ridx[ni->ni_txrate]; 1319 1320 phyctl = 0; 1321 macctl = AR_TX_MAC_BACKOFF | AR_TX_MAC_HW_DUR | AR_TX_MAC_QID(qid); 1322 1323 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1324 (hasqos && ((qos & IEEE80211_QOS_ACK_POLICY_MASK) == 1325 IEEE80211_QOS_ACK_POLICY_NOACK))) 1326 macctl |= AR_TX_MAC_NOACK; 1327 1328 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1329 if (m->m_pkthdr.len + IEEE80211_CRC_LEN >= ic->ic_rtsthreshold) 1330 macctl |= AR_TX_MAC_RTS; 1331 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1332 ridx >= OTUS_RIDX_OFDM6) { 1333 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 1334 macctl |= AR_TX_MAC_CTS; 1335 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 1336 macctl |= AR_TX_MAC_RTS; 1337 } 1338 } 1339 1340 phyctl |= AR_TX_PHY_MCS(otus_rates[ridx].mcs); 1341 if (ridx >= OTUS_RIDX_OFDM6) { 1342 phyctl |= AR_TX_PHY_MT_OFDM; 1343 if (ridx <= OTUS_RIDX_OFDM24) 1344 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 1345 else 1346 phyctl |= AR_TX_PHY_ANTMSK(1); 1347 } else { /* CCK */ 1348 phyctl |= AR_TX_PHY_MT_CCK; 1349 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 1350 } 1351 1352 /* Update rate control stats for frames that are ACK'ed. */ 1353 if (!(macctl & AR_TX_MAC_NOACK)) 1354 ((struct otus_node *)ni)->amn.amn_txcnt++; 1355 1356 data = &sc->tx_data[sc->tx_cur]; 1357 /* Fill Tx descriptor. */ 1358 head = (struct ar_tx_head *)data->buf; 1359 head->len = htole16(m->m_pkthdr.len + IEEE80211_CRC_LEN); 1360 head->macctl = htole16(macctl); 1361 head->phyctl = htole32(phyctl); 1362 1363 #if NBPFILTER > 0 1364 if (__predict_false(sc->sc_drvbpf != NULL)) { 1365 struct otus_tx_radiotap_header *tap = &sc->sc_txtap; 1366 struct mbuf mb; 1367 1368 tap->wt_flags = 0; 1369 tap->wt_rate = otus_rates[ridx].rate; 1370 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1371 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1372 1373 mb.m_data = (caddr_t)tap; 1374 mb.m_len = sc->sc_txtap_len; 1375 mb.m_next = m; 1376 mb.m_nextpkt = NULL; 1377 mb.m_type = 0; 1378 mb.m_flags = 0; 1379 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1380 } 1381 #endif 1382 1383 xferlen = sizeof (*head) + m->m_pkthdr.len; 1384 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&head[1]); 1385 m_freem(m); 1386 1387 DPRINTFN(5, ("tx queued=%d len=%d mac=0x%04x phy=0x%08x rate=%d\n", 1388 sc->tx_queued, head->len, head->macctl, head->phyctl, 1389 otus_rates[ridx].rate)); 1390 usbd_setup_xfer(data->xfer, sc->data_tx_pipe, data, data->buf, xferlen, 1391 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, OTUS_TX_TIMEOUT, otus_txeof); 1392 error = usbd_transfer(data->xfer); 1393 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) 1394 return error; 1395 1396 ieee80211_release_node(ic, ni); 1397 1398 sc->tx_queued++; 1399 sc->tx_cur = (sc->tx_cur + 1) % OTUS_TX_DATA_LIST_COUNT; 1400 1401 return 0; 1402 } 1403 1404 void 1405 otus_start(struct ifnet *ifp) 1406 { 1407 struct otus_softc *sc = ifp->if_softc; 1408 struct ieee80211com *ic = &sc->sc_ic; 1409 struct ieee80211_node *ni; 1410 struct mbuf *m; 1411 1412 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1413 return; 1414 1415 for (;;) { 1416 if (sc->tx_queued >= OTUS_TX_DATA_LIST_COUNT) { 1417 ifp->if_flags |= IFF_OACTIVE; 1418 break; 1419 } 1420 /* Send pending management frames first. */ 1421 IF_DEQUEUE(&ic->ic_mgtq, m); 1422 if (m != NULL) { 1423 ni = m->m_pkthdr.ph_cookie; 1424 goto sendit; 1425 } 1426 if (ic->ic_state != IEEE80211_S_RUN) 1427 break; 1428 1429 /* Encapsulate and send data frames. */ 1430 IFQ_DEQUEUE(&ifp->if_snd, m); 1431 if (m == NULL) 1432 break; 1433 #if NBPFILTER > 0 1434 if (ifp->if_bpf != NULL) 1435 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1436 #endif 1437 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1438 continue; 1439 sendit: 1440 #if NBPFILTER > 0 1441 if (ic->ic_rawbpf != NULL) 1442 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1443 #endif 1444 if (otus_tx(sc, m, ni) != 0) { 1445 ieee80211_release_node(ic, ni); 1446 ifp->if_oerrors++; 1447 continue; 1448 } 1449 1450 sc->sc_tx_timer = 5; 1451 ifp->if_timer = 1; 1452 } 1453 } 1454 1455 void 1456 otus_watchdog(struct ifnet *ifp) 1457 { 1458 struct otus_softc *sc = ifp->if_softc; 1459 1460 ifp->if_timer = 0; 1461 1462 if (sc->sc_tx_timer > 0) { 1463 if (--sc->sc_tx_timer == 0) { 1464 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1465 /* otus_init(ifp); XXX needs a process context! */ 1466 ifp->if_oerrors++; 1467 return; 1468 } 1469 ifp->if_timer = 1; 1470 } 1471 ieee80211_watchdog(ifp); 1472 } 1473 1474 int 1475 otus_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1476 { 1477 struct otus_softc *sc = ifp->if_softc; 1478 struct ieee80211com *ic = &sc->sc_ic; 1479 struct ifaddr *ifa; 1480 struct ifreq *ifr; 1481 int s, error = 0; 1482 1483 if (usbd_is_dying(sc->sc_udev)) 1484 return ENXIO; 1485 1486 usbd_ref_incr(sc->sc_udev); 1487 1488 s = splnet(); 1489 1490 switch (cmd) { 1491 case SIOCSIFADDR: 1492 ifa = (struct ifaddr *)data; 1493 ifp->if_flags |= IFF_UP; 1494 #ifdef INET 1495 if (ifa->ifa_addr->sa_family == AF_INET) 1496 arp_ifinit(&ic->ic_ac, ifa); 1497 #endif 1498 /* FALLTHROUGH */ 1499 case SIOCSIFFLAGS: 1500 if (ifp->if_flags & IFF_UP) { 1501 if ((ifp->if_flags & IFF_RUNNING) && 1502 ((ifp->if_flags ^ sc->sc_if_flags) & 1503 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1504 otus_set_multi(sc); 1505 } else if (!(ifp->if_flags & IFF_RUNNING)) 1506 otus_init(ifp); 1507 1508 } else if (ifp->if_flags & IFF_RUNNING) 1509 otus_stop(ifp); 1510 1511 sc->sc_if_flags = ifp->if_flags; 1512 break; 1513 case SIOCADDMULTI: 1514 case SIOCDELMULTI: 1515 ifr = (struct ifreq *)data; 1516 error = (cmd == SIOCADDMULTI) ? 1517 ether_addmulti(ifr, &ic->ic_ac) : 1518 ether_delmulti(ifr, &ic->ic_ac); 1519 if (error == ENETRESET) 1520 error = 0; 1521 break; 1522 case SIOCS80211CHANNEL: 1523 error = ieee80211_ioctl(ifp, cmd, data); 1524 if (error == ENETRESET && 1525 ic->ic_opmode == IEEE80211_M_MONITOR) { 1526 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1527 (IFF_UP | IFF_RUNNING)) 1528 otus_set_chan(sc, ic->ic_ibss_chan, 0); 1529 error = 0; 1530 } 1531 break; 1532 default: 1533 error = ieee80211_ioctl(ifp, cmd, data); 1534 } 1535 1536 if (error == ENETRESET) { 1537 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1538 (IFF_UP | IFF_RUNNING)) 1539 otus_init(ifp); 1540 error = 0; 1541 } 1542 1543 splx(s); 1544 1545 usbd_ref_decr(sc->sc_udev); 1546 1547 return error; 1548 } 1549 1550 int 1551 otus_set_multi(struct otus_softc *sc) 1552 { 1553 struct arpcom *ac = &sc->sc_ic.ic_ac; 1554 struct ifnet *ifp = &ac->ac_if; 1555 struct ether_multi *enm; 1556 struct ether_multistep step; 1557 uint32_t lo, hi; 1558 uint8_t bit; 1559 1560 if (ac->ac_multirangecnt > 0) 1561 ifp->if_flags |= IFF_ALLMULTI; 1562 1563 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1564 lo = hi = 0xffffffff; 1565 goto done; 1566 } 1567 lo = hi = 0; 1568 ETHER_FIRST_MULTI(step, ac, enm); 1569 while (enm != NULL) { 1570 bit = enm->enm_addrlo[5] >> 2; 1571 if (bit < 32) 1572 lo |= 1 << bit; 1573 else 1574 hi |= 1 << (bit - 32); 1575 ETHER_NEXT_MULTI(step, enm); 1576 } 1577 done: 1578 hi |= 1U << 31; /* Make sure the broadcast bit is set. */ 1579 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_L, lo); 1580 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_H, hi); 1581 return otus_write_barrier(sc); 1582 } 1583 1584 void 1585 otus_updateedca(struct ieee80211com *ic) 1586 { 1587 /* Do it in a process context. */ 1588 otus_do_async(ic->ic_softc, otus_updateedca_cb, NULL, 0); 1589 } 1590 1591 /* ARGSUSED */ 1592 void 1593 otus_updateedca_cb(struct otus_softc *sc, void *arg) 1594 { 1595 #define EXP2(val) ((1 << (val)) - 1) 1596 #define AIFS(val) ((val) * 9 + 10) 1597 struct ieee80211com *ic = &sc->sc_ic; 1598 const struct ieee80211_edca_ac_params *edca; 1599 int s; 1600 1601 s = splnet(); 1602 1603 edca = (ic->ic_flags & IEEE80211_F_QOS) ? 1604 ic->ic_edca_ac : otus_edca_def; 1605 1606 /* Set CWmin/CWmax values. */ 1607 otus_write(sc, AR_MAC_REG_AC0_CW, 1608 EXP2(edca[EDCA_AC_BE].ac_ecwmax) << 16 | 1609 EXP2(edca[EDCA_AC_BE].ac_ecwmin)); 1610 otus_write(sc, AR_MAC_REG_AC1_CW, 1611 EXP2(edca[EDCA_AC_BK].ac_ecwmax) << 16 | 1612 EXP2(edca[EDCA_AC_BK].ac_ecwmin)); 1613 otus_write(sc, AR_MAC_REG_AC2_CW, 1614 EXP2(edca[EDCA_AC_VI].ac_ecwmax) << 16 | 1615 EXP2(edca[EDCA_AC_VI].ac_ecwmin)); 1616 otus_write(sc, AR_MAC_REG_AC3_CW, 1617 EXP2(edca[EDCA_AC_VO].ac_ecwmax) << 16 | 1618 EXP2(edca[EDCA_AC_VO].ac_ecwmin)); 1619 otus_write(sc, AR_MAC_REG_AC4_CW, /* Special TXQ. */ 1620 EXP2(edca[EDCA_AC_VO].ac_ecwmax) << 16 | 1621 EXP2(edca[EDCA_AC_VO].ac_ecwmin)); 1622 1623 /* Set AIFSN values. */ 1624 otus_write(sc, AR_MAC_REG_AC1_AC0_AIFS, 1625 AIFS(edca[EDCA_AC_VI].ac_aifsn) << 24 | 1626 AIFS(edca[EDCA_AC_BK].ac_aifsn) << 12 | 1627 AIFS(edca[EDCA_AC_BE].ac_aifsn)); 1628 otus_write(sc, AR_MAC_REG_AC3_AC2_AIFS, 1629 AIFS(edca[EDCA_AC_VO].ac_aifsn) << 16 | /* Special TXQ. */ 1630 AIFS(edca[EDCA_AC_VO].ac_aifsn) << 4 | 1631 AIFS(edca[EDCA_AC_VI].ac_aifsn) >> 8); 1632 1633 /* Set TXOP limit. */ 1634 otus_write(sc, AR_MAC_REG_AC1_AC0_TXOP, 1635 edca[EDCA_AC_BK].ac_txoplimit << 16 | 1636 edca[EDCA_AC_BE].ac_txoplimit); 1637 otus_write(sc, AR_MAC_REG_AC3_AC2_TXOP, 1638 edca[EDCA_AC_VO].ac_txoplimit << 16 | 1639 edca[EDCA_AC_VI].ac_txoplimit); 1640 1641 splx(s); 1642 1643 (void)otus_write_barrier(sc); 1644 #undef AIFS 1645 #undef EXP2 1646 } 1647 1648 void 1649 otus_updateslot(struct ieee80211com *ic) 1650 { 1651 /* Do it in a process context. */ 1652 otus_do_async(ic->ic_softc, otus_updateslot_cb, NULL, 0); 1653 } 1654 1655 /* ARGSUSED */ 1656 void 1657 otus_updateslot_cb(struct otus_softc *sc, void *arg) 1658 { 1659 uint32_t slottime; 1660 1661 slottime = (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1662 otus_write(sc, AR_MAC_REG_SLOT_TIME, slottime << 10); 1663 (void)otus_write_barrier(sc); 1664 } 1665 1666 int 1667 otus_init_mac(struct otus_softc *sc) 1668 { 1669 int error; 1670 1671 otus_write(sc, AR_MAC_REG_ACK_EXTENSION, 0x40); 1672 otus_write(sc, AR_MAC_REG_RETRY_MAX, 0); 1673 otus_write(sc, AR_MAC_REG_SNIFFER, 0x2000000); 1674 otus_write(sc, AR_MAC_REG_RX_THRESHOLD, 0xc1f80); 1675 otus_write(sc, AR_MAC_REG_RX_PE_DELAY, 0x70); 1676 otus_write(sc, AR_MAC_REG_EIFS_AND_SIFS, 0xa144000); 1677 otus_write(sc, AR_MAC_REG_SLOT_TIME, 9 << 10); 1678 otus_write(sc, 0x1c3b2c, 0x19000000); 1679 /* NAV protects ACK only (in TXOP). */ 1680 otus_write(sc, 0x1c3b38, 0x201); 1681 /* Set beacon Tx power to 0x7. */ 1682 otus_write(sc, AR_MAC_REG_BCN_HT1, 0x8000170); 1683 otus_write(sc, AR_MAC_REG_BACKOFF_PROTECT, 0x105); 1684 otus_write(sc, 0x1c3b9c, 0x10000a); 1685 /* Filter any control frames, BAR is bit 24. */ 1686 otus_write(sc, 0x1c368c, 0x0500ffff); 1687 otus_write(sc, 0x1c3c40, 0x1); 1688 otus_write(sc, AR_MAC_REG_BASIC_RATE, 0x150f); 1689 otus_write(sc, AR_MAC_REG_MANDATORY_RATE, 0x150f); 1690 otus_write(sc, AR_MAC_REG_RTS_CTS_RATE, 0x10b01bb); 1691 otus_write(sc, 0x1c3694, 0x4003c1e); 1692 /* Enable LED0 and LED1. */ 1693 otus_write(sc, 0x1d0100, 0x3); 1694 otus_write(sc, 0x1d0104, 0x3); 1695 /* Switch MAC to OTUS interface. */ 1696 otus_write(sc, 0x1c3600, 0x3); 1697 otus_write(sc, 0x1c3c50, 0xffff); 1698 otus_write(sc, 0x1c3680, 0xf00008); 1699 /* Disable Rx timeout (workaround). */ 1700 otus_write(sc, 0x1c362c, 0); 1701 1702 /* Set USB Rx stream mode maximum frame number to 2. */ 1703 otus_write(sc, 0x1e1110, 0x4); 1704 /* Set USB Rx stream mode timeout to 10us. */ 1705 otus_write(sc, 0x1e1114, 0x80); 1706 1707 /* Set clock frequency to 88/80MHz. */ 1708 otus_write(sc, 0x1d4008, 0x73); 1709 /* Set WLAN DMA interrupt mode: generate intr per packet. */ 1710 otus_write(sc, 0x1c3d7c, 0x110011); 1711 otus_write(sc, 0x1c3bb0, 0x4); 1712 otus_write(sc, AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141e0f48); 1713 1714 /* Disable HW decryption for now. */ 1715 otus_write(sc, 0x1c3678, 0x78); 1716 1717 if ((error = otus_write_barrier(sc)) != 0) 1718 return error; 1719 1720 /* Set default EDCA parameters. */ 1721 otus_updateedca_cb(sc, NULL); 1722 1723 return 0; 1724 } 1725 1726 /* 1727 * Return default value for PHY register based on current operating mode. 1728 */ 1729 uint32_t 1730 otus_phy_get_def(struct otus_softc *sc, uint32_t reg) 1731 { 1732 int i; 1733 1734 for (i = 0; i < nitems(ar5416_phy_regs); i++) 1735 if (AR_PHY(ar5416_phy_regs[i]) == reg) 1736 return sc->phy_vals[i]; 1737 return 0; /* Register not found. */ 1738 } 1739 1740 /* 1741 * Update PHY's programming based on vendor-specific data stored in EEPROM. 1742 * This is for FEM-type devices only. 1743 */ 1744 int 1745 otus_set_board_values(struct otus_softc *sc, struct ieee80211_channel *c) 1746 { 1747 const struct ModalEepHeader *eep; 1748 uint32_t tmp, offset; 1749 1750 if (IEEE80211_IS_CHAN_5GHZ(c)) 1751 eep = &sc->eeprom.modalHeader[0]; 1752 else 1753 eep = &sc->eeprom.modalHeader[1]; 1754 1755 /* Offset of chain 2. */ 1756 offset = 2 * 0x1000; 1757 1758 tmp = letoh32(eep->antCtrlCommon); 1759 otus_write(sc, AR_PHY_SWITCH_COM, tmp); 1760 1761 tmp = letoh32(eep->antCtrlChain[0]); 1762 otus_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp); 1763 1764 tmp = letoh32(eep->antCtrlChain[1]); 1765 otus_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp); 1766 1767 if (1 /* sc->sc_sco == AR_SCO_SCN */) { 1768 tmp = otus_phy_get_def(sc, AR_PHY_SETTLING); 1769 tmp &= ~(0x7f << 7); 1770 tmp |= (eep->switchSettling & 0x7f) << 7; 1771 otus_write(sc, AR_PHY_SETTLING, tmp); 1772 } 1773 1774 tmp = otus_phy_get_def(sc, AR_PHY_DESIRED_SZ); 1775 tmp &= ~0xffff; 1776 tmp |= eep->pgaDesiredSize << 8 | eep->adcDesiredSize; 1777 otus_write(sc, AR_PHY_DESIRED_SZ, tmp); 1778 1779 tmp = eep->txEndToXpaOff << 24 | eep->txEndToXpaOff << 16 | 1780 eep->txFrameToXpaOn << 8 | eep->txFrameToXpaOn; 1781 otus_write(sc, AR_PHY_RF_CTL4, tmp); 1782 1783 tmp = otus_phy_get_def(sc, AR_PHY_RF_CTL3); 1784 tmp &= ~(0xff << 16); 1785 tmp |= eep->txEndToRxOn << 16; 1786 otus_write(sc, AR_PHY_RF_CTL3, tmp); 1787 1788 tmp = otus_phy_get_def(sc, AR_PHY_CCA); 1789 tmp &= ~(0x7f << 12); 1790 tmp |= (eep->thresh62 & 0x7f) << 12; 1791 otus_write(sc, AR_PHY_CCA, tmp); 1792 1793 tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN); 1794 tmp &= ~(0x3f << 12); 1795 tmp |= (eep->txRxAttenCh[0] & 0x3f) << 12; 1796 otus_write(sc, AR_PHY_RXGAIN, tmp); 1797 1798 tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN + offset); 1799 tmp &= ~(0x3f << 12); 1800 tmp |= (eep->txRxAttenCh[1] & 0x3f) << 12; 1801 otus_write(sc, AR_PHY_RXGAIN + offset, tmp); 1802 1803 tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ); 1804 tmp &= ~(0x3f << 18); 1805 tmp |= (eep->rxTxMarginCh[0] & 0x3f) << 18; 1806 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1807 tmp &= ~(0xf << 10); 1808 tmp |= (eep->bswMargin[0] & 0xf) << 10; 1809 } 1810 otus_write(sc, AR_PHY_GAIN_2GHZ, tmp); 1811 1812 tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ + offset); 1813 tmp &= ~(0x3f << 18); 1814 tmp |= (eep->rxTxMarginCh[1] & 0x3f) << 18; 1815 otus_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp); 1816 1817 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4); 1818 tmp &= ~(0x3f << 5 | 0x1f); 1819 tmp |= (eep->iqCalICh[0] & 0x3f) << 5 | (eep->iqCalQCh[0] & 0x1f); 1820 otus_write(sc, AR_PHY_TIMING_CTRL4, tmp); 1821 1822 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4 + offset); 1823 tmp &= ~(0x3f << 5 | 0x1f); 1824 tmp |= (eep->iqCalICh[1] & 0x3f) << 5 | (eep->iqCalQCh[1] & 0x1f); 1825 otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp); 1826 1827 tmp = otus_phy_get_def(sc, AR_PHY_TPCRG1); 1828 tmp &= ~(0xf << 16); 1829 tmp |= (eep->xpd & 0xf) << 16; 1830 otus_write(sc, AR_PHY_TPCRG1, tmp); 1831 1832 return otus_write_barrier(sc); 1833 } 1834 1835 int 1836 otus_program_phy(struct otus_softc *sc, struct ieee80211_channel *c) 1837 { 1838 const uint32_t *vals; 1839 int error, i; 1840 1841 /* Select PHY programming based on band and bandwidth. */ 1842 if (IEEE80211_IS_CHAN_2GHZ(c)) 1843 vals = ar5416_phy_vals_2ghz_20mhz; 1844 else 1845 vals = ar5416_phy_vals_5ghz_20mhz; 1846 for (i = 0; i < nitems(ar5416_phy_regs); i++) 1847 otus_write(sc, AR_PHY(ar5416_phy_regs[i]), vals[i]); 1848 sc->phy_vals = vals; 1849 1850 if (sc->eeprom.baseEepHeader.deviceType == 0x80) /* FEM */ 1851 if ((error = otus_set_board_values(sc, c)) != 0) 1852 return error; 1853 1854 /* Initial Tx power settings. */ 1855 otus_write(sc, AR_PHY_POWER_TX_RATE_MAX, 0x7f); 1856 otus_write(sc, AR_PHY_POWER_TX_RATE1, 0x3f3f3f3f); 1857 otus_write(sc, AR_PHY_POWER_TX_RATE2, 0x3f3f3f3f); 1858 otus_write(sc, AR_PHY_POWER_TX_RATE3, 0x3f3f3f3f); 1859 otus_write(sc, AR_PHY_POWER_TX_RATE4, 0x3f3f3f3f); 1860 otus_write(sc, AR_PHY_POWER_TX_RATE5, 0x3f3f3f3f); 1861 otus_write(sc, AR_PHY_POWER_TX_RATE6, 0x3f3f3f3f); 1862 otus_write(sc, AR_PHY_POWER_TX_RATE7, 0x3f3f3f3f); 1863 otus_write(sc, AR_PHY_POWER_TX_RATE8, 0x3f3f3f3f); 1864 otus_write(sc, AR_PHY_POWER_TX_RATE9, 0x3f3f3f3f); 1865 1866 if (IEEE80211_IS_CHAN_2GHZ(c)) 1867 otus_write(sc, 0x1d4014, 0x5163); 1868 else 1869 otus_write(sc, 0x1d4014, 0x5143); 1870 1871 return otus_write_barrier(sc); 1872 } 1873 1874 static __inline uint8_t 1875 otus_reverse_bits(uint8_t v) 1876 { 1877 v = ((v >> 1) & 0x55) | ((v & 0x55) << 1); 1878 v = ((v >> 2) & 0x33) | ((v & 0x33) << 2); 1879 v = ((v >> 4) & 0x0f) | ((v & 0x0f) << 4); 1880 return v; 1881 } 1882 1883 int 1884 otus_set_rf_bank4(struct otus_softc *sc, struct ieee80211_channel *c) 1885 { 1886 uint8_t chansel, d0, d1; 1887 uint16_t data; 1888 int error; 1889 1890 d0 = 0; 1891 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1892 chansel = (c->ic_freq - 4800) / 5; 1893 if (chansel & 1) 1894 d0 |= AR_BANK4_AMODE_REFSEL(2); 1895 else 1896 d0 |= AR_BANK4_AMODE_REFSEL(1); 1897 } else { 1898 d0 |= AR_BANK4_AMODE_REFSEL(2); 1899 if (c->ic_freq == 2484) { /* CH 14 */ 1900 d0 |= AR_BANK4_BMODE_LF_SYNTH_FREQ; 1901 chansel = 10 + (c->ic_freq - 2274) / 5; 1902 } else 1903 chansel = 16 + (c->ic_freq - 2272) / 5; 1904 chansel <<= 2; 1905 } 1906 d0 |= AR_BANK4_ADDR(1) | AR_BANK4_CHUP; 1907 d1 = otus_reverse_bits(chansel); 1908 1909 /* Write bits 0-4 of d0 and d1. */ 1910 data = (d1 & 0x1f) << 5 | (d0 & 0x1f); 1911 otus_write(sc, AR_PHY(44), data); 1912 /* Write bits 5-7 of d0 and d1. */ 1913 data = (d1 >> 5) << 5 | (d0 >> 5); 1914 otus_write(sc, AR_PHY(58), data); 1915 1916 if ((error = otus_write_barrier(sc)) == 0) 1917 usbd_delay_ms(sc->sc_udev, 10); 1918 return error; 1919 } 1920 1921 void 1922 otus_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 1923 { 1924 #define COEFF_SCALE_SHIFT 24 1925 uint32_t exp, man; 1926 1927 /* exponent = 14 - floor(log2(coeff)) */ 1928 for (exp = 31; exp > 0; exp--) 1929 if (coeff & (1 << exp)) 1930 break; 1931 KASSERT(exp != 0); 1932 exp = 14 - (exp - COEFF_SCALE_SHIFT); 1933 1934 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 1935 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 1936 1937 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 1938 *exponent = exp - 16; 1939 #undef COEFF_SCALE_SHIFT 1940 } 1941 1942 int 1943 otus_set_chan(struct otus_softc *sc, struct ieee80211_channel *c, int assoc) 1944 { 1945 struct ieee80211com *ic = &sc->sc_ic; 1946 struct ar_cmd_frequency cmd; 1947 struct ar_rsp_frequency rsp; 1948 const uint32_t *vals; 1949 uint32_t coeff, exp, man, tmp; 1950 uint8_t code; 1951 int error, chan, i; 1952 1953 chan = ieee80211_chan2ieee(ic, c); 1954 DPRINTF(("setting channel %d (%dMHz)\n", chan, c->ic_freq)); 1955 1956 tmp = IEEE80211_IS_CHAN_2GHZ(c) ? 0x105 : 0x104; 1957 otus_write(sc, AR_MAC_REG_DYNAMIC_SIFS_ACK, tmp); 1958 if ((error = otus_write_barrier(sc)) != 0) 1959 return error; 1960 1961 /* Disable BB Heavy Clip. */ 1962 otus_write(sc, AR_PHY_HEAVY_CLIP_ENABLE, 0x200); 1963 if ((error = otus_write_barrier(sc)) != 0) 1964 return error; 1965 1966 /* XXX Is that FREQ_START ? */ 1967 error = otus_cmd(sc, AR_CMD_FREQ_STRAT, NULL, 0, NULL); 1968 if (error != 0) 1969 return error; 1970 1971 /* Reprogram PHY and RF on channel band or bandwidth changes. */ 1972 if (sc->bb_reset || c->ic_flags != sc->sc_curchan->ic_flags) { 1973 DPRINTF(("band switch\n")); 1974 1975 /* Cold/Warm reset BB/ADDA. */ 1976 otus_write(sc, 0x1d4004, sc->bb_reset ? 0x800 : 0x400); 1977 if ((error = otus_write_barrier(sc)) != 0) 1978 return error; 1979 otus_write(sc, 0x1d4004, 0); 1980 if ((error = otus_write_barrier(sc)) != 0) 1981 return error; 1982 sc->bb_reset = 0; 1983 1984 if ((error = otus_program_phy(sc, c)) != 0) { 1985 printf("%s: could not program PHY\n", 1986 sc->sc_dev.dv_xname); 1987 return error; 1988 } 1989 1990 /* Select RF programming based on band. */ 1991 if (IEEE80211_IS_CHAN_5GHZ(c)) 1992 vals = ar5416_banks_vals_5ghz; 1993 else 1994 vals = ar5416_banks_vals_2ghz; 1995 for (i = 0; i < nitems(ar5416_banks_regs); i++) 1996 otus_write(sc, AR_PHY(ar5416_banks_regs[i]), vals[i]); 1997 if ((error = otus_write_barrier(sc)) != 0) { 1998 printf("%s: could not program RF\n", 1999 sc->sc_dev.dv_xname); 2000 return error; 2001 } 2002 code = AR_CMD_RF_INIT; 2003 } else { 2004 code = AR_CMD_FREQUENCY; 2005 } 2006 2007 if ((error = otus_set_rf_bank4(sc, c)) != 0) 2008 return error; 2009 2010 tmp = (sc->txmask == 0x5) ? 0x340 : 0x240; 2011 otus_write(sc, AR_PHY_TURBO, tmp); 2012 if ((error = otus_write_barrier(sc)) != 0) 2013 return error; 2014 2015 /* Send firmware command to set channel. */ 2016 cmd.freq = htole32((uint32_t)c->ic_freq * 1000); 2017 cmd.dynht2040 = htole32(0); 2018 cmd.htena = htole32(1); 2019 /* Set Delta Slope (exponent and mantissa). */ 2020 coeff = (100 << 24) / c->ic_freq; 2021 otus_get_delta_slope(coeff, &exp, &man); 2022 cmd.dsc_exp = htole32(exp); 2023 cmd.dsc_man = htole32(man); 2024 DPRINTF(("ds coeff=%u exp=%u man=%u\n", coeff, exp, man)); 2025 /* For Short GI, coeff is 9/10 that of normal coeff. */ 2026 coeff = (9 * coeff) / 10; 2027 otus_get_delta_slope(coeff, &exp, &man); 2028 cmd.dsc_shgi_exp = htole32(exp); 2029 cmd.dsc_shgi_man = htole32(man); 2030 DPRINTF(("ds shgi coeff=%u exp=%u man=%u\n", coeff, exp, man)); 2031 /* Set wait time for AGC and noise calibration (100 or 200ms). */ 2032 cmd.check_loop_count = assoc ? htole32(2000) : htole32(1000); 2033 DPRINTF(("%s\n", (code == AR_CMD_RF_INIT) ? "RF_INIT" : "FREQUENCY")); 2034 error = otus_cmd(sc, code, &cmd, sizeof cmd, &rsp); 2035 if (error != 0) 2036 return error; 2037 if ((rsp.status & htole32(AR_CAL_ERR_AGC | AR_CAL_ERR_NF_VAL)) != 0) { 2038 DPRINTF(("status=0x%x\n", letoh32(rsp.status))); 2039 /* Force cold reset on next channel. */ 2040 sc->bb_reset = 1; 2041 } 2042 #ifdef OTUS_DEBUG 2043 if (otus_debug) { 2044 printf("calibration status=0x%x\n", letoh32(rsp.status)); 2045 for (i = 0; i < 2; i++) { /* 2 Rx chains */ 2046 /* Sign-extend 9-bit NF values. */ 2047 printf("noisefloor chain %d=%d\n", i, 2048 (((int32_t)letoh32(rsp.nf[i])) << 4) >> 23); 2049 printf("noisefloor ext chain %d=%d\n", i, 2050 ((int32_t)letoh32(rsp.nf_ext[i])) >> 23); 2051 } 2052 } 2053 #endif 2054 sc->sc_curchan = c; 2055 return 0; 2056 } 2057 2058 #ifdef notyet 2059 int 2060 otus_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2061 struct ieee80211_key *k) 2062 { 2063 struct otus_softc *sc = ic->ic_softc; 2064 struct otus_cmd_key cmd; 2065 2066 /* Defer setting of WEP keys until interface is brought up. */ 2067 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 2068 (IFF_UP | IFF_RUNNING)) 2069 return 0; 2070 2071 /* Do it in a process context. */ 2072 cmd.key = *k; 2073 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2074 otus_do_async(sc, otus_set_key_cb, &cmd, sizeof cmd); 2075 return 0; 2076 } 2077 2078 void 2079 otus_set_key_cb(struct otus_softc *sc, void *arg) 2080 { 2081 struct otus_cmd_key *cmd = arg; 2082 struct ieee80211_key *k = &cmd->key; 2083 struct ar_cmd_ekey key; 2084 uint16_t cipher; 2085 int error; 2086 2087 memset(&key, 0, sizeof key); 2088 if (k->k_flags & IEEE80211_KEY_GROUP) { 2089 key.uid = htole16(k->k_id); 2090 IEEE80211_ADDR_COPY(key.macaddr, sc->sc_ic.ic_myaddr); 2091 key.macaddr[0] |= 0x80; 2092 } else { 2093 key.uid = htole16(OTUS_UID(cmd->associd)); 2094 IEEE80211_ADDR_COPY(key.macaddr, ni->ni_macaddr); 2095 } 2096 key.kix = htole16(0); 2097 /* Map net80211 cipher to hardware. */ 2098 switch (k->k_cipher) { 2099 case IEEE80211_CIPHER_WEP40: 2100 cipher = AR_CIPHER_WEP64; 2101 break; 2102 case IEEE80211_CIPHER_WEP104: 2103 cipher = AR_CIPHER_WEP128; 2104 break; 2105 case IEEE80211_CIPHER_TKIP: 2106 cipher = AR_CIPHER_TKIP; 2107 break; 2108 case IEEE80211_CIPHER_CCMP: 2109 cipher = AR_CIPHER_AES; 2110 break; 2111 default: 2112 return; 2113 } 2114 key.cipher = htole16(cipher); 2115 memcpy(key.key, k->k_key, MIN(k->k_len, 16)); 2116 error = otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL); 2117 if (error != 0 || k->k_cipher != IEEE80211_CIPHER_TKIP) 2118 return; 2119 2120 /* TKIP: set Tx/Rx MIC Key. */ 2121 key.kix = htole16(1); 2122 memcpy(key.key, k->k_key + 16, 16); 2123 (void)otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL); 2124 } 2125 2126 void 2127 otus_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2128 struct ieee80211_key *k) 2129 { 2130 struct otus_softc *sc = ic->ic_softc; 2131 struct otus_cmd_key cmd; 2132 2133 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 2134 ic->ic_state != IEEE80211_S_RUN) 2135 return; /* Nothing to do. */ 2136 2137 /* Do it in a process context. */ 2138 cmd.key = *k; 2139 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2140 otus_do_async(sc, otus_delete_key_cb, &cmd, sizeof cmd); 2141 } 2142 2143 void 2144 otus_delete_key_cb(struct otus_softc *sc, void *arg) 2145 { 2146 struct otus_cmd_key *cmd = arg; 2147 struct ieee80211_key *k = &cmd->key; 2148 uint32_t uid; 2149 2150 if (k->k_flags & IEEE80211_KEY_GROUP) 2151 uid = htole32(k->k_id); 2152 else 2153 uid = htole32(OTUS_UID(cmd->associd)); 2154 (void)otus_cmd(sc, AR_CMD_DKEY, &uid, sizeof uid, NULL); 2155 } 2156 #endif 2157 2158 void 2159 otus_calibrate_to(void *arg) 2160 { 2161 struct otus_softc *sc = arg; 2162 struct ieee80211com *ic = &sc->sc_ic; 2163 struct ieee80211_node *ni; 2164 int s; 2165 2166 if (usbd_is_dying(sc->sc_udev)) 2167 return; 2168 2169 usbd_ref_incr(sc->sc_udev); 2170 2171 s = splnet(); 2172 ni = ic->ic_bss; 2173 ieee80211_amrr_choose(&sc->amrr, ni, &((struct otus_node *)ni)->amn); 2174 splx(s); 2175 2176 if (!usbd_is_dying(sc->sc_udev)) 2177 timeout_add_sec(&sc->calib_to, 1); 2178 2179 usbd_ref_decr(sc->sc_udev); 2180 } 2181 2182 int 2183 otus_set_bssid(struct otus_softc *sc, const uint8_t *bssid) 2184 { 2185 otus_write(sc, AR_MAC_REG_BSSID_L, 2186 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 2187 otus_write(sc, AR_MAC_REG_BSSID_H, 2188 bssid[4] | bssid[5] << 8); 2189 return otus_write_barrier(sc); 2190 } 2191 2192 int 2193 otus_set_macaddr(struct otus_softc *sc, const uint8_t *addr) 2194 { 2195 otus_write(sc, AR_MAC_REG_MAC_ADDR_L, 2196 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2197 otus_write(sc, AR_MAC_REG_MAC_ADDR_H, 2198 addr[4] | addr[5] << 8); 2199 return otus_write_barrier(sc); 2200 } 2201 2202 /* Default single-LED. */ 2203 void 2204 otus_led_newstate_type1(struct otus_softc *sc) 2205 { 2206 /* TBD */ 2207 } 2208 2209 /* NETGEAR, dual-LED. */ 2210 void 2211 otus_led_newstate_type2(struct otus_softc *sc) 2212 { 2213 /* TBD */ 2214 } 2215 2216 /* NETGEAR, single-LED/3 colors (blue, red, purple.) */ 2217 void 2218 otus_led_newstate_type3(struct otus_softc *sc) 2219 { 2220 struct ieee80211com *ic = &sc->sc_ic; 2221 uint32_t state = sc->led_state; 2222 2223 if (ic->ic_state == IEEE80211_S_INIT) { 2224 state = 0; /* LED off. */ 2225 } else if (ic->ic_state == IEEE80211_S_RUN) { 2226 /* Associated, LED always on. */ 2227 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) 2228 state = AR_LED0_ON; /* 2GHz=>Red. */ 2229 else 2230 state = AR_LED1_ON; /* 5GHz=>Blue. */ 2231 } else { 2232 /* Scanning, blink LED. */ 2233 state ^= AR_LED0_ON | AR_LED1_ON; 2234 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) 2235 state &= ~AR_LED1_ON; 2236 else 2237 state &= ~AR_LED0_ON; 2238 } 2239 if (state != sc->led_state) { 2240 otus_write(sc, 0x1d0104, state); 2241 if (otus_write_barrier(sc) == 0) 2242 sc->led_state = state; 2243 } 2244 } 2245 2246 int 2247 otus_init(struct ifnet *ifp) 2248 { 2249 struct otus_softc *sc = ifp->if_softc; 2250 struct ieee80211com *ic = &sc->sc_ic; 2251 int error; 2252 2253 /* Init host command ring. */ 2254 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2255 2256 if ((error = otus_init_mac(sc)) != 0) { 2257 printf("%s: could not initialize MAC\n", sc->sc_dev.dv_xname); 2258 return error; 2259 } 2260 2261 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2262 (void)otus_set_macaddr(sc, ic->ic_myaddr); 2263 2264 switch (ic->ic_opmode) { 2265 #ifdef notyet 2266 #ifndef IEEE80211_STA_ONLY 2267 case IEEE80211_M_HOSTAP: 2268 otus_write(sc, 0x1c3700, 0x0f0000a1); 2269 otus_write(sc, 0x1c3c40, 0x1); 2270 break; 2271 case IEEE80211_M_IBSS: 2272 otus_write(sc, 0x1c3700, 0x0f000000); 2273 otus_write(sc, 0x1c3c40, 0x1); 2274 break; 2275 #endif 2276 #endif 2277 case IEEE80211_M_STA: 2278 otus_write(sc, 0x1c3700, 0x0f000002); 2279 otus_write(sc, 0x1c3c40, 0x1); 2280 break; 2281 default: 2282 break; 2283 } 2284 otus_write(sc, AR_MAC_REG_SNIFFER, 2285 (ic->ic_opmode == IEEE80211_M_MONITOR) ? 0x2000001 : 0x2000000); 2286 (void)otus_write_barrier(sc); 2287 2288 sc->bb_reset = 1; /* Force cold reset. */ 2289 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2290 if ((error = otus_set_chan(sc, ic->ic_ibss_chan, 0)) != 0) { 2291 printf("%s: could not set channel\n", sc->sc_dev.dv_xname); 2292 return error; 2293 } 2294 2295 /* Start Rx. */ 2296 otus_write(sc, 0x1c3d30, 0x100); 2297 (void)otus_write_barrier(sc); 2298 2299 ifp->if_flags &= ~IFF_OACTIVE; 2300 ifp->if_flags |= IFF_RUNNING; 2301 2302 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2303 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2304 else 2305 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2306 2307 return 0; 2308 } 2309 2310 void 2311 otus_stop(struct ifnet *ifp) 2312 { 2313 struct otus_softc *sc = ifp->if_softc; 2314 struct ieee80211com *ic = &sc->sc_ic; 2315 int s; 2316 2317 sc->sc_tx_timer = 0; 2318 ifp->if_timer = 0; 2319 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2320 2321 timeout_del(&sc->scan_to); 2322 timeout_del(&sc->calib_to); 2323 2324 s = splusb(); 2325 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2326 /* Wait for all queued asynchronous commands to complete. */ 2327 usb_wait_task(sc->sc_udev, &sc->sc_task); 2328 splx(s); 2329 2330 /* Stop Rx. */ 2331 otus_write(sc, 0x1c3d30, 0); 2332 (void)otus_write_barrier(sc); 2333 2334 sc->tx_queued = 0; 2335 } 2336