1 /* $OpenBSD: if_otus.c,v 1.14 2009/11/17 18:07:09 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /*- 20 * Driver for Atheros AR9001U chipset. 21 * http://www.atheros.com/pt/bulletins/AR9001USBBulletin.pdf 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/sysctl.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/timeout.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 37 #include <machine/bus.h> 38 #include <machine/endian.h> 39 #include <machine/intr.h> 40 41 #if NBPFILTER > 0 42 #include <net/bpf.h> 43 #endif 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 #include <net/if_types.h> 49 50 #include <netinet/in.h> 51 #include <netinet/in_systm.h> 52 #include <netinet/in_var.h> 53 #include <netinet/if_ether.h> 54 #include <netinet/ip.h> 55 56 #include <net80211/ieee80211_var.h> 57 #include <net80211/ieee80211_amrr.h> 58 #include <net80211/ieee80211_radiotap.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbdevs.h> 64 65 #include <dev/usb/if_otusreg.h> 66 67 #ifdef USB_DEBUG 68 #define OTUS_DEBUG 69 #endif 70 71 #ifdef OTUS_DEBUG 72 #define DPRINTF(x) do { if (otus_debug) printf x; } while (0) 73 #define DPRINTFN(n, x) do { if (otus_debug >= (n)) printf x; } while (0) 74 int otus_debug = 1; 75 #else 76 #define DPRINTF(x) 77 #define DPRINTFN(n, x) 78 #endif 79 80 static const struct usb_devno otus_devs[] = { 81 { USB_VENDOR_ACCTON, USB_PRODUCT_ACCTON_WN7512 }, 82 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_TG121N }, 83 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_AR9170 }, 84 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN821NV2 }, 85 { USB_VENDOR_AVM, USB_PRODUCT_AVM_FRITZWLAN }, 86 { USB_VENDOR_CACE, USB_PRODUCT_CACE_AIRPCAPNX }, 87 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA130D1 }, 88 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A1 }, 89 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A2 }, 90 { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_WNGDNUS2 }, 91 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WN111V2 }, 92 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNDA3100 }, 93 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_GW_US300 }, 94 { USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB81 }, 95 { USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB82 }, 96 { USB_VENDOR_ZYDAS, USB_PRODUCT_ZYDAS_ZD1221 }, 97 { USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_NWD271N } 98 }; 99 100 int otus_match(struct device *, void *, void *); 101 void otus_attach(struct device *, struct device *, void *); 102 int otus_detach(struct device *, int); 103 void otus_attachhook(void *); 104 void otus_get_chanlist(struct otus_softc *); 105 int otus_load_firmware(struct otus_softc *, const char *, 106 uint32_t); 107 int otus_open_pipes(struct otus_softc *); 108 void otus_close_pipes(struct otus_softc *); 109 int otus_alloc_tx_cmd(struct otus_softc *); 110 void otus_free_tx_cmd(struct otus_softc *); 111 int otus_alloc_tx_data_list(struct otus_softc *); 112 void otus_free_tx_data_list(struct otus_softc *); 113 int otus_alloc_rx_data_list(struct otus_softc *); 114 void otus_free_rx_data_list(struct otus_softc *); 115 void otus_next_scan(void *); 116 void otus_task(void *); 117 void otus_do_async(struct otus_softc *, 118 void (*)(struct otus_softc *, void *), void *, int); 119 int otus_newstate(struct ieee80211com *, enum ieee80211_state, 120 int); 121 void otus_newstate_cb(struct otus_softc *, void *); 122 int otus_cmd(struct otus_softc *, uint8_t, const void *, int, 123 void *); 124 void otus_write(struct otus_softc *, uint32_t, uint32_t); 125 int otus_write_barrier(struct otus_softc *); 126 struct ieee80211_node *otus_node_alloc(struct ieee80211com *); 127 int otus_media_change(struct ifnet *); 128 int otus_read_eeprom(struct otus_softc *); 129 void otus_newassoc(struct ieee80211com *, struct ieee80211_node *, 130 int); 131 void otus_intr(usbd_xfer_handle, usbd_private_handle, usbd_status); 132 void otus_cmd_rxeof(struct otus_softc *, uint8_t *, int); 133 void otus_sub_rxeof(struct otus_softc *, uint8_t *, int); 134 void otus_rxeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 135 void otus_txeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 136 int otus_tx(struct otus_softc *, struct mbuf *, 137 struct ieee80211_node *); 138 void otus_start(struct ifnet *); 139 void otus_watchdog(struct ifnet *); 140 int otus_ioctl(struct ifnet *, u_long, caddr_t); 141 int otus_set_multi(struct otus_softc *); 142 void otus_updateedca(struct ieee80211com *); 143 void otus_updateedca_cb(struct otus_softc *, void *); 144 void otus_updateslot(struct ieee80211com *); 145 void otus_updateslot_cb(struct otus_softc *, void *); 146 int otus_init_mac(struct otus_softc *); 147 uint32_t otus_phy_get_def(struct otus_softc *, uint32_t); 148 int otus_set_board_values(struct otus_softc *, 149 struct ieee80211_channel *); 150 int otus_program_phy(struct otus_softc *, 151 struct ieee80211_channel *); 152 int otus_set_rf_bank4(struct otus_softc *, 153 struct ieee80211_channel *); 154 void otus_get_delta_slope(uint32_t, uint32_t *, uint32_t *); 155 int otus_set_chan(struct otus_softc *, struct ieee80211_channel *, 156 int); 157 int otus_set_key(struct ieee80211com *, struct ieee80211_node *, 158 struct ieee80211_key *); 159 void otus_set_key_cb(struct otus_softc *, void *); 160 void otus_delete_key(struct ieee80211com *, struct ieee80211_node *, 161 struct ieee80211_key *); 162 void otus_delete_key_cb(struct otus_softc *, void *); 163 void otus_calibrate_to(void *); 164 int otus_set_bssid(struct otus_softc *, const uint8_t *); 165 int otus_set_macaddr(struct otus_softc *, const uint8_t *); 166 void otus_led_newstate_type1(struct otus_softc *); 167 void otus_led_newstate_type2(struct otus_softc *); 168 void otus_led_newstate_type3(struct otus_softc *); 169 int otus_init(struct ifnet *); 170 void otus_stop(struct ifnet *); 171 172 struct cfdriver otus_cd = { 173 NULL, "otus", DV_IFNET 174 }; 175 176 const struct cfattach otus_ca = { 177 sizeof (struct otus_softc), otus_match, otus_attach, otus_detach 178 }; 179 180 int 181 otus_match(struct device *parent, void *match, void *aux) 182 { 183 struct usb_attach_arg *uaa = aux; 184 185 if (uaa->iface != NULL) 186 return UMATCH_NONE; 187 188 return (usb_lookup(otus_devs, uaa->vendor, uaa->product) != NULL) ? 189 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 190 } 191 192 void 193 otus_attach(struct device *parent, struct device *self, void *aux) 194 { 195 struct otus_softc *sc = (struct otus_softc *)self; 196 struct usb_attach_arg *uaa = aux; 197 int error; 198 199 sc->sc_udev = uaa->device; 200 201 usb_init_task(&sc->sc_task, otus_task, sc); 202 timeout_set(&sc->scan_to, otus_next_scan, sc); 203 timeout_set(&sc->calib_to, otus_calibrate_to, sc); 204 205 sc->amrr.amrr_min_success_threshold = 1; 206 sc->amrr.amrr_max_success_threshold = 10; 207 208 if (usbd_set_config_no(sc->sc_udev, 1, 0) != 0) { 209 printf("%s: could not set configuration no\n", 210 sc->sc_dev.dv_xname); 211 return; 212 } 213 214 /* Get the first interface handle. */ 215 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 216 if (error != 0) { 217 printf("%s: could not get interface handle\n", 218 sc->sc_dev.dv_xname); 219 return; 220 } 221 222 if ((error = otus_open_pipes(sc)) != 0) { 223 printf("%s: could not open pipes\n", sc->sc_dev.dv_xname); 224 return; 225 } 226 227 if (rootvp == NULL) 228 mountroothook_establish(otus_attachhook, sc); 229 else 230 otus_attachhook(sc); 231 232 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, &sc->sc_dev); 233 } 234 235 int 236 otus_detach(struct device *self, int flags) 237 { 238 struct otus_softc *sc = (struct otus_softc *)self; 239 struct ifnet *ifp = &sc->sc_ic.ic_if; 240 int s; 241 242 s = splnet(); 243 244 /* Wait for all queued asynchronous commands to complete. */ 245 while (sc->cmdq.queued > 0) 246 tsleep(&sc->cmdq, 0, "cmdq", 0); 247 248 timeout_del(&sc->scan_to); 249 timeout_del(&sc->calib_to); 250 251 if (ifp->if_flags != 0) { /* if_attach() has been called. */ 252 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 253 ieee80211_ifdetach(ifp); 254 if_detach(ifp); 255 } 256 257 otus_close_pipes(sc); 258 259 splx(s); 260 261 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, &sc->sc_dev); 262 263 return 0; 264 } 265 266 void 267 otus_attachhook(void *xsc) 268 { 269 struct otus_softc *sc = xsc; 270 struct ieee80211com *ic = &sc->sc_ic; 271 struct ifnet *ifp = &ic->ic_if; 272 usb_device_request_t req; 273 uint32_t in, out; 274 int error; 275 276 error = otus_load_firmware(sc, "otus-init", AR_FW_INIT_ADDR); 277 if (error != 0) { 278 printf("%s: could not load %s firmware\n", 279 sc->sc_dev.dv_xname, "init"); 280 return; 281 } 282 283 usbd_delay_ms(sc->sc_udev, 1000); 284 285 error = otus_load_firmware(sc, "otus-main", AR_FW_MAIN_ADDR); 286 if (error != 0) { 287 printf("%s: could not load %s firmware\n", 288 sc->sc_dev.dv_xname, "main"); 289 return; 290 } 291 292 /* Tell device that firmware transfer is complete. */ 293 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 294 req.bRequest = AR_FW_DOWNLOAD_COMPLETE; 295 USETW(req.wValue, 0); 296 USETW(req.wIndex, 0); 297 USETW(req.wLength, 0); 298 if (usbd_do_request(sc->sc_udev, &req, NULL) != 0) { 299 printf("%s: firmware initialization failed\n", 300 sc->sc_dev.dv_xname); 301 return; 302 } 303 304 /* Send an ECHO command to check that everything is settled. */ 305 in = 0xbadc0ffe; 306 if (otus_cmd(sc, AR_CMD_ECHO, &in, sizeof in, &out) != 0) { 307 printf("%s: echo command failed\n", sc->sc_dev.dv_xname); 308 return; 309 } 310 if (in != out) { 311 printf("%s: echo reply mismatch: 0x%08x!=0x%08x\n", 312 sc->sc_dev.dv_xname, in, out); 313 return; 314 } 315 316 /* Read entire EEPROM. */ 317 if (otus_read_eeprom(sc) != 0) { 318 printf("%s: could not read EEPROM\n", sc->sc_dev.dv_xname); 319 return; 320 } 321 322 sc->txmask = sc->eeprom.baseEepHeader.txMask; 323 sc->rxmask = sc->eeprom.baseEepHeader.rxMask; 324 sc->capflags = sc->eeprom.baseEepHeader.opCapFlags; 325 IEEE80211_ADDR_COPY(ic->ic_myaddr, sc->eeprom.baseEepHeader.macAddr); 326 sc->sc_led_newstate = otus_led_newstate_type3; /* XXX */ 327 328 printf("%s: MAC/BBP AR9170, RF AR%X, MIMO %dT%dR, address %s\n", 329 sc->sc_dev.dv_xname, (sc->capflags & AR5416_OPFLAGS_11A) ? 330 0x9104 : ((sc->txmask == 0x5) ? 0x9102 : 0x9101), 331 (sc->txmask == 0x5) ? 2 : 1, (sc->rxmask == 0x5) ? 2 : 1, 332 ether_sprintf(ic->ic_myaddr)); 333 334 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 335 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 336 ic->ic_state = IEEE80211_S_INIT; 337 338 /* Set device capabilities. */ 339 ic->ic_caps = 340 IEEE80211_C_MONITOR | /* monitor mode supported */ 341 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 342 IEEE80211_C_SHSLOT | /* short slot time supported */ 343 IEEE80211_C_WEP | /* WEP */ 344 IEEE80211_C_RSN; /* WPA/RSN */ 345 346 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { 347 /* Set supported .11b and .11g rates. */ 348 ic->ic_sup_rates[IEEE80211_MODE_11B] = 349 ieee80211_std_rateset_11b; 350 ic->ic_sup_rates[IEEE80211_MODE_11G] = 351 ieee80211_std_rateset_11g; 352 } 353 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { 354 /* Set supported .11a rates. */ 355 ic->ic_sup_rates[IEEE80211_MODE_11A] = 356 ieee80211_std_rateset_11a; 357 } 358 359 /* Build the list of supported channels. */ 360 otus_get_chanlist(sc); 361 362 ifp->if_softc = sc; 363 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 364 ifp->if_init = otus_init; 365 ifp->if_ioctl = otus_ioctl; 366 ifp->if_start = otus_start; 367 ifp->if_watchdog = otus_watchdog; 368 IFQ_SET_READY(&ifp->if_snd); 369 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 370 371 if_attach(ifp); 372 ieee80211_ifattach(ifp); 373 ic->ic_node_alloc = otus_node_alloc; 374 ic->ic_newassoc = otus_newassoc; 375 ic->ic_updateslot = otus_updateslot; 376 ic->ic_updateedca = otus_updateedca; 377 #ifdef notyet 378 ic->ic_set_key = otus_set_key; 379 ic->ic_delete_key = otus_delete_key; 380 #endif 381 /* Override state transition machine. */ 382 sc->sc_newstate = ic->ic_newstate; 383 ic->ic_newstate = otus_newstate; 384 ieee80211_media_init(ifp, otus_media_change, ieee80211_media_status); 385 386 #if NBPFILTER > 0 387 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 388 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 389 390 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 391 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 392 sc->sc_rxtap.wr_ihdr.it_present = htole32(OTUS_RX_RADIOTAP_PRESENT); 393 394 sc->sc_txtap_len = sizeof sc->sc_txtapu; 395 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 396 sc->sc_txtap.wt_ihdr.it_present = htole32(OTUS_TX_RADIOTAP_PRESENT); 397 #endif 398 } 399 400 void 401 otus_get_chanlist(struct otus_softc *sc) 402 { 403 struct ieee80211com *ic = &sc->sc_ic; 404 uint16_t domain; 405 uint8_t chan; 406 int i; 407 408 /* XXX regulatory domain. */ 409 domain = letoh16(sc->eeprom.baseEepHeader.regDmn[0]); 410 DPRINTF(("regdomain=0x%04x\n", domain)); 411 412 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { 413 for (i = 0; i < 14; i++) { 414 chan = ar_chans[i]; 415 ic->ic_channels[chan].ic_freq = 416 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 417 ic->ic_channels[chan].ic_flags = 418 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 419 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 420 } 421 } 422 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { 423 for (i = 14; i < nitems(ar_chans); i++) { 424 chan = ar_chans[i]; 425 ic->ic_channels[chan].ic_freq = 426 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 427 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 428 } 429 } 430 } 431 432 int 433 otus_load_firmware(struct otus_softc *sc, const char *name, uint32_t addr) 434 { 435 usb_device_request_t req; 436 size_t size; 437 u_char *fw, *ptr; 438 int mlen, error; 439 440 /* Read firmware image from the filesystem. */ 441 if ((error = loadfirmware(name, &fw, &size)) != 0) { 442 printf("%s: failed loadfirmware of file %s (error %d)\n", 443 sc->sc_dev.dv_xname, name, error); 444 return error; 445 } 446 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 447 req.bRequest = AR_FW_DOWNLOAD; 448 USETW(req.wIndex, 0); 449 450 ptr = fw; 451 addr >>= 8; 452 while (size > 0) { 453 mlen = MIN(size, 4096); 454 455 USETW(req.wValue, addr); 456 USETW(req.wLength, mlen); 457 if (usbd_do_request(sc->sc_udev, &req, ptr) != 0) { 458 error = EIO; 459 break; 460 } 461 addr += mlen >> 8; 462 ptr += mlen; 463 size -= mlen; 464 } 465 free(fw, M_DEVBUF); 466 return error; 467 } 468 469 int 470 otus_open_pipes(struct otus_softc *sc) 471 { 472 usb_endpoint_descriptor_t *ed; 473 int i, isize, error; 474 475 error = usbd_open_pipe(sc->sc_iface, AR_EPT_BULK_RX_NO, 0, 476 &sc->data_rx_pipe); 477 if (error != 0) { 478 printf("%s: could not open Rx bulk pipe\n", 479 sc->sc_dev.dv_xname); 480 goto fail; 481 } 482 483 ed = usbd_get_endpoint_descriptor(sc->sc_iface, AR_EPT_INTR_RX_NO); 484 if (ed == NULL) { 485 printf("%s: could not retrieve Rx intr pipe descriptor\n", 486 sc->sc_dev.dv_xname); 487 goto fail; 488 } 489 isize = UGETW(ed->wMaxPacketSize); 490 if (isize == 0) { 491 printf("%s: invalid Rx intr pipe descriptor\n", 492 sc->sc_dev.dv_xname); 493 goto fail; 494 } 495 sc->ibuf = malloc(isize, M_USBDEV, M_NOWAIT); 496 if (sc->ibuf == NULL) { 497 printf("%s: could not allocate Rx intr buffer\n", 498 sc->sc_dev.dv_xname); 499 goto fail; 500 } 501 error = usbd_open_pipe_intr(sc->sc_iface, AR_EPT_INTR_RX_NO, 502 USBD_SHORT_XFER_OK, &sc->cmd_rx_pipe, sc, sc->ibuf, isize, 503 otus_intr, USBD_DEFAULT_INTERVAL); 504 if (error != 0) { 505 printf("%s: could not open Rx intr pipe\n", 506 sc->sc_dev.dv_xname); 507 goto fail; 508 } 509 510 error = usbd_open_pipe(sc->sc_iface, AR_EPT_BULK_TX_NO, 0, 511 &sc->data_tx_pipe); 512 if (error != 0) { 513 printf("%s: could not open Tx bulk pipe\n", 514 sc->sc_dev.dv_xname); 515 goto fail; 516 } 517 518 error = usbd_open_pipe(sc->sc_iface, AR_EPT_INTR_TX_NO, 0, 519 &sc->cmd_tx_pipe); 520 if (error != 0) { 521 printf("%s: could not open Tx intr pipe\n", 522 sc->sc_dev.dv_xname); 523 goto fail; 524 } 525 526 if (otus_alloc_tx_cmd(sc) != 0) { 527 printf("%s: could not allocate command xfer\n", 528 sc->sc_dev.dv_xname); 529 goto fail; 530 } 531 532 if (otus_alloc_tx_data_list(sc) != 0) { 533 printf("%s: could not allocate Tx xfers\n", 534 sc->sc_dev.dv_xname); 535 goto fail; 536 } 537 538 if (otus_alloc_rx_data_list(sc) != 0) { 539 printf("%s: could not allocate Rx xfers\n", 540 sc->sc_dev.dv_xname); 541 goto fail; 542 } 543 544 for (i = 0; i < OTUS_RX_DATA_LIST_COUNT; i++) { 545 struct otus_rx_data *data = &sc->rx_data[i]; 546 547 usbd_setup_xfer(data->xfer, sc->data_rx_pipe, data, data->buf, 548 OTUS_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 549 USBD_NO_TIMEOUT, otus_rxeof); 550 error = usbd_transfer(data->xfer); 551 if (error != USBD_IN_PROGRESS && error != 0) { 552 printf("%s: could not queue Rx xfer\n", 553 sc->sc_dev.dv_xname); 554 goto fail; 555 } 556 } 557 return 0; 558 559 fail: otus_close_pipes(sc); 560 return error; 561 } 562 563 void 564 otus_close_pipes(struct otus_softc *sc) 565 { 566 otus_free_tx_cmd(sc); 567 otus_free_tx_data_list(sc); 568 otus_free_rx_data_list(sc); 569 570 if (sc->data_rx_pipe != NULL) 571 usbd_close_pipe(sc->data_rx_pipe); 572 if (sc->cmd_rx_pipe != NULL) { 573 usbd_abort_pipe(sc->cmd_rx_pipe); 574 usbd_close_pipe(sc->cmd_rx_pipe); 575 } 576 if (sc->ibuf != NULL) 577 free(sc->ibuf, M_USBDEV); 578 if (sc->data_tx_pipe != NULL) 579 usbd_close_pipe(sc->data_tx_pipe); 580 if (sc->cmd_tx_pipe != NULL) 581 usbd_close_pipe(sc->cmd_tx_pipe); 582 } 583 584 int 585 otus_alloc_tx_cmd(struct otus_softc *sc) 586 { 587 struct otus_tx_cmd *cmd = &sc->tx_cmd; 588 589 cmd->xfer = usbd_alloc_xfer(sc->sc_udev); 590 if (cmd->xfer == NULL) { 591 printf("%s: could not allocate xfer\n", 592 sc->sc_dev.dv_xname); 593 return ENOMEM; 594 } 595 cmd->buf = usbd_alloc_buffer(cmd->xfer, OTUS_MAX_TXCMDSZ); 596 if (cmd->buf == NULL) { 597 printf("%s: could not allocate xfer buffer\n", 598 sc->sc_dev.dv_xname); 599 usbd_free_xfer(cmd->xfer); 600 return ENOMEM; 601 } 602 return 0; 603 } 604 605 void 606 otus_free_tx_cmd(struct otus_softc *sc) 607 { 608 /* Make sure no transfers are pending. */ 609 usbd_abort_pipe(sc->cmd_tx_pipe); 610 611 if (sc->tx_cmd.xfer != NULL) 612 usbd_free_xfer(sc->tx_cmd.xfer); 613 } 614 615 int 616 otus_alloc_tx_data_list(struct otus_softc *sc) 617 { 618 struct otus_tx_data *data; 619 int i, error; 620 621 for (i = 0; i < OTUS_TX_DATA_LIST_COUNT; i++) { 622 data = &sc->tx_data[i]; 623 624 data->sc = sc; /* Backpointer for callbacks. */ 625 626 data->xfer = usbd_alloc_xfer(sc->sc_udev); 627 if (data->xfer == NULL) { 628 printf("%s: could not allocate xfer\n", 629 sc->sc_dev.dv_xname); 630 error = ENOMEM; 631 goto fail; 632 } 633 data->buf = usbd_alloc_buffer(data->xfer, OTUS_TXBUFSZ); 634 if (data->buf == NULL) { 635 printf("%s: could not allocate xfer buffer\n", 636 sc->sc_dev.dv_xname); 637 error = ENOMEM; 638 goto fail; 639 } 640 } 641 return 0; 642 643 fail: otus_free_tx_data_list(sc); 644 return error; 645 } 646 647 void 648 otus_free_tx_data_list(struct otus_softc *sc) 649 { 650 int i; 651 652 /* Make sure no transfers are pending. */ 653 usbd_abort_pipe(sc->data_tx_pipe); 654 655 for (i = 0; i < OTUS_TX_DATA_LIST_COUNT; i++) 656 if (sc->tx_data[i].xfer != NULL) 657 usbd_free_xfer(sc->tx_data[i].xfer); 658 } 659 660 int 661 otus_alloc_rx_data_list(struct otus_softc *sc) 662 { 663 struct otus_rx_data *data; 664 int i, error; 665 666 for (i = 0; i < OTUS_RX_DATA_LIST_COUNT; i++) { 667 data = &sc->rx_data[i]; 668 669 data->sc = sc; /* Backpointer for callbacks. */ 670 671 data->xfer = usbd_alloc_xfer(sc->sc_udev); 672 if (data->xfer == NULL) { 673 printf("%s: could not allocate xfer\n", 674 sc->sc_dev.dv_xname); 675 error = ENOMEM; 676 goto fail; 677 } 678 data->buf = usbd_alloc_buffer(data->xfer, OTUS_RXBUFSZ); 679 if (data->buf == NULL) { 680 printf("%s: could not allocate xfer buffer\n", 681 sc->sc_dev.dv_xname); 682 error = ENOMEM; 683 goto fail; 684 } 685 } 686 return 0; 687 688 fail: otus_free_rx_data_list(sc); 689 return error; 690 } 691 692 void 693 otus_free_rx_data_list(struct otus_softc *sc) 694 { 695 int i; 696 697 /* Make sure no transfers are pending. */ 698 usbd_abort_pipe(sc->data_rx_pipe); 699 700 for (i = 0; i < OTUS_RX_DATA_LIST_COUNT; i++) 701 if (sc->rx_data[i].xfer != NULL) 702 usbd_free_xfer(sc->rx_data[i].xfer); 703 } 704 705 void 706 otus_next_scan(void *arg) 707 { 708 struct otus_softc *sc = arg; 709 710 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 711 ieee80211_next_scan(&sc->sc_ic.ic_if); 712 } 713 714 void 715 otus_task(void *arg) 716 { 717 struct otus_softc *sc = arg; 718 struct otus_host_cmd_ring *ring = &sc->cmdq; 719 struct otus_host_cmd *cmd; 720 int s; 721 722 /* Process host commands. */ 723 s = splusb(); 724 while (ring->next != ring->cur) { 725 cmd = &ring->cmd[ring->next]; 726 splx(s); 727 /* Callback. */ 728 cmd->cb(sc, cmd->data); 729 s = splusb(); 730 ring->queued--; 731 ring->next = (ring->next + 1) % OTUS_HOST_CMD_RING_COUNT; 732 } 733 wakeup(ring); 734 splx(s); 735 } 736 737 void 738 otus_do_async(struct otus_softc *sc, void (*cb)(struct otus_softc *, void *), 739 void *arg, int len) 740 { 741 struct otus_host_cmd_ring *ring = &sc->cmdq; 742 struct otus_host_cmd *cmd; 743 int s; 744 745 s = splusb(); 746 cmd = &ring->cmd[ring->cur]; 747 cmd->cb = cb; 748 KASSERT(len <= sizeof (cmd->data)); 749 memcpy(cmd->data, arg, len); 750 ring->cur = (ring->cur + 1) % OTUS_HOST_CMD_RING_COUNT; 751 752 /* If there is no pending command already, schedule a task. */ 753 if (++ring->queued == 1) 754 usb_add_task(sc->sc_udev, &sc->sc_task); 755 splx(s); 756 } 757 758 int 759 otus_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 760 { 761 struct otus_softc *sc = ic->ic_softc; 762 struct otus_cmd_newstate cmd; 763 764 /* Do it in a process context. */ 765 cmd.state = nstate; 766 cmd.arg = arg; 767 otus_do_async(sc, otus_newstate_cb, &cmd, sizeof cmd); 768 return 0; 769 } 770 771 void 772 otus_newstate_cb(struct otus_softc *sc, void *arg) 773 { 774 struct otus_cmd_newstate *cmd = arg; 775 struct ieee80211com *ic = &sc->sc_ic; 776 struct ieee80211_node *ni; 777 int s; 778 779 s = splnet(); 780 781 switch (cmd->state) { 782 case IEEE80211_S_INIT: 783 break; 784 785 case IEEE80211_S_SCAN: 786 (void)otus_set_chan(sc, ic->ic_bss->ni_chan, 0); 787 timeout_add_msec(&sc->scan_to, 200); 788 break; 789 790 case IEEE80211_S_AUTH: 791 case IEEE80211_S_ASSOC: 792 (void)otus_set_chan(sc, ic->ic_bss->ni_chan, 0); 793 break; 794 795 case IEEE80211_S_RUN: 796 (void)otus_set_chan(sc, ic->ic_bss->ni_chan, 1); 797 798 ni = ic->ic_bss; 799 800 if (ic->ic_opmode == IEEE80211_M_STA) { 801 otus_updateslot(ic); 802 otus_set_bssid(sc, ni->ni_bssid); 803 804 /* Fake a join to init the Tx rate. */ 805 otus_newassoc(ic, ni, 1); 806 807 /* Start calibration timer. */ 808 timeout_add_sec(&sc->calib_to, 1); 809 } 810 break; 811 } 812 813 sc->sc_led_newstate(sc); 814 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 815 816 splx(s); 817 } 818 819 int 820 otus_cmd(struct otus_softc *sc, uint8_t code, const void *idata, int ilen, 821 void *odata) 822 { 823 struct otus_tx_cmd *cmd = &sc->tx_cmd; 824 struct ar_cmd_hdr *hdr; 825 int s, xferlen, error; 826 827 /* Always bulk-out a multiple of 4 bytes. */ 828 xferlen = (sizeof (*hdr) + ilen + 3) & ~3; 829 830 hdr = (struct ar_cmd_hdr *)cmd->buf; 831 hdr->code = code; 832 hdr->len = ilen; 833 hdr->token = ++cmd->token; /* Don't care about endianness. */ 834 memcpy((uint8_t *)&hdr[1], idata, ilen); 835 836 DPRINTFN(2, ("sending command code=0x%02x len=%d token=%d\n", 837 code, ilen, hdr->token)); 838 839 s = splusb(); 840 cmd->odata = odata; 841 cmd->done = 0; 842 843 usbd_setup_xfer(cmd->xfer, sc->cmd_tx_pipe, cmd, cmd->buf, xferlen, 844 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, OTUS_CMD_TIMEOUT, NULL); 845 error = usbd_sync_transfer(cmd->xfer); 846 if (error != 0) { 847 splx(s); 848 printf("%s: could not send command 0x%x (error=%s)\n", 849 sc->sc_dev.dv_xname, code, usbd_errstr(error)); 850 return EIO; 851 } 852 if (!cmd->done) 853 error = tsleep(cmd, PCATCH, "otuscmd", hz); 854 cmd->odata = NULL; /* In case answer is received too late. */ 855 splx(s); 856 if (error != 0) { 857 printf("%s: timeout waiting for command 0x%02x reply\n", 858 sc->sc_dev.dv_xname, code); 859 } 860 return error; 861 } 862 863 void 864 otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val) 865 { 866 sc->write_buf[sc->write_idx].reg = htole32(reg); 867 sc->write_buf[sc->write_idx].val = htole32(val); 868 869 if (++sc->write_idx > AR_MAX_WRITE_IDX) 870 (void)otus_write_barrier(sc); 871 } 872 873 int 874 otus_write_barrier(struct otus_softc *sc) 875 { 876 int error; 877 878 if (sc->write_idx == 0) 879 return 0; /* Nothing to flush. */ 880 881 error = otus_cmd(sc, AR_CMD_WREG, sc->write_buf, 882 sizeof (sc->write_buf[0]) * sc->write_idx, NULL); 883 sc->write_idx = 0; 884 return error; 885 } 886 887 struct ieee80211_node * 888 otus_node_alloc(struct ieee80211com *ic) 889 { 890 return malloc(sizeof (struct otus_node), M_DEVBUF, M_NOWAIT | M_ZERO); 891 } 892 893 int 894 otus_media_change(struct ifnet *ifp) 895 { 896 struct otus_softc *sc = ifp->if_softc; 897 struct ieee80211com *ic = &sc->sc_ic; 898 uint8_t rate, ridx; 899 int error; 900 901 error = ieee80211_media_change(ifp); 902 if (error != ENETRESET) 903 return error; 904 905 if (ic->ic_fixed_rate != -1) { 906 rate = ic->ic_sup_rates[ic->ic_curmode]. 907 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 908 for (ridx = 0; ridx <= OTUS_RIDX_MAX; ridx++) 909 if (otus_rates[ridx].rate == rate) 910 break; 911 sc->fixed_ridx = ridx; 912 } 913 914 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 915 error = otus_init(ifp); 916 917 return error; 918 } 919 920 int 921 otus_read_eeprom(struct otus_softc *sc) 922 { 923 uint32_t regs[8], reg; 924 uint8_t *eep; 925 int i, j, error; 926 927 /* Read EEPROM by blocks of 32 bytes. */ 928 eep = (uint8_t *)&sc->eeprom; 929 reg = AR_EEPROM_OFFSET; 930 for (i = 0; i < sizeof (sc->eeprom) / 32; i++) { 931 for (j = 0; j < 8; j++, reg += 4) 932 regs[j] = htole32(reg); 933 error = otus_cmd(sc, AR_CMD_RREG, regs, sizeof regs, eep); 934 if (error != 0) 935 break; 936 eep += 32; 937 } 938 return error; 939 } 940 941 void 942 otus_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 943 { 944 struct otus_softc *sc = ic->ic_softc; 945 struct otus_node *on = (void *)ni; 946 struct ieee80211_rateset *rs = &ni->ni_rates; 947 uint8_t rate; 948 int ridx, i; 949 950 DPRINTF(("new assoc isnew=%d addr=%s\n", 951 isnew, ether_sprintf(ni->ni_macaddr))); 952 953 ieee80211_amrr_node_init(&sc->amrr, &on->amn); 954 /* Start at lowest available bit-rate, AMRR will raise. */ 955 ni->ni_txrate = 0; 956 957 for (i = 0; i < rs->rs_nrates; i++) { 958 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 959 /* Convert 802.11 rate to hardware rate index. */ 960 for (ridx = 0; ridx <= OTUS_RIDX_MAX; ridx++) 961 if (otus_rates[ridx].rate == rate) 962 break; 963 on->ridx[i] = ridx; 964 DPRINTF(("rate=0x%02x ridx=%d\n", 965 rs->rs_rates[i], on->ridx[i])); 966 } 967 } 968 969 /* ARGSUSED */ 970 void 971 otus_intr(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 972 { 973 #if 0 974 struct otus_softc *sc = priv; 975 int len; 976 977 /* 978 * The Rx intr pipe is unused with current firmware. Notifications 979 * and replies to commands are sent through the Rx bulk pipe instead 980 * (with a magic PLCP header.) 981 */ 982 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 983 DPRINTF(("intr status=%d\n", status)); 984 if (status == USBD_STALLED) 985 usbd_clear_endpoint_stall_async(sc->cmd_rx_pipe); 986 return; 987 } 988 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 989 990 otus_cmd_rxeof(sc, sc->ibuf, len); 991 #endif 992 } 993 994 void 995 otus_cmd_rxeof(struct otus_softc *sc, uint8_t *buf, int len) 996 { 997 struct ieee80211com *ic = &sc->sc_ic; 998 struct otus_tx_cmd *cmd; 999 struct ar_cmd_hdr *hdr; 1000 int s; 1001 1002 if (__predict_false(len < sizeof (*hdr))) { 1003 DPRINTF(("cmd too small %d\n", len)); 1004 return; 1005 } 1006 hdr = (struct ar_cmd_hdr *)buf; 1007 if (__predict_false(sizeof (*hdr) + hdr->len > len || 1008 sizeof (*hdr) + hdr->len > 64)) { 1009 DPRINTF(("cmd too large %d\n", hdr->len)); 1010 return; 1011 } 1012 1013 if ((hdr->code & 0xc0) != 0xc0) { 1014 DPRINTFN(2, ("received reply code=0x%02x len=%d token=%d\n", 1015 hdr->code, hdr->len, hdr->token)); 1016 cmd = &sc->tx_cmd; 1017 if (__predict_false(hdr->token != cmd->token)) 1018 return; 1019 /* Copy answer into caller's supplied buffer. */ 1020 if (cmd->odata != NULL) 1021 memcpy(cmd->odata, &hdr[1], hdr->len); 1022 cmd->done = 1; 1023 wakeup(cmd); 1024 return; 1025 } 1026 1027 /* Received unsolicited notification. */ 1028 DPRINTF(("received notification code=0x%02x len=%d\n", 1029 hdr->code, hdr->len)); 1030 switch (hdr->code & 0x3f) { 1031 case AR_EVT_BEACON: 1032 break; 1033 case AR_EVT_TX_COMP: 1034 { 1035 struct ar_evt_tx_comp *tx = (struct ar_evt_tx_comp *)&hdr[1]; 1036 struct ieee80211_node *ni; 1037 struct otus_node *on; 1038 1039 DPRINTF(("tx completed %s status=%d phy=0x%x\n", 1040 ether_sprintf(tx->macaddr), letoh16(tx->status), 1041 letoh32(tx->phy))); 1042 s = splnet(); 1043 #ifdef notyet 1044 #ifndef IEEE80211_STA_ONLY 1045 if (ic->ic_opmode != IEEE80211_M_STA) { 1046 ni = ieee80211_find_node(ic, tx->macaddr); 1047 if (__predict_false(ni == NULL)) { 1048 splx(s); 1049 break; 1050 } 1051 } else 1052 #endif 1053 #endif 1054 ni = ic->ic_bss; 1055 /* Update rate control statistics. */ 1056 on = (void *)ni; 1057 /* NB: we do not set the TX_MAC_RATE_PROBING flag. */ 1058 if (__predict_true(tx->status != 0)) 1059 on->amn.amn_retrycnt++; 1060 splx(s); 1061 break; 1062 } 1063 case AR_EVT_TBTT: 1064 break; 1065 } 1066 } 1067 1068 void 1069 otus_sub_rxeof(struct otus_softc *sc, uint8_t *buf, int len) 1070 { 1071 struct ieee80211com *ic = &sc->sc_ic; 1072 struct ifnet *ifp = &ic->ic_if; 1073 struct ieee80211_rxinfo rxi; 1074 struct ieee80211_node *ni; 1075 struct ar_rx_tail *tail; 1076 struct ieee80211_frame *wh; 1077 struct mbuf *m; 1078 uint8_t *plcp; 1079 int s, mlen, align; 1080 1081 if (__predict_false(len < AR_PLCP_HDR_LEN)) { 1082 DPRINTF(("sub-xfer too short %d\n", len)); 1083 return; 1084 } 1085 plcp = buf; 1086 1087 /* All bits in the PLCP header are set to 1 for non-MPDU. */ 1088 if (memcmp(plcp, AR_PLCP_HDR_INTR, AR_PLCP_HDR_LEN) == 0) { 1089 otus_cmd_rxeof(sc, plcp + AR_PLCP_HDR_LEN, 1090 len - AR_PLCP_HDR_LEN); 1091 return; 1092 } 1093 1094 /* Received MPDU. */ 1095 if (__predict_false(len < AR_PLCP_HDR_LEN + sizeof (*tail))) { 1096 DPRINTF(("MPDU too short %d\n", len)); 1097 ifp->if_ierrors++; 1098 return; 1099 } 1100 tail = (struct ar_rx_tail *)(plcp + len - sizeof (*tail)); 1101 1102 /* Discard error frames. */ 1103 if (__predict_false(tail->error != 0)) { 1104 DPRINTF(("error frame 0x%02x\n", tail->error)); 1105 if (tail->error & AR_RX_ERROR_FCS) { 1106 DPRINTFN(3, ("bad FCS\n")); 1107 } else if (tail->error & AR_RX_ERROR_MMIC) { 1108 /* Report Michael MIC failures to net80211. */ 1109 ic->ic_stats.is_rx_locmicfail++; 1110 ieee80211_michael_mic_failure(ic, 0); 1111 } 1112 ifp->if_ierrors++; 1113 return; 1114 } 1115 /* Compute MPDU's length. */ 1116 mlen = len - AR_PLCP_HDR_LEN - sizeof (*tail); 1117 /* Make sure there's room for an 802.11 header + FCS. */ 1118 if (__predict_false(mlen < IEEE80211_MIN_LEN)) { 1119 ifp->if_ierrors++; 1120 return; 1121 } 1122 mlen -= IEEE80211_CRC_LEN; /* strip 802.11 FCS */ 1123 1124 wh = (struct ieee80211_frame *)(plcp + AR_PLCP_HDR_LEN); 1125 /* Provide a 32-bit aligned protocol header to the stack. */ 1126 align = (ieee80211_has_qos(wh) ^ ieee80211_has_addr4(wh)) ? 2 : 0; 1127 1128 MGETHDR(m, M_DONTWAIT, MT_DATA); 1129 if (__predict_false(m == NULL)) { 1130 ifp->if_ierrors++; 1131 return; 1132 } 1133 if (align + mlen > MHLEN) { 1134 MCLGET(m, M_DONTWAIT); 1135 if (__predict_false(!(m->m_flags & M_EXT))) { 1136 ifp->if_ierrors++; 1137 m_freem(m); 1138 return; 1139 } 1140 } 1141 /* Finalize mbuf. */ 1142 m->m_pkthdr.rcvif = ifp; 1143 m->m_data += align; 1144 memcpy(mtod(m, caddr_t), wh, mlen); 1145 m->m_pkthdr.len = m->m_len = mlen; 1146 1147 #if NBPFILTER > 0 1148 if (__predict_false(sc->sc_drvbpf != NULL)) { 1149 struct otus_rx_radiotap_header *tap = &sc->sc_rxtap; 1150 struct mbuf mb; 1151 1152 tap->wr_flags = 0; 1153 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1154 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1155 tap->wr_antsignal = tail->rssi; 1156 tap->wr_rate = 2; /* In case it can't be found below. */ 1157 switch (tail->status & AR_RX_STATUS_MT_MASK) { 1158 case AR_RX_STATUS_MT_CCK: 1159 switch (plcp[0]) { 1160 case 10: tap->wr_rate = 2; break; 1161 case 20: tap->wr_rate = 4; break; 1162 case 55: tap->wr_rate = 11; break; 1163 case 110: tap->wr_rate = 22; break; 1164 } 1165 if (tail->status & AR_RX_STATUS_SHPREAMBLE) 1166 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1167 break; 1168 case AR_RX_STATUS_MT_OFDM: 1169 switch (plcp[0] & 0xf) { 1170 case 0xb: tap->wr_rate = 12; break; 1171 case 0xf: tap->wr_rate = 18; break; 1172 case 0xa: tap->wr_rate = 24; break; 1173 case 0xe: tap->wr_rate = 36; break; 1174 case 0x9: tap->wr_rate = 48; break; 1175 case 0xd: tap->wr_rate = 72; break; 1176 case 0x8: tap->wr_rate = 96; break; 1177 case 0xc: tap->wr_rate = 108; break; 1178 } 1179 break; 1180 } 1181 mb.m_data = (caddr_t)tap; 1182 mb.m_len = sc->sc_rxtap_len; 1183 mb.m_next = m; 1184 mb.m_nextpkt = NULL; 1185 mb.m_type = 0; 1186 mb.m_flags = 0; 1187 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1188 } 1189 #endif 1190 1191 s = splnet(); 1192 ni = ieee80211_find_rxnode(ic, wh); 1193 rxi.rxi_flags = 0; 1194 rxi.rxi_rssi = tail->rssi; 1195 rxi.rxi_tstamp = 0; /* unused */ 1196 ieee80211_input(ifp, m, ni, &rxi); 1197 1198 /* Node is no longer needed. */ 1199 ieee80211_release_node(ic, ni); 1200 splx(s); 1201 } 1202 1203 void 1204 otus_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 1205 { 1206 struct otus_rx_data *data = priv; 1207 struct otus_softc *sc = data->sc; 1208 caddr_t buf = data->buf; 1209 struct ar_rx_head *head; 1210 uint16_t hlen; 1211 int len; 1212 1213 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1214 DPRINTF(("RX status=%d\n", status)); 1215 if (status == USBD_STALLED) 1216 usbd_clear_endpoint_stall_async(sc->data_rx_pipe); 1217 if (status != USBD_CANCELLED) 1218 goto resubmit; 1219 return; 1220 } 1221 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1222 1223 while (len >= sizeof (*head)) { 1224 head = (struct ar_rx_head *)buf; 1225 if (__predict_false(head->tag != htole16(AR_RX_HEAD_TAG))) { 1226 DPRINTF(("tag not valid 0x%x\n", letoh16(head->tag))); 1227 break; 1228 } 1229 hlen = letoh16(head->len); 1230 if (__predict_false(sizeof (*head) + hlen > len)) { 1231 DPRINTF(("xfer too short %d/%d\n", len, hlen)); 1232 break; 1233 } 1234 /* Process sub-xfer. */ 1235 otus_sub_rxeof(sc, (uint8_t *)&head[1], hlen); 1236 1237 /* Next sub-xfer is aligned on a 32-bit boundary. */ 1238 hlen = (sizeof (*head) + hlen + 3) & ~3; 1239 buf += hlen; 1240 len -= hlen; 1241 } 1242 1243 resubmit: 1244 usbd_setup_xfer(xfer, sc->data_rx_pipe, data, data->buf, OTUS_RXBUFSZ, 1245 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, otus_rxeof); 1246 (void)usbd_transfer(data->xfer); 1247 } 1248 1249 void 1250 otus_txeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 1251 { 1252 struct otus_tx_data *data = priv; 1253 struct otus_softc *sc = data->sc; 1254 struct ieee80211com *ic = &sc->sc_ic; 1255 struct ifnet *ifp = &ic->ic_if; 1256 int s; 1257 1258 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1259 DPRINTF(("TX status=%d\n", status)); 1260 if (status == USBD_STALLED) 1261 usbd_clear_endpoint_stall_async(sc->data_tx_pipe); 1262 ifp->if_oerrors++; 1263 return; 1264 } 1265 s = splnet(); 1266 sc->tx_queued--; 1267 sc->sc_tx_timer = 0; 1268 ifp->if_flags &= ~IFF_OACTIVE; 1269 otus_start(ifp); 1270 splx(s); 1271 } 1272 1273 int 1274 otus_tx(struct otus_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1275 { 1276 struct ieee80211com *ic = &sc->sc_ic; 1277 struct otus_node *on = (void *)ni; 1278 struct otus_tx_data *data; 1279 struct ieee80211_frame *wh; 1280 struct ieee80211_key *k; 1281 struct ar_tx_head *head; 1282 uint32_t phyctl; 1283 uint16_t macctl, qos; 1284 uint8_t tid, qid; 1285 int error, ridx, hasqos, xferlen; 1286 1287 wh = mtod(m, struct ieee80211_frame *); 1288 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1289 k = ieee80211_get_txkey(ic, wh, ni); 1290 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1291 return ENOBUFS; 1292 wh = mtod(m, struct ieee80211_frame *); 1293 } 1294 1295 if ((hasqos = ieee80211_has_qos(wh))) { 1296 qos = ieee80211_get_qos(wh); 1297 tid = qos & IEEE80211_QOS_TID; 1298 qid = ieee80211_up_to_ac(ic, tid); 1299 } else 1300 qid = EDCA_AC_BE; 1301 1302 /* Pickup a rate index. */ 1303 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1304 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA) 1305 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1306 OTUS_RIDX_OFDM6 : OTUS_RIDX_CCK1; 1307 else if (ic->ic_fixed_rate != -1) 1308 ridx = sc->fixed_ridx; 1309 else 1310 ridx = on->ridx[ni->ni_txrate]; 1311 1312 phyctl = 0; 1313 macctl = AR_TX_MAC_BACKOFF | AR_TX_MAC_HW_DUR | AR_TX_MAC_QID(qid); 1314 1315 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1316 (hasqos && ((qos & IEEE80211_QOS_ACK_POLICY_MASK) == 1317 IEEE80211_QOS_ACK_POLICY_NOACK))) 1318 macctl |= AR_TX_MAC_NOACK; 1319 1320 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1321 if (m->m_pkthdr.len + IEEE80211_CRC_LEN >= ic->ic_rtsthreshold) 1322 macctl |= AR_TX_MAC_RTS; 1323 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1324 ridx >= OTUS_RIDX_OFDM6) { 1325 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 1326 macctl |= AR_TX_MAC_CTS; 1327 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 1328 macctl |= AR_TX_MAC_RTS; 1329 } 1330 } 1331 1332 phyctl |= AR_TX_PHY_MCS(otus_rates[ridx].mcs); 1333 if (ridx >= OTUS_RIDX_OFDM6) { 1334 phyctl |= AR_TX_PHY_MT_OFDM; 1335 if (ridx <= OTUS_RIDX_OFDM24) 1336 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 1337 else 1338 phyctl |= AR_TX_PHY_ANTMSK(1); 1339 } else { /* CCK */ 1340 phyctl |= AR_TX_PHY_MT_CCK; 1341 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 1342 } 1343 1344 /* Update rate control stats for frames that are ACK'ed. */ 1345 if (!(macctl & AR_TX_MAC_NOACK)) 1346 ((struct otus_node *)ni)->amn.amn_txcnt++; 1347 1348 data = &sc->tx_data[sc->tx_cur]; 1349 /* Fill Tx descriptor. */ 1350 head = (struct ar_tx_head *)data->buf; 1351 head->len = htole16(m->m_pkthdr.len + IEEE80211_CRC_LEN); 1352 head->macctl = htole16(macctl); 1353 head->phyctl = htole32(phyctl); 1354 1355 #if NBPFILTER > 0 1356 if (__predict_false(sc->sc_drvbpf != NULL)) { 1357 struct otus_tx_radiotap_header *tap = &sc->sc_txtap; 1358 struct mbuf mb; 1359 1360 tap->wt_flags = 0; 1361 tap->wt_rate = otus_rates[ridx].rate; 1362 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1363 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1364 1365 mb.m_data = (caddr_t)tap; 1366 mb.m_len = sc->sc_txtap_len; 1367 mb.m_next = m; 1368 mb.m_nextpkt = NULL; 1369 mb.m_type = 0; 1370 mb.m_flags = 0; 1371 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1372 } 1373 #endif 1374 1375 xferlen = sizeof (*head) + m->m_pkthdr.len; 1376 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&head[1]); 1377 m_freem(m); 1378 ieee80211_release_node(ic, ni); 1379 1380 DPRINTFN(5, ("tx queued=%d len=%d mac=0x%04x phy=0x%08x rate=%d\n", 1381 sc->tx_queued, head->len, head->macctl, head->phyctl, 1382 otus_rates[ridx].rate)); 1383 usbd_setup_xfer(data->xfer, sc->data_tx_pipe, data, data->buf, xferlen, 1384 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, OTUS_TX_TIMEOUT, otus_txeof); 1385 error = usbd_transfer(data->xfer); 1386 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) 1387 return error; 1388 1389 sc->tx_queued++; 1390 sc->tx_cur = (sc->tx_cur + 1) % OTUS_TX_DATA_LIST_COUNT; 1391 1392 return 0; 1393 } 1394 1395 void 1396 otus_start(struct ifnet *ifp) 1397 { 1398 struct otus_softc *sc = ifp->if_softc; 1399 struct ieee80211com *ic = &sc->sc_ic; 1400 struct ieee80211_node *ni; 1401 struct mbuf *m; 1402 1403 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1404 return; 1405 1406 for (;;) { 1407 if (sc->tx_queued >= OTUS_TX_DATA_LIST_COUNT) { 1408 ifp->if_flags |= IFF_OACTIVE; 1409 break; 1410 } 1411 /* Send pending management frames first. */ 1412 IF_DEQUEUE(&ic->ic_mgtq, m); 1413 if (m != NULL) { 1414 ni = (void *)m->m_pkthdr.rcvif; 1415 goto sendit; 1416 } 1417 if (ic->ic_state != IEEE80211_S_RUN) 1418 break; 1419 1420 /* Encapsulate and send data frames. */ 1421 IFQ_DEQUEUE(&ifp->if_snd, m); 1422 if (m == NULL) 1423 break; 1424 #if NBPFILTER > 0 1425 if (ifp->if_bpf != NULL) 1426 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1427 #endif 1428 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1429 continue; 1430 sendit: 1431 #if NBPFILTER > 0 1432 if (ic->ic_rawbpf != NULL) 1433 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1434 #endif 1435 if (otus_tx(sc, m, ni) != 0) { 1436 ieee80211_release_node(ic, ni); 1437 ifp->if_oerrors++; 1438 continue; 1439 } 1440 1441 sc->sc_tx_timer = 5; 1442 ifp->if_timer = 1; 1443 } 1444 } 1445 1446 void 1447 otus_watchdog(struct ifnet *ifp) 1448 { 1449 struct otus_softc *sc = ifp->if_softc; 1450 1451 ifp->if_timer = 0; 1452 1453 if (sc->sc_tx_timer > 0) { 1454 if (--sc->sc_tx_timer == 0) { 1455 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1456 /* otus_init(ifp); XXX needs a process context! */ 1457 ifp->if_oerrors++; 1458 return; 1459 } 1460 ifp->if_timer = 1; 1461 } 1462 ieee80211_watchdog(ifp); 1463 } 1464 1465 int 1466 otus_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1467 { 1468 struct otus_softc *sc = ifp->if_softc; 1469 struct ieee80211com *ic = &sc->sc_ic; 1470 struct ifaddr *ifa; 1471 struct ifreq *ifr; 1472 int s, error = 0; 1473 1474 s = splnet(); 1475 1476 switch (cmd) { 1477 case SIOCSIFADDR: 1478 ifa = (struct ifaddr *)data; 1479 ifp->if_flags |= IFF_UP; 1480 #ifdef INET 1481 if (ifa->ifa_addr->sa_family == AF_INET) 1482 arp_ifinit(&ic->ic_ac, ifa); 1483 #endif 1484 /* FALLTHROUGH */ 1485 case SIOCSIFFLAGS: 1486 if (ifp->if_flags & IFF_UP) { 1487 if ((ifp->if_flags & IFF_RUNNING) && 1488 ((ifp->if_flags ^ sc->sc_if_flags) & 1489 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1490 otus_set_multi(sc); 1491 } else if (!(ifp->if_flags & IFF_RUNNING)) 1492 otus_init(ifp); 1493 1494 } else if (ifp->if_flags & IFF_RUNNING) 1495 otus_stop(ifp); 1496 1497 sc->sc_if_flags = ifp->if_flags; 1498 break; 1499 case SIOCADDMULTI: 1500 case SIOCDELMULTI: 1501 ifr = (struct ifreq *)data; 1502 error = (cmd == SIOCADDMULTI) ? 1503 ether_addmulti(ifr, &ic->ic_ac) : 1504 ether_delmulti(ifr, &ic->ic_ac); 1505 if (error == ENETRESET) 1506 error = 0; 1507 break; 1508 case SIOCS80211CHANNEL: 1509 error = ieee80211_ioctl(ifp, cmd, data); 1510 if (error == ENETRESET && 1511 ic->ic_opmode == IEEE80211_M_MONITOR) { 1512 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1513 (IFF_UP | IFF_RUNNING)) 1514 otus_set_chan(sc, ic->ic_ibss_chan, 0); 1515 error = 0; 1516 } 1517 break; 1518 default: 1519 error = ieee80211_ioctl(ifp, cmd, data); 1520 } 1521 1522 if (error == ENETRESET) { 1523 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1524 (IFF_UP | IFF_RUNNING)) 1525 otus_init(ifp); 1526 error = 0; 1527 } 1528 1529 splx(s); 1530 return error; 1531 } 1532 1533 int 1534 otus_set_multi(struct otus_softc *sc) 1535 { 1536 struct arpcom *ac = &sc->sc_ic.ic_ac; 1537 struct ifnet *ifp = &ac->ac_if; 1538 struct ether_multi *enm; 1539 struct ether_multistep step; 1540 uint32_t lo, hi; 1541 uint8_t bit; 1542 1543 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1544 lo = hi = 0xffffffff; 1545 goto done; 1546 } 1547 lo = hi = 0; 1548 ETHER_FIRST_MULTI(step, ac, enm); 1549 while (enm != NULL) { 1550 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1551 ifp->if_flags |= IFF_ALLMULTI; 1552 lo = hi = 0xffffffff; 1553 goto done; 1554 } 1555 bit = enm->enm_addrlo[5] >> 2; 1556 if (bit < 32) 1557 lo |= 1 << bit; 1558 else 1559 hi |= 1 << (bit - 32); 1560 ETHER_NEXT_MULTI(step, enm); 1561 } 1562 done: 1563 hi |= 1 << 31; /* Make sure the broadcast bit is set. */ 1564 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_L, lo); 1565 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_H, hi); 1566 return otus_write_barrier(sc); 1567 } 1568 1569 void 1570 otus_updateedca(struct ieee80211com *ic) 1571 { 1572 /* Do it in a process context. */ 1573 otus_do_async(ic->ic_softc, otus_updateedca_cb, NULL, 0); 1574 } 1575 1576 /* ARGSUSED */ 1577 void 1578 otus_updateedca_cb(struct otus_softc *sc, void *arg) 1579 { 1580 #define EXP2(val) ((1 << (val)) - 1) 1581 #define AIFS(val) ((val) * 9 + 10) 1582 struct ieee80211com *ic = &sc->sc_ic; 1583 const struct ieee80211_edca_ac_params *edca; 1584 int s; 1585 1586 s = splnet(); 1587 1588 edca = (ic->ic_flags & IEEE80211_F_QOS) ? 1589 ic->ic_edca_ac : otus_edca_def; 1590 1591 /* Set CWmin/CWmax values. */ 1592 otus_write(sc, AR_MAC_REG_AC0_CW, 1593 EXP2(edca[EDCA_AC_BE].ac_ecwmax) << 16 | 1594 EXP2(edca[EDCA_AC_BE].ac_ecwmin)); 1595 otus_write(sc, AR_MAC_REG_AC1_CW, 1596 EXP2(edca[EDCA_AC_BK].ac_ecwmax) << 16 | 1597 EXP2(edca[EDCA_AC_BK].ac_ecwmin)); 1598 otus_write(sc, AR_MAC_REG_AC2_CW, 1599 EXP2(edca[EDCA_AC_VI].ac_ecwmax) << 16 | 1600 EXP2(edca[EDCA_AC_VI].ac_ecwmin)); 1601 otus_write(sc, AR_MAC_REG_AC3_CW, 1602 EXP2(edca[EDCA_AC_VO].ac_ecwmax) << 16 | 1603 EXP2(edca[EDCA_AC_VO].ac_ecwmin)); 1604 otus_write(sc, AR_MAC_REG_AC4_CW, /* Special TXQ. */ 1605 EXP2(edca[EDCA_AC_VO].ac_ecwmax) << 16 | 1606 EXP2(edca[EDCA_AC_VO].ac_ecwmin)); 1607 1608 /* Set AIFSN values. */ 1609 otus_write(sc, AR_MAC_REG_AC1_AC0_AIFS, 1610 AIFS(edca[EDCA_AC_VI].ac_aifsn) << 24 | 1611 AIFS(edca[EDCA_AC_BK].ac_aifsn) << 12 | 1612 AIFS(edca[EDCA_AC_BE].ac_aifsn)); 1613 otus_write(sc, AR_MAC_REG_AC3_AC2_AIFS, 1614 AIFS(edca[EDCA_AC_VO].ac_aifsn) << 16 | /* Special TXQ. */ 1615 AIFS(edca[EDCA_AC_VO].ac_aifsn) << 4 | 1616 AIFS(edca[EDCA_AC_VI].ac_aifsn) >> 8); 1617 1618 /* Set TXOP limit. */ 1619 otus_write(sc, AR_MAC_REG_AC1_AC0_TXOP, 1620 edca[EDCA_AC_BK].ac_txoplimit << 16 | 1621 edca[EDCA_AC_BE].ac_txoplimit); 1622 otus_write(sc, AR_MAC_REG_AC3_AC2_TXOP, 1623 edca[EDCA_AC_VO].ac_txoplimit << 16 | 1624 edca[EDCA_AC_VI].ac_txoplimit); 1625 1626 splx(s); 1627 1628 (void)otus_write_barrier(sc); 1629 #undef AIFS 1630 #undef EXP2 1631 } 1632 1633 void 1634 otus_updateslot(struct ieee80211com *ic) 1635 { 1636 /* Do it in a process context. */ 1637 otus_do_async(ic->ic_softc, otus_updateslot_cb, NULL, 0); 1638 } 1639 1640 /* ARGSUSED */ 1641 void 1642 otus_updateslot_cb(struct otus_softc *sc, void *arg) 1643 { 1644 uint32_t slottime; 1645 1646 slottime = (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1647 otus_write(sc, AR_MAC_REG_SLOT_TIME, slottime << 10); 1648 (void)otus_write_barrier(sc); 1649 } 1650 1651 int 1652 otus_init_mac(struct otus_softc *sc) 1653 { 1654 int error; 1655 1656 otus_write(sc, AR_MAC_REG_ACK_EXTENSION, 0x40); 1657 otus_write(sc, AR_MAC_REG_RETRY_MAX, 0); 1658 otus_write(sc, AR_MAC_REG_SNIFFER, 0x2000000); 1659 otus_write(sc, AR_MAC_REG_RX_THRESHOLD, 0xc1f80); 1660 otus_write(sc, AR_MAC_REG_RX_PE_DELAY, 0x70); 1661 otus_write(sc, AR_MAC_REG_EIFS_AND_SIFS, 0xa144000); 1662 otus_write(sc, AR_MAC_REG_SLOT_TIME, 9 << 10); 1663 otus_write(sc, 0x1c3b2c, 0x19000000); 1664 /* NAV protects ACK only (in TXOP). */ 1665 otus_write(sc, 0x1c3b38, 0x201); 1666 /* Set beacon Tx power to 0x7. */ 1667 otus_write(sc, AR_MAC_REG_BCN_HT1, 0x8000170); 1668 otus_write(sc, AR_MAC_REG_BACKOFF_PROTECT, 0x105); 1669 otus_write(sc, 0x1c3b9c, 0x10000a); 1670 /* Filter any control frames, BAR is bit 24. */ 1671 otus_write(sc, 0x1c368c, 0x0500ffff); 1672 otus_write(sc, 0x1c3c40, 0x1); 1673 otus_write(sc, AR_MAC_REG_BASIC_RATE, 0x150f); 1674 otus_write(sc, AR_MAC_REG_MANDATORY_RATE, 0x150f); 1675 otus_write(sc, AR_MAC_REG_RTS_CTS_RATE, 0x10b01bb); 1676 otus_write(sc, 0x1c3694, 0x4003c1e); 1677 /* Enable LED0 and LED1. */ 1678 otus_write(sc, 0x1d0100, 0x3); 1679 otus_write(sc, 0x1d0104, 0x3); 1680 /* Switch MAC to OTUS interface. */ 1681 otus_write(sc, 0x1c3600, 0x3); 1682 otus_write(sc, 0x1c3c50, 0xffff); 1683 otus_write(sc, 0x1c3680, 0xf00008); 1684 /* Disable Rx timeout (workaround). */ 1685 otus_write(sc, 0x1c362c, 0); 1686 1687 /* Set USB Rx stream mode maximum frame number to 2. */ 1688 otus_write(sc, 0x1e1110, 0x4); 1689 /* Set USB Rx stream mode timeout to 10us. */ 1690 otus_write(sc, 0x1e1114, 0x80); 1691 1692 /* Set clock frequency to 88/80MHz. */ 1693 otus_write(sc, 0x1d4008, 0x73); 1694 /* Set WLAN DMA interrupt mode: generate intr per packet. */ 1695 otus_write(sc, 0x1c3d7c, 0x110011); 1696 otus_write(sc, 0x1c3bb0, 0x4); 1697 otus_write(sc, AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141e0f48); 1698 1699 /* Disable HW decryption for now. */ 1700 otus_write(sc, 0x1c3678, 0x78); 1701 1702 if ((error = otus_write_barrier(sc)) != 0) 1703 return error; 1704 1705 /* Set default EDCA parameters. */ 1706 otus_updateedca_cb(sc, NULL); 1707 1708 return 0; 1709 } 1710 1711 /* 1712 * Return default value for PHY register based on current operating mode. 1713 */ 1714 uint32_t 1715 otus_phy_get_def(struct otus_softc *sc, uint32_t reg) 1716 { 1717 int i; 1718 1719 for (i = 0; i < nitems(ar5416_phy_regs); i++) 1720 if (AR_PHY(ar5416_phy_regs[i]) == reg) 1721 return sc->phy_vals[i]; 1722 return 0; /* Register not found. */ 1723 } 1724 1725 /* 1726 * Update PHY's programming based on vendor-specific data stored in EEPROM. 1727 * This is for FEM-type devices only. 1728 */ 1729 int 1730 otus_set_board_values(struct otus_softc *sc, struct ieee80211_channel *c) 1731 { 1732 const struct ModalEepHeader *eep; 1733 uint32_t tmp, offset; 1734 1735 if (IEEE80211_IS_CHAN_5GHZ(c)) 1736 eep = &sc->eeprom.modalHeader[0]; 1737 else 1738 eep = &sc->eeprom.modalHeader[1]; 1739 1740 /* Offset of chain 2. */ 1741 offset = 2 * 0x1000; 1742 1743 tmp = letoh32(eep->antCtrlCommon); 1744 otus_write(sc, AR_PHY_SWITCH_COM, tmp); 1745 1746 tmp = letoh32(eep->antCtrlChain[0]); 1747 otus_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp); 1748 1749 tmp = letoh32(eep->antCtrlChain[1]); 1750 otus_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp); 1751 1752 if (1 /* sc->sc_sco == AR_SCO_SCN */) { 1753 tmp = otus_phy_get_def(sc, AR_PHY_SETTLING); 1754 tmp &= ~(0x7f << 7); 1755 tmp |= (eep->switchSettling & 0x7f) << 7; 1756 otus_write(sc, AR_PHY_SETTLING, tmp); 1757 } 1758 1759 tmp = otus_phy_get_def(sc, AR_PHY_DESIRED_SZ); 1760 tmp &= ~0xffff; 1761 tmp |= eep->pgaDesiredSize << 8 | eep->adcDesiredSize; 1762 otus_write(sc, AR_PHY_DESIRED_SZ, tmp); 1763 1764 tmp = eep->txEndToXpaOff << 24 | eep->txEndToXpaOff << 16 | 1765 eep->txFrameToXpaOn << 8 | eep->txFrameToXpaOn; 1766 otus_write(sc, AR_PHY_RF_CTL4, tmp); 1767 1768 tmp = otus_phy_get_def(sc, AR_PHY_RF_CTL3); 1769 tmp &= ~(0xff << 16); 1770 tmp |= eep->txEndToRxOn << 16; 1771 otus_write(sc, AR_PHY_RF_CTL3, tmp); 1772 1773 tmp = otus_phy_get_def(sc, AR_PHY_CCA); 1774 tmp &= ~(0x7f << 12); 1775 tmp |= (eep->thresh62 & 0x7f) << 12; 1776 otus_write(sc, AR_PHY_CCA, tmp); 1777 1778 tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN); 1779 tmp &= ~(0x3f << 12); 1780 tmp |= (eep->txRxAttenCh[0] & 0x3f) << 12; 1781 otus_write(sc, AR_PHY_RXGAIN, tmp); 1782 1783 tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN + offset); 1784 tmp &= ~(0x3f << 12); 1785 tmp |= (eep->txRxAttenCh[1] & 0x3f) << 12; 1786 otus_write(sc, AR_PHY_RXGAIN + offset, tmp); 1787 1788 tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ); 1789 tmp &= ~(0x3f << 18); 1790 tmp |= (eep->rxTxMarginCh[0] & 0x3f) << 18; 1791 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1792 tmp &= ~(0xf << 10); 1793 tmp |= (eep->bswMargin[0] & 0xf) << 10; 1794 } 1795 otus_write(sc, AR_PHY_GAIN_2GHZ, tmp); 1796 1797 tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ + offset); 1798 tmp &= ~(0x3f << 18); 1799 tmp |= (eep->rxTxMarginCh[1] & 0x3f) << 18; 1800 otus_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp); 1801 1802 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4); 1803 tmp &= ~(0x3f << 5 | 0x1f); 1804 tmp |= (eep->iqCalICh[0] & 0x3f) << 5 | (eep->iqCalQCh[0] & 0x1f); 1805 otus_write(sc, AR_PHY_TIMING_CTRL4, tmp); 1806 1807 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4 + offset); 1808 tmp &= ~(0x3f << 5 | 0x1f); 1809 tmp |= (eep->iqCalICh[1] & 0x3f) << 5 | (eep->iqCalQCh[1] & 0x1f); 1810 otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp); 1811 1812 tmp = otus_phy_get_def(sc, AR_PHY_TPCRG1); 1813 tmp &= ~(0xf << 16); 1814 tmp |= (eep->xpd & 0xf) << 16; 1815 otus_write(sc, AR_PHY_TPCRG1, tmp); 1816 1817 return otus_write_barrier(sc); 1818 } 1819 1820 int 1821 otus_program_phy(struct otus_softc *sc, struct ieee80211_channel *c) 1822 { 1823 const uint32_t *vals; 1824 int error, i; 1825 1826 /* Select PHY programming based on band and bandwidth. */ 1827 if (IEEE80211_IS_CHAN_2GHZ(c)) 1828 vals = ar5416_phy_vals_2ghz_20mhz; 1829 else 1830 vals = ar5416_phy_vals_5ghz_20mhz; 1831 for (i = 0; i < nitems(ar5416_phy_regs); i++) 1832 otus_write(sc, AR_PHY(ar5416_phy_regs[i]), vals[i]); 1833 sc->phy_vals = vals; 1834 1835 if (sc->eeprom.baseEepHeader.deviceType == 0x80) /* FEM */ 1836 if ((error = otus_set_board_values(sc, c)) != 0) 1837 return error; 1838 1839 /* Initial Tx power settings. */ 1840 otus_write(sc, AR_PHY_POWER_TX_RATE_MAX, 0x7f); 1841 otus_write(sc, AR_PHY_POWER_TX_RATE1, 0x3f3f3f3f); 1842 otus_write(sc, AR_PHY_POWER_TX_RATE2, 0x3f3f3f3f); 1843 otus_write(sc, AR_PHY_POWER_TX_RATE3, 0x3f3f3f3f); 1844 otus_write(sc, AR_PHY_POWER_TX_RATE4, 0x3f3f3f3f); 1845 otus_write(sc, AR_PHY_POWER_TX_RATE5, 0x3f3f3f3f); 1846 otus_write(sc, AR_PHY_POWER_TX_RATE6, 0x3f3f3f3f); 1847 otus_write(sc, AR_PHY_POWER_TX_RATE7, 0x3f3f3f3f); 1848 otus_write(sc, AR_PHY_POWER_TX_RATE8, 0x3f3f3f3f); 1849 otus_write(sc, AR_PHY_POWER_TX_RATE9, 0x3f3f3f3f); 1850 1851 if (IEEE80211_IS_CHAN_2GHZ(c)) 1852 otus_write(sc, 0x1d4014, 0x5163); 1853 else 1854 otus_write(sc, 0x1d4014, 0x5143); 1855 1856 return otus_write_barrier(sc); 1857 } 1858 1859 static __inline uint8_t 1860 otus_reverse_bits(uint8_t v) 1861 { 1862 v = ((v >> 1) & 0x55) | ((v & 0x55) << 1); 1863 v = ((v >> 2) & 0x33) | ((v & 0x33) << 2); 1864 v = ((v >> 4) & 0x0f) | ((v & 0x0f) << 4); 1865 return v; 1866 } 1867 1868 int 1869 otus_set_rf_bank4(struct otus_softc *sc, struct ieee80211_channel *c) 1870 { 1871 uint8_t chansel, d0, d1; 1872 uint16_t data; 1873 int error; 1874 1875 d0 = 0; 1876 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1877 chansel = (c->ic_freq - 4800) / 5; 1878 if (chansel & 1) 1879 d0 |= AR_BANK4_AMODE_REFSEL(2); 1880 else 1881 d0 |= AR_BANK4_AMODE_REFSEL(1); 1882 } else { 1883 d0 |= AR_BANK4_AMODE_REFSEL(2); 1884 if (c->ic_freq == 2484) { /* CH 14 */ 1885 d0 |= AR_BANK4_BMODE_LF_SYNTH_FREQ; 1886 chansel = 10 + (c->ic_freq - 2274) / 5; 1887 } else 1888 chansel = 16 + (c->ic_freq - 2272) / 5; 1889 chansel <<= 2; 1890 } 1891 d0 |= AR_BANK4_ADDR(1) | AR_BANK4_CHUP; 1892 d1 = otus_reverse_bits(chansel); 1893 1894 /* Write bits 0-4 of d0 and d1. */ 1895 data = (d1 & 0x1f) << 5 | (d0 & 0x1f); 1896 otus_write(sc, AR_PHY(44), data); 1897 /* Write bits 5-7 of d0 and d1. */ 1898 data = (d1 >> 5) << 5 | (d0 >> 5); 1899 otus_write(sc, AR_PHY(58), data); 1900 1901 if ((error = otus_write_barrier(sc)) == 0) 1902 usbd_delay_ms(sc->sc_udev, 10); 1903 return error; 1904 } 1905 1906 void 1907 otus_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 1908 { 1909 #define COEFF_SCALE_SHIFT 24 1910 uint32_t exp, man; 1911 1912 /* exponent = 14 - floor(log2(coeff)) */ 1913 for (exp = 31; exp > 0; exp--) 1914 if (coeff & (1 << exp)) 1915 break; 1916 KASSERT(exp != 0); 1917 exp = 14 - (exp - COEFF_SCALE_SHIFT); 1918 1919 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 1920 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 1921 1922 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 1923 *exponent = exp - 16; 1924 #undef COEFF_SCALE_SHIFT 1925 } 1926 1927 int 1928 otus_set_chan(struct otus_softc *sc, struct ieee80211_channel *c, int assoc) 1929 { 1930 struct ieee80211com *ic = &sc->sc_ic; 1931 struct ar_cmd_frequency cmd; 1932 struct ar_rsp_frequency rsp; 1933 const uint32_t *vals; 1934 uint32_t coeff, exp, man, tmp; 1935 uint8_t code; 1936 int error, chan, i; 1937 1938 chan = ieee80211_chan2ieee(ic, c); 1939 DPRINTF(("setting channel %d (%dMHz)\n", chan, c->ic_freq)); 1940 1941 tmp = IEEE80211_IS_CHAN_2GHZ(c) ? 0x105 : 0x104; 1942 otus_write(sc, AR_MAC_REG_DYNAMIC_SIFS_ACK, tmp); 1943 if ((error = otus_write_barrier(sc)) != 0) 1944 return error; 1945 1946 /* Disable BB Heavy Clip. */ 1947 otus_write(sc, AR_PHY_HEAVY_CLIP_ENABLE, 0x200); 1948 if ((error = otus_write_barrier(sc)) != 0) 1949 return error; 1950 1951 /* XXX Is that FREQ_START ? */ 1952 error = otus_cmd(sc, AR_CMD_FREQ_STRAT, NULL, 0, NULL); 1953 if (error != 0) 1954 return error; 1955 1956 /* Reprogram PHY and RF on channel band or bandwidth changes. */ 1957 if (sc->bb_reset || c->ic_flags != sc->sc_curchan->ic_flags) { 1958 DPRINTF(("band switch\n")); 1959 1960 /* Cold/Warm reset BB/ADDA. */ 1961 otus_write(sc, 0x1d4004, sc->bb_reset ? 0x800 : 0x400); 1962 if ((error = otus_write_barrier(sc)) != 0) 1963 return error; 1964 otus_write(sc, 0x1d4004, 0); 1965 if ((error = otus_write_barrier(sc)) != 0) 1966 return error; 1967 sc->bb_reset = 0; 1968 1969 if ((error = otus_program_phy(sc, c)) != 0) { 1970 printf("%s: could not program PHY\n", 1971 sc->sc_dev.dv_xname); 1972 return error; 1973 } 1974 1975 /* Select RF programming based on band. */ 1976 if (IEEE80211_IS_CHAN_5GHZ(c)) 1977 vals = ar5416_banks_vals_5ghz; 1978 else 1979 vals = ar5416_banks_vals_2ghz; 1980 for (i = 0; i < nitems(ar5416_banks_regs); i++) 1981 otus_write(sc, AR_PHY(ar5416_banks_regs[i]), vals[i]); 1982 if ((error = otus_write_barrier(sc)) != 0) { 1983 printf("%s: could not program RF\n", 1984 sc->sc_dev.dv_xname); 1985 return error; 1986 } 1987 code = AR_CMD_RF_INIT; 1988 } else { 1989 code = AR_CMD_FREQUENCY; 1990 } 1991 1992 if ((error = otus_set_rf_bank4(sc, c)) != 0) 1993 return error; 1994 1995 tmp = (sc->txmask == 0x5) ? 0x340 : 0x240; 1996 otus_write(sc, AR_PHY_TURBO, tmp); 1997 if ((error = otus_write_barrier(sc)) != 0) 1998 return error; 1999 2000 /* Send firmware command to set channel. */ 2001 cmd.freq = htole32((uint32_t)c->ic_freq * 1000); 2002 cmd.dynht2040 = htole32(0); 2003 cmd.htena = htole32(1); 2004 /* Set Delta Slope (exponent and mantissa). */ 2005 coeff = (100 << 24) / c->ic_freq; 2006 otus_get_delta_slope(coeff, &exp, &man); 2007 cmd.dsc_exp = htole32(exp); 2008 cmd.dsc_man = htole32(man); 2009 DPRINTF(("ds coeff=%u exp=%u man=%u\n", coeff, exp, man)); 2010 /* For Short GI, coeff is 9/10 that of normal coeff. */ 2011 coeff = (9 * coeff) / 10; 2012 otus_get_delta_slope(coeff, &exp, &man); 2013 cmd.dsc_shgi_exp = htole32(exp); 2014 cmd.dsc_shgi_man = htole32(man); 2015 DPRINTF(("ds shgi coeff=%u exp=%u man=%u\n", coeff, exp, man)); 2016 /* Set wait time for AGC and noise calibration (100 or 200ms). */ 2017 cmd.check_loop_count = assoc ? htole32(2000) : htole32(1000); 2018 DPRINTF(("%s\n", (code == AR_CMD_RF_INIT) ? "RF_INIT" : "FREQUENCY")); 2019 error = otus_cmd(sc, code, &cmd, sizeof cmd, &rsp); 2020 if (error != 0) 2021 return error; 2022 if ((rsp.status & htole32(AR_CAL_ERR_AGC | AR_CAL_ERR_NF_VAL)) != 0) { 2023 DPRINTF(("status=0x%x\n", letoh32(rsp.status))); 2024 /* Force cold reset on next channel. */ 2025 sc->bb_reset = 1; 2026 } 2027 #ifdef OTUS_DEBUG 2028 if (otus_debug) { 2029 printf("calibration status=0x%x\n", letoh32(rsp.status)); 2030 for (i = 0; i < 2; i++) { /* 2 Rx chains */ 2031 /* Sign-extend 9-bit NF values. */ 2032 printf("noisefloor chain %d=%d\n", i, 2033 (((int32_t)letoh32(rsp.nf[i])) << 4) >> 23); 2034 printf("noisefloor ext chain %d=%d\n", i, 2035 ((int32_t)letoh32(rsp.nf_ext[i])) >> 23); 2036 } 2037 } 2038 #endif 2039 sc->sc_curchan = c; 2040 return 0; 2041 } 2042 2043 #ifdef notyet 2044 int 2045 otus_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2046 struct ieee80211_key *k) 2047 { 2048 struct otus_softc *sc = ic->ic_softc; 2049 struct otus_cmd_key cmd; 2050 2051 /* Defer setting of WEP keys until interface is brought up. */ 2052 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 2053 (IFF_UP | IFF_RUNNING)) 2054 return 0; 2055 2056 /* Do it in a process context. */ 2057 cmd.key = *k; 2058 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2059 otus_do_async(sc, otus_set_key_cb, &cmd, sizeof cmd); 2060 return 0; 2061 } 2062 2063 void 2064 otus_set_key_cb(struct otus_softc *sc, void *arg) 2065 { 2066 struct otus_cmd_key *cmd = arg; 2067 struct ieee80211_key *k = &cmd->key; 2068 struct ar_cmd_ekey key; 2069 uint16_t cipher; 2070 int error; 2071 2072 memset(&key, 0, sizeof key); 2073 if (k->k_flags & IEEE80211_KEY_GROUP) { 2074 key.uid = htole16(k->k_id); 2075 IEEE80211_ADDR_COPY(key.macaddr, sc->sc_ic.ic_myaddr); 2076 key.macaddr[0] |= 0x80; 2077 } else { 2078 key.uid = htole16(OTUS_UID(cmd->associd)); 2079 IEEE80211_ADDR_COPY(key.macaddr, ni->ni_macaddr); 2080 } 2081 key.kix = htole16(0); 2082 /* Map net80211 cipher to hardware. */ 2083 switch (k->k_cipher) { 2084 case IEEE80211_CIPHER_WEP40: 2085 cipher = AR_CIPHER_WEP64; 2086 break; 2087 case IEEE80211_CIPHER_WEP104: 2088 cipher = AR_CIPHER_WEP128; 2089 break; 2090 case IEEE80211_CIPHER_TKIP: 2091 cipher = AR_CIPHER_TKIP; 2092 break; 2093 case IEEE80211_CIPHER_CCMP: 2094 cipher = AR_CIPHER_AES; 2095 break; 2096 default: 2097 return; 2098 } 2099 key.cipher = htole16(cipher); 2100 memcpy(key.key, k->k_key, MIN(k->k_len, 16)); 2101 error = otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL); 2102 if (error != 0 || k->k_cipher != IEEE80211_CIPHER_TKIP) 2103 return; 2104 2105 /* TKIP: set Tx/Rx MIC Key. */ 2106 key.kix = htole16(1); 2107 memcpy(key.key, k->k_key + 16, 16); 2108 (void)otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL); 2109 } 2110 2111 void 2112 otus_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2113 struct ieee80211_key *k) 2114 { 2115 struct otus_softc *sc = ic->ic_softc; 2116 struct otus_cmd_key cmd; 2117 2118 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 2119 ic->ic_state != IEEE80211_S_RUN) 2120 return; /* Nothing to do. */ 2121 2122 /* Do it in a process context. */ 2123 cmd.key = *k; 2124 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2125 otus_do_async(sc, otus_delete_key_cb, &cmd, sizeof cmd); 2126 } 2127 2128 void 2129 otus_delete_key_cb(struct otus_softc *sc, void *arg) 2130 { 2131 struct otus_cmd_key *cmd = arg; 2132 struct ieee80211_key *k = &cmd->key; 2133 uint32_t uid; 2134 2135 if (k->k_flags & IEEE80211_KEY_GROUP) 2136 uid = htole32(k->k_id); 2137 else 2138 uid = htole32(OTUS_UID(cmd->associd)); 2139 (void)otus_cmd(sc, AR_CMD_DKEY, &uid, sizeof uid, NULL); 2140 } 2141 #endif 2142 2143 void 2144 otus_calibrate_to(void *arg) 2145 { 2146 struct otus_softc *sc = arg; 2147 struct ieee80211com *ic = &sc->sc_ic; 2148 struct ieee80211_node *ni; 2149 int s; 2150 2151 s = splnet(); 2152 ni = ic->ic_bss; 2153 ieee80211_amrr_choose(&sc->amrr, ni, &((struct otus_node *)ni)->amn); 2154 splx(s); 2155 2156 timeout_add_sec(&sc->calib_to, 1); 2157 } 2158 2159 int 2160 otus_set_bssid(struct otus_softc *sc, const uint8_t *bssid) 2161 { 2162 otus_write(sc, AR_MAC_REG_BSSID_L, 2163 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 2164 otus_write(sc, AR_MAC_REG_BSSID_H, 2165 bssid[4] | bssid[5] << 8); 2166 return otus_write_barrier(sc); 2167 } 2168 2169 int 2170 otus_set_macaddr(struct otus_softc *sc, const uint8_t *addr) 2171 { 2172 otus_write(sc, AR_MAC_REG_MAC_ADDR_L, 2173 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2174 otus_write(sc, AR_MAC_REG_MAC_ADDR_H, 2175 addr[4] | addr[5] << 8); 2176 return otus_write_barrier(sc); 2177 } 2178 2179 /* Default single-LED. */ 2180 void 2181 otus_led_newstate_type1(struct otus_softc *sc) 2182 { 2183 /* TBD */ 2184 } 2185 2186 /* NETGEAR, dual-LED. */ 2187 void 2188 otus_led_newstate_type2(struct otus_softc *sc) 2189 { 2190 /* TBD */ 2191 } 2192 2193 /* NETGEAR, single-LED/3 colors (blue, red, purple.) */ 2194 void 2195 otus_led_newstate_type3(struct otus_softc *sc) 2196 { 2197 struct ieee80211com *ic = &sc->sc_ic; 2198 uint32_t state = sc->led_state; 2199 2200 if (ic->ic_state == IEEE80211_S_INIT) { 2201 state = 0; /* LED off. */ 2202 } else if (ic->ic_state == IEEE80211_S_RUN) { 2203 /* Associated, LED always on. */ 2204 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) 2205 state = AR_LED0_ON; /* 2GHz=>Red. */ 2206 else 2207 state = AR_LED1_ON; /* 5GHz=>Blue. */ 2208 } else { 2209 /* Scanning, blink LED. */ 2210 state ^= AR_LED0_ON | AR_LED1_ON; 2211 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) 2212 state &= ~AR_LED1_ON; 2213 else 2214 state &= ~AR_LED0_ON; 2215 } 2216 if (state != sc->led_state) { 2217 otus_write(sc, 0x1d0104, state); 2218 if (otus_write_barrier(sc) == 0) 2219 sc->led_state = state; 2220 } 2221 } 2222 2223 int 2224 otus_init(struct ifnet *ifp) 2225 { 2226 struct otus_softc *sc = ifp->if_softc; 2227 struct ieee80211com *ic = &sc->sc_ic; 2228 int error; 2229 2230 /* Init host command ring. */ 2231 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2232 2233 if ((error = otus_init_mac(sc)) != 0) { 2234 printf("%s: could not initialize MAC\n", sc->sc_dev.dv_xname); 2235 return error; 2236 } 2237 2238 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2239 (void)otus_set_macaddr(sc, ic->ic_myaddr); 2240 2241 switch (ic->ic_opmode) { 2242 #ifdef notyet 2243 #ifndef IEEE80211_STA_ONLY 2244 case IEEE80211_M_HOSTAP: 2245 otus_write(sc, 0x1c3700, 0x0f0000a1); 2246 otus_write(sc, 0x1c3c40, 0x1); 2247 break; 2248 case IEEE80211_M_IBSS: 2249 otus_write(sc, 0x1c3700, 0x0f000000); 2250 otus_write(sc, 0x1c3c40, 0x1); 2251 break; 2252 #endif 2253 #endif 2254 case IEEE80211_M_STA: 2255 otus_write(sc, 0x1c3700, 0x0f000002); 2256 otus_write(sc, 0x1c3c40, 0x1); 2257 break; 2258 default: 2259 break; 2260 } 2261 otus_write(sc, AR_MAC_REG_SNIFFER, 2262 (ic->ic_opmode == IEEE80211_M_MONITOR) ? 0x2000001 : 0x2000000); 2263 (void)otus_write_barrier(sc); 2264 2265 sc->bb_reset = 1; /* Force cold reset. */ 2266 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2267 if ((error = otus_set_chan(sc, ic->ic_ibss_chan, 0)) != 0) { 2268 printf("%s: could not set channel\n", sc->sc_dev.dv_xname); 2269 return error; 2270 } 2271 2272 /* Start Rx. */ 2273 otus_write(sc, 0x1c3d30, 0x100); 2274 (void)otus_write_barrier(sc); 2275 2276 ifp->if_flags &= ~IFF_OACTIVE; 2277 ifp->if_flags |= IFF_RUNNING; 2278 2279 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2280 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2281 else 2282 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2283 2284 return 0; 2285 } 2286 2287 void 2288 otus_stop(struct ifnet *ifp) 2289 { 2290 struct otus_softc *sc = ifp->if_softc; 2291 struct ieee80211com *ic = &sc->sc_ic; 2292 int s; 2293 2294 sc->sc_tx_timer = 0; 2295 ifp->if_timer = 0; 2296 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2297 2298 timeout_del(&sc->scan_to); 2299 timeout_del(&sc->calib_to); 2300 2301 s = splusb(); 2302 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2303 /* Wait for all queued asynchronous commands to complete. */ 2304 while (sc->cmdq.queued > 0) 2305 tsleep(&sc->cmdq, 0, "cmdq", 0); 2306 splx(s); 2307 2308 /* Stop Rx. */ 2309 otus_write(sc, 0x1c3d30, 0); 2310 (void)otus_write_barrier(sc); 2311 2312 sc->tx_queued = 0; 2313 } 2314