1 /* $OpenBSD: if_mue.c,v 1.5 2018/09/19 07:47:54 mestre Exp $ */ 2 3 /* 4 * Copyright (c) 2018 Kevin Lo <kevlo@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* Driver for Microchip LAN7500/LAN7800 chipsets. */ 20 21 #include "bpfilter.h" 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/sockio.h> 26 #include <sys/rwlock.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 31 #include <sys/device.h> 32 33 #include <machine/bus.h> 34 35 #include <net/if.h> 36 #include <net/if_dl.h> 37 #include <net/if_media.h> 38 39 #if NBPFILTER > 0 40 #include <net/bpf.h> 41 #endif 42 43 #include <netinet/in.h> 44 #include <netinet/if_ether.h> 45 46 #include <dev/mii/miivar.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdi_util.h> 51 #include <dev/usb/usbdivar.h> 52 #include <dev/usb/usbdevs.h> 53 54 #include <dev/usb/if_muereg.h> 55 56 #ifdef MUE_DEBUG 57 #define DPRINTF(x) do { if (muedebug) printf x; } while (0) 58 #define DPRINTFN(n,x) do { if (muedebug >= (n)) printf x; } while (0) 59 int muedebug = 0; 60 #else 61 #define DPRINTF(x) 62 #define DPRINTFN(n,x) 63 #endif 64 65 /* 66 * Various supported device vendors/products. 67 */ 68 struct mue_type { 69 struct usb_devno mue_dev; 70 uint16_t mue_flags; 71 #define LAN7500 0x0001 /* LAN7500 */ 72 }; 73 74 const struct mue_type mue_devs[] = { 75 { { USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN7500 }, LAN7500 }, 76 { { USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN7505 }, LAN7500 }, 77 { { USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN7800 }, 0 }, 78 { { USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN7801 }, 0 }, 79 { { USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN7850 }, 0 } 80 }; 81 82 #define mue_lookup(v, p) ((struct mue_type *)usb_lookup(mue_devs, v, p)) 83 84 int mue_match(struct device *, void *, void *); 85 void mue_attach(struct device *, struct device *, void *); 86 int mue_detach(struct device *, int); 87 88 struct cfdriver mue_cd = { 89 NULL, "mue", DV_IFNET 90 }; 91 92 const struct cfattach mue_ca = { 93 sizeof(struct mue_softc), mue_match, mue_attach, mue_detach 94 }; 95 96 uint32_t mue_csr_read(struct mue_softc *, uint32_t); 97 int mue_csr_write(struct mue_softc *, uint32_t, uint32_t); 98 99 void mue_lock_mii(struct mue_softc *); 100 void mue_unlock_mii(struct mue_softc *); 101 102 int mue_mii_wait(struct mue_softc *); 103 int mue_miibus_readreg(struct device *, int, int); 104 void mue_miibus_writereg(struct device *, int, int, int); 105 void mue_miibus_statchg(struct device *); 106 int mue_ifmedia_upd(struct ifnet *); 107 void mue_ifmedia_sts(struct ifnet *, struct ifmediareq *); 108 109 int mue_eeprom_wait(struct mue_softc *); 110 uint8_t mue_eeprom_getbyte(struct mue_softc *, int, uint8_t *); 111 int mue_read_eeprom(struct mue_softc *, caddr_t, int, int); 112 int mue_dataport_wait(struct mue_softc *); 113 void mue_dataport_write(struct mue_softc *, uint32_t, uint32_t, 114 uint32_t, uint32_t *); 115 void mue_init_ltm(struct mue_softc *); 116 int mue_chip_init(struct mue_softc *); 117 void mue_set_macaddr(struct mue_softc *); 118 119 int mue_rx_list_init(struct mue_softc *); 120 int mue_tx_list_init(struct mue_softc *); 121 int mue_open_pipes(struct mue_softc *); 122 int mue_encap(struct mue_softc *, struct mbuf *, int); 123 void mue_iff(struct mue_softc *); 124 void mue_rxeof(struct usbd_xfer *, void *, usbd_status); 125 void mue_txeof(struct usbd_xfer *, void *, usbd_status); 126 127 void mue_init(void *); 128 int mue_ioctl(struct ifnet *, u_long, caddr_t); 129 void mue_watchdog(struct ifnet *); 130 void mue_reset(struct mue_softc *); 131 void mue_start(struct ifnet *); 132 void mue_stop(struct mue_softc *); 133 void mue_tick(void *); 134 void mue_tick_task(void *); 135 136 #define MUE_SETBIT(sc, reg, x) \ 137 mue_csr_write(sc, reg, mue_csr_read(sc, reg) | (x)) 138 139 #define MUE_CLRBIT(sc, reg, x) \ 140 mue_csr_write(sc, reg, mue_csr_read(sc, reg) & ~(x)) 141 142 #if defined(__arm__) || defined(__arm64__) 143 144 #include <dev/ofw/openfirm.h> 145 146 void 147 mue_enaddr_OF(struct mue_softc *sc) 148 { 149 char *device = "/axi/usb/hub/ethernet"; 150 char prop[64]; 151 int node; 152 153 if (sc->mue_dev.dv_unit != 0) 154 return; 155 156 /* Get the Raspberry Pi MAC address from FDT. */ 157 if ((node = OF_finddevice("/aliases")) == -1) 158 return; 159 if (OF_getprop(node, "ethernet0", prop, sizeof(prop)) > 0 || 160 OF_getprop(node, "ethernet", prop, sizeof(prop)) > 0) 161 device = prop; 162 163 if ((node = OF_finddevice(device)) == -1) 164 return; 165 if (OF_getprop(node, "local-mac-address", sc->arpcom.ac_enaddr, 166 sizeof(sc->arpcom.ac_enaddr)) != sizeof(sc->arpcom.ac_enaddr)) { 167 OF_getprop(node, "mac-address", sc->arpcom.ac_enaddr, 168 sizeof(sc->arpcom.ac_enaddr)); 169 } 170 } 171 #else 172 #define mue_enaddr_OF(x) do {} while(0) 173 #endif 174 175 uint32_t 176 mue_csr_read(struct mue_softc *sc, uint32_t reg) 177 { 178 usb_device_request_t req; 179 usbd_status err; 180 uDWord val; 181 182 if (usbd_is_dying(sc->mue_udev)) 183 return (0); 184 185 USETDW(val, 0); 186 req.bmRequestType = UT_READ_VENDOR_DEVICE; 187 req.bRequest = MUE_UR_READREG; 188 USETW(req.wValue, 0); 189 USETW(req.wIndex, reg); 190 USETW(req.wLength, 4); 191 192 err = usbd_do_request(sc->mue_udev, &req, &val); 193 if (err) { 194 DPRINTF(("%s: mue_csr_read: reg=0x%x err=%s\n", 195 sc->mue_dev.dv_xname, reg, usbd_errstr(err))); 196 return (0); 197 } 198 199 return (UGETDW(val)); 200 } 201 202 int 203 mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval) 204 { 205 usb_device_request_t req; 206 usbd_status err; 207 uDWord val; 208 209 if (usbd_is_dying(sc->mue_udev)) 210 return (0); 211 212 USETDW(val, aval); 213 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 214 req.bRequest = MUE_UR_WRITEREG; 215 USETW(req.wValue, 0); 216 USETW(req.wIndex, reg); 217 USETW(req.wLength, 4); 218 219 err = usbd_do_request(sc->mue_udev, &req, &val); 220 if (err) { 221 DPRINTF(("%s: mue_csr_write: reg=0x%x err=%s\n", 222 sc->mue_dev.dv_xname, reg, usbd_errstr(err))); 223 return (-1); 224 } 225 226 return (0); 227 } 228 229 /* 230 * Get exclusive access to the MII registers. 231 */ 232 void 233 mue_lock_mii(struct mue_softc *sc) 234 { 235 sc->mue_refcnt++; 236 rw_enter_write(&sc->mue_mii_lock); 237 } 238 239 void 240 mue_unlock_mii(struct mue_softc *sc) 241 { 242 rw_exit_write(&sc->mue_mii_lock); 243 if (--sc->mue_refcnt < 0) 244 usb_detach_wakeup(&sc->mue_dev); 245 } 246 247 /* 248 * Wait for the MII to become ready. 249 */ 250 int 251 mue_mii_wait(struct mue_softc *sc) 252 { 253 int ntries; 254 255 for (ntries = 0; ntries < 100; ntries++) { 256 if (!(mue_csr_read(sc, MUE_MII_ACCESS) & MUE_MII_ACCESS_BUSY)) 257 return (0); 258 DELAY(5); 259 } 260 261 printf("%s: MII timed out\n", sc->mue_dev.dv_xname); 262 return (1); 263 } 264 265 int 266 mue_miibus_readreg(struct device *dev, int phy, int reg) 267 { 268 struct mue_softc *sc = (void *)dev; 269 uint32_t val; 270 271 if (usbd_is_dying(sc->mue_udev)) 272 return (0); 273 274 if (sc->mue_phyno != phy) 275 return (0); 276 277 mue_lock_mii(sc); 278 if (mue_mii_wait(sc) != 0) 279 return (0); 280 281 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_READ | 282 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) | 283 MUE_MII_ACCESS_PHYADDR(phy)); 284 285 if (mue_mii_wait(sc) != 0) 286 printf("%s: MII read timed out\n", sc->mue_dev.dv_xname); 287 288 val = mue_csr_read(sc, MUE_MII_DATA); 289 mue_unlock_mii(sc); 290 return (val & 0xffff); 291 } 292 293 void 294 mue_miibus_writereg(struct device *dev, int phy, int reg, int data) 295 { 296 struct mue_softc *sc = (void *)dev; 297 298 if (usbd_is_dying(sc->mue_udev)) 299 return; 300 301 if (sc->mue_phyno != phy) 302 return; 303 304 mue_lock_mii(sc); 305 if (mue_mii_wait(sc) != 0) 306 return; 307 308 mue_csr_write(sc, MUE_MII_DATA, data); 309 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE | 310 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) | 311 MUE_MII_ACCESS_PHYADDR(phy)); 312 313 if (mue_mii_wait(sc) != 0) 314 printf("%s: MII write timed out\n", sc->mue_dev.dv_xname); 315 316 mue_unlock_mii(sc); 317 } 318 319 void 320 mue_miibus_statchg(struct device *dev) 321 { 322 struct mue_softc *sc = (void *)dev; 323 struct mii_data *mii = GET_MII(sc); 324 struct ifnet *ifp = GET_IFP(sc); 325 uint32_t flow, threshold; 326 327 if (mii == NULL || ifp == NULL || 328 (ifp->if_flags & IFF_RUNNING) == 0) 329 return; 330 331 sc->mue_link = 0; 332 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 333 (IFM_ACTIVE | IFM_AVALID)) { 334 switch (IFM_SUBTYPE(mii->mii_media_active)) { 335 case IFM_10_T: 336 case IFM_100_TX: 337 case IFM_1000_T: 338 sc->mue_link++; 339 break; 340 default: 341 break; 342 } 343 } 344 345 /* Lost link, do nothing. */ 346 if (sc->mue_link == 0) 347 return; 348 349 if (!(sc->mue_flags & LAN7500)) { 350 if (sc->mue_udev->speed == USB_SPEED_SUPER) { 351 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 352 /* Disable U2 and enable U1. */ 353 MUE_CLRBIT(sc, MUE_USB_CFG1, 354 MUE_USB_CFG1_DEV_U2_INIT_EN); 355 MUE_SETBIT(sc, MUE_USB_CFG1, 356 MUE_USB_CFG1_DEV_U1_INIT_EN); 357 } else { 358 /* Enable U1 and U2. */ 359 MUE_SETBIT(sc, MUE_USB_CFG1, 360 MUE_USB_CFG1_DEV_U1_INIT_EN | 361 MUE_USB_CFG1_DEV_U2_INIT_EN); 362 } 363 } 364 } 365 366 threshold = 0; 367 flow = 0; 368 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) { 369 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) { 370 flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME; 371 372 /* XXX magic numbers come from Linux driver. */ 373 if (sc->mue_flags & LAN7500) { 374 threshold = 0x820; 375 } else { 376 threshold = 377 (sc->mue_udev->speed == USB_SPEED_SUPER) ? 378 0x817 : 0x211; 379 } 380 } 381 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) 382 flow |= MUE_FLOW_RX_FCEN; 383 } 384 mue_csr_write(sc, (sc->mue_flags & LAN7500) ? 385 MUE_FCT_FLOW : MUE_7800_FCT_FLOW, threshold); 386 387 /* Threshold value should be set before enabling flow. */ 388 mue_csr_write(sc, MUE_FLOW, flow); 389 } 390 391 /* 392 * Set media options. 393 */ 394 int 395 mue_ifmedia_upd(struct ifnet *ifp) 396 { 397 struct mue_softc *sc = ifp->if_softc; 398 struct mii_data *mii = GET_MII(sc); 399 400 if (mii->mii_instance) { 401 struct mii_softc *miisc; 402 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 403 mii_phy_reset(miisc); 404 } 405 return (mii_mediachg(mii)); 406 } 407 408 /* 409 * Report current media status. 410 */ 411 void 412 mue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 413 { 414 struct mue_softc *sc = ifp->if_softc; 415 struct mii_data *mii = GET_MII(sc); 416 417 mii_pollstat(mii); 418 ifmr->ifm_active = mii->mii_media_active; 419 ifmr->ifm_status = mii->mii_media_status; 420 } 421 422 int 423 mue_eeprom_wait(struct mue_softc *sc) 424 { 425 uint32_t val; 426 int ntries; 427 428 for (ntries = 0; ntries < 100; ntries++) { 429 val = mue_csr_read(sc, MUE_E2P_CMD); 430 if (!(val & MUE_E2P_CMD_BUSY) || (val & MUE_E2P_CMD_TIMEOUT)) 431 return (0); 432 DELAY(5); 433 } 434 435 return (1); 436 } 437 438 uint8_t 439 mue_eeprom_getbyte(struct mue_softc *sc, int addr, uint8_t *dest) 440 { 441 uint32_t byte = 0; 442 int ntries; 443 444 for (ntries = 0; ntries < 100; ntries++) { 445 if (!(mue_csr_read(sc, MUE_E2P_CMD) & MUE_E2P_CMD_BUSY)) 446 break; 447 DELAY(5); 448 } 449 450 if (ntries == 100) { 451 printf("%s: EEPROM failed to come ready\n", 452 sc->mue_dev.dv_xname); 453 return (ETIMEDOUT); 454 } 455 456 mue_csr_write(sc, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY | 457 (addr & MUE_E2P_CMD_ADDR_MASK)); 458 459 if (mue_eeprom_wait(sc) != 0) { 460 printf("%s: EEPROM read timed out\n", sc->mue_dev.dv_xname); 461 return (ETIMEDOUT); 462 } 463 464 byte = mue_csr_read(sc, MUE_E2P_DATA); 465 *dest = byte & 0xff; 466 467 return (0); 468 } 469 470 int 471 mue_read_eeprom(struct mue_softc *sc, caddr_t dest, int off, int cnt) 472 { 473 uint32_t val; 474 uint8_t byte = 0; 475 int i, err = 0; 476 477 /* 478 * EEPROM pins are muxed with the LED function on LAN7800 device. 479 */ 480 val = mue_csr_read(sc, MUE_HW_CFG); 481 if (sc->mue_product == USB_PRODUCT_SMC2_LAN7800) { 482 MUE_CLRBIT(sc, MUE_HW_CFG, 483 MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN); 484 } 485 486 for (i = 0; i < cnt; i++) { 487 err = mue_eeprom_getbyte(sc, off + i, &byte); 488 if (err) 489 break; 490 *(dest + i) = byte; 491 } 492 493 if (sc->mue_product == USB_PRODUCT_SMC2_LAN7800) 494 mue_csr_write(sc, MUE_HW_CFG, val); 495 496 return (err ? 1 : 0); 497 } 498 499 int 500 mue_dataport_wait(struct mue_softc *sc) 501 { 502 int ntries; 503 504 for (ntries = 0; ntries < 100; ntries++) { 505 if (mue_csr_read(sc, MUE_DP_SEL) & MUE_DP_SEL_DPRDY) 506 return (0); 507 DELAY(5); 508 } 509 510 printf("%s: dataport timed out\n", sc->mue_dev.dv_xname); 511 return (1); 512 } 513 514 void 515 mue_dataport_write(struct mue_softc *sc, uint32_t sel, uint32_t addr, 516 uint32_t cnt, uint32_t *data) 517 { 518 int i; 519 520 if (mue_dataport_wait(sc) != 0) 521 return; 522 523 mue_csr_write(sc, MUE_DP_SEL, 524 (mue_csr_read(sc, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel); 525 526 for (i = 0; i < cnt; i++) { 527 mue_csr_write(sc, MUE_DP_ADDR, addr + i); 528 mue_csr_write(sc, MUE_DP_DATA, data[i]); 529 mue_csr_write(sc, MUE_DP_CMD, MUE_DP_CMD_WRITE); 530 if (mue_dataport_wait(sc) != 0) 531 return; 532 } 533 } 534 535 void 536 mue_init_ltm(struct mue_softc *sc) 537 { 538 uint8_t idx[6] = { 0 }; 539 int i; 540 541 if (mue_csr_read(sc, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) { 542 uint8_t temp[2]; 543 544 if (mue_read_eeprom(sc, (caddr_t)&temp, MUE_EE_LTM_OFFSET, 2)) { 545 if (temp[0] != 24) 546 goto done; 547 mue_read_eeprom(sc, (caddr_t)&idx, temp[1] << 1, 24); 548 } 549 } 550 done: 551 for (i = 0; i < sizeof(idx); i++) 552 mue_csr_write(sc, MUE_LTM_INDEX(i), idx[i]); 553 } 554 555 int 556 mue_chip_init(struct mue_softc *sc) 557 { 558 uint32_t val; 559 int ntries; 560 561 if (sc->mue_flags & LAN7500) { 562 for (ntries = 0; ntries < 100; ntries++) { 563 if (mue_csr_read(sc, MUE_PMT_CTL) & MUE_PMT_CTL_READY) 564 break; 565 DELAY(1000); /* 1 msec */ 566 } 567 if (ntries == 100) { 568 printf("%s: timeout waiting for device ready\n", 569 sc->mue_dev.dv_xname); 570 return (ETIMEDOUT); 571 } 572 } 573 574 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_LRST); 575 576 for (ntries = 0; ntries < 1000; ntries++) { 577 if (!(mue_csr_read(sc, MUE_HW_CFG) & MUE_HW_CFG_LRST)) 578 break; 579 DELAY(5); 580 } 581 if (ntries == 1000) { 582 printf("%s: timeout on lite software reset\n", 583 sc->mue_dev.dv_xname); 584 return (ETIMEDOUT); 585 } 586 587 /* Respond to the IN token with a NAK. */ 588 if (sc->mue_flags & LAN7500) 589 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BIR); 590 else 591 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BIR); 592 593 if (sc->mue_flags & LAN7500) { 594 mue_csr_write(sc, MUE_BURST_CAP, 595 (sc->mue_udev->speed == USB_SPEED_HIGH) ? 596 MUE_BURST_MIN_BUFSZ : MUE_BURST_MAX_BUFSZ); 597 mue_csr_write(sc, MUE_BULK_IN_DELAY, MUE_DEFAULT_BULKIN_DELAY); 598 599 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF); 600 601 /* Set undocumented FIFO sizes. */ 602 mue_csr_write(sc, MUE_FCT_RX_FIFO_END, 0x27); 603 mue_csr_write(sc, MUE_FCT_TX_FIFO_END, 0x17); 604 } else { 605 /* Init LTM. */ 606 mue_init_ltm(sc); 607 608 val = (sc->mue_udev->speed == USB_SPEED_SUPER) ? 609 MUE_7800_BURST_MIN_BUFSZ : MUE_7800_BURST_MAX_BUFSZ; 610 mue_csr_write(sc, MUE_7800_BURST_CAP, val); 611 mue_csr_write(sc, MUE_7800_BULK_IN_DELAY, 612 MUE_7800_DEFAULT_BULKIN_DELAY); 613 614 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_MEF); 615 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BCE); 616 } 617 618 mue_csr_write(sc, MUE_INT_STATUS, 0xffffffff); 619 mue_csr_write(sc, (sc->mue_flags & LAN7500) ? 620 MUE_FCT_FLOW : MUE_7800_FCT_FLOW, 0); 621 mue_csr_write(sc, MUE_FLOW, 0); 622 623 /* Reset PHY. */ 624 MUE_SETBIT(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST); 625 for (ntries = 0; ntries < 100; ntries++) { 626 val = mue_csr_read(sc, MUE_PMT_CTL); 627 if (!(val & MUE_PMT_CTL_PHY_RST) && (val & MUE_PMT_CTL_READY)) 628 break; 629 DELAY(10000); 630 } 631 if (ntries == 100) { 632 printf("%s: timeout waiting for PHY reset\n", 633 sc->mue_dev.dv_xname); 634 return (ETIMEDOUT); 635 } 636 637 /* LAN7801 only has RGMII mode. */ 638 if (sc->mue_product == USB_PRODUCT_SMC2_LAN7801) 639 MUE_CLRBIT(sc, MUE_MAC_CR, MUE_MAC_CR_GMII_EN); 640 641 if (sc->mue_flags & LAN7500 || !sc->mue_eeprom_present) { 642 /* Allow MAC to detect speed and duplex from PHY. */ 643 MUE_SETBIT(sc, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED | 644 MUE_MAC_CR_AUTO_DUPLEX); 645 } 646 647 MUE_SETBIT(sc, MUE_MAC_TX, MUE_MAC_TX_TXEN); 648 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ? 649 MUE_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN); 650 651 /* Set the maximum frame size. */ 652 MUE_CLRBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN); 653 MUE_SETBIT(sc, MUE_MAC_RX, MUE_MAC_RX_MAX_LEN(ETHER_MAX_LEN)); 654 MUE_SETBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN); 655 656 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ? 657 MUE_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN); 658 659 return (0); 660 } 661 662 void 663 mue_set_macaddr(struct mue_softc *sc) 664 { 665 struct ifnet *ifp = &sc->arpcom.ac_if; 666 const uint8_t *eaddr = LLADDR(ifp->if_sadl); 667 uint32_t val, reg; 668 669 reg = (sc->mue_flags & LAN7500) ? MUE_ADDR_FILTX : MUE_7800_ADDR_FILTX; 670 671 val = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | eaddr[0]; 672 mue_csr_write(sc, MUE_RX_ADDRL, val); 673 mue_csr_write(sc, reg + 4, val); 674 val = (eaddr[5] << 8) | eaddr[4]; 675 mue_csr_write(sc, MUE_RX_ADDRH, val); 676 mue_csr_write(sc, reg, val | MUE_ADDR_FILTX_VALID); 677 } 678 679 /* 680 * Probe for a Microchip chip. 681 */ 682 int 683 mue_match(struct device *parent, void *match, void *aux) 684 { 685 struct usb_attach_arg *uaa = aux; 686 687 if (uaa->iface == NULL || uaa->configno != 1) 688 return (UMATCH_NONE); 689 690 return (mue_lookup(uaa->vendor, uaa->product) != NULL ? 691 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 692 } 693 694 void 695 mue_attach(struct device *parent, struct device *self, void *aux) 696 { 697 struct mue_softc *sc = (struct mue_softc *)self; 698 struct usb_attach_arg *uaa = aux; 699 usb_interface_descriptor_t *id; 700 usb_endpoint_descriptor_t *ed; 701 struct mii_data *mii; 702 struct ifnet *ifp; 703 int i, s; 704 705 sc->mue_udev = uaa->device; 706 sc->mue_iface = uaa->iface; 707 sc->mue_product = uaa->product; 708 sc->mue_flags = mue_lookup(uaa->vendor, uaa->product)->mue_flags; 709 710 usb_init_task(&sc->mue_tick_task, mue_tick_task, sc, 711 USB_TASK_TYPE_GENERIC); 712 rw_init(&sc->mue_mii_lock, "muemii"); 713 usb_init_task(&sc->mue_stop_task, (void (*)(void *))mue_stop, sc, 714 USB_TASK_TYPE_GENERIC); 715 716 /* Decide on what our bufsize will be. */ 717 if (sc->mue_flags & LAN7500) 718 sc->mue_bufsz = (sc->mue_udev->speed == USB_SPEED_HIGH) ? 719 MUE_MAX_BUFSZ : MUE_MIN_BUFSZ; 720 else 721 sc->mue_bufsz = MUE_7800_BUFSZ; 722 723 /* Find endpoints. */ 724 id = usbd_get_interface_descriptor(sc->mue_iface); 725 for (i = 0; i < id->bNumEndpoints; i++) { 726 ed = usbd_interface2endpoint_descriptor(sc->mue_iface, i); 727 if (ed == NULL) { 728 printf("%s: couldn't get ep %d\n", 729 sc->mue_dev.dv_xname, i); 730 return; 731 } 732 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 733 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 734 sc->mue_ed[MUE_ENDPT_RX] = ed->bEndpointAddress; 735 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 736 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 737 sc->mue_ed[MUE_ENDPT_TX] = ed->bEndpointAddress; 738 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 739 UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) { 740 sc->mue_ed[MUE_ENDPT_INTR] = ed->bEndpointAddress; 741 } 742 } 743 744 s = splnet(); 745 746 sc->mue_phyno = 1; 747 748 /* Check if the EEPROM programmed indicator is present. */ 749 mue_read_eeprom(sc, (caddr_t)&i, MUE_EE_IND_OFFSET, 1); 750 sc->mue_eeprom_present = (i == MUE_EEPROM_INDICATOR) ? 1 : 0; 751 752 if (mue_chip_init(sc) != 0) { 753 printf("%s: chip initialization failed\n", 754 sc->mue_dev.dv_xname); 755 splx(s); 756 return; 757 } 758 759 /* Get station address from the EEPROM. */ 760 if (sc->mue_eeprom_present) { 761 if (mue_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 762 MUE_EE_MAC_OFFSET, ETHER_ADDR_LEN)) { 763 printf("%s: failed to read station address\n", 764 sc->mue_dev.dv_xname); 765 splx(s); 766 return; 767 } 768 } else 769 mue_enaddr_OF(sc); 770 771 /* A Microchip chip was detected. Inform the world. */ 772 printf("%s:", sc->mue_dev.dv_xname); 773 if (sc->mue_flags & LAN7500) 774 printf(" LAN7500"); 775 else 776 printf(" LAN7800"); 777 printf(", address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); 778 779 /* Initialize interface info.*/ 780 ifp = GET_IFP(sc); 781 ifp->if_softc = sc; 782 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 783 ifp->if_ioctl = mue_ioctl; 784 ifp->if_start = mue_start; 785 ifp->if_watchdog = mue_watchdog; 786 strlcpy(ifp->if_xname, sc->mue_dev.dv_xname, IFNAMSIZ); 787 788 ifp->if_capabilities = IFCAP_VLAN_MTU; 789 790 /* Initialize MII/media info. */ 791 mii = GET_MII(sc); 792 mii->mii_ifp = ifp; 793 mii->mii_readreg = mue_miibus_readreg; 794 mii->mii_writereg = mue_miibus_writereg; 795 mii->mii_statchg = mue_miibus_statchg; 796 mii->mii_flags = MIIF_AUTOTSLEEP; 797 798 ifmedia_init(&mii->mii_media, 0, mue_ifmedia_upd, mue_ifmedia_sts); 799 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 800 MIIF_DOPAUSE); 801 802 if (LIST_FIRST(&mii->mii_phys) == NULL) { 803 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 804 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 805 } else 806 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 807 808 /* Attach the interface. */ 809 if_attach(ifp); 810 ether_ifattach(ifp); 811 812 timeout_set(&sc->mue_stat_ch, mue_tick, sc); 813 814 splx(s); 815 } 816 817 int 818 mue_detach(struct device *self, int flags) 819 { 820 struct mue_softc *sc = (struct mue_softc *)self; 821 struct ifnet *ifp = GET_IFP(sc); 822 int s; 823 824 if (timeout_initialized(&sc->mue_stat_ch)) 825 timeout_del(&sc->mue_stat_ch); 826 827 if (sc->mue_ep[MUE_ENDPT_TX] != NULL) 828 usbd_abort_pipe(sc->mue_ep[MUE_ENDPT_TX]); 829 if (sc->mue_ep[MUE_ENDPT_RX] != NULL) 830 usbd_abort_pipe(sc->mue_ep[MUE_ENDPT_RX]); 831 if (sc->mue_ep[MUE_ENDPT_INTR] != NULL) 832 usbd_abort_pipe(sc->mue_ep[MUE_ENDPT_INTR]); 833 834 /* 835 * Remove any pending tasks. They cannot be executing because they run 836 * in the same thread as detach. 837 */ 838 usb_rem_task(sc->mue_udev, &sc->mue_tick_task); 839 usb_rem_task(sc->mue_udev, &sc->mue_stop_task); 840 841 s = splusb(); 842 843 if (--sc->mue_refcnt >= 0) { 844 /* Wait for processes to go away */ 845 usb_detach_wait(&sc->mue_dev); 846 } 847 848 if (ifp->if_flags & IFF_RUNNING) 849 mue_stop(sc); 850 851 mii_detach(&sc->mue_mii, MII_PHY_ANY, MII_OFFSET_ANY); 852 ifmedia_delete_instance(&sc->mue_mii.mii_media, IFM_INST_ANY); 853 if (ifp->if_softc != NULL) { 854 ether_ifdetach(ifp); 855 if_detach(ifp); 856 } 857 858 if (--sc->mue_refcnt >= 0) { 859 /* Wait for processes to go away. */ 860 usb_detach_wait(&sc->mue_dev); 861 } 862 splx(s); 863 864 return (0); 865 } 866 867 int 868 mue_rx_list_init(struct mue_softc *sc) 869 { 870 struct mue_cdata *cd; 871 struct mue_chain *c; 872 int i; 873 874 DPRINTF(("%s: %s: enter\n", sc->mue_dev.dv_xname, __func__)); 875 876 cd = &sc->mue_cdata; 877 for (i = 0; i < MUE_RX_LIST_CNT; i++) { 878 c = &cd->mue_rx_chain[i]; 879 c->mue_sc = sc; 880 c->mue_idx = i; 881 c->mue_mbuf = NULL; 882 if (c->mue_xfer == NULL) { 883 c->mue_xfer = usbd_alloc_xfer(sc->mue_udev); 884 if (c->mue_xfer == NULL) 885 return (ENOBUFS); 886 c->mue_buf = usbd_alloc_buffer(c->mue_xfer, 887 sc->mue_bufsz); 888 if (c->mue_buf == NULL) { 889 usbd_free_xfer(c->mue_xfer); 890 return (ENOBUFS); 891 } 892 } 893 } 894 895 return (0); 896 } 897 898 int 899 mue_tx_list_init(struct mue_softc *sc) 900 { 901 struct mue_cdata *cd; 902 struct mue_chain *c; 903 int i; 904 905 DPRINTF(("%s: %s: enter\n", sc->mue_dev.dv_xname, __func__)); 906 907 cd = &sc->mue_cdata; 908 for (i = 0; i < MUE_TX_LIST_CNT; i++) { 909 c = &cd->mue_tx_chain[i]; 910 c->mue_sc = sc; 911 c->mue_idx = i; 912 c->mue_mbuf = NULL; 913 if (c->mue_xfer == NULL) { 914 c->mue_xfer = usbd_alloc_xfer(sc->mue_udev); 915 if (c->mue_xfer == NULL) 916 return (ENOBUFS); 917 c->mue_buf = usbd_alloc_buffer(c->mue_xfer, 918 sc->mue_bufsz); 919 if (c->mue_buf == NULL) { 920 usbd_free_xfer(c->mue_xfer); 921 return (ENOBUFS); 922 } 923 } 924 } 925 926 return (0); 927 } 928 929 int 930 mue_open_pipes(struct mue_softc *sc) 931 { 932 struct mue_chain *c; 933 usbd_status err; 934 int i; 935 936 /* Open RX and TX pipes. */ 937 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_RX], 938 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_RX]); 939 if (err) { 940 printf("%s: open rx pipe failed: %s\n", 941 sc->mue_dev.dv_xname, usbd_errstr(err)); 942 return (EIO); 943 } 944 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_TX], 945 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_TX]); 946 if (err) { 947 printf("%s: open tx pipe failed: %s\n", 948 sc->mue_dev.dv_xname, usbd_errstr(err)); 949 return (EIO); 950 } 951 952 /* Start up the receive pipe. */ 953 for (i = 0; i < MUE_RX_LIST_CNT; i++) { 954 c = &sc->mue_cdata.mue_rx_chain[i]; 955 usbd_setup_xfer(c->mue_xfer, sc->mue_ep[MUE_ENDPT_RX], 956 c, c->mue_buf, sc->mue_bufsz, 957 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, 958 mue_rxeof); 959 usbd_transfer(c->mue_xfer); 960 } 961 962 return (0); 963 } 964 965 int 966 mue_encap(struct mue_softc *sc, struct mbuf *m, int idx) 967 { 968 struct mue_chain *c; 969 usbd_status err; 970 struct mue_txbuf_hdr hdr; 971 int length; 972 973 c = &sc->mue_cdata.mue_tx_chain[idx]; 974 975 hdr.tx_cmd_a = htole32((m->m_pkthdr.len & MUE_TX_CMD_A_LEN_MASK) | 976 MUE_TX_CMD_A_FCS); 977 /* Disable segmentation offload. */ 978 hdr.tx_cmd_b = htole32(0); 979 memcpy(c->mue_buf, &hdr, sizeof(hdr)); 980 length = sizeof(hdr); 981 982 m_copydata(m, 0, m->m_pkthdr.len, c->mue_buf + length); 983 length += m->m_pkthdr.len; 984 985 c->mue_mbuf = m; 986 987 usbd_setup_xfer(c->mue_xfer, sc->mue_ep[MUE_ENDPT_TX], 988 c, c->mue_buf, length, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, 989 10000, mue_txeof); 990 991 /* Transmit */ 992 err = usbd_transfer(c->mue_xfer); 993 if (err != USBD_IN_PROGRESS) { 994 mue_stop(sc); 995 return(EIO); 996 } 997 998 sc->mue_cdata.mue_tx_cnt++; 999 1000 return(0); 1001 } 1002 1003 void 1004 mue_iff(struct mue_softc *sc) 1005 { 1006 struct ifnet *ifp = GET_IFP(sc); 1007 struct arpcom *ac = &sc->arpcom; 1008 struct ether_multi *enm; 1009 struct ether_multistep step; 1010 uint32_t h = 0, hashtbl[MUE_DP_SEL_VHF_HASH_LEN], reg, rxfilt; 1011 1012 if (usbd_is_dying(sc->mue_udev)) 1013 return; 1014 1015 reg = (sc->mue_flags & LAN7500) ? MUE_RFE_CTL : MUE_7800_RFE_CTL; 1016 rxfilt = mue_csr_read(sc, reg); 1017 rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH | 1018 MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST); 1019 memset(hashtbl, 0, sizeof(hashtbl)); 1020 ifp->if_flags &= ~IFF_ALLMULTI; 1021 1022 /* Always accept broadcast frames. */ 1023 rxfilt |= MUE_RFE_CTL_BROADCAST; 1024 1025 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1026 ifp->if_flags |= IFF_ALLMULTI; 1027 rxfilt |= MUE_RFE_CTL_MULTICAST; 1028 if (ifp->if_flags & IFF_PROMISC) 1029 rxfilt |= MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST; 1030 } else { 1031 rxfilt |= MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH; 1032 1033 /* Now program new ones. */ 1034 ETHER_FIRST_MULTI(step, ac, enm); 1035 while (enm != NULL) { 1036 h = ether_crc32_be(enm->enm_addrlo, 1037 ETHER_ADDR_LEN) >> 23; 1038 hashtbl[h / 32] |= 1 << (h % 32); 1039 ETHER_NEXT_MULTI(step, enm); 1040 } 1041 } 1042 1043 mue_dataport_write(sc, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN, 1044 MUE_DP_SEL_VHF_HASH_LEN, hashtbl); 1045 mue_csr_write(sc, reg, rxfilt); 1046 } 1047 1048 void 1049 mue_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1050 { 1051 struct mue_chain *c = (struct mue_chain *)priv; 1052 struct mue_softc *sc = c->mue_sc; 1053 struct ifnet *ifp = GET_IFP(sc); 1054 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1055 struct mbuf *m; 1056 struct mue_rxbuf_hdr hdr; 1057 u_char *buf = c->mue_buf; 1058 uint32_t total_len; 1059 int pktlen = 0; 1060 int s; 1061 1062 if (usbd_is_dying(sc->mue_udev)) 1063 return; 1064 1065 if (!(ifp->if_flags & IFF_RUNNING)) 1066 return; 1067 1068 if (status != USBD_NORMAL_COMPLETION) { 1069 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1070 return; 1071 if (usbd_ratecheck(&sc->mue_rx_notice)) { 1072 printf("%s: usb errors on rx: %s\n", 1073 sc->mue_dev.dv_xname, usbd_errstr(status)); 1074 } 1075 if (status == USBD_STALLED) 1076 usbd_clear_endpoint_stall_async(sc->mue_ep[MUE_ENDPT_RX]); 1077 goto done; 1078 } 1079 1080 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1081 1082 do { 1083 if (total_len < sizeof(hdr)) { 1084 ifp->if_ierrors++; 1085 goto done; 1086 } 1087 1088 buf += pktlen; 1089 1090 memcpy(&hdr, buf, sizeof(hdr)); 1091 total_len -= sizeof(hdr); 1092 1093 if (letoh32(hdr.rx_cmd_a) & MUE_RX_CMD_A_RED) { 1094 ifp->if_ierrors++; 1095 goto done; 1096 } 1097 1098 pktlen = letoh32(hdr.rx_cmd_a) & MUE_RX_CMD_A_LEN_MASK; 1099 if (sc->mue_flags & LAN7500) 1100 pktlen -= 2; 1101 1102 if (pktlen > total_len) { 1103 ifp->if_ierrors++; 1104 goto done; 1105 } 1106 1107 buf += sizeof(hdr); 1108 1109 if (total_len < pktlen) 1110 total_len = 0; 1111 else 1112 total_len -= pktlen; 1113 1114 m = m_devget(buf, pktlen - ETHER_CRC_LEN, ETHER_ALIGN); 1115 if (m == NULL) { 1116 DPRINTF(("unable to allocate mbuf for next packet\n")); 1117 ifp->if_ierrors++; 1118 goto done; 1119 } 1120 ml_enqueue(&ml, m); 1121 } while (total_len > 0); 1122 1123 done: 1124 s = splnet(); 1125 if_input(ifp, &ml); 1126 splx(s); 1127 1128 memset(c->mue_buf, 0, sc->mue_bufsz); 1129 1130 /* Setup new transfer. */ 1131 usbd_setup_xfer(xfer, sc->mue_ep[MUE_ENDPT_RX], 1132 c, c->mue_buf, sc->mue_bufsz, USBD_SHORT_XFER_OK | USBD_NO_COPY, 1133 USBD_NO_TIMEOUT, mue_rxeof); 1134 usbd_transfer(xfer); 1135 1136 DPRINTFN(10,("%s: %s: start rx\n", sc->mue_dev.dv_xname, __func__)); 1137 } 1138 1139 void 1140 mue_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1141 { 1142 struct mue_chain *c = priv; 1143 struct mue_softc *sc = c->mue_sc; 1144 struct ifnet *ifp = GET_IFP(sc); 1145 int s; 1146 1147 if (usbd_is_dying(sc->mue_udev)) 1148 return; 1149 1150 s = splnet(); 1151 1152 DPRINTFN(10,("%s: %s: enter status=%d\n", sc->mue_dev.dv_xname, 1153 __func__, status)); 1154 1155 if (status != USBD_NORMAL_COMPLETION) { 1156 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1157 splx(s); 1158 return; 1159 } 1160 ifp->if_oerrors++; 1161 printf("%s: usb error on tx: %s\n", sc->mue_dev.dv_xname, 1162 usbd_errstr(status)); 1163 if (status == USBD_STALLED) 1164 usbd_clear_endpoint_stall_async(sc->mue_ep[MUE_ENDPT_TX]); 1165 splx(s); 1166 return; 1167 } 1168 1169 ifp->if_timer = 0; 1170 ifq_clr_oactive(&ifp->if_snd); 1171 1172 m_freem(c->mue_mbuf); 1173 c->mue_mbuf = NULL; 1174 1175 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1176 mue_start(ifp); 1177 1178 splx(s); 1179 } 1180 1181 void 1182 mue_init(void *xsc) 1183 { 1184 struct mue_softc *sc = xsc; 1185 struct ifnet *ifp = GET_IFP(sc); 1186 int s; 1187 1188 s = splnet(); 1189 1190 /* Cancel pending I/O and free all TX/RX buffers. */ 1191 mue_reset(sc); 1192 1193 /* Set MAC address. */ 1194 mue_set_macaddr(sc); 1195 1196 /* Init RX ring. */ 1197 if (mue_rx_list_init(sc) == ENOBUFS) { 1198 printf("%s: rx list init failed\n", sc->mue_dev.dv_xname); 1199 splx(s); 1200 return; 1201 } 1202 1203 /* Init TX ring. */ 1204 if (mue_tx_list_init(sc) == ENOBUFS) { 1205 printf("%s: tx list init failed\n", sc->mue_dev.dv_xname); 1206 splx(s); 1207 return; 1208 } 1209 1210 /* Program promiscuous mode and multicast filters. */ 1211 mue_iff(sc); 1212 1213 if (mue_open_pipes(sc) != 0) { 1214 splx(s); 1215 return; 1216 } 1217 1218 sc->mue_link = 0; 1219 ifp->if_flags |= IFF_RUNNING; 1220 ifq_clr_oactive(&ifp->if_snd); 1221 1222 splx(s); 1223 1224 timeout_add_sec(&sc->mue_stat_ch, 1); 1225 } 1226 1227 int 1228 mue_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1229 { 1230 struct mue_softc *sc = ifp->if_softc; 1231 struct ifreq *ifr = (struct ifreq *)data; 1232 int s, error = 0; 1233 1234 s = splnet(); 1235 1236 switch(cmd) { 1237 case SIOCSIFADDR: 1238 ifp->if_flags |= IFF_UP; 1239 if (!(ifp->if_flags & IFF_RUNNING)) 1240 mue_init(sc); 1241 break; 1242 case SIOCSIFFLAGS: 1243 if (ifp->if_flags & IFF_UP) { 1244 if (ifp->if_flags & IFF_RUNNING) 1245 error = ENETRESET; 1246 else 1247 mue_init(sc); 1248 } else { 1249 if (ifp->if_flags & IFF_RUNNING) 1250 mue_stop(sc); 1251 } 1252 break; 1253 case SIOCGIFMEDIA: 1254 case SIOCSIFMEDIA: 1255 error = ifmedia_ioctl(ifp, ifr, &sc->mue_mii.mii_media, cmd); 1256 break; 1257 default: 1258 error = ether_ioctl(ifp, &sc->arpcom, cmd, data); 1259 } 1260 1261 if (error == ENETRESET) { 1262 if (ifp->if_flags & IFF_RUNNING) 1263 mue_iff(sc); 1264 error = 0; 1265 } 1266 1267 splx(s); 1268 1269 return(error); 1270 } 1271 1272 void 1273 mue_watchdog(struct ifnet *ifp) 1274 { 1275 struct mue_softc *sc = ifp->if_softc; 1276 struct mue_chain *c; 1277 usbd_status stat; 1278 int s; 1279 1280 ifp->if_oerrors++; 1281 printf("%s: watchdog timeout\n", sc->mue_dev.dv_xname); 1282 1283 s = splusb(); 1284 c = &sc->mue_cdata.mue_tx_chain[0]; 1285 usbd_get_xfer_status(c->mue_xfer, NULL, NULL, NULL, &stat); 1286 mue_txeof(c->mue_xfer, c, stat); 1287 1288 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1289 mue_start(ifp); 1290 splx(s); 1291 } 1292 1293 void 1294 mue_reset(struct mue_softc *sc) 1295 { 1296 if (usbd_is_dying(sc->mue_udev)) 1297 return; 1298 1299 /* Wait a little while for the chip to get its brains in order. */ 1300 DELAY(1000); 1301 } 1302 1303 void 1304 mue_start(struct ifnet *ifp) 1305 { 1306 struct mue_softc *sc = ifp->if_softc; 1307 struct mbuf *m_head = NULL; 1308 1309 if (!sc->mue_link) 1310 return; 1311 1312 if (ifq_is_oactive(&ifp->if_snd)) 1313 return; 1314 1315 m_head = ifq_deq_begin(&ifp->if_snd); 1316 if (m_head == NULL) 1317 return; 1318 1319 if (mue_encap(sc, m_head, 0)) { 1320 ifq_deq_rollback(&ifp->if_snd, m_head); 1321 ifq_set_oactive(&ifp->if_snd); 1322 return; 1323 } 1324 ifq_deq_commit(&ifp->if_snd, m_head); 1325 1326 /* If there's a BPF listener, bounce a copy of this frame to him. */ 1327 #if NBPFILTER > 0 1328 if (ifp->if_bpf) 1329 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1330 #endif 1331 1332 ifq_set_oactive(&ifp->if_snd); 1333 1334 /* Set a timeout in case the chip goes out to lunch. */ 1335 ifp->if_timer = 5; 1336 } 1337 1338 void 1339 mue_stop(struct mue_softc *sc) 1340 { 1341 struct ifnet *ifp; 1342 1343 ifp = GET_IFP(sc); 1344 ifp->if_timer = 0; 1345 ifp->if_flags &= ~IFF_RUNNING; 1346 ifq_clr_oactive(&ifp->if_snd); 1347 1348 timeout_del(&sc->mue_stat_ch); 1349 1350 sc->mue_link = 0; 1351 } 1352 1353 void 1354 mue_tick(void *xsc) 1355 { 1356 struct mue_softc *sc = xsc; 1357 1358 if (sc == NULL) 1359 return; 1360 1361 if (usbd_is_dying(sc->mue_udev)) 1362 return; 1363 1364 /* Perform periodic stuff in process context. */ 1365 usb_add_task(sc->mue_udev, &sc->mue_tick_task); 1366 } 1367 1368 void 1369 mue_tick_task(void *xsc) 1370 { 1371 struct mue_softc *sc =xsc; 1372 struct mii_data *mii; 1373 int s; 1374 1375 if (sc == NULL) 1376 return; 1377 1378 if (usbd_is_dying(sc->mue_udev)) 1379 return; 1380 1381 mii = GET_MII(sc); 1382 1383 s = splnet(); 1384 mii_tick(mii); 1385 if (sc->mue_link == 0) 1386 mue_miibus_statchg(&sc->mue_dev); 1387 timeout_add_sec(&sc->mue_stat_ch, 1); 1388 splx(s); 1389 } 1390