1 /* $OpenBSD: ehci.c,v 1.193 2016/09/15 02:00:17 dlg Exp $ */ 2 /* $NetBSD: ehci.c,v 1.66 2004/06/30 03:11:56 mycroft Exp $ */ 3 4 /* 5 * Copyright (c) 2014-2015 Martin Pieuchot 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 /* 20 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 21 * All rights reserved. 22 * 23 * This code is derived from software contributed to The NetBSD Foundation 24 * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and 25 * Jeremy Morse (jeremy.morse@gmail.com). 26 * 27 * Redistribution and use in source and binary forms, with or without 28 * modification, are permitted provided that the following conditions 29 * are met: 30 * 1. Redistributions of source code must retain the above copyright 31 * notice, this list of conditions and the following disclaimer. 32 * 2. Redistributions in binary form must reproduce the above copyright 33 * notice, this list of conditions and the following disclaimer in the 34 * documentation and/or other materials provided with the distribution. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 37 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 38 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 39 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 40 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 41 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 42 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 43 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 44 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 45 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 46 * POSSIBILITY OF SUCH DAMAGE. 47 */ 48 49 /* 50 * TODO: 51 * 1) The hub driver needs to handle and schedule the transaction translator, 52 * to assign place in frame where different devices get to go. See chapter 53 * on hubs in USB 2.0 for details. 54 * 55 * 2) Command failures are not recovered correctly. 56 */ 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/kernel.h> 61 #include <sys/rwlock.h> 62 #include <sys/malloc.h> 63 #include <sys/device.h> 64 #include <sys/queue.h> 65 #include <sys/timeout.h> 66 #include <sys/pool.h> 67 #include <sys/endian.h> 68 #include <sys/atomic.h> 69 70 #include <machine/bus.h> 71 72 #include <dev/usb/usb.h> 73 #include <dev/usb/usbdi.h> 74 #include <dev/usb/usbdivar.h> 75 #include <dev/usb/usb_mem.h> 76 77 #include <dev/usb/ehcireg.h> 78 #include <dev/usb/ehcivar.h> 79 80 struct cfdriver ehci_cd = { 81 NULL, "ehci", DV_DULL 82 }; 83 84 #ifdef EHCI_DEBUG 85 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 86 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 87 int ehcidebug = 0; 88 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 89 #else 90 #define DPRINTF(x) 91 #define DPRINTFN(n,x) 92 #endif 93 94 struct pool *ehcixfer; 95 96 struct ehci_pipe { 97 struct usbd_pipe pipe; 98 99 struct ehci_soft_qh *sqh; 100 union { 101 /* Control pipe */ 102 struct { 103 struct usb_dma reqdma; 104 } ctl; 105 /* Iso pipe */ 106 struct { 107 u_int next_frame; 108 u_int cur_xfers; 109 } isoc; 110 } u; 111 }; 112 113 u_int8_t ehci_reverse_bits(u_int8_t, int); 114 115 usbd_status ehci_open(struct usbd_pipe *); 116 int ehci_setaddr(struct usbd_device *, int); 117 void ehci_poll(struct usbd_bus *); 118 void ehci_softintr(void *); 119 int ehci_intr1(struct ehci_softc *); 120 void ehci_waitintr(struct ehci_softc *, struct usbd_xfer *); 121 void ehci_check_intr(struct ehci_softc *, struct usbd_xfer *); 122 void ehci_check_qh_intr(struct ehci_softc *, struct usbd_xfer *); 123 void ehci_check_itd_intr(struct ehci_softc *, struct usbd_xfer *); 124 void ehci_idone(struct usbd_xfer *); 125 void ehci_isoc_idone(struct usbd_xfer *); 126 void ehci_timeout(void *); 127 void ehci_timeout_task(void *); 128 void ehci_intrlist_timeout(void *); 129 130 struct usbd_xfer *ehci_allocx(struct usbd_bus *); 131 void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 132 133 usbd_status ehci_root_ctrl_transfer(struct usbd_xfer *); 134 usbd_status ehci_root_ctrl_start(struct usbd_xfer *); 135 void ehci_root_ctrl_abort(struct usbd_xfer *); 136 void ehci_root_ctrl_close(struct usbd_pipe *); 137 void ehci_root_ctrl_done(struct usbd_xfer *); 138 139 usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 140 usbd_status ehci_root_intr_start(struct usbd_xfer *); 141 void ehci_root_intr_abort(struct usbd_xfer *); 142 void ehci_root_intr_close(struct usbd_pipe *); 143 void ehci_root_intr_done(struct usbd_xfer *); 144 145 usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 146 usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 147 void ehci_device_ctrl_abort(struct usbd_xfer *); 148 void ehci_device_ctrl_close(struct usbd_pipe *); 149 void ehci_device_ctrl_done(struct usbd_xfer *); 150 151 usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 152 usbd_status ehci_device_bulk_start(struct usbd_xfer *); 153 void ehci_device_bulk_abort(struct usbd_xfer *); 154 void ehci_device_bulk_close(struct usbd_pipe *); 155 void ehci_device_bulk_done(struct usbd_xfer *); 156 157 usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 158 usbd_status ehci_device_intr_start(struct usbd_xfer *); 159 void ehci_device_intr_abort(struct usbd_xfer *); 160 void ehci_device_intr_close(struct usbd_pipe *); 161 void ehci_device_intr_done(struct usbd_xfer *); 162 163 usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 164 usbd_status ehci_device_isoc_start(struct usbd_xfer *); 165 void ehci_device_isoc_abort(struct usbd_xfer *); 166 void ehci_device_isoc_close(struct usbd_pipe *); 167 void ehci_device_isoc_done(struct usbd_xfer *); 168 169 void ehci_device_clear_toggle(struct usbd_pipe *pipe); 170 171 void ehci_pcd(struct ehci_softc *, struct usbd_xfer *); 172 void ehci_disown(struct ehci_softc *, int, int); 173 174 struct ehci_soft_qh *ehci_alloc_sqh(struct ehci_softc *); 175 void ehci_free_sqh(struct ehci_softc *, struct ehci_soft_qh *); 176 177 struct ehci_soft_qtd *ehci_alloc_sqtd(struct ehci_softc *); 178 void ehci_free_sqtd(struct ehci_softc *, struct ehci_soft_qtd *); 179 usbd_status ehci_alloc_sqtd_chain(struct ehci_softc *, u_int, 180 struct usbd_xfer *, struct ehci_soft_qtd **, struct ehci_soft_qtd **); 181 void ehci_free_sqtd_chain(struct ehci_softc *, struct ehci_xfer *); 182 183 struct ehci_soft_itd *ehci_alloc_itd(struct ehci_softc *); 184 void ehci_free_itd(struct ehci_softc *, struct ehci_soft_itd *); 185 void ehci_rem_itd_chain(struct ehci_softc *, struct ehci_xfer *); 186 void ehci_free_itd_chain(struct ehci_softc *, struct ehci_xfer *); 187 int ehci_alloc_itd_chain(struct ehci_softc *, struct usbd_xfer *); 188 int ehci_alloc_sitd_chain(struct ehci_softc *, struct usbd_xfer *); 189 void ehci_abort_isoc_xfer(struct usbd_xfer *xfer, 190 usbd_status status); 191 192 usbd_status ehci_device_setintr(struct ehci_softc *, struct ehci_soft_qh *, 193 int ival); 194 195 void ehci_add_qh(struct ehci_soft_qh *, struct ehci_soft_qh *); 196 void ehci_rem_qh(struct ehci_softc *, struct ehci_soft_qh *); 197 void ehci_set_qh_qtd(struct ehci_soft_qh *, struct ehci_soft_qtd *); 198 void ehci_sync_hc(struct ehci_softc *); 199 200 void ehci_close_pipe(struct usbd_pipe *); 201 void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 202 203 #ifdef EHCI_DEBUG 204 void ehci_dump_regs(struct ehci_softc *); 205 void ehci_dump(void); 206 struct ehci_softc *theehci; 207 void ehci_dump_link(ehci_link_t, int); 208 void ehci_dump_sqtds(struct ehci_soft_qtd *); 209 void ehci_dump_sqtd(struct ehci_soft_qtd *); 210 void ehci_dump_qtd(struct ehci_qtd *); 211 void ehci_dump_sqh(struct ehci_soft_qh *); 212 #if notyet 213 void ehci_dump_itd(struct ehci_soft_itd *); 214 #endif 215 #ifdef DIAGNOSTIC 216 void ehci_dump_exfer(struct ehci_xfer *); 217 #endif 218 #endif 219 220 #define EHCI_INTR_ENDPT 1 221 222 struct usbd_bus_methods ehci_bus_methods = { 223 .open_pipe = ehci_open, 224 .dev_setaddr = ehci_setaddr, 225 .soft_intr = ehci_softintr, 226 .do_poll = ehci_poll, 227 .allocx = ehci_allocx, 228 .freex = ehci_freex, 229 }; 230 231 struct usbd_pipe_methods ehci_root_ctrl_methods = { 232 .transfer = ehci_root_ctrl_transfer, 233 .start = ehci_root_ctrl_start, 234 .abort = ehci_root_ctrl_abort, 235 .close = ehci_root_ctrl_close, 236 .done = ehci_root_ctrl_done, 237 }; 238 239 struct usbd_pipe_methods ehci_root_intr_methods = { 240 .transfer = ehci_root_intr_transfer, 241 .start = ehci_root_intr_start, 242 .abort = ehci_root_intr_abort, 243 .close = ehci_root_intr_close, 244 .done = ehci_root_intr_done, 245 }; 246 247 struct usbd_pipe_methods ehci_device_ctrl_methods = { 248 .transfer = ehci_device_ctrl_transfer, 249 .start = ehci_device_ctrl_start, 250 .abort = ehci_device_ctrl_abort, 251 .close = ehci_device_ctrl_close, 252 .done = ehci_device_ctrl_done, 253 }; 254 255 struct usbd_pipe_methods ehci_device_intr_methods = { 256 .transfer = ehci_device_intr_transfer, 257 .start = ehci_device_intr_start, 258 .abort = ehci_device_intr_abort, 259 .close = ehci_device_intr_close, 260 .cleartoggle = ehci_device_clear_toggle, 261 .done = ehci_device_intr_done, 262 }; 263 264 struct usbd_pipe_methods ehci_device_bulk_methods = { 265 .transfer = ehci_device_bulk_transfer, 266 .start = ehci_device_bulk_start, 267 .abort = ehci_device_bulk_abort, 268 .close = ehci_device_bulk_close, 269 .cleartoggle = ehci_device_clear_toggle, 270 .done = ehci_device_bulk_done, 271 }; 272 273 struct usbd_pipe_methods ehci_device_isoc_methods = { 274 .transfer = ehci_device_isoc_transfer, 275 .start = ehci_device_isoc_start, 276 .abort = ehci_device_isoc_abort, 277 .close = ehci_device_isoc_close, 278 .done = ehci_device_isoc_done, 279 }; 280 281 /* 282 * Reverse a number with nbits bits. Used to evenly distribute lower-level 283 * interrupt heads in the periodic schedule. 284 * Suitable for use with EHCI_IPOLLRATES <= 9. 285 */ 286 u_int8_t 287 ehci_reverse_bits(u_int8_t c, int nbits) 288 { 289 c = ((c >> 1) & 0x55) | ((c << 1) & 0xaa); 290 c = ((c >> 2) & 0x33) | ((c << 2) & 0xcc); 291 c = ((c >> 4) & 0x0f) | ((c << 4) & 0xf0); 292 293 return c >> (8 - nbits); 294 } 295 296 usbd_status 297 ehci_init(struct ehci_softc *sc) 298 { 299 u_int32_t sparams, cparams, hcr; 300 u_int i, j; 301 usbd_status err; 302 struct ehci_soft_qh *sqh; 303 304 #ifdef EHCI_DEBUG 305 u_int32_t vers; 306 theehci = sc; 307 308 DPRINTF(("ehci_init: start\n")); 309 310 vers = EREAD2(sc, EHCI_HCIVERSION); 311 DPRINTF(("%s: EHCI version %x.%x\n", sc->sc_bus.bdev.dv_xname, 312 vers >> 8, vers & 0xff)); 313 #endif 314 315 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 316 317 sparams = EREAD4(sc, EHCI_HCSPARAMS); 318 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 319 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 320 cparams = EREAD4(sc, EHCI_HCCPARAMS); 321 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 322 323 /* MUST clear segment register if 64 bit capable. */ 324 if (EHCI_HCC_64BIT(cparams)) 325 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 326 327 sc->sc_bus.usbrev = USBREV_2_0; 328 329 DPRINTF(("%s: resetting\n", sc->sc_bus.bdev.dv_xname)); 330 err = ehci_reset(sc); 331 if (err) 332 return (err); 333 334 if (ehcixfer == NULL) { 335 ehcixfer = malloc(sizeof(struct pool), M_DEVBUF, M_NOWAIT); 336 if (ehcixfer == NULL) { 337 printf("%s: unable to allocate pool descriptor\n", 338 sc->sc_bus.bdev.dv_xname); 339 return (ENOMEM); 340 } 341 pool_init(ehcixfer, sizeof(struct ehci_xfer), 0, IPL_SOFTUSB, 342 0, "ehcixfer", NULL); 343 } 344 345 /* frame list size at default, read back what we got and use that */ 346 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 347 case 0: 348 sc->sc_flsize = 1024; 349 break; 350 case 1: 351 sc->sc_flsize = 512; 352 break; 353 case 2: 354 sc->sc_flsize = 256; 355 break; 356 case 3: 357 return (USBD_IOERROR); 358 } 359 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 360 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 361 if (err) 362 return (err); 363 DPRINTF(("%s: flsize=%d\n", sc->sc_bus.bdev.dv_xname,sc->sc_flsize)); 364 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 365 366 for (i = 0; i < sc->sc_flsize; i++) 367 sc->sc_flist[i] = htole32(EHCI_LINK_TERMINATE); 368 369 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 370 371 sc->sc_softitds = mallocarray(sc->sc_flsize, 372 sizeof(struct ehci_soft_itd *), M_USB, M_NOWAIT | M_ZERO); 373 if (sc->sc_softitds == NULL) { 374 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 375 return (ENOMEM); 376 } 377 LIST_INIT(&sc->sc_freeitds); 378 TAILQ_INIT(&sc->sc_intrhead); 379 380 /* Set up the bus struct. */ 381 sc->sc_bus.methods = &ehci_bus_methods; 382 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 383 384 sc->sc_eintrs = EHCI_NORMAL_INTRS; 385 386 /* 387 * Allocate the interrupt dummy QHs. These are arranged to give poll 388 * intervals that are powers of 2 times 1ms. 389 */ 390 for (i = 0; i < EHCI_INTRQHS; i++) { 391 sqh = ehci_alloc_sqh(sc); 392 if (sqh == NULL) { 393 err = USBD_NOMEM; 394 goto bad1; 395 } 396 sc->sc_islots[i].sqh = sqh; 397 } 398 for (i = 0; i < EHCI_INTRQHS; i++) { 399 sqh = sc->sc_islots[i].sqh; 400 if (i == 0) { 401 /* The last (1ms) QH terminates. */ 402 sqh->qh.qh_link = htole32(EHCI_LINK_TERMINATE); 403 sqh->next = NULL; 404 } else { 405 /* Otherwise the next QH has half the poll interval */ 406 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 407 sqh->qh.qh_link = htole32(sqh->next->physaddr | 408 EHCI_LINK_QH); 409 } 410 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 411 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 412 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 413 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 414 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 415 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 416 sqh->sqtd = NULL; 417 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 418 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 419 } 420 /* Point the frame list at the last level (128ms). */ 421 for (i = 0; i < (1 << (EHCI_IPOLLRATES - 1)); i++) 422 for (j = i; j < sc->sc_flsize; j += 1 << (EHCI_IPOLLRATES - 1)) 423 sc->sc_flist[j] = htole32(EHCI_LINK_QH | sc->sc_islots[ 424 EHCI_IQHIDX(EHCI_IPOLLRATES - 1, ehci_reverse_bits( 425 i, EHCI_IPOLLRATES - 1))].sqh->physaddr); 426 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 427 BUS_DMASYNC_PREWRITE); 428 429 /* Allocate dummy QH that starts the async list. */ 430 sqh = ehci_alloc_sqh(sc); 431 if (sqh == NULL) { 432 err = USBD_NOMEM; 433 goto bad1; 434 } 435 /* Fill the QH */ 436 sqh->qh.qh_endp = 437 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 438 sqh->qh.qh_link = 439 htole32(sqh->physaddr | EHCI_LINK_QH); 440 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 441 sqh->prev = sqh; /*It's a circular list.. */ 442 sqh->next = sqh; 443 /* Fill the overlay qTD */ 444 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 445 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 446 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 447 sqh->sqtd = NULL; 448 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 449 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 450 451 /* Point to async list */ 452 sc->sc_async_head = sqh; 453 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 454 455 timeout_set(&sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 456 457 rw_init(&sc->sc_doorbell_lock, "ehcidb"); 458 459 /* Turn on controller */ 460 EOWRITE4(sc, EHCI_USBCMD, 461 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 462 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 463 EHCI_CMD_ASE | 464 EHCI_CMD_PSE | 465 EHCI_CMD_RS); 466 467 /* Take over port ownership */ 468 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 469 470 for (i = 0; i < 100; i++) { 471 usb_delay_ms(&sc->sc_bus, 1); 472 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 473 if (!hcr) 474 break; 475 } 476 if (hcr) { 477 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 478 return (USBD_IOERROR); 479 } 480 481 /* Enable interrupts */ 482 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 483 484 return (USBD_NORMAL_COMPLETION); 485 486 #if 0 487 bad2: 488 ehci_free_sqh(sc, sc->sc_async_head); 489 #endif 490 bad1: 491 free(sc->sc_softitds, M_USB, sc->sc_flsize); 492 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 493 return (err); 494 } 495 496 int 497 ehci_intr(void *v) 498 { 499 struct ehci_softc *sc = v; 500 501 if (sc == NULL || sc->sc_bus.dying) 502 return (0); 503 504 /* If we get an interrupt while polling, then just ignore it. */ 505 if (sc->sc_bus.use_polling) { 506 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 507 508 if (intrs) 509 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 510 return (0); 511 } 512 513 return (ehci_intr1(sc)); 514 } 515 516 int 517 ehci_intr1(struct ehci_softc *sc) 518 { 519 u_int32_t intrs, eintrs; 520 521 /* In case the interrupt occurs before initialization has completed. */ 522 if (sc == NULL) { 523 #ifdef DIAGNOSTIC 524 printf("ehci_intr1: sc == NULL\n"); 525 #endif 526 return (0); 527 } 528 529 intrs = EOREAD4(sc, EHCI_USBSTS); 530 if (intrs == 0xffffffff) { 531 sc->sc_bus.dying = 1; 532 return (0); 533 } 534 intrs = EHCI_STS_INTRS(intrs); 535 if (!intrs) 536 return (0); 537 538 eintrs = intrs & sc->sc_eintrs; 539 if (!eintrs) 540 return (0); 541 542 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 543 sc->sc_bus.no_intrs++; 544 545 if (eintrs & EHCI_STS_HSE) { 546 printf("%s: unrecoverable error, controller halted\n", 547 sc->sc_bus.bdev.dv_xname); 548 sc->sc_bus.dying = 1; 549 return (1); 550 } 551 if (eintrs & EHCI_STS_IAA) { 552 wakeup(&sc->sc_async_head); 553 eintrs &= ~EHCI_STS_IAA; 554 } 555 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 556 usb_schedsoftintr(&sc->sc_bus); 557 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 558 } 559 if (eintrs & EHCI_STS_PCD) { 560 atomic_setbits_int(&sc->sc_flags, EHCIF_PCB_INTR); 561 usb_schedsoftintr(&sc->sc_bus); 562 eintrs &= ~EHCI_STS_PCD; 563 } 564 565 if (eintrs != 0) { 566 /* Block unprocessed interrupts. */ 567 sc->sc_eintrs &= ~eintrs; 568 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 569 printf("%s: blocking intrs 0x%x\n", 570 sc->sc_bus.bdev.dv_xname, eintrs); 571 } 572 573 return (1); 574 } 575 576 void 577 ehci_pcd(struct ehci_softc *sc, struct usbd_xfer *xfer) 578 { 579 u_char *p; 580 int i, m; 581 582 if (xfer == NULL) { 583 /* Just ignore the change. */ 584 return; 585 } 586 587 p = KERNADDR(&xfer->dmabuf, 0); 588 m = min(sc->sc_noport, xfer->length * 8 - 1); 589 memset(p, 0, xfer->length); 590 for (i = 1; i <= m; i++) { 591 /* Pick out CHANGE bits from the status reg. */ 592 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 593 p[i / 8] |= 1 << (i % 8); 594 } 595 xfer->actlen = xfer->length; 596 xfer->status = USBD_NORMAL_COMPLETION; 597 598 usb_transfer_complete(xfer); 599 } 600 601 /* 602 * Work around the half configured control (default) pipe when setting 603 * the address of a device. 604 * 605 * Because a single QH is setup per endpoint in ehci_open(), and the 606 * control pipe is configured before we could have set the address 607 * of the device or read the wMaxPacketSize of the endpoint, we have 608 * to re-open the pipe twice here. 609 */ 610 int 611 ehci_setaddr(struct usbd_device *dev, int addr) 612 { 613 /* Root Hub */ 614 if (dev->depth == 0) 615 return (0); 616 617 /* Re-establish the default pipe with the new max packet size. */ 618 ehci_close_pipe(dev->default_pipe); 619 if (ehci_open(dev->default_pipe)) 620 return (EINVAL); 621 622 if (usbd_set_address(dev, addr)) 623 return (1); 624 625 dev->address = addr; 626 627 /* Re-establish the default pipe with the new address. */ 628 ehci_close_pipe(dev->default_pipe); 629 if (ehci_open(dev->default_pipe)) 630 return (EINVAL); 631 632 return (0); 633 } 634 635 void 636 ehci_softintr(void *v) 637 { 638 struct ehci_softc *sc = v; 639 struct ehci_xfer *ex, *nextex; 640 641 if (sc->sc_bus.dying) 642 return; 643 644 sc->sc_bus.intr_context++; 645 646 if (sc->sc_flags & EHCIF_PCB_INTR) { 647 atomic_clearbits_int(&sc->sc_flags, EHCIF_PCB_INTR); 648 ehci_pcd(sc, sc->sc_intrxfer); 649 } 650 651 /* 652 * The only explanation I can think of for why EHCI is as brain dead 653 * as UHCI interrupt-wise is that Intel was involved in both. 654 * An interrupt just tells us that something is done, we have no 655 * clue what, so we need to scan through all active transfers. :-( 656 */ 657 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 658 nextex = TAILQ_NEXT(ex, inext); 659 ehci_check_intr(sc, &ex->xfer); 660 } 661 662 /* Schedule a callout to catch any dropped transactions. */ 663 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 664 !TAILQ_EMPTY(&sc->sc_intrhead)) { 665 timeout_add_sec(&sc->sc_tmo_intrlist, 1); 666 } 667 668 if (sc->sc_softwake) { 669 sc->sc_softwake = 0; 670 wakeup(&sc->sc_softwake); 671 } 672 673 sc->sc_bus.intr_context--; 674 } 675 676 void 677 ehci_check_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 678 { 679 int attr = xfer->pipe->endpoint->edesc->bmAttributes; 680 681 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 682 ehci_check_itd_intr(sc, xfer); 683 else 684 ehci_check_qh_intr(sc, xfer); 685 } 686 687 void 688 ehci_check_qh_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 689 { 690 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 691 struct ehci_soft_qtd *sqtd, *lsqtd = ex->sqtdend; 692 uint32_t status; 693 694 KASSERT(ex->sqtdstart != NULL && ex->sqtdend != NULL); 695 696 usb_syncmem(&lsqtd->dma, 697 lsqtd->offs + offsetof(struct ehci_qtd, qtd_status), 698 sizeof(lsqtd->qtd.qtd_status), 699 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 700 701 /* 702 * If the last TD is still active we need to check whether there 703 * is a an error somewhere in the middle, or whether there was a 704 * short packet (SPD and not ACTIVE). 705 */ 706 if (letoh32(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 707 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 708 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 709 usb_syncmem(&sqtd->dma, 710 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 711 sizeof(sqtd->qtd.qtd_status), 712 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 713 status = letoh32(sqtd->qtd.qtd_status); 714 usb_syncmem(&sqtd->dma, 715 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 716 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 717 /* If there's an active QTD the xfer isn't done. */ 718 if (status & EHCI_QTD_ACTIVE) 719 break; 720 /* Any kind of error makes the xfer done. */ 721 if (status & EHCI_QTD_HALTED) 722 goto done; 723 /* We want short packets, and it is short: it's done */ 724 if (EHCI_QTD_GET_BYTES(status) != 0) 725 goto done; 726 } 727 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 728 ex, ex->sqtdstart)); 729 usb_syncmem(&lsqtd->dma, 730 lsqtd->offs + offsetof(struct ehci_qtd, qtd_status), 731 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 732 return; 733 } 734 done: 735 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 736 timeout_del(&xfer->timeout_handle); 737 usb_rem_task(xfer->pipe->device, &xfer->abort_task); 738 ehci_idone(xfer); 739 } 740 741 void 742 ehci_check_itd_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 743 { 744 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 745 struct ehci_soft_itd *itd = ex->itdend; 746 int i; 747 748 if (xfer != SIMPLEQ_FIRST(&xfer->pipe->queue)) 749 return; 750 751 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 752 753 /* Check no active transfers in last itd, meaning we're finished */ 754 if (xfer->device->speed == USB_SPEED_HIGH) { 755 usb_syncmem(&itd->dma, 756 itd->offs + offsetof(struct ehci_itd, itd_ctl), 757 sizeof(itd->itd.itd_ctl), 758 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 759 760 for (i = 0; i < 8; i++) { 761 if (letoh32(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 762 return; 763 } 764 } else { 765 usb_syncmem(&itd->dma, 766 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 767 sizeof(itd->sitd.sitd_trans), 768 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 769 770 if (le32toh(itd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 771 return; 772 } 773 774 /* All descriptor(s) inactive, it's done */ 775 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 776 timeout_del(&xfer->timeout_handle); 777 usb_rem_task(xfer->pipe->device, &xfer->abort_task); 778 ehci_isoc_idone(xfer); 779 } 780 781 void 782 ehci_isoc_idone(struct usbd_xfer *xfer) 783 { 784 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 785 struct ehci_soft_itd *itd; 786 int i, len, uframes, nframes = 0, actlen = 0; 787 uint32_t status = 0; 788 789 if (xfer->status == USBD_CANCELLED || xfer->status == USBD_TIMEOUT) 790 return; 791 792 if (xfer->device->speed == USB_SPEED_HIGH) { 793 switch (xfer->pipe->endpoint->edesc->bInterval) { 794 case 0: 795 panic("isoc xfer suddenly has 0 bInterval, invalid"); 796 case 1: 797 uframes = 1; 798 break; 799 case 2: 800 uframes = 2; 801 break; 802 case 3: 803 uframes = 4; 804 break; 805 default: 806 uframes = 8; 807 break; 808 } 809 810 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 811 usb_syncmem(&itd->dma, 812 itd->offs + offsetof(struct ehci_itd, itd_ctl), 813 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 814 BUS_DMASYNC_POSTREAD); 815 816 for (i = 0; i < 8; i += uframes) { 817 /* XXX - driver didn't fill in the frame full 818 * of uframes. This leads to scheduling 819 * inefficiencies, but working around 820 * this doubles complexity of tracking 821 * an xfer. 822 */ 823 if (nframes >= xfer->nframes) 824 break; 825 826 status = letoh32(itd->itd.itd_ctl[i]); 827 len = EHCI_ITD_GET_LEN(status); 828 if (EHCI_ITD_GET_STATUS(status) != 0) 829 len = 0; /*No valid data on error*/ 830 831 xfer->frlengths[nframes++] = len; 832 actlen += len; 833 } 834 } 835 } else { 836 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 837 usb_syncmem(&itd->dma, 838 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 839 sizeof(itd->sitd.sitd_trans), 840 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 841 842 status = le32toh(itd->sitd.sitd_trans); 843 len = EHCI_SITD_GET_LEN(status); 844 if (xfer->frlengths[nframes] >= len) 845 len = xfer->frlengths[nframes] - len; 846 else 847 len = 0; 848 849 xfer->frlengths[nframes++] = len; 850 actlen += len; 851 } 852 } 853 854 #ifdef DIAGNOSTIC 855 ex->isdone = 1; 856 #endif 857 xfer->actlen = actlen; 858 xfer->status = USBD_NORMAL_COMPLETION; 859 usb_transfer_complete(xfer); 860 } 861 862 void 863 ehci_idone(struct usbd_xfer *xfer) 864 { 865 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 866 struct ehci_soft_qtd *sqtd; 867 u_int32_t status = 0, nstatus = 0; 868 int actlen, cerr; 869 870 #ifdef DIAGNOSTIC 871 { 872 int s = splhigh(); 873 if (ex->isdone) { 874 splx(s); 875 printf("ehci_idone: ex=%p is done!\n", ex); 876 return; 877 } 878 ex->isdone = 1; 879 splx(s); 880 } 881 #endif 882 if (xfer->status == USBD_CANCELLED || xfer->status == USBD_TIMEOUT) 883 return; 884 885 actlen = 0; 886 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) { 887 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 888 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 889 nstatus = letoh32(sqtd->qtd.qtd_status); 890 if (nstatus & EHCI_QTD_ACTIVE) 891 break; 892 893 status = nstatus; 894 /* halt is ok if descriptor is last, and complete */ 895 if (sqtd->qtd.qtd_next == htole32(EHCI_LINK_TERMINATE) && 896 EHCI_QTD_GET_BYTES(status) == 0) 897 status &= ~EHCI_QTD_HALTED; 898 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 899 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 900 } 901 902 cerr = EHCI_QTD_GET_CERR(status); 903 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 904 "status=0x%x\n", xfer->length, actlen, cerr, status)); 905 xfer->actlen = actlen; 906 if ((status & EHCI_QTD_HALTED) != 0) { 907 if ((status & EHCI_QTD_BABBLE) == 0 && cerr > 0) 908 xfer->status = USBD_STALLED; 909 else 910 xfer->status = USBD_IOERROR; /* more info XXX */ 911 } else 912 xfer->status = USBD_NORMAL_COMPLETION; 913 914 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 915 * during this call, before methods->done is called: dma sync required 916 * beforehand? */ 917 usb_transfer_complete(xfer); 918 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 919 } 920 921 /* 922 * Wait here until controller claims to have an interrupt. 923 * Then call ehci_intr and return. Use timeout to avoid waiting 924 * too long. 925 */ 926 void 927 ehci_waitintr(struct ehci_softc *sc, struct usbd_xfer *xfer) 928 { 929 int timo; 930 u_int32_t intrs; 931 932 xfer->status = USBD_IN_PROGRESS; 933 for (timo = xfer->timeout; timo >= 0; timo--) { 934 usb_delay_ms(&sc->sc_bus, 1); 935 if (sc->sc_bus.dying) 936 break; 937 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 938 sc->sc_eintrs; 939 if (intrs) { 940 ehci_intr1(sc); 941 if (xfer->status != USBD_IN_PROGRESS) 942 return; 943 } 944 } 945 946 /* Timeout */ 947 xfer->status = USBD_TIMEOUT; 948 usb_transfer_complete(xfer); 949 /* XXX should free TD */ 950 } 951 952 void 953 ehci_poll(struct usbd_bus *bus) 954 { 955 struct ehci_softc *sc = (struct ehci_softc *)bus; 956 957 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 958 ehci_intr1(sc); 959 } 960 961 int 962 ehci_detach(struct device *self, int flags) 963 { 964 struct ehci_softc *sc = (struct ehci_softc *)self; 965 int rv; 966 967 rv = config_detach_children(self, flags); 968 if (rv != 0) 969 return (rv); 970 971 timeout_del(&sc->sc_tmo_intrlist); 972 973 ehci_reset(sc); 974 975 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 976 977 free(sc->sc_softitds, M_USB, sc->sc_flsize); 978 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 979 /* XXX free other data structures XXX */ 980 981 return (rv); 982 } 983 984 985 int 986 ehci_activate(struct device *self, int act) 987 { 988 struct ehci_softc *sc = (struct ehci_softc *)self; 989 u_int32_t cmd, hcr, cparams; 990 int i, rv = 0; 991 992 switch (act) { 993 case DVACT_SUSPEND: 994 rv = config_activate_children(self, act); 995 996 #ifdef DIAGNOSTIC 997 if (!TAILQ_EMPTY(&sc->sc_intrhead)) { 998 printf("%s: interrupt list not empty\n", 999 sc->sc_bus.bdev.dv_xname); 1000 return (-1); 1001 } 1002 #endif 1003 1004 sc->sc_bus.use_polling++; 1005 1006 for (i = 1; i <= sc->sc_noport; i++) { 1007 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1008 if ((cmd & (EHCI_PS_PO|EHCI_PS_PE)) == EHCI_PS_PE) 1009 EOWRITE4(sc, EHCI_PORTSC(i), 1010 cmd | EHCI_PS_SUSP); 1011 } 1012 1013 /* 1014 * First tell the host to stop processing Asynchronous 1015 * and Periodic schedules. 1016 */ 1017 cmd = EOREAD4(sc, EHCI_USBCMD) & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1018 EOWRITE4(sc, EHCI_USBCMD, cmd); 1019 for (i = 0; i < 100; i++) { 1020 usb_delay_ms(&sc->sc_bus, 1); 1021 hcr = EOREAD4(sc, EHCI_USBSTS) & 1022 (EHCI_STS_ASS | EHCI_STS_PSS); 1023 if (hcr == 0) 1024 break; 1025 } 1026 if (hcr != 0) 1027 printf("%s: disable schedules timeout\n", 1028 sc->sc_bus.bdev.dv_xname); 1029 1030 /* 1031 * Then reset the host as if it was a shutdown. 1032 * 1033 * All USB devices are disconnected/reconnected during 1034 * a suspend/resume cycle so keep it simple. 1035 */ 1036 ehci_reset(sc); 1037 1038 sc->sc_bus.use_polling--; 1039 break; 1040 case DVACT_RESUME: 1041 sc->sc_bus.use_polling++; 1042 1043 ehci_reset(sc); 1044 1045 cparams = EREAD4(sc, EHCI_HCCPARAMS); 1046 /* MUST clear segment register if 64 bit capable. */ 1047 if (EHCI_HCC_64BIT(cparams)) 1048 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1049 1050 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1051 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1052 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1053 1054 hcr = 0; 1055 for (i = 1; i <= sc->sc_noport; i++) { 1056 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1057 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == EHCI_PS_SUSP) { 1058 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1059 hcr = 1; 1060 } 1061 } 1062 1063 if (hcr) { 1064 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1065 for (i = 1; i <= sc->sc_noport; i++) { 1066 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1067 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == 1068 EHCI_PS_SUSP) 1069 EOWRITE4(sc, EHCI_PORTSC(i), 1070 cmd & ~EHCI_PS_FPR); 1071 } 1072 } 1073 1074 /* Turn on controller */ 1075 EOWRITE4(sc, EHCI_USBCMD, 1076 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 1077 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 1078 EHCI_CMD_ASE | 1079 EHCI_CMD_PSE | 1080 EHCI_CMD_RS); 1081 1082 /* Take over port ownership */ 1083 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 1084 for (i = 0; i < 100; i++) { 1085 usb_delay_ms(&sc->sc_bus, 1); 1086 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1087 if (!hcr) 1088 break; 1089 } 1090 1091 if (hcr) { 1092 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 1093 /* XXX should we bail here? */ 1094 } 1095 1096 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1097 1098 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1099 1100 sc->sc_bus.use_polling--; 1101 rv = config_activate_children(self, act); 1102 break; 1103 case DVACT_POWERDOWN: 1104 rv = config_activate_children(self, act); 1105 ehci_reset(sc); 1106 break; 1107 default: 1108 rv = config_activate_children(self, act); 1109 break; 1110 } 1111 return (rv); 1112 } 1113 1114 usbd_status 1115 ehci_reset(struct ehci_softc *sc) 1116 { 1117 u_int32_t hcr; 1118 int i; 1119 1120 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1121 for (i = 0; i < 100; i++) { 1122 usb_delay_ms(&sc->sc_bus, 1); 1123 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1124 if (hcr) 1125 break; 1126 } 1127 1128 if (!hcr) 1129 printf("%s: halt timeout\n", sc->sc_bus.bdev.dv_xname); 1130 1131 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1132 for (i = 0; i < 100; i++) { 1133 usb_delay_ms(&sc->sc_bus, 1); 1134 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 1135 if (!hcr) 1136 break; 1137 } 1138 1139 if (hcr) { 1140 printf("%s: reset timeout\n", sc->sc_bus.bdev.dv_xname); 1141 return (USBD_IOERROR); 1142 } 1143 1144 return (USBD_NORMAL_COMPLETION); 1145 } 1146 1147 struct usbd_xfer * 1148 ehci_allocx(struct usbd_bus *bus) 1149 { 1150 struct ehci_xfer *ex; 1151 1152 ex = pool_get(ehcixfer, PR_NOWAIT | PR_ZERO); 1153 #ifdef DIAGNOSTIC 1154 if (ex != NULL) 1155 ex->isdone = 1; 1156 #endif 1157 return ((struct usbd_xfer *)ex); 1158 } 1159 1160 void 1161 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1162 { 1163 struct ehci_xfer *ex = (struct ehci_xfer*)xfer; 1164 1165 #ifdef DIAGNOSTIC 1166 if (!ex->isdone) { 1167 printf("%s: !isdone\n", __func__); 1168 return; 1169 } 1170 #endif 1171 pool_put(ehcixfer, ex); 1172 } 1173 1174 void 1175 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1176 { 1177 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1178 1179 #ifdef DIAGNOSTIC 1180 if ((epipe->sqh->qh.qh_qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) != 0) 1181 panic("ehci_device_clear_toggle: queue active"); 1182 #endif 1183 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1184 } 1185 1186 #ifdef EHCI_DEBUG 1187 void 1188 ehci_dump_regs(struct ehci_softc *sc) 1189 { 1190 int i; 1191 1192 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1193 EOREAD4(sc, EHCI_USBCMD), 1194 EOREAD4(sc, EHCI_USBSTS), 1195 EOREAD4(sc, EHCI_USBINTR)); 1196 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1197 EOREAD4(sc, EHCI_FRINDEX), 1198 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1199 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1200 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1201 for (i = 1; i <= sc->sc_noport; i++) 1202 printf("port %d status=0x%08x\n", i, 1203 EOREAD4(sc, EHCI_PORTSC(i))); 1204 } 1205 1206 /* 1207 * Unused function - this is meant to be called from a kernel 1208 * debugger. 1209 */ 1210 void 1211 ehci_dump(void) 1212 { 1213 ehci_dump_regs(theehci); 1214 } 1215 1216 void 1217 ehci_dump_link(ehci_link_t link, int type) 1218 { 1219 link = letoh32(link); 1220 printf("0x%08x", link); 1221 if (link & EHCI_LINK_TERMINATE) 1222 printf("<T>"); 1223 else { 1224 printf("<"); 1225 if (type) { 1226 switch (EHCI_LINK_TYPE(link)) { 1227 case EHCI_LINK_ITD: 1228 printf("ITD"); 1229 break; 1230 case EHCI_LINK_QH: 1231 printf("QH"); 1232 break; 1233 case EHCI_LINK_SITD: 1234 printf("SITD"); 1235 break; 1236 case EHCI_LINK_FSTN: 1237 printf("FSTN"); 1238 break; 1239 } 1240 } 1241 printf(">"); 1242 } 1243 } 1244 1245 void 1246 ehci_dump_sqtds(struct ehci_soft_qtd *sqtd) 1247 { 1248 int i; 1249 u_int32_t stop; 1250 1251 stop = 0; 1252 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1253 ehci_dump_sqtd(sqtd); 1254 usb_syncmem(&sqtd->dma, 1255 sqtd->offs + offsetof(struct ehci_qtd, qtd_next), 1256 sizeof(sqtd->qtd), 1257 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1258 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1259 usb_syncmem(&sqtd->dma, 1260 sqtd->offs + offsetof(struct ehci_qtd, qtd_next), 1261 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1262 } 1263 if (!stop) 1264 printf("dump aborted, too many TDs\n"); 1265 } 1266 1267 void 1268 ehci_dump_sqtd(struct ehci_soft_qtd *sqtd) 1269 { 1270 usb_syncmem(&sqtd->dma, sqtd->offs, 1271 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1272 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1273 ehci_dump_qtd(&sqtd->qtd); 1274 usb_syncmem(&sqtd->dma, sqtd->offs, 1275 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1276 } 1277 1278 void 1279 ehci_dump_qtd(struct ehci_qtd *qtd) 1280 { 1281 u_int32_t s; 1282 char sbuf[128]; 1283 1284 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1285 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1286 printf("\n"); 1287 s = letoh32(qtd->qtd_status); 1288 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), "\20\10ACTIVE\7HALTED" 1289 "\6BUFERR\5BABBLE\4XACTERR\3MISSED\2SPLIT\1PING", 1290 sbuf, sizeof(sbuf)); 1291 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1292 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1293 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1294 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1295 EHCI_QTD_GET_PID(s), sbuf); 1296 for (s = 0; s < 5; s++) 1297 printf(" buffer[%d]=0x%08x\n", s, letoh32(qtd->qtd_buffer[s])); 1298 } 1299 1300 void 1301 ehci_dump_sqh(struct ehci_soft_qh *sqh) 1302 { 1303 struct ehci_qh *qh = &sqh->qh; 1304 u_int32_t endp, endphub; 1305 1306 usb_syncmem(&sqh->dma, sqh->offs, 1307 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1308 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1309 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1310 endp = letoh32(qh->qh_endp); 1311 printf(" endp=0x%08x\n", endp); 1312 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1313 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1314 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1315 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1316 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1317 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1318 EHCI_QH_GET_NRL(endp)); 1319 endphub = letoh32(qh->qh_endphub); 1320 printf(" endphub=0x%08x\n", endphub); 1321 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1322 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1323 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1324 EHCI_QH_GET_MULT(endphub)); 1325 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1326 printf("Overlay qTD:\n"); 1327 ehci_dump_qtd(&qh->qh_qtd); 1328 usb_syncmem(&sqh->dma, sqh->offs, 1329 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1330 } 1331 1332 #if notyet 1333 void 1334 ehci_dump_itd(struct ehci_soft_itd *itd) 1335 { 1336 ehci_isoc_trans_t t; 1337 ehci_isoc_bufr_ptr_t b, b2, b3; 1338 int i; 1339 1340 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1341 1342 for (i = 0; i < 8; i++) { 1343 t = letoh32(itd->itd.itd_ctl[i]); 1344 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1345 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1346 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1347 EHCI_ITD_GET_OFFS(t)); 1348 } 1349 printf("ITDbufr: "); 1350 for (i = 0; i < 7; i++) 1351 printf("%X,", EHCI_ITD_GET_BPTR(letoh32(itd->itd.itd_bufr[i]))); 1352 1353 b = letoh32(itd->itd.itd_bufr[0]); 1354 b2 = letoh32(itd->itd.itd_bufr[1]); 1355 b3 = letoh32(itd->itd.itd_bufr[2]); 1356 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1357 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1358 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1359 } 1360 #endif 1361 1362 #ifdef DIAGNOSTIC 1363 void 1364 ehci_dump_exfer(struct ehci_xfer *ex) 1365 { 1366 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p " 1367 "isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, 1368 ex->itdend, ex->isdone); 1369 } 1370 #endif 1371 1372 #endif /* EHCI_DEBUG */ 1373 1374 usbd_status 1375 ehci_open(struct usbd_pipe *pipe) 1376 { 1377 struct usbd_device *dev = pipe->device; 1378 struct ehci_softc *sc = (struct ehci_softc *)dev->bus; 1379 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1380 u_int8_t addr = dev->address; 1381 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1382 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1383 struct ehci_soft_qh *sqh; 1384 usbd_status err; 1385 int s; 1386 int ival, speed, naks; 1387 int hshubaddr, hshubport; 1388 1389 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d\n", 1390 pipe, addr, ed->bEndpointAddress)); 1391 1392 if (sc->sc_bus.dying) 1393 return (USBD_IOERROR); 1394 1395 if (dev->myhsport) { 1396 hshubaddr = dev->myhsport->parent->address; 1397 hshubport = dev->myhsport->portno; 1398 } else { 1399 hshubaddr = 0; 1400 hshubport = 0; 1401 } 1402 1403 /* Root Hub */ 1404 if (pipe->device->depth == 0) { 1405 switch (ed->bEndpointAddress) { 1406 case USB_CONTROL_ENDPOINT: 1407 pipe->methods = &ehci_root_ctrl_methods; 1408 break; 1409 case UE_DIR_IN | EHCI_INTR_ENDPT: 1410 pipe->methods = &ehci_root_intr_methods; 1411 break; 1412 default: 1413 return (USBD_INVAL); 1414 } 1415 return (USBD_NORMAL_COMPLETION); 1416 } 1417 1418 /* XXX All this stuff is only valid for async. */ 1419 switch (dev->speed) { 1420 case USB_SPEED_LOW: 1421 speed = EHCI_QH_SPEED_LOW; 1422 break; 1423 case USB_SPEED_FULL: 1424 speed = EHCI_QH_SPEED_FULL; 1425 break; 1426 case USB_SPEED_HIGH: 1427 speed = EHCI_QH_SPEED_HIGH; 1428 break; 1429 default: 1430 panic("ehci_open: bad device speed %d", dev->speed); 1431 } 1432 1433 naks = 8; /* XXX */ 1434 1435 /* Allocate sqh for everything, save isoc xfers */ 1436 if (xfertype != UE_ISOCHRONOUS) { 1437 sqh = ehci_alloc_sqh(sc); 1438 if (sqh == NULL) 1439 return (USBD_NOMEM); 1440 /* qh_link filled when the QH is added */ 1441 sqh->qh.qh_endp = htole32( 1442 EHCI_QH_SET_ADDR(addr) | 1443 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1444 EHCI_QH_SET_EPS(speed) | 1445 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1446 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1447 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1448 EHCI_QH_CTL : 0) | 1449 EHCI_QH_SET_NRL(naks) 1450 ); 1451 sqh->qh.qh_endphub = htole32( 1452 EHCI_QH_SET_MULT(1) | 1453 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0) 1454 ); 1455 if (speed != EHCI_QH_SPEED_HIGH) { 1456 sqh->qh.qh_endphub |= htole32( 1457 EHCI_QH_SET_HUBA(hshubaddr) | 1458 EHCI_QH_SET_PORT(hshubport) | 1459 EHCI_QH_SET_CMASK(0x1c) /* XXX */ 1460 ); 1461 } 1462 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 1463 /* Fill the overlay qTD */ 1464 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 1465 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1466 sqh->qh.qh_qtd.qtd_status = 1467 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1468 1469 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1470 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1471 epipe->sqh = sqh; 1472 } /*xfertype == UE_ISOC*/ 1473 1474 switch (xfertype) { 1475 case UE_CONTROL: 1476 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1477 0, &epipe->u.ctl.reqdma); 1478 if (err) { 1479 ehci_free_sqh(sc, sqh); 1480 return (err); 1481 } 1482 pipe->methods = &ehci_device_ctrl_methods; 1483 s = splusb(); 1484 ehci_add_qh(sqh, sc->sc_async_head); 1485 splx(s); 1486 break; 1487 case UE_BULK: 1488 pipe->methods = &ehci_device_bulk_methods; 1489 s = splusb(); 1490 ehci_add_qh(sqh, sc->sc_async_head); 1491 splx(s); 1492 break; 1493 case UE_INTERRUPT: 1494 pipe->methods = &ehci_device_intr_methods; 1495 ival = pipe->interval; 1496 if (ival == USBD_DEFAULT_INTERVAL) 1497 ival = ed->bInterval; 1498 s = splusb(); 1499 err = ehci_device_setintr(sc, sqh, ival); 1500 splx(s); 1501 return (err); 1502 case UE_ISOCHRONOUS: 1503 switch (speed) { 1504 case EHCI_QH_SPEED_HIGH: 1505 case EHCI_QH_SPEED_FULL: 1506 pipe->methods = &ehci_device_isoc_methods; 1507 break; 1508 case EHCI_QH_SPEED_LOW: 1509 default: 1510 return (USBD_INVAL); 1511 } 1512 /* Spec page 271 says intervals > 16 are invalid */ 1513 if (ed->bInterval == 0 || ed->bInterval > 16) { 1514 printf("ehci: opening pipe with invalid bInterval\n"); 1515 return (USBD_INVAL); 1516 } 1517 if (UGETW(ed->wMaxPacketSize) == 0) { 1518 printf("ehci: zero length endpoint open request\n"); 1519 return (USBD_INVAL); 1520 } 1521 epipe->u.isoc.next_frame = 0; 1522 epipe->u.isoc.cur_xfers = 0; 1523 break; 1524 default: 1525 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1526 return (USBD_INVAL); 1527 } 1528 return (USBD_NORMAL_COMPLETION); 1529 } 1530 1531 /* 1532 * Add an ED to the schedule. Called at splusb(). 1533 * If in the async schedule, it will always have a next. 1534 * If in the intr schedule it may not. 1535 */ 1536 void 1537 ehci_add_qh(struct ehci_soft_qh *sqh, struct ehci_soft_qh *head) 1538 { 1539 SPLUSBCHECK; 1540 1541 usb_syncmem(&head->dma, head->offs + offsetof(struct ehci_qh, qh_link), 1542 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1543 sqh->next = head->next; 1544 sqh->prev = head; 1545 sqh->qh.qh_link = head->qh.qh_link; 1546 usb_syncmem(&sqh->dma, sqh->offs + offsetof(struct ehci_qh, qh_link), 1547 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1548 head->next = sqh; 1549 if (sqh->next) 1550 sqh->next->prev = sqh; 1551 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1552 usb_syncmem(&head->dma, head->offs + offsetof(struct ehci_qh, qh_link), 1553 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1554 } 1555 1556 /* 1557 * Remove an ED from the schedule. Called at splusb(). 1558 * Will always have a 'next' if it's in the async list as it's circular. 1559 */ 1560 void 1561 ehci_rem_qh(struct ehci_softc *sc, struct ehci_soft_qh *sqh) 1562 { 1563 SPLUSBCHECK; 1564 /* XXX */ 1565 usb_syncmem(&sqh->dma, sqh->offs + offsetof(struct ehci_qh, qh_link), 1566 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1567 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1568 sqh->prev->next = sqh->next; 1569 if (sqh->next) 1570 sqh->next->prev = sqh->prev; 1571 usb_syncmem(&sqh->prev->dma, 1572 sqh->prev->offs + offsetof(struct ehci_qh, qh_link), 1573 sizeof(sqh->prev->qh.qh_link), BUS_DMASYNC_PREWRITE); 1574 1575 ehci_sync_hc(sc); 1576 } 1577 1578 void 1579 ehci_set_qh_qtd(struct ehci_soft_qh *sqh, struct ehci_soft_qtd *sqtd) 1580 { 1581 int i; 1582 u_int32_t status; 1583 1584 /* Save toggle bit and ping status. */ 1585 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1586 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1587 status = sqh->qh.qh_qtd.qtd_status & 1588 htole32(EHCI_QTD_TOGGLE_MASK | 1589 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1590 /* Set HALTED to make hw leave it alone. */ 1591 sqh->qh.qh_qtd.qtd_status = 1592 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1593 usb_syncmem(&sqh->dma, 1594 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 1595 sizeof(sqh->qh.qh_qtd.qtd_status), 1596 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1597 sqh->qh.qh_curqtd = 0; 1598 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1599 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1600 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1601 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1602 sqh->sqtd = sqtd; 1603 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1604 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1605 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1606 sqh->qh.qh_qtd.qtd_status = status; 1607 usb_syncmem(&sqh->dma, 1608 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 1609 sizeof(sqh->qh.qh_qtd.qtd_status), 1610 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1611 } 1612 1613 /* 1614 * Ensure that the HC has released all references to the QH. We do this 1615 * by asking for a Async Advance Doorbell interrupt and then we wait for 1616 * the interrupt. 1617 * To make this easier we first obtain exclusive use of the doorbell. 1618 */ 1619 void 1620 ehci_sync_hc(struct ehci_softc *sc) 1621 { 1622 int s, error; 1623 int tries = 0; 1624 1625 if (sc->sc_bus.dying) { 1626 return; 1627 } 1628 1629 /* get doorbell */ 1630 rw_enter_write(&sc->sc_doorbell_lock); 1631 s = splhardusb(); 1632 do { 1633 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | 1634 EHCI_CMD_IAAD); 1635 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz / 2); 1636 } while (error && ++tries < 10); 1637 splx(s); 1638 /* release doorbell */ 1639 rw_exit_write(&sc->sc_doorbell_lock); 1640 #ifdef DIAGNOSTIC 1641 if (error) 1642 printf("ehci_sync_hc: tsleep() = %d\n", error); 1643 #endif 1644 } 1645 1646 void 1647 ehci_rem_itd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 1648 { 1649 struct ehci_soft_itd *itd, *prev = NULL; 1650 1651 splsoftassert(IPL_SOFTUSB); 1652 1653 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 1654 1655 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1656 prev = itd->u.frame_list.prev; 1657 /* Unlink itd from hardware chain, or frame array */ 1658 if (prev == NULL) { /* We're at the table head */ 1659 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1660 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1661 usb_syncmem(&sc->sc_fldma, 1662 sizeof(uint32_t) * itd->slot, sizeof(uint32_t), 1663 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1664 1665 if (itd->u.frame_list.next != NULL) 1666 itd->u.frame_list.next->u.frame_list.prev = 1667 NULL; 1668 } else { 1669 /* XXX this part is untested... */ 1670 prev->itd.itd_next = itd->itd.itd_next; 1671 usb_syncmem(&itd->dma, 1672 itd->offs + offsetof(struct ehci_itd, itd_next), 1673 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1674 1675 prev->u.frame_list.next = itd->u.frame_list.next; 1676 if (itd->u.frame_list.next != NULL) 1677 itd->u.frame_list.next->u.frame_list.prev = 1678 prev; 1679 } 1680 } 1681 } 1682 1683 void 1684 ehci_free_itd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 1685 { 1686 struct ehci_soft_itd *itd, *prev = NULL; 1687 1688 splsoftassert(IPL_SOFTUSB); 1689 1690 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 1691 1692 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1693 if (prev != NULL) 1694 ehci_free_itd(sc, prev); 1695 prev = itd; 1696 } 1697 if (prev) 1698 ehci_free_itd(sc, prev); 1699 ex->itdstart = NULL; 1700 ex->itdend = NULL; 1701 } 1702 1703 /* 1704 * Data structures and routines to emulate the root hub. 1705 */ 1706 usb_device_descriptor_t ehci_devd = { 1707 USB_DEVICE_DESCRIPTOR_SIZE, 1708 UDESC_DEVICE, /* type */ 1709 {0x00, 0x02}, /* USB version */ 1710 UDCLASS_HUB, /* class */ 1711 UDSUBCLASS_HUB, /* subclass */ 1712 UDPROTO_HSHUBSTT, /* protocol */ 1713 64, /* max packet */ 1714 {0},{0},{0x00,0x01}, /* device id */ 1715 1,2,0, /* string indicies */ 1716 1 /* # of configurations */ 1717 }; 1718 1719 usb_device_qualifier_t ehci_odevd = { 1720 USB_DEVICE_DESCRIPTOR_SIZE, 1721 UDESC_DEVICE_QUALIFIER, /* type */ 1722 {0x00, 0x02}, /* USB version */ 1723 UDCLASS_HUB, /* class */ 1724 UDSUBCLASS_HUB, /* subclass */ 1725 UDPROTO_FSHUB, /* protocol */ 1726 64, /* max packet */ 1727 1, /* # of configurations */ 1728 0 1729 }; 1730 1731 usb_config_descriptor_t ehci_confd = { 1732 USB_CONFIG_DESCRIPTOR_SIZE, 1733 UDESC_CONFIG, 1734 {USB_CONFIG_DESCRIPTOR_SIZE + 1735 USB_INTERFACE_DESCRIPTOR_SIZE + 1736 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1737 1, 1738 1, 1739 0, 1740 UC_SELF_POWERED, 1741 0 /* max power */ 1742 }; 1743 1744 usb_interface_descriptor_t ehci_ifcd = { 1745 USB_INTERFACE_DESCRIPTOR_SIZE, 1746 UDESC_INTERFACE, 1747 0, 1748 0, 1749 1, 1750 UICLASS_HUB, 1751 UISUBCLASS_HUB, 1752 UIPROTO_HSHUBSTT, 1753 0 1754 }; 1755 1756 usb_endpoint_descriptor_t ehci_endpd = { 1757 USB_ENDPOINT_DESCRIPTOR_SIZE, 1758 UDESC_ENDPOINT, 1759 UE_DIR_IN | EHCI_INTR_ENDPT, 1760 UE_INTERRUPT, 1761 {8, 0}, /* max packet */ 1762 12 1763 }; 1764 1765 usb_hub_descriptor_t ehci_hubd = { 1766 USB_HUB_DESCRIPTOR_SIZE, 1767 UDESC_HUB, 1768 0, 1769 {0,0}, 1770 0, 1771 0, 1772 {0}, 1773 }; 1774 1775 /* 1776 * Simulate a hardware hub by handling all the necessary requests. 1777 */ 1778 usbd_status 1779 ehci_root_ctrl_transfer(struct usbd_xfer *xfer) 1780 { 1781 usbd_status err; 1782 1783 /* Insert last in queue. */ 1784 err = usb_insert_transfer(xfer); 1785 if (err) 1786 return (err); 1787 1788 /* Pipe isn't running, start first */ 1789 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1790 } 1791 1792 usbd_status 1793 ehci_root_ctrl_start(struct usbd_xfer *xfer) 1794 { 1795 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1796 usb_device_request_t *req; 1797 void *buf = NULL; 1798 int port, i; 1799 int s, len, value, index, l, totlen = 0; 1800 usb_port_status_t ps; 1801 usb_hub_descriptor_t hubd; 1802 usbd_status err; 1803 u_int32_t v; 1804 1805 if (sc->sc_bus.dying) 1806 return (USBD_IOERROR); 1807 1808 #ifdef DIAGNOSTIC 1809 if (!(xfer->rqflags & URQ_REQUEST)) 1810 /* XXX panic */ 1811 return (USBD_INVAL); 1812 #endif 1813 req = &xfer->request; 1814 1815 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1816 req->bmRequestType, req->bRequest)); 1817 1818 len = UGETW(req->wLength); 1819 value = UGETW(req->wValue); 1820 index = UGETW(req->wIndex); 1821 1822 if (len != 0) 1823 buf = KERNADDR(&xfer->dmabuf, 0); 1824 1825 #define C(x,y) ((x) | ((y) << 8)) 1826 switch(C(req->bRequest, req->bmRequestType)) { 1827 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1828 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1829 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1830 /* 1831 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1832 * for the integrated root hub. 1833 */ 1834 break; 1835 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1836 if (len > 0) { 1837 *(u_int8_t *)buf = sc->sc_conf; 1838 totlen = 1; 1839 } 1840 break; 1841 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1842 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1843 switch(value >> 8) { 1844 case UDESC_DEVICE: 1845 if ((value & 0xff) != 0) { 1846 err = USBD_IOERROR; 1847 goto ret; 1848 } 1849 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1850 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1851 memcpy(buf, &ehci_devd, l); 1852 break; 1853 /* 1854 * We can't really operate at another speed, but the spec says 1855 * we need this descriptor. 1856 */ 1857 case UDESC_DEVICE_QUALIFIER: 1858 if ((value & 0xff) != 0) { 1859 err = USBD_IOERROR; 1860 goto ret; 1861 } 1862 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1863 memcpy(buf, &ehci_odevd, l); 1864 break; 1865 /* 1866 * We can't really operate at another speed, but the spec says 1867 * we need this descriptor. 1868 */ 1869 case UDESC_OTHER_SPEED_CONFIGURATION: 1870 case UDESC_CONFIG: 1871 if ((value & 0xff) != 0) { 1872 err = USBD_IOERROR; 1873 goto ret; 1874 } 1875 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1876 memcpy(buf, &ehci_confd, l); 1877 ((usb_config_descriptor_t *)buf)->bDescriptorType = 1878 value >> 8; 1879 buf = (char *)buf + l; 1880 len -= l; 1881 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1882 totlen += l; 1883 memcpy(buf, &ehci_ifcd, l); 1884 buf = (char *)buf + l; 1885 len -= l; 1886 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1887 totlen += l; 1888 memcpy(buf, &ehci_endpd, l); 1889 break; 1890 case UDESC_STRING: 1891 if (len == 0) 1892 break; 1893 *(u_int8_t *)buf = 0; 1894 totlen = 1; 1895 switch (value & 0xff) { 1896 case 0: /* Language table */ 1897 totlen = usbd_str(buf, len, "\001"); 1898 break; 1899 case 1: /* Vendor */ 1900 totlen = usbd_str(buf, len, sc->sc_vendor); 1901 break; 1902 case 2: /* Product */ 1903 totlen = usbd_str(buf, len, "EHCI root hub"); 1904 break; 1905 } 1906 break; 1907 default: 1908 err = USBD_IOERROR; 1909 goto ret; 1910 } 1911 break; 1912 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1913 if (len > 0) { 1914 *(u_int8_t *)buf = 0; 1915 totlen = 1; 1916 } 1917 break; 1918 case C(UR_GET_STATUS, UT_READ_DEVICE): 1919 if (len > 1) { 1920 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1921 totlen = 2; 1922 } 1923 break; 1924 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1925 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1926 if (len > 1) { 1927 USETW(((usb_status_t *)buf)->wStatus, 0); 1928 totlen = 2; 1929 } 1930 break; 1931 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1932 if (value >= USB_MAX_DEVICES) { 1933 err = USBD_IOERROR; 1934 goto ret; 1935 } 1936 break; 1937 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1938 if (value != 0 && value != 1) { 1939 err = USBD_IOERROR; 1940 goto ret; 1941 } 1942 sc->sc_conf = value; 1943 break; 1944 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1945 break; 1946 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1947 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1948 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1949 err = USBD_IOERROR; 1950 goto ret; 1951 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1952 break; 1953 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1954 break; 1955 /* Hub requests */ 1956 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1957 break; 1958 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1959 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 1960 "port=%d feature=%d\n", index, value)); 1961 if (index < 1 || index > sc->sc_noport) { 1962 err = USBD_IOERROR; 1963 goto ret; 1964 } 1965 port = EHCI_PORTSC(index); 1966 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 1967 switch(value) { 1968 case UHF_PORT_ENABLE: 1969 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 1970 break; 1971 case UHF_PORT_SUSPEND: 1972 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 1973 break; 1974 case UHF_PORT_POWER: 1975 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 1976 break; 1977 case UHF_PORT_TEST: 1978 DPRINTFN(2,("ehci_root_ctrl_start: " 1979 "clear port test %d\n", index)); 1980 break; 1981 case UHF_PORT_INDICATOR: 1982 DPRINTFN(2,("ehci_root_ctrl_start: " 1983 "clear port index %d\n", index)); 1984 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 1985 break; 1986 case UHF_C_PORT_CONNECTION: 1987 EOWRITE4(sc, port, v | EHCI_PS_CSC); 1988 break; 1989 case UHF_C_PORT_ENABLE: 1990 EOWRITE4(sc, port, v | EHCI_PS_PEC); 1991 break; 1992 case UHF_C_PORT_SUSPEND: 1993 /* how? */ 1994 break; 1995 case UHF_C_PORT_OVER_CURRENT: 1996 EOWRITE4(sc, port, v | EHCI_PS_OCC); 1997 break; 1998 case UHF_C_PORT_RESET: 1999 sc->sc_isreset = 0; 2000 break; 2001 default: 2002 err = USBD_IOERROR; 2003 goto ret; 2004 } 2005 break; 2006 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2007 if ((value & 0xff) != 0) { 2008 err = USBD_IOERROR; 2009 goto ret; 2010 } 2011 hubd = ehci_hubd; 2012 hubd.bNbrPorts = sc->sc_noport; 2013 v = EREAD4(sc, EHCI_HCSPARAMS); 2014 USETW(hubd.wHubCharacteristics, 2015 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 2016 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0)); 2017 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2018 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2019 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2020 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2021 l = min(len, hubd.bDescLength); 2022 totlen = l; 2023 memcpy(buf, &hubd, l); 2024 break; 2025 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2026 if (len != 4) { 2027 err = USBD_IOERROR; 2028 goto ret; 2029 } 2030 memset(buf, 0, len); /* ? XXX */ 2031 totlen = len; 2032 break; 2033 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2034 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2035 index)); 2036 if (index < 1 || index > sc->sc_noport) { 2037 err = USBD_IOERROR; 2038 goto ret; 2039 } 2040 if (len != 4) { 2041 err = USBD_IOERROR; 2042 goto ret; 2043 } 2044 v = EOREAD4(sc, EHCI_PORTSC(index)); 2045 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2046 i = UPS_HIGH_SPEED; 2047 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2048 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2049 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2050 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2051 if (v & EHCI_PS_PR) i |= UPS_RESET; 2052 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2053 USETW(ps.wPortStatus, i); 2054 i = 0; 2055 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2056 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2057 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2058 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 2059 USETW(ps.wPortChange, i); 2060 l = min(len, sizeof(ps)); 2061 memcpy(buf, &ps, l); 2062 totlen = l; 2063 break; 2064 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2065 err = USBD_IOERROR; 2066 goto ret; 2067 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2068 break; 2069 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2070 if (index < 1 || index > sc->sc_noport) { 2071 err = USBD_IOERROR; 2072 goto ret; 2073 } 2074 port = EHCI_PORTSC(index); 2075 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2076 switch(value) { 2077 case UHF_PORT_ENABLE: 2078 EOWRITE4(sc, port, v | EHCI_PS_PE); 2079 break; 2080 case UHF_PORT_SUSPEND: 2081 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2082 break; 2083 case UHF_PORT_DISOWN_TO_1_1: 2084 /* enter to Port Reset State */ 2085 v &= ~EHCI_PS_PE; 2086 EOWRITE4(sc, port, v | EHCI_PS_PR); 2087 ehci_disown(sc, index, 0); 2088 break; 2089 case UHF_PORT_RESET: 2090 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2091 index)); 2092 if (EHCI_PS_IS_LOWSPEED(v)) { 2093 /* Low speed device, give up ownership. */ 2094 ehci_disown(sc, index, 1); 2095 break; 2096 } 2097 /* Start reset sequence. */ 2098 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2099 EOWRITE4(sc, port, v | EHCI_PS_PR); 2100 /* Wait for reset to complete. */ 2101 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2102 if (sc->sc_bus.dying) { 2103 err = USBD_IOERROR; 2104 goto ret; 2105 } 2106 /* Terminate reset sequence. */ 2107 v = EOREAD4(sc, port); 2108 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2109 /* Wait for HC to complete reset. */ 2110 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2111 if (sc->sc_bus.dying) { 2112 err = USBD_IOERROR; 2113 goto ret; 2114 } 2115 v = EOREAD4(sc, port); 2116 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2117 if (v & EHCI_PS_PR) { 2118 printf("%s: port reset timeout\n", 2119 sc->sc_bus.bdev.dv_xname); 2120 err = USBD_IOERROR; 2121 goto ret; 2122 } 2123 if (!(v & EHCI_PS_PE)) { 2124 /* Not a high speed device, give up ownership.*/ 2125 ehci_disown(sc, index, 0); 2126 break; 2127 } 2128 sc->sc_isreset = 1; 2129 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2130 index, v)); 2131 break; 2132 case UHF_PORT_POWER: 2133 DPRINTFN(2,("ehci_root_ctrl_start: " 2134 "set port power %d\n", index)); 2135 EOWRITE4(sc, port, v | EHCI_PS_PP); 2136 break; 2137 case UHF_PORT_TEST: 2138 DPRINTFN(2,("ehci_root_ctrl_start: " 2139 "set port test %d\n", index)); 2140 break; 2141 case UHF_PORT_INDICATOR: 2142 DPRINTFN(2,("ehci_root_ctrl_start: " 2143 "set port ind %d\n", index)); 2144 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2145 break; 2146 default: 2147 err = USBD_IOERROR; 2148 goto ret; 2149 } 2150 break; 2151 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2152 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2153 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2154 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2155 break; 2156 default: 2157 err = USBD_IOERROR; 2158 goto ret; 2159 } 2160 xfer->actlen = totlen; 2161 err = USBD_NORMAL_COMPLETION; 2162 ret: 2163 xfer->status = err; 2164 s = splusb(); 2165 usb_transfer_complete(xfer); 2166 splx(s); 2167 return (USBD_IN_PROGRESS); 2168 } 2169 2170 void 2171 ehci_disown(struct ehci_softc *sc, int index, int lowspeed) 2172 { 2173 int port; 2174 u_int32_t v; 2175 2176 port = EHCI_PORTSC(index); 2177 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2178 EOWRITE4(sc, port, v | EHCI_PS_PO); 2179 } 2180 2181 /* Abort a root control request. */ 2182 void 2183 ehci_root_ctrl_abort(struct usbd_xfer *xfer) 2184 { 2185 /* Nothing to do, all transfers are synchronous. */ 2186 } 2187 2188 /* Close the root pipe. */ 2189 void 2190 ehci_root_ctrl_close(struct usbd_pipe *pipe) 2191 { 2192 /* Nothing to do. */ 2193 } 2194 2195 void 2196 ehci_root_intr_done(struct usbd_xfer *xfer) 2197 { 2198 } 2199 2200 usbd_status 2201 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2202 { 2203 usbd_status err; 2204 2205 /* Insert last in queue. */ 2206 err = usb_insert_transfer(xfer); 2207 if (err) 2208 return (err); 2209 2210 /* Pipe isn't running, start first */ 2211 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2212 } 2213 2214 usbd_status 2215 ehci_root_intr_start(struct usbd_xfer *xfer) 2216 { 2217 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2218 2219 if (sc->sc_bus.dying) 2220 return (USBD_IOERROR); 2221 2222 sc->sc_intrxfer = xfer; 2223 2224 return (USBD_IN_PROGRESS); 2225 } 2226 2227 void 2228 ehci_root_intr_abort(struct usbd_xfer *xfer) 2229 { 2230 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2231 int s; 2232 2233 sc->sc_intrxfer = NULL; 2234 2235 xfer->status = USBD_CANCELLED; 2236 s = splusb(); 2237 usb_transfer_complete(xfer); 2238 splx(s); 2239 } 2240 2241 void 2242 ehci_root_intr_close(struct usbd_pipe *pipe) 2243 { 2244 } 2245 2246 void 2247 ehci_root_ctrl_done(struct usbd_xfer *xfer) 2248 { 2249 } 2250 2251 struct ehci_soft_qh * 2252 ehci_alloc_sqh(struct ehci_softc *sc) 2253 { 2254 struct ehci_soft_qh *sqh = NULL; 2255 usbd_status err; 2256 int i, offs; 2257 struct usb_dma dma; 2258 int s; 2259 2260 s = splusb(); 2261 if (sc->sc_freeqhs == NULL) { 2262 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2263 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2264 EHCI_PAGE_SIZE, &dma); 2265 if (err) 2266 goto out; 2267 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2268 offs = i * EHCI_SQH_SIZE; 2269 sqh = KERNADDR(&dma, offs); 2270 sqh->physaddr = DMAADDR(&dma, offs); 2271 sqh->dma = dma; 2272 sqh->offs = offs; 2273 sqh->next = sc->sc_freeqhs; 2274 sc->sc_freeqhs = sqh; 2275 } 2276 } 2277 sqh = sc->sc_freeqhs; 2278 sc->sc_freeqhs = sqh->next; 2279 memset(&sqh->qh, 0, sizeof(struct ehci_qh)); 2280 sqh->next = NULL; 2281 sqh->prev = NULL; 2282 2283 out: 2284 splx(s); 2285 return (sqh); 2286 } 2287 2288 void 2289 ehci_free_sqh(struct ehci_softc *sc, struct ehci_soft_qh *sqh) 2290 { 2291 int s; 2292 2293 s = splusb(); 2294 sqh->next = sc->sc_freeqhs; 2295 sc->sc_freeqhs = sqh; 2296 splx(s); 2297 } 2298 2299 struct ehci_soft_qtd * 2300 ehci_alloc_sqtd(struct ehci_softc *sc) 2301 { 2302 struct ehci_soft_qtd *sqtd = NULL; 2303 usbd_status err; 2304 int i, offs; 2305 struct usb_dma dma; 2306 int s; 2307 2308 s = splusb(); 2309 if (sc->sc_freeqtds == NULL) { 2310 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2311 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2312 EHCI_PAGE_SIZE, &dma); 2313 if (err) 2314 goto out; 2315 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2316 offs = i * EHCI_SQTD_SIZE; 2317 sqtd = KERNADDR(&dma, offs); 2318 sqtd->physaddr = DMAADDR(&dma, offs); 2319 sqtd->dma = dma; 2320 sqtd->offs = offs; 2321 sqtd->nextqtd = sc->sc_freeqtds; 2322 sc->sc_freeqtds = sqtd; 2323 } 2324 } 2325 2326 sqtd = sc->sc_freeqtds; 2327 sc->sc_freeqtds = sqtd->nextqtd; 2328 memset(&sqtd->qtd, 0, sizeof(struct ehci_qtd)); 2329 sqtd->nextqtd = NULL; 2330 2331 out: 2332 splx(s); 2333 return (sqtd); 2334 } 2335 2336 void 2337 ehci_free_sqtd(struct ehci_softc *sc, struct ehci_soft_qtd *sqtd) 2338 { 2339 int s; 2340 2341 s = splusb(); 2342 sqtd->nextqtd = sc->sc_freeqtds; 2343 sc->sc_freeqtds = sqtd; 2344 splx(s); 2345 } 2346 2347 usbd_status 2348 ehci_alloc_sqtd_chain(struct ehci_softc *sc, u_int alen, struct usbd_xfer *xfer, 2349 struct ehci_soft_qtd **sp, struct ehci_soft_qtd **ep) 2350 { 2351 struct ehci_soft_qtd *next, *cur; 2352 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2353 u_int32_t qtdstatus; 2354 u_int len, curlen; 2355 int mps, i, iscontrol, forceshort; 2356 int rd = usbd_xfer_isread(xfer); 2357 struct usb_dma *dma = &xfer->dmabuf; 2358 2359 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2360 2361 len = alen; 2362 iscontrol = (xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) == 2363 UE_CONTROL; 2364 2365 dataphys = DMAADDR(dma, 0); 2366 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2367 qtdstatus = EHCI_QTD_ACTIVE | 2368 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2369 EHCI_QTD_SET_CERR(3); /* IOC and BYTES set below */ 2370 mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize); 2371 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2372 len % mps == 0; 2373 /* 2374 * The control transfer data stage always starts with a toggle of 1. 2375 * For other transfers we let the hardware track the toggle state. 2376 */ 2377 if (iscontrol) 2378 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2379 2380 cur = ehci_alloc_sqtd(sc); 2381 *sp = cur; 2382 if (cur == NULL) 2383 goto nomem; 2384 2385 usb_syncmem(dma, 0, alen, 2386 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2387 for (;;) { 2388 dataphyspage = EHCI_PAGE(dataphys); 2389 /* The EHCI hardware can handle at most 5 pages. */ 2390 if (dataphyslastpage - dataphyspage < 2391 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2392 /* we can handle it in this QTD */ 2393 curlen = len; 2394 } else { 2395 /* must use multiple TDs, fill as much as possible. */ 2396 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2397 EHCI_PAGE_OFFSET(dataphys); 2398 #ifdef DIAGNOSTIC 2399 if (curlen > len) { 2400 printf("ehci_alloc_sqtd_chain: curlen=%u " 2401 "len=%u offs=0x%x\n", curlen, len, 2402 EHCI_PAGE_OFFSET(dataphys)); 2403 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2404 dataphyslastpage, dataphyspage, dataphys); 2405 curlen = len; 2406 } 2407 #endif 2408 /* the length must be a multiple of the max size */ 2409 curlen -= curlen % mps; 2410 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2411 "curlen=%u\n", curlen)); 2412 #ifdef DIAGNOSTIC 2413 if (curlen == 0) 2414 panic("ehci_alloc_std: curlen == 0"); 2415 #endif 2416 } 2417 2418 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2419 "dataphyslastpage=0x%08x len=%u curlen=%u\n", 2420 dataphys, dataphyslastpage, len, curlen)); 2421 len -= curlen; 2422 2423 /* 2424 * Allocate another transfer if there's more data left, 2425 * or if force last short transfer flag is set and we're 2426 * allocating a multiple of the max packet size. 2427 */ 2428 if (len != 0 || forceshort) { 2429 next = ehci_alloc_sqtd(sc); 2430 if (next == NULL) 2431 goto nomem; 2432 nextphys = htole32(next->physaddr); 2433 } else { 2434 next = NULL; 2435 nextphys = htole32(EHCI_LINK_TERMINATE); 2436 } 2437 2438 for (i = 0; i * EHCI_PAGE_SIZE < 2439 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2440 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2441 if (i != 0) /* use offset only in first buffer */ 2442 a = EHCI_PAGE(a); 2443 #ifdef DIAGNOSTIC 2444 if (i >= EHCI_QTD_NBUFFERS) { 2445 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2446 goto nomem; 2447 } 2448 #endif 2449 cur->qtd.qtd_buffer[i] = htole32(a); 2450 cur->qtd.qtd_buffer_hi[i] = 0; 2451 } 2452 cur->nextqtd = next; 2453 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2454 cur->qtd.qtd_status = htole32(qtdstatus | 2455 EHCI_QTD_SET_BYTES(curlen)); 2456 cur->len = curlen; 2457 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2458 dataphys, dataphys + curlen)); 2459 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%u\n", curlen)); 2460 if (iscontrol) { 2461 /* 2462 * adjust the toggle based on the number of packets 2463 * in this qtd 2464 */ 2465 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2466 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2467 } 2468 if (len == 0) { 2469 if (! forceshort) 2470 break; 2471 forceshort = 0; 2472 } 2473 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2474 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2475 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2476 dataphys += curlen; 2477 cur = next; 2478 } 2479 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2480 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2481 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2482 *ep = cur; 2483 2484 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2485 *sp, *ep)); 2486 2487 return (USBD_NORMAL_COMPLETION); 2488 2489 nomem: 2490 /* XXX free chain */ 2491 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2492 return (USBD_NOMEM); 2493 } 2494 2495 void 2496 ehci_free_sqtd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 2497 { 2498 struct ehci_pipe *epipe = (struct ehci_pipe *)ex->xfer.pipe; 2499 struct ehci_soft_qtd *sqtd, *next; 2500 2501 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p\n", ex->sqtdstart)); 2502 2503 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = next) { 2504 next = sqtd->nextqtd; 2505 ehci_free_sqtd(sc, sqtd); 2506 } 2507 ex->sqtdstart = ex->sqtdend = NULL; 2508 epipe->sqh->sqtd = NULL; 2509 } 2510 2511 struct ehci_soft_itd * 2512 ehci_alloc_itd(struct ehci_softc *sc) 2513 { 2514 struct ehci_soft_itd *itd, *freeitd; 2515 usbd_status err; 2516 int i, s, offs, frindex, previndex; 2517 struct usb_dma dma; 2518 2519 s = splusb(); 2520 2521 /* Find an itd that wasn't freed this frame or last frame. This can 2522 * discard itds that were freed before frindex wrapped around 2523 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2524 * interrupt and fiddling with list when that happens */ 2525 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2526 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2527 2528 freeitd = NULL; 2529 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2530 if (itd == NULL) 2531 break; 2532 if (itd->slot != frindex && itd->slot != previndex) { 2533 freeitd = itd; 2534 break; 2535 } 2536 } 2537 2538 if (freeitd == NULL) { 2539 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2540 EHCI_PAGE_SIZE, &dma); 2541 if (err) { 2542 splx(s); 2543 return (NULL); 2544 } 2545 2546 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2547 offs = i * EHCI_ITD_SIZE; 2548 itd = KERNADDR(&dma, offs); 2549 itd->physaddr = DMAADDR(&dma, offs); 2550 itd->dma = dma; 2551 itd->offs = offs; 2552 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2553 } 2554 freeitd = LIST_FIRST(&sc->sc_freeitds); 2555 } 2556 2557 itd = freeitd; 2558 LIST_REMOVE(itd, u.free_list); 2559 memset(&itd->itd, 0, sizeof(struct ehci_itd)); 2560 usb_syncmem(&itd->dma, itd->offs + offsetof(struct ehci_itd, itd_next), 2561 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2562 BUS_DMASYNC_PREREAD); 2563 2564 itd->u.frame_list.next = NULL; 2565 itd->u.frame_list.prev = NULL; 2566 itd->xfer_next = NULL; 2567 itd->slot = 0; 2568 splx(s); 2569 2570 return (itd); 2571 } 2572 2573 void 2574 ehci_free_itd(struct ehci_softc *sc, struct ehci_soft_itd *itd) 2575 { 2576 int s; 2577 2578 s = splusb(); 2579 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2580 splx(s); 2581 } 2582 2583 /* 2584 * Close a reqular pipe. 2585 * Assumes that there are no pending transactions. 2586 */ 2587 void 2588 ehci_close_pipe(struct usbd_pipe *pipe) 2589 { 2590 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2591 struct ehci_softc *sc = (struct ehci_softc *)pipe->device->bus; 2592 struct ehci_soft_qh *sqh = epipe->sqh; 2593 int s; 2594 2595 s = splusb(); 2596 ehci_rem_qh(sc, sqh); 2597 splx(s); 2598 pipe->endpoint->savedtoggle = 2599 EHCI_QTD_GET_TOGGLE(letoh32(sqh->qh.qh_qtd.qtd_status)); 2600 ehci_free_sqh(sc, epipe->sqh); 2601 } 2602 2603 /* 2604 * Abort a device request. 2605 * If this routine is called at splusb() it guarantees that the request 2606 * will be removed from the hardware scheduling and that the callback 2607 * for it will be called with USBD_CANCELLED status. 2608 * It's impossible to guarantee that the requested transfer will not 2609 * have happened since the hardware runs concurrently. 2610 * If the transaction has already happened we rely on the ordinary 2611 * interrupt processing to process it. 2612 */ 2613 void 2614 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2615 { 2616 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2617 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2618 struct ehci_xfer *ex = (struct ehci_xfer*)xfer; 2619 struct ehci_soft_qh *sqh = epipe->sqh; 2620 struct ehci_soft_qtd *sqtd; 2621 int s; 2622 2623 if (sc->sc_bus.dying || xfer->status == USBD_NOT_STARTED) { 2624 s = splusb(); 2625 if (xfer->status != USBD_NOT_STARTED) 2626 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2627 xfer->status = status; /* make software ignore it */ 2628 timeout_del(&xfer->timeout_handle); 2629 usb_rem_task(xfer->device, &xfer->abort_task); 2630 #ifdef DIAGNOSTIC 2631 ex->isdone = 1; 2632 #endif 2633 usb_transfer_complete(xfer); 2634 splx(s); 2635 return; 2636 } 2637 2638 if (xfer->device->bus->intr_context) 2639 panic("ehci_abort_xfer: not in process context"); 2640 2641 /* 2642 * If an abort is already in progress then just wait for it to 2643 * complete and return. 2644 */ 2645 if (ex->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2646 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2647 /* No need to wait if we're aborting from a timeout. */ 2648 if (status == USBD_TIMEOUT) 2649 return; 2650 /* Override the status which might be USBD_TIMEOUT. */ 2651 xfer->status = status; 2652 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2653 ex->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 2654 while (ex->ehci_xfer_flags & EHCI_XFER_ABORTING) 2655 tsleep(&ex->ehci_xfer_flags, PZERO, "ehciaw", 0); 2656 return; 2657 } 2658 2659 /* 2660 * Step 1: Make interrupt routine and timeouts ignore xfer. 2661 */ 2662 s = splusb(); 2663 ex->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2664 xfer->status = status; /* make software ignore it */ 2665 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2666 timeout_del(&xfer->timeout_handle); 2667 usb_rem_task(xfer->device, &xfer->abort_task); 2668 splx(s); 2669 2670 /* 2671 * Step 2: Deactivate all of the qTDs that we will be removing, 2672 * otherwise the queue head may go active again. 2673 */ 2674 usb_syncmem(&sqh->dma, 2675 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 2676 sizeof(sqh->qh.qh_qtd.qtd_status), 2677 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2678 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2679 usb_syncmem(&sqh->dma, 2680 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 2681 sizeof(sqh->qh.qh_qtd.qtd_status), 2682 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2683 2684 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) { 2685 usb_syncmem(&sqtd->dma, 2686 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 2687 sizeof(sqtd->qtd.qtd_status), 2688 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2689 sqtd->qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2690 usb_syncmem(&sqtd->dma, 2691 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 2692 sizeof(sqtd->qtd.qtd_status), 2693 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2694 } 2695 ehci_sync_hc(sc); 2696 2697 /* 2698 * Step 3: Make sure the soft interrupt routine has run. This 2699 * should remove any completed items off the queue. 2700 * The hardware has no reference to completed items (TDs). 2701 * It's safe to remove them at any time. 2702 */ 2703 s = splusb(); 2704 sc->sc_softwake = 1; 2705 usb_schedsoftintr(&sc->sc_bus); 2706 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2707 2708 #ifdef DIAGNOSTIC 2709 ex->isdone = 1; 2710 #endif 2711 /* Do the wakeup first to avoid touching the xfer after the callback. */ 2712 ex->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 2713 if (ex->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 2714 ex->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 2715 wakeup(&ex->ehci_xfer_flags); 2716 } 2717 usb_transfer_complete(xfer); 2718 2719 splx(s); 2720 } 2721 2722 void 2723 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 2724 { 2725 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2726 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2727 ehci_isoc_trans_t trans_status; 2728 struct ehci_soft_itd *itd; 2729 int i; 2730 2731 splsoftassert(IPL_SOFTUSB); 2732 2733 if (sc->sc_bus.dying || xfer->status == USBD_NOT_STARTED) { 2734 if (xfer->status != USBD_NOT_STARTED) 2735 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2736 xfer->status = status; 2737 timeout_del(&xfer->timeout_handle); 2738 usb_rem_task(xfer->device, &xfer->abort_task); 2739 usb_transfer_complete(xfer); 2740 return; 2741 } 2742 2743 /* Transfer is already done. */ 2744 if (xfer->status != USBD_IN_PROGRESS) { 2745 DPRINTF(("%s: already done \n", __func__)); 2746 return; 2747 } 2748 2749 2750 #ifdef DIAGNOSTIC 2751 ex->isdone = 1; 2752 #endif 2753 xfer->status = status; 2754 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2755 timeout_del(&xfer->timeout_handle); 2756 usb_rem_task(xfer->device, &xfer->abort_task); 2757 2758 if (xfer->device->speed == USB_SPEED_HIGH) { 2759 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 2760 usb_syncmem(&itd->dma, 2761 itd->offs + offsetof(struct ehci_itd, itd_ctl), 2762 sizeof(itd->itd.itd_ctl), 2763 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2764 2765 for (i = 0; i < 8; i++) { 2766 trans_status = le32toh(itd->itd.itd_ctl[i]); 2767 trans_status &= ~EHCI_ITD_ACTIVE; 2768 itd->itd.itd_ctl[i] = htole32(trans_status); 2769 } 2770 2771 usb_syncmem(&itd->dma, 2772 itd->offs + offsetof(struct ehci_itd, itd_ctl), 2773 sizeof(itd->itd.itd_ctl), 2774 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2775 } 2776 } else { 2777 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 2778 usb_syncmem(&itd->dma, 2779 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 2780 sizeof(itd->sitd.sitd_trans), 2781 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2782 2783 trans_status = le32toh(itd->sitd.sitd_trans); 2784 trans_status &= ~EHCI_SITD_ACTIVE; 2785 itd->sitd.sitd_trans = htole32(trans_status); 2786 2787 usb_syncmem(&itd->dma, 2788 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 2789 sizeof(itd->sitd.sitd_trans), 2790 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2791 } 2792 } 2793 2794 sc->sc_softwake = 1; 2795 usb_schedsoftintr(&sc->sc_bus); 2796 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2797 2798 usb_transfer_complete(xfer); 2799 } 2800 2801 void 2802 ehci_timeout(void *addr) 2803 { 2804 struct usbd_xfer *xfer = addr; 2805 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2806 2807 if (sc->sc_bus.dying) { 2808 ehci_timeout_task(addr); 2809 return; 2810 } 2811 2812 usb_init_task(&xfer->abort_task, ehci_timeout_task, addr, 2813 USB_TASK_TYPE_ABORT); 2814 usb_add_task(xfer->device, &xfer->abort_task); 2815 } 2816 2817 void 2818 ehci_timeout_task(void *addr) 2819 { 2820 struct usbd_xfer *xfer = addr; 2821 int s; 2822 2823 s = splusb(); 2824 ehci_abort_xfer(xfer, USBD_TIMEOUT); 2825 splx(s); 2826 } 2827 2828 /* 2829 * Some EHCI chips from VIA / ATI seem to trigger interrupts before writing 2830 * back the qTD status, or miss signalling occasionally under heavy load. 2831 * If the host machine is too fast, we can miss transaction completion - when 2832 * we scan the active list the transaction still seems to be active. This 2833 * generally exhibits itself as a umass stall that never recovers. 2834 * 2835 * We work around this behaviour by setting up this callback after any softintr 2836 * that completes with transactions still pending, giving us another chance to 2837 * check for completion after the writeback has taken place. 2838 */ 2839 void 2840 ehci_intrlist_timeout(void *arg) 2841 { 2842 struct ehci_softc *sc = arg; 2843 int s; 2844 2845 if (sc->sc_bus.dying) 2846 return; 2847 2848 s = splusb(); 2849 DPRINTFN(1, ("ehci_intrlist_timeout\n")); 2850 usb_schedsoftintr(&sc->sc_bus); 2851 splx(s); 2852 } 2853 2854 usbd_status 2855 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 2856 { 2857 usbd_status err; 2858 2859 /* Insert last in queue. */ 2860 err = usb_insert_transfer(xfer); 2861 if (err) 2862 return (err); 2863 2864 /* Pipe isn't running, start first */ 2865 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2866 } 2867 2868 usbd_status 2869 ehci_device_ctrl_start(struct usbd_xfer *xfer) 2870 { 2871 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2872 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2873 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2874 usb_device_request_t *req = &xfer->request; 2875 struct ehci_soft_qtd *setup, *stat, *next; 2876 struct ehci_soft_qh *sqh; 2877 u_int len = UGETW(req->wLength); 2878 usbd_status err; 2879 int s; 2880 2881 KASSERT(xfer->rqflags & URQ_REQUEST); 2882 2883 if (sc->sc_bus.dying) 2884 return (USBD_IOERROR); 2885 2886 setup = ehci_alloc_sqtd(sc); 2887 if (setup == NULL) { 2888 err = USBD_NOMEM; 2889 goto bad1; 2890 } 2891 stat = ehci_alloc_sqtd(sc); 2892 if (stat == NULL) { 2893 err = USBD_NOMEM; 2894 goto bad2; 2895 } 2896 2897 sqh = epipe->sqh; 2898 2899 /* Set up data transaction */ 2900 if (len != 0) { 2901 struct ehci_soft_qtd *end; 2902 2903 err = ehci_alloc_sqtd_chain(sc, len, xfer, &next, &end); 2904 if (err) 2905 goto bad3; 2906 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 2907 end->nextqtd = stat; 2908 end->qtd.qtd_next = 2909 end->qtd.qtd_altnext = htole32(stat->physaddr); 2910 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 2911 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2912 } else { 2913 next = stat; 2914 } 2915 2916 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 2917 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2918 2919 /* Clear toggle */ 2920 setup->qtd.qtd_status = htole32( 2921 EHCI_QTD_ACTIVE | 2922 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 2923 EHCI_QTD_SET_CERR(3) | 2924 EHCI_QTD_SET_TOGGLE(0) | 2925 EHCI_QTD_SET_BYTES(sizeof(*req))); 2926 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 2927 setup->qtd.qtd_buffer_hi[0] = 0; 2928 setup->nextqtd = next; 2929 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 2930 setup->len = sizeof(*req); 2931 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 2932 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2933 2934 stat->qtd.qtd_status = htole32( 2935 EHCI_QTD_ACTIVE | 2936 EHCI_QTD_SET_PID(usbd_xfer_isread(xfer) ? 2937 EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 2938 EHCI_QTD_SET_CERR(3) | 2939 EHCI_QTD_SET_TOGGLE(1) | 2940 EHCI_QTD_IOC); 2941 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 2942 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 2943 stat->nextqtd = NULL; 2944 stat->qtd.qtd_next = stat->qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 2945 stat->len = 0; 2946 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 2947 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2948 2949 ex->sqtdstart = setup; 2950 ex->sqtdend = stat; 2951 #ifdef DIAGNOSTIC 2952 if (!ex->isdone) { 2953 printf("%s: not done, ex=%p\n", __func__, ex); 2954 } 2955 ex->isdone = 0; 2956 #endif 2957 2958 /* Insert qTD in QH list. */ 2959 s = splusb(); 2960 ehci_set_qh_qtd(sqh, setup); 2961 if (xfer->timeout && !sc->sc_bus.use_polling) { 2962 timeout_del(&xfer->timeout_handle); 2963 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 2964 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 2965 } 2966 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 2967 xfer->status = USBD_IN_PROGRESS; 2968 splx(s); 2969 2970 if (sc->sc_bus.use_polling) 2971 ehci_waitintr(sc, xfer); 2972 2973 return (USBD_IN_PROGRESS); 2974 2975 bad3: 2976 ehci_free_sqtd(sc, stat); 2977 bad2: 2978 ehci_free_sqtd(sc, setup); 2979 bad1: 2980 xfer->status = err; 2981 usb_transfer_complete(xfer); 2982 return (err); 2983 } 2984 2985 void 2986 ehci_device_ctrl_done(struct usbd_xfer *xfer) 2987 { 2988 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2989 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2990 2991 KASSERT(xfer->rqflags & URQ_REQUEST); 2992 2993 if (xfer->status != USBD_NOMEM) { 2994 ehci_free_sqtd_chain(sc, ex); 2995 } 2996 } 2997 2998 void 2999 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3000 { 3001 ehci_abort_xfer(xfer, USBD_CANCELLED); 3002 } 3003 3004 void 3005 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3006 { 3007 ehci_close_pipe(pipe); 3008 } 3009 3010 usbd_status 3011 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3012 { 3013 usbd_status err; 3014 3015 /* Insert last in queue. */ 3016 err = usb_insert_transfer(xfer); 3017 if (err) 3018 return (err); 3019 3020 /* Pipe isn't running, start first */ 3021 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3022 } 3023 3024 usbd_status 3025 ehci_device_bulk_start(struct usbd_xfer *xfer) 3026 { 3027 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3028 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3029 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3030 struct ehci_soft_qtd *data, *dataend; 3031 struct ehci_soft_qh *sqh; 3032 usbd_status err; 3033 int s; 3034 3035 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3036 3037 if (sc->sc_bus.dying) 3038 return (USBD_IOERROR); 3039 3040 sqh = epipe->sqh; 3041 3042 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3043 if (err) { 3044 xfer->status = err; 3045 usb_transfer_complete(xfer); 3046 return (err); 3047 } 3048 3049 /* Set up interrupt info. */ 3050 ex->sqtdstart = data; 3051 ex->sqtdend = dataend; 3052 #ifdef DIAGNOSTIC 3053 if (!ex->isdone) { 3054 printf("ehci_device_bulk_start: not done, ex=%p\n", ex); 3055 } 3056 ex->isdone = 0; 3057 #endif 3058 3059 s = splusb(); 3060 ehci_set_qh_qtd(sqh, data); 3061 if (xfer->timeout && !sc->sc_bus.use_polling) { 3062 timeout_del(&xfer->timeout_handle); 3063 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3064 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3065 } 3066 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3067 xfer->status = USBD_IN_PROGRESS; 3068 splx(s); 3069 3070 if (sc->sc_bus.use_polling) 3071 ehci_waitintr(sc, xfer); 3072 3073 return (USBD_IN_PROGRESS); 3074 } 3075 3076 void 3077 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3078 { 3079 ehci_abort_xfer(xfer, USBD_CANCELLED); 3080 } 3081 3082 /* 3083 * Close a device bulk pipe. 3084 */ 3085 void 3086 ehci_device_bulk_close(struct usbd_pipe *pipe) 3087 { 3088 ehci_close_pipe(pipe); 3089 } 3090 3091 void 3092 ehci_device_bulk_done(struct usbd_xfer *xfer) 3093 { 3094 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3095 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3096 3097 if (xfer->status != USBD_NOMEM) { 3098 ehci_free_sqtd_chain(sc, ex); 3099 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3100 usbd_xfer_isread(xfer) ? 3101 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3102 } 3103 } 3104 3105 usbd_status 3106 ehci_device_setintr(struct ehci_softc *sc, struct ehci_soft_qh *sqh, int ival) 3107 { 3108 struct ehci_soft_islot *isp; 3109 int islot, lev; 3110 3111 /* Find a poll rate that is large enough. */ 3112 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3113 if (EHCI_ILEV_IVAL(lev) <= ival) 3114 break; 3115 3116 /* Pick an interrupt slot at the right level. */ 3117 /* XXX could do better than picking at random */ 3118 islot = EHCI_IQHIDX(lev, arc4random()); 3119 3120 sqh->islot = islot; 3121 isp = &sc->sc_islots[islot]; 3122 ehci_add_qh(sqh, isp->sqh); 3123 3124 return (USBD_NORMAL_COMPLETION); 3125 } 3126 3127 usbd_status 3128 ehci_device_intr_transfer(struct usbd_xfer *xfer) 3129 { 3130 usbd_status err; 3131 3132 /* Insert last in queue. */ 3133 err = usb_insert_transfer(xfer); 3134 if (err) 3135 return (err); 3136 3137 /* 3138 * Pipe isn't running (otherwise err would be USBD_INPROG), 3139 * so start it first. 3140 */ 3141 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3142 } 3143 3144 usbd_status 3145 ehci_device_intr_start(struct usbd_xfer *xfer) 3146 { 3147 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3148 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3149 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3150 struct ehci_soft_qtd *data, *dataend; 3151 struct ehci_soft_qh *sqh; 3152 usbd_status err; 3153 int s; 3154 3155 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3156 3157 if (sc->sc_bus.dying) 3158 return (USBD_IOERROR); 3159 3160 sqh = epipe->sqh; 3161 3162 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3163 if (err) { 3164 xfer->status = err; 3165 usb_transfer_complete(xfer); 3166 return (err); 3167 } 3168 3169 /* Set up interrupt info. */ 3170 ex->sqtdstart = data; 3171 ex->sqtdend = dataend; 3172 #ifdef DIAGNOSTIC 3173 if (!ex->isdone) 3174 printf("ehci_device_intr_start: not done, ex=%p\n", ex); 3175 ex->isdone = 0; 3176 #endif 3177 3178 s = splusb(); 3179 ehci_set_qh_qtd(sqh, data); 3180 if (xfer->timeout && !sc->sc_bus.use_polling) { 3181 timeout_del(&xfer->timeout_handle); 3182 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3183 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3184 } 3185 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3186 xfer->status = USBD_IN_PROGRESS; 3187 splx(s); 3188 3189 if (sc->sc_bus.use_polling) 3190 ehci_waitintr(sc, xfer); 3191 3192 return (USBD_IN_PROGRESS); 3193 } 3194 3195 void 3196 ehci_device_intr_abort(struct usbd_xfer *xfer) 3197 { 3198 KASSERT(!xfer->pipe->repeat || xfer->pipe->intrxfer == xfer); 3199 3200 /* 3201 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3202 * async doorbell. That's dependant on the async list, wheras 3203 * intr xfers are periodic, should not use this? 3204 */ 3205 ehci_abort_xfer(xfer, USBD_CANCELLED); 3206 } 3207 3208 void 3209 ehci_device_intr_close(struct usbd_pipe *pipe) 3210 { 3211 ehci_close_pipe(pipe); 3212 } 3213 3214 void 3215 ehci_device_intr_done(struct usbd_xfer *xfer) 3216 { 3217 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3218 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3219 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3220 struct ehci_soft_qtd *data, *dataend; 3221 struct ehci_soft_qh *sqh; 3222 usbd_status err; 3223 int s; 3224 3225 if (xfer->pipe->repeat) { 3226 ehci_free_sqtd_chain(sc, ex); 3227 3228 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3229 usbd_xfer_isread(xfer) ? 3230 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3231 sqh = epipe->sqh; 3232 3233 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3234 if (err) { 3235 xfer->status = err; 3236 return; 3237 } 3238 3239 /* Set up interrupt info. */ 3240 ex->sqtdstart = data; 3241 ex->sqtdend = dataend; 3242 #ifdef DIAGNOSTIC 3243 if (!ex->isdone) { 3244 printf("ehci_device_intr_done: not done, ex=%p\n", 3245 ex); 3246 } 3247 ex->isdone = 0; 3248 #endif 3249 3250 s = splusb(); 3251 ehci_set_qh_qtd(sqh, data); 3252 if (xfer->timeout && !sc->sc_bus.use_polling) { 3253 timeout_del(&xfer->timeout_handle); 3254 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3255 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3256 } 3257 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3258 xfer->status = USBD_IN_PROGRESS; 3259 splx(s); 3260 } else if (xfer->status != USBD_NOMEM) { 3261 ehci_free_sqtd_chain(sc, ex); 3262 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3263 usbd_xfer_isread(xfer) ? 3264 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3265 } 3266 } 3267 3268 usbd_status 3269 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 3270 { 3271 usbd_status err; 3272 3273 err = usb_insert_transfer(xfer); 3274 if (err && err != USBD_IN_PROGRESS) 3275 return (err); 3276 3277 return (ehci_device_isoc_start(xfer)); 3278 } 3279 3280 usbd_status 3281 ehci_device_isoc_start(struct usbd_xfer *xfer) 3282 { 3283 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3284 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3285 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3286 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3287 uint8_t ival = ed->bInterval; 3288 struct ehci_soft_itd *itd; 3289 int s, frindex; 3290 uint32_t link; 3291 3292 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3293 KASSERT(ival > 0 && ival <= 16); 3294 3295 /* 3296 * To allow continuous transfers, above we start all transfers 3297 * immediately. However, we're still going to get usbd_start_next call 3298 * this when another xfer completes. So, check if this is already 3299 * in progress or not 3300 */ 3301 if (ex->itdstart != NULL) 3302 return (USBD_IN_PROGRESS); 3303 3304 if (sc->sc_bus.dying) 3305 return (USBD_IOERROR); 3306 3307 /* Why would you do that anyway? */ 3308 if (sc->sc_bus.use_polling) 3309 return (USBD_INVAL); 3310 3311 /* 3312 * To avoid complication, don't allow a request right now that'll span 3313 * the entire frame table. To within 4 frames, to allow some leeway 3314 * on either side of where the hc currently is. 3315 */ 3316 if ((1 << (ival - 1)) * xfer->nframes >= (sc->sc_flsize - 4) * 8) 3317 return (USBD_INVAL); 3318 3319 /* 3320 * Step 1: Allocate and initialize itds. 3321 */ 3322 if (xfer->device->speed == USB_SPEED_HIGH) { 3323 if (ehci_alloc_itd_chain(sc, xfer)) 3324 return (USBD_INVAL); 3325 3326 link = EHCI_LINK_ITD; 3327 } else { 3328 if (ehci_alloc_sitd_chain(sc, xfer)) 3329 return (USBD_INVAL); 3330 3331 link = EHCI_LINK_SITD; 3332 } 3333 3334 #ifdef DIAGNOSTIC 3335 if (!ex->isdone) { 3336 printf("%s: not done, ex=%p\n", __func__, ex); 3337 } 3338 ex->isdone = 0; 3339 #endif 3340 3341 /* 3342 * Part 2: Transfer descriptors have now been set up, now they must 3343 * be scheduled into the period frame list. Erk. Not wanting to 3344 * complicate matters, transfer is denied if the transfer spans 3345 * more than the period frame list. 3346 */ 3347 s = splusb(); 3348 3349 /* Start inserting frames */ 3350 if (epipe->u.isoc.cur_xfers > 0) { 3351 frindex = epipe->u.isoc.next_frame; 3352 } else { 3353 frindex = EOREAD4(sc, EHCI_FRINDEX); 3354 frindex = frindex >> 3; /* Erase microframe index */ 3355 frindex += 2; 3356 } 3357 3358 if (frindex >= sc->sc_flsize) 3359 frindex &= (sc->sc_flsize - 1); 3360 3361 /* What's the frame interval? */ 3362 ival = (1 << (ival - 1)); 3363 if (ival / 8 == 0) 3364 ival = 1; 3365 else 3366 ival /= 8; 3367 3368 /* Abuse the fact that itd_next == sitd_next. */ 3369 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 3370 itd->itd.itd_next = sc->sc_flist[frindex]; 3371 if (itd->itd.itd_next == 0) 3372 itd->itd.itd_next = htole32(EHCI_LINK_TERMINATE); 3373 3374 sc->sc_flist[frindex] = htole32(link | itd->physaddr); 3375 itd->u.frame_list.next = sc->sc_softitds[frindex]; 3376 sc->sc_softitds[frindex] = itd; 3377 if (itd->u.frame_list.next != NULL) 3378 itd->u.frame_list.next->u.frame_list.prev = itd; 3379 itd->slot = frindex; 3380 itd->u.frame_list.prev = NULL; 3381 3382 frindex += ival; 3383 if (frindex >= sc->sc_flsize) 3384 frindex -= sc->sc_flsize; 3385 } 3386 3387 epipe->u.isoc.cur_xfers++; 3388 epipe->u.isoc.next_frame = frindex; 3389 3390 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3391 xfer->status = USBD_IN_PROGRESS; 3392 xfer->done = 0; 3393 splx(s); 3394 3395 return (USBD_IN_PROGRESS); 3396 } 3397 3398 int 3399 ehci_alloc_itd_chain(struct ehci_softc *sc, struct usbd_xfer *xfer) 3400 { 3401 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3402 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3403 const uint32_t mps = UGETW(ed->wMaxPacketSize); 3404 struct ehci_soft_itd *itd = NULL, *pitd = NULL; 3405 int i, j, nframes, uframes, ufrperframe; 3406 int offs = 0, trans_count = 0; 3407 3408 /* 3409 * How many itds do we need? One per transfer if interval >= 8 3410 * microframes, fewer if we use multiple microframes per frame. 3411 */ 3412 switch (ed->bInterval) { 3413 case 1: 3414 ufrperframe = 8; 3415 break; 3416 case 2: 3417 ufrperframe = 4; 3418 break; 3419 case 3: 3420 ufrperframe = 2; 3421 break; 3422 default: 3423 ufrperframe = 1; 3424 break; 3425 } 3426 nframes = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3427 uframes = 8 / ufrperframe; 3428 if (nframes == 0) 3429 return (1); 3430 3431 for (i = 0; i < nframes; i++) { 3432 uint32_t froffs = offs; 3433 3434 itd = ehci_alloc_itd(sc); 3435 if (itd == NULL) { 3436 ehci_free_itd_chain(sc, ex); 3437 return (1); 3438 } 3439 3440 if (pitd != NULL) 3441 pitd->xfer_next = itd; 3442 else 3443 ex->itdstart = itd; 3444 3445 /* 3446 * Step 1.5, initialize uframes 3447 */ 3448 for (j = 0; j < 8; j += uframes) { 3449 /* Calculate which page in the list this starts in */ 3450 int addr = DMAADDR(&xfer->dmabuf, froffs); 3451 addr = EHCI_PAGE_OFFSET(addr) + (offs - froffs); 3452 addr = EHCI_PAGE(addr) / EHCI_PAGE_SIZE; 3453 3454 /* This gets the initial offset into the first page, 3455 * looks how far further along the current uframe 3456 * offset is. Works out how many pages that is. 3457 */ 3458 itd->itd.itd_ctl[j] = htole32( 3459 EHCI_ITD_ACTIVE | 3460 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3461 EHCI_ITD_SET_PG(addr) | 3462 EHCI_ITD_SET_OFFS(DMAADDR(&xfer->dmabuf, offs)) 3463 ); 3464 3465 offs += xfer->frlengths[trans_count]; 3466 trans_count++; 3467 3468 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3469 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3470 break; 3471 } 3472 } 3473 3474 /* Step 1.75, set buffer pointers. To simplify matters, all 3475 * pointers are filled out for the next 7 hardware pages in 3476 * the dma block, so no need to worry what pages to cover 3477 * and what to not. 3478 */ 3479 3480 for (j = 0; j < 7; j++) { 3481 /* 3482 * Don't try to lookup a page that's past the end 3483 * of buffer 3484 */ 3485 int page_offs = EHCI_PAGE(froffs + 3486 (EHCI_PAGE_SIZE * j)); 3487 3488 if (page_offs >= xfer->dmabuf.block->size) 3489 break; 3490 3491 long long page = DMAADDR(&xfer->dmabuf, page_offs); 3492 page = EHCI_PAGE(page); 3493 itd->itd.itd_bufr[j] = htole32(page); 3494 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 3495 } 3496 3497 /* 3498 * Other special values 3499 */ 3500 itd->itd.itd_bufr[0] |= htole32( 3501 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 3502 EHCI_ITD_SET_DADDR(xfer->pipe->device->address) 3503 ); 3504 3505 itd->itd.itd_bufr[1] |= htole32( 3506 (usbd_xfer_isread(xfer) ? EHCI_ITD_SET_DIR(1) : 0) | 3507 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(mps)) 3508 ); 3509 /* FIXME: handle invalid trans */ 3510 itd->itd.itd_bufr[2] |= htole32( 3511 EHCI_ITD_SET_MULTI(UE_GET_TRANS(mps)+1) 3512 ); 3513 3514 pitd = itd; 3515 } 3516 3517 ex->itdend = itd; 3518 3519 return (0); 3520 } 3521 3522 int 3523 ehci_alloc_sitd_chain(struct ehci_softc *sc, struct usbd_xfer *xfer) 3524 { 3525 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3526 struct usbd_device *hshub = xfer->device->myhsport->parent; 3527 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3528 struct ehci_soft_itd *itd = NULL, *pitd = NULL; 3529 uint8_t smask, cmask, tp, uf; 3530 int i, nframes, offs = 0; 3531 uint32_t endp; 3532 3533 nframes = xfer->nframes; 3534 if (nframes == 0) 3535 return (1); 3536 3537 endp = EHCI_SITD_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 3538 EHCI_SITD_SET_ADDR(xfer->device->address) | 3539 EHCI_SITD_SET_PORT(xfer->device->myhsport->portno) | 3540 EHCI_SITD_SET_HUBA(hshub->address); 3541 3542 if (usbd_xfer_isread(xfer)) 3543 endp |= EHCI_SITD_SET_DIR(1); 3544 3545 for (i = 0; i < nframes; i++) { 3546 uint32_t addr = DMAADDR(&xfer->dmabuf, offs); 3547 uint32_t page = EHCI_PAGE(addr + xfer->frlengths[i] - 1); 3548 3549 itd = ehci_alloc_itd(sc); 3550 if (itd == NULL) { 3551 ehci_free_itd_chain(sc, ex); 3552 return (1); 3553 } 3554 if (pitd) 3555 pitd->xfer_next = itd; 3556 else 3557 ex->itdstart = itd; 3558 3559 itd->sitd.sitd_endp = htole32(endp); 3560 itd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 3561 itd->sitd.sitd_trans = htole32( 3562 EHCI_SITD_ACTIVE | 3563 EHCI_SITD_SET_LEN(xfer->frlengths[i]) | 3564 ((i == nframes - 1) ? EHCI_SITD_IOC : 0) 3565 ); 3566 3567 uf = max(1, ((xfer->frlengths[i] + 187) / 188)); 3568 3569 /* 3570 * Since we do not yet budget and schedule micro-frames 3571 * we assume there is no other transfer using the same 3572 * TT. 3573 */ 3574 if (usbd_xfer_isread(xfer)) { 3575 smask = 0x01; 3576 cmask = ((1 << (uf + 2)) - 1) << 2; 3577 } else { 3578 /* Is the payload is greater than 188 bytes? */ 3579 if (uf == 1) 3580 tp = EHCI_SITD_TP_ALL; 3581 else 3582 tp = EHCI_SITD_TP_BEGIN; 3583 3584 page |= EHCI_SITD_SET_TCOUNT(uf) | EHCI_SITD_SET_TP(tp); 3585 smask = (1 << uf) - 1; 3586 cmask = 0x00; 3587 } 3588 3589 itd->sitd.sitd_sched = htole32( 3590 EHCI_SITD_SET_SMASK(smask) | EHCI_SITD_SET_CMASK(cmask) 3591 ); 3592 itd->sitd.sitd_bufr[0] = htole32(addr); 3593 itd->sitd.sitd_bufr[1] = htole32(page); 3594 3595 offs += xfer->frlengths[i]; 3596 pitd = itd; 3597 } 3598 3599 ex->itdend = itd; 3600 3601 return (0); 3602 } 3603 3604 void 3605 ehci_device_isoc_abort(struct usbd_xfer *xfer) 3606 { 3607 int s; 3608 3609 s = splusb(); 3610 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 3611 splx(s); 3612 } 3613 3614 void 3615 ehci_device_isoc_close(struct usbd_pipe *pipe) 3616 { 3617 } 3618 3619 void 3620 ehci_device_isoc_done(struct usbd_xfer *xfer) 3621 { 3622 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3623 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3624 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3625 int s; 3626 3627 s = splusb(); 3628 epipe->u.isoc.cur_xfers--; 3629 if (xfer->status != USBD_NOMEM) { 3630 ehci_rem_itd_chain(sc, ex); 3631 ehci_free_itd_chain(sc, ex); 3632 } 3633 splx(s); 3634 } 3635