1 /* $OpenBSD: ehci.c,v 1.195 2016/11/08 10:31:30 mpi Exp $ */ 2 /* $NetBSD: ehci.c,v 1.66 2004/06/30 03:11:56 mycroft Exp $ */ 3 4 /* 5 * Copyright (c) 2014-2015 Martin Pieuchot 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 /* 20 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 21 * All rights reserved. 22 * 23 * This code is derived from software contributed to The NetBSD Foundation 24 * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and 25 * Jeremy Morse (jeremy.morse@gmail.com). 26 * 27 * Redistribution and use in source and binary forms, with or without 28 * modification, are permitted provided that the following conditions 29 * are met: 30 * 1. Redistributions of source code must retain the above copyright 31 * notice, this list of conditions and the following disclaimer. 32 * 2. Redistributions in binary form must reproduce the above copyright 33 * notice, this list of conditions and the following disclaimer in the 34 * documentation and/or other materials provided with the distribution. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 37 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 38 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 39 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 40 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 41 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 42 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 43 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 44 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 45 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 46 * POSSIBILITY OF SUCH DAMAGE. 47 */ 48 49 /* 50 * TODO: 51 * 1) The hub driver needs to handle and schedule the transaction translator, 52 * to assign place in frame where different devices get to go. See chapter 53 * on hubs in USB 2.0 for details. 54 * 55 * 2) Command failures are not recovered correctly. 56 */ 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/kernel.h> 61 #include <sys/rwlock.h> 62 #include <sys/malloc.h> 63 #include <sys/device.h> 64 #include <sys/queue.h> 65 #include <sys/timeout.h> 66 #include <sys/pool.h> 67 #include <sys/endian.h> 68 #include <sys/atomic.h> 69 70 #include <machine/bus.h> 71 72 #include <dev/usb/usb.h> 73 #include <dev/usb/usbdi.h> 74 #include <dev/usb/usbdivar.h> 75 #include <dev/usb/usb_mem.h> 76 77 #include <dev/usb/ehcireg.h> 78 #include <dev/usb/ehcivar.h> 79 80 struct cfdriver ehci_cd = { 81 NULL, "ehci", DV_DULL 82 }; 83 84 #ifdef EHCI_DEBUG 85 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 86 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 87 int ehcidebug = 0; 88 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 89 #else 90 #define DPRINTF(x) 91 #define DPRINTFN(n,x) 92 #endif 93 94 struct pool *ehcixfer; 95 96 struct ehci_pipe { 97 struct usbd_pipe pipe; 98 99 struct ehci_soft_qh *sqh; 100 union { 101 /* Control pipe */ 102 struct { 103 struct usb_dma reqdma; 104 } ctl; 105 /* Iso pipe */ 106 struct { 107 u_int next_frame; 108 u_int cur_xfers; 109 } isoc; 110 } u; 111 }; 112 113 u_int8_t ehci_reverse_bits(u_int8_t, int); 114 115 usbd_status ehci_open(struct usbd_pipe *); 116 int ehci_setaddr(struct usbd_device *, int); 117 void ehci_poll(struct usbd_bus *); 118 void ehci_softintr(void *); 119 int ehci_intr1(struct ehci_softc *); 120 void ehci_waitintr(struct ehci_softc *, struct usbd_xfer *); 121 void ehci_check_intr(struct ehci_softc *, struct usbd_xfer *); 122 void ehci_check_qh_intr(struct ehci_softc *, struct usbd_xfer *); 123 void ehci_check_itd_intr(struct ehci_softc *, struct usbd_xfer *); 124 void ehci_idone(struct usbd_xfer *); 125 void ehci_isoc_idone(struct usbd_xfer *); 126 void ehci_timeout(void *); 127 void ehci_timeout_task(void *); 128 void ehci_intrlist_timeout(void *); 129 130 struct usbd_xfer *ehci_allocx(struct usbd_bus *); 131 void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 132 133 usbd_status ehci_root_ctrl_transfer(struct usbd_xfer *); 134 usbd_status ehci_root_ctrl_start(struct usbd_xfer *); 135 void ehci_root_ctrl_abort(struct usbd_xfer *); 136 void ehci_root_ctrl_close(struct usbd_pipe *); 137 void ehci_root_ctrl_done(struct usbd_xfer *); 138 139 usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 140 usbd_status ehci_root_intr_start(struct usbd_xfer *); 141 void ehci_root_intr_abort(struct usbd_xfer *); 142 void ehci_root_intr_close(struct usbd_pipe *); 143 void ehci_root_intr_done(struct usbd_xfer *); 144 145 usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 146 usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 147 void ehci_device_ctrl_abort(struct usbd_xfer *); 148 void ehci_device_ctrl_close(struct usbd_pipe *); 149 void ehci_device_ctrl_done(struct usbd_xfer *); 150 151 usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 152 usbd_status ehci_device_bulk_start(struct usbd_xfer *); 153 void ehci_device_bulk_abort(struct usbd_xfer *); 154 void ehci_device_bulk_close(struct usbd_pipe *); 155 void ehci_device_bulk_done(struct usbd_xfer *); 156 157 usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 158 usbd_status ehci_device_intr_start(struct usbd_xfer *); 159 void ehci_device_intr_abort(struct usbd_xfer *); 160 void ehci_device_intr_close(struct usbd_pipe *); 161 void ehci_device_intr_done(struct usbd_xfer *); 162 163 usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 164 usbd_status ehci_device_isoc_start(struct usbd_xfer *); 165 void ehci_device_isoc_abort(struct usbd_xfer *); 166 void ehci_device_isoc_close(struct usbd_pipe *); 167 void ehci_device_isoc_done(struct usbd_xfer *); 168 169 void ehci_device_clear_toggle(struct usbd_pipe *pipe); 170 171 void ehci_pcd(struct ehci_softc *, struct usbd_xfer *); 172 void ehci_disown(struct ehci_softc *, int, int); 173 174 struct ehci_soft_qh *ehci_alloc_sqh(struct ehci_softc *); 175 void ehci_free_sqh(struct ehci_softc *, struct ehci_soft_qh *); 176 177 struct ehci_soft_qtd *ehci_alloc_sqtd(struct ehci_softc *); 178 void ehci_free_sqtd(struct ehci_softc *, struct ehci_soft_qtd *); 179 usbd_status ehci_alloc_sqtd_chain(struct ehci_softc *, u_int, 180 struct usbd_xfer *, struct ehci_soft_qtd **, struct ehci_soft_qtd **); 181 void ehci_free_sqtd_chain(struct ehci_softc *, struct ehci_xfer *); 182 183 struct ehci_soft_itd *ehci_alloc_itd(struct ehci_softc *); 184 void ehci_free_itd(struct ehci_softc *, struct ehci_soft_itd *); 185 void ehci_rem_itd_chain(struct ehci_softc *, struct ehci_xfer *); 186 void ehci_free_itd_chain(struct ehci_softc *, struct ehci_xfer *); 187 int ehci_alloc_itd_chain(struct ehci_softc *, struct usbd_xfer *); 188 int ehci_alloc_sitd_chain(struct ehci_softc *, struct usbd_xfer *); 189 void ehci_abort_isoc_xfer(struct usbd_xfer *xfer, 190 usbd_status status); 191 192 usbd_status ehci_device_setintr(struct ehci_softc *, struct ehci_soft_qh *, 193 int ival); 194 195 void ehci_add_qh(struct ehci_soft_qh *, struct ehci_soft_qh *); 196 void ehci_rem_qh(struct ehci_softc *, struct ehci_soft_qh *); 197 void ehci_set_qh_qtd(struct ehci_soft_qh *, struct ehci_soft_qtd *); 198 void ehci_sync_hc(struct ehci_softc *); 199 200 void ehci_close_pipe(struct usbd_pipe *); 201 void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 202 203 #ifdef EHCI_DEBUG 204 void ehci_dump_regs(struct ehci_softc *); 205 void ehci_dump(void); 206 struct ehci_softc *theehci; 207 void ehci_dump_link(ehci_link_t, int); 208 void ehci_dump_sqtds(struct ehci_soft_qtd *); 209 void ehci_dump_sqtd(struct ehci_soft_qtd *); 210 void ehci_dump_qtd(struct ehci_qtd *); 211 void ehci_dump_sqh(struct ehci_soft_qh *); 212 #if notyet 213 void ehci_dump_itd(struct ehci_soft_itd *); 214 #endif 215 #ifdef DIAGNOSTIC 216 void ehci_dump_exfer(struct ehci_xfer *); 217 #endif 218 #endif 219 220 #define EHCI_INTR_ENDPT 1 221 222 struct usbd_bus_methods ehci_bus_methods = { 223 .open_pipe = ehci_open, 224 .dev_setaddr = ehci_setaddr, 225 .soft_intr = ehci_softintr, 226 .do_poll = ehci_poll, 227 .allocx = ehci_allocx, 228 .freex = ehci_freex, 229 }; 230 231 struct usbd_pipe_methods ehci_root_ctrl_methods = { 232 .transfer = ehci_root_ctrl_transfer, 233 .start = ehci_root_ctrl_start, 234 .abort = ehci_root_ctrl_abort, 235 .close = ehci_root_ctrl_close, 236 .done = ehci_root_ctrl_done, 237 }; 238 239 struct usbd_pipe_methods ehci_root_intr_methods = { 240 .transfer = ehci_root_intr_transfer, 241 .start = ehci_root_intr_start, 242 .abort = ehci_root_intr_abort, 243 .close = ehci_root_intr_close, 244 .done = ehci_root_intr_done, 245 }; 246 247 struct usbd_pipe_methods ehci_device_ctrl_methods = { 248 .transfer = ehci_device_ctrl_transfer, 249 .start = ehci_device_ctrl_start, 250 .abort = ehci_device_ctrl_abort, 251 .close = ehci_device_ctrl_close, 252 .done = ehci_device_ctrl_done, 253 }; 254 255 struct usbd_pipe_methods ehci_device_intr_methods = { 256 .transfer = ehci_device_intr_transfer, 257 .start = ehci_device_intr_start, 258 .abort = ehci_device_intr_abort, 259 .close = ehci_device_intr_close, 260 .cleartoggle = ehci_device_clear_toggle, 261 .done = ehci_device_intr_done, 262 }; 263 264 struct usbd_pipe_methods ehci_device_bulk_methods = { 265 .transfer = ehci_device_bulk_transfer, 266 .start = ehci_device_bulk_start, 267 .abort = ehci_device_bulk_abort, 268 .close = ehci_device_bulk_close, 269 .cleartoggle = ehci_device_clear_toggle, 270 .done = ehci_device_bulk_done, 271 }; 272 273 struct usbd_pipe_methods ehci_device_isoc_methods = { 274 .transfer = ehci_device_isoc_transfer, 275 .start = ehci_device_isoc_start, 276 .abort = ehci_device_isoc_abort, 277 .close = ehci_device_isoc_close, 278 .done = ehci_device_isoc_done, 279 }; 280 281 /* 282 * Reverse a number with nbits bits. Used to evenly distribute lower-level 283 * interrupt heads in the periodic schedule. 284 * Suitable for use with EHCI_IPOLLRATES <= 9. 285 */ 286 u_int8_t 287 ehci_reverse_bits(u_int8_t c, int nbits) 288 { 289 c = ((c >> 1) & 0x55) | ((c << 1) & 0xaa); 290 c = ((c >> 2) & 0x33) | ((c << 2) & 0xcc); 291 c = ((c >> 4) & 0x0f) | ((c << 4) & 0xf0); 292 293 return c >> (8 - nbits); 294 } 295 296 usbd_status 297 ehci_init(struct ehci_softc *sc) 298 { 299 u_int32_t sparams, cparams, hcr; 300 u_int i, j; 301 usbd_status err; 302 struct ehci_soft_qh *sqh; 303 304 #ifdef EHCI_DEBUG 305 u_int32_t vers; 306 theehci = sc; 307 308 DPRINTF(("ehci_init: start\n")); 309 310 vers = EREAD2(sc, EHCI_HCIVERSION); 311 DPRINTF(("%s: EHCI version %x.%x\n", sc->sc_bus.bdev.dv_xname, 312 vers >> 8, vers & 0xff)); 313 #endif 314 315 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 316 317 sparams = EREAD4(sc, EHCI_HCSPARAMS); 318 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 319 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 320 cparams = EREAD4(sc, EHCI_HCCPARAMS); 321 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 322 323 /* MUST clear segment register if 64 bit capable. */ 324 if (EHCI_HCC_64BIT(cparams)) 325 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 326 327 sc->sc_bus.usbrev = USBREV_2_0; 328 329 DPRINTF(("%s: resetting\n", sc->sc_bus.bdev.dv_xname)); 330 err = ehci_reset(sc); 331 if (err) 332 return (err); 333 334 if (ehcixfer == NULL) { 335 ehcixfer = malloc(sizeof(struct pool), M_DEVBUF, M_NOWAIT); 336 if (ehcixfer == NULL) { 337 printf("%s: unable to allocate pool descriptor\n", 338 sc->sc_bus.bdev.dv_xname); 339 return (ENOMEM); 340 } 341 pool_init(ehcixfer, sizeof(struct ehci_xfer), 0, IPL_SOFTUSB, 342 0, "ehcixfer", NULL); 343 } 344 345 /* frame list size at default, read back what we got and use that */ 346 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 347 case 0: 348 sc->sc_flsize = 1024; 349 break; 350 case 1: 351 sc->sc_flsize = 512; 352 break; 353 case 2: 354 sc->sc_flsize = 256; 355 break; 356 case 3: 357 return (USBD_IOERROR); 358 } 359 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 360 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 361 if (err) 362 return (err); 363 DPRINTF(("%s: flsize=%d\n", sc->sc_bus.bdev.dv_xname,sc->sc_flsize)); 364 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 365 366 for (i = 0; i < sc->sc_flsize; i++) 367 sc->sc_flist[i] = htole32(EHCI_LINK_TERMINATE); 368 369 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 370 371 sc->sc_softitds = mallocarray(sc->sc_flsize, 372 sizeof(struct ehci_soft_itd *), M_USB, M_NOWAIT | M_ZERO); 373 if (sc->sc_softitds == NULL) { 374 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 375 return (ENOMEM); 376 } 377 LIST_INIT(&sc->sc_freeitds); 378 TAILQ_INIT(&sc->sc_intrhead); 379 380 /* Set up the bus struct. */ 381 sc->sc_bus.methods = &ehci_bus_methods; 382 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 383 384 sc->sc_eintrs = EHCI_NORMAL_INTRS; 385 386 /* 387 * Allocate the interrupt dummy QHs. These are arranged to give poll 388 * intervals that are powers of 2 times 1ms. 389 */ 390 for (i = 0; i < EHCI_INTRQHS; i++) { 391 sqh = ehci_alloc_sqh(sc); 392 if (sqh == NULL) { 393 err = USBD_NOMEM; 394 goto bad1; 395 } 396 sc->sc_islots[i].sqh = sqh; 397 } 398 for (i = 0; i < EHCI_INTRQHS; i++) { 399 sqh = sc->sc_islots[i].sqh; 400 if (i == 0) { 401 /* The last (1ms) QH terminates. */ 402 sqh->qh.qh_link = htole32(EHCI_LINK_TERMINATE); 403 sqh->next = NULL; 404 } else { 405 /* Otherwise the next QH has half the poll interval */ 406 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 407 sqh->qh.qh_link = htole32(sqh->next->physaddr | 408 EHCI_LINK_QH); 409 } 410 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 411 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 412 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 413 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 414 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 415 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 416 sqh->sqtd = NULL; 417 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 418 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 419 } 420 /* Point the frame list at the last level (128ms). */ 421 for (i = 0; i < (1 << (EHCI_IPOLLRATES - 1)); i++) 422 for (j = i; j < sc->sc_flsize; j += 1 << (EHCI_IPOLLRATES - 1)) 423 sc->sc_flist[j] = htole32(EHCI_LINK_QH | sc->sc_islots[ 424 EHCI_IQHIDX(EHCI_IPOLLRATES - 1, ehci_reverse_bits( 425 i, EHCI_IPOLLRATES - 1))].sqh->physaddr); 426 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 427 BUS_DMASYNC_PREWRITE); 428 429 /* Allocate dummy QH that starts the async list. */ 430 sqh = ehci_alloc_sqh(sc); 431 if (sqh == NULL) { 432 err = USBD_NOMEM; 433 goto bad1; 434 } 435 /* Fill the QH */ 436 sqh->qh.qh_endp = 437 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 438 sqh->qh.qh_link = 439 htole32(sqh->physaddr | EHCI_LINK_QH); 440 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 441 sqh->prev = sqh; /*It's a circular list.. */ 442 sqh->next = sqh; 443 /* Fill the overlay qTD */ 444 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 445 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 446 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 447 sqh->sqtd = NULL; 448 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 449 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 450 451 /* Point to async list */ 452 sc->sc_async_head = sqh; 453 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 454 455 timeout_set(&sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 456 457 rw_init(&sc->sc_doorbell_lock, "ehcidb"); 458 459 /* Turn on controller */ 460 EOWRITE4(sc, EHCI_USBCMD, 461 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 462 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 463 EHCI_CMD_ASE | 464 EHCI_CMD_PSE | 465 EHCI_CMD_RS); 466 467 /* Take over port ownership */ 468 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 469 470 for (i = 0; i < 100; i++) { 471 usb_delay_ms(&sc->sc_bus, 1); 472 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 473 if (!hcr) 474 break; 475 } 476 if (hcr) { 477 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 478 return (USBD_IOERROR); 479 } 480 481 /* Enable interrupts */ 482 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 483 484 return (USBD_NORMAL_COMPLETION); 485 486 #if 0 487 bad2: 488 ehci_free_sqh(sc, sc->sc_async_head); 489 #endif 490 bad1: 491 free(sc->sc_softitds, M_USB, sc->sc_flsize); 492 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 493 return (err); 494 } 495 496 int 497 ehci_intr(void *v) 498 { 499 struct ehci_softc *sc = v; 500 501 if (sc == NULL || sc->sc_bus.dying) 502 return (0); 503 504 /* If we get an interrupt while polling, then just ignore it. */ 505 if (sc->sc_bus.use_polling) { 506 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 507 508 if (intrs) 509 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 510 return (0); 511 } 512 513 return (ehci_intr1(sc)); 514 } 515 516 int 517 ehci_intr1(struct ehci_softc *sc) 518 { 519 u_int32_t intrs, eintrs; 520 521 /* In case the interrupt occurs before initialization has completed. */ 522 if (sc == NULL) { 523 #ifdef DIAGNOSTIC 524 printf("ehci_intr1: sc == NULL\n"); 525 #endif 526 return (0); 527 } 528 529 intrs = EOREAD4(sc, EHCI_USBSTS); 530 if (intrs == 0xffffffff) { 531 sc->sc_bus.dying = 1; 532 return (0); 533 } 534 intrs = EHCI_STS_INTRS(intrs); 535 if (!intrs) 536 return (0); 537 538 eintrs = intrs & sc->sc_eintrs; 539 if (!eintrs) 540 return (0); 541 542 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 543 sc->sc_bus.no_intrs++; 544 545 if (eintrs & EHCI_STS_HSE) { 546 printf("%s: unrecoverable error, controller halted\n", 547 sc->sc_bus.bdev.dv_xname); 548 sc->sc_bus.dying = 1; 549 return (1); 550 } 551 if (eintrs & EHCI_STS_IAA) { 552 wakeup(&sc->sc_async_head); 553 eintrs &= ~EHCI_STS_IAA; 554 } 555 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 556 usb_schedsoftintr(&sc->sc_bus); 557 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 558 } 559 if (eintrs & EHCI_STS_PCD) { 560 atomic_setbits_int(&sc->sc_flags, EHCIF_PCB_INTR); 561 usb_schedsoftintr(&sc->sc_bus); 562 eintrs &= ~EHCI_STS_PCD; 563 } 564 565 if (eintrs != 0) { 566 /* Block unprocessed interrupts. */ 567 sc->sc_eintrs &= ~eintrs; 568 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 569 printf("%s: blocking intrs 0x%x\n", 570 sc->sc_bus.bdev.dv_xname, eintrs); 571 } 572 573 return (1); 574 } 575 576 void 577 ehci_pcd(struct ehci_softc *sc, struct usbd_xfer *xfer) 578 { 579 u_char *p; 580 int i, m; 581 582 if (xfer == NULL) { 583 /* Just ignore the change. */ 584 return; 585 } 586 587 p = KERNADDR(&xfer->dmabuf, 0); 588 m = min(sc->sc_noport, xfer->length * 8 - 1); 589 memset(p, 0, xfer->length); 590 for (i = 1; i <= m; i++) { 591 /* Pick out CHANGE bits from the status reg. */ 592 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 593 p[i / 8] |= 1 << (i % 8); 594 } 595 xfer->actlen = xfer->length; 596 xfer->status = USBD_NORMAL_COMPLETION; 597 598 usb_transfer_complete(xfer); 599 } 600 601 /* 602 * Work around the half configured control (default) pipe when setting 603 * the address of a device. 604 * 605 * Because a single QH is setup per endpoint in ehci_open(), and the 606 * control pipe is configured before we could have set the address 607 * of the device or read the wMaxPacketSize of the endpoint, we have 608 * to re-open the pipe twice here. 609 */ 610 int 611 ehci_setaddr(struct usbd_device *dev, int addr) 612 { 613 /* Root Hub */ 614 if (dev->depth == 0) 615 return (0); 616 617 /* Re-establish the default pipe with the new max packet size. */ 618 ehci_close_pipe(dev->default_pipe); 619 if (ehci_open(dev->default_pipe)) 620 return (EINVAL); 621 622 if (usbd_set_address(dev, addr)) 623 return (1); 624 625 dev->address = addr; 626 627 /* Re-establish the default pipe with the new address. */ 628 ehci_close_pipe(dev->default_pipe); 629 if (ehci_open(dev->default_pipe)) 630 return (EINVAL); 631 632 return (0); 633 } 634 635 void 636 ehci_softintr(void *v) 637 { 638 struct ehci_softc *sc = v; 639 struct ehci_xfer *ex, *nextex; 640 641 if (sc->sc_bus.dying) 642 return; 643 644 sc->sc_bus.intr_context++; 645 646 if (sc->sc_flags & EHCIF_PCB_INTR) { 647 atomic_clearbits_int(&sc->sc_flags, EHCIF_PCB_INTR); 648 ehci_pcd(sc, sc->sc_intrxfer); 649 } 650 651 /* 652 * The only explanation I can think of for why EHCI is as brain dead 653 * as UHCI interrupt-wise is that Intel was involved in both. 654 * An interrupt just tells us that something is done, we have no 655 * clue what, so we need to scan through all active transfers. :-( 656 */ 657 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 658 nextex = TAILQ_NEXT(ex, inext); 659 ehci_check_intr(sc, &ex->xfer); 660 } 661 662 /* Schedule a callout to catch any dropped transactions. */ 663 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 664 !TAILQ_EMPTY(&sc->sc_intrhead)) { 665 timeout_add_sec(&sc->sc_tmo_intrlist, 1); 666 } 667 668 if (sc->sc_softwake) { 669 sc->sc_softwake = 0; 670 wakeup(&sc->sc_softwake); 671 } 672 673 sc->sc_bus.intr_context--; 674 } 675 676 void 677 ehci_check_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 678 { 679 int attr = xfer->pipe->endpoint->edesc->bmAttributes; 680 681 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 682 ehci_check_itd_intr(sc, xfer); 683 else 684 ehci_check_qh_intr(sc, xfer); 685 } 686 687 void 688 ehci_check_qh_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 689 { 690 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 691 struct ehci_soft_qtd *sqtd, *lsqtd = ex->sqtdend; 692 uint32_t status; 693 694 KASSERT(ex->sqtdstart != NULL && ex->sqtdend != NULL); 695 696 usb_syncmem(&lsqtd->dma, 697 lsqtd->offs + offsetof(struct ehci_qtd, qtd_status), 698 sizeof(lsqtd->qtd.qtd_status), 699 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 700 701 /* 702 * If the last TD is still active we need to check whether there 703 * is a an error somewhere in the middle, or whether there was a 704 * short packet (SPD and not ACTIVE). 705 */ 706 if (letoh32(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 707 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 708 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 709 usb_syncmem(&sqtd->dma, 710 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 711 sizeof(sqtd->qtd.qtd_status), 712 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 713 status = letoh32(sqtd->qtd.qtd_status); 714 usb_syncmem(&sqtd->dma, 715 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 716 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 717 /* If there's an active QTD the xfer isn't done. */ 718 if (status & EHCI_QTD_ACTIVE) 719 break; 720 /* Any kind of error makes the xfer done. */ 721 if (status & EHCI_QTD_HALTED) 722 goto done; 723 /* We want short packets, and it is short: it's done */ 724 if (EHCI_QTD_GET_BYTES(status) != 0) 725 goto done; 726 } 727 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 728 ex, ex->sqtdstart)); 729 usb_syncmem(&lsqtd->dma, 730 lsqtd->offs + offsetof(struct ehci_qtd, qtd_status), 731 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 732 return; 733 } 734 done: 735 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 736 timeout_del(&xfer->timeout_handle); 737 usb_rem_task(xfer->pipe->device, &xfer->abort_task); 738 ehci_idone(xfer); 739 } 740 741 void 742 ehci_check_itd_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 743 { 744 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 745 struct ehci_soft_itd *itd = ex->itdend; 746 int i; 747 748 if (xfer != SIMPLEQ_FIRST(&xfer->pipe->queue)) 749 return; 750 751 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 752 753 /* Check no active transfers in last itd, meaning we're finished */ 754 if (xfer->device->speed == USB_SPEED_HIGH) { 755 usb_syncmem(&itd->dma, 756 itd->offs + offsetof(struct ehci_itd, itd_ctl), 757 sizeof(itd->itd.itd_ctl), 758 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 759 760 for (i = 0; i < 8; i++) { 761 if (letoh32(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 762 return; 763 } 764 } else { 765 usb_syncmem(&itd->dma, 766 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 767 sizeof(itd->sitd.sitd_trans), 768 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 769 770 if (le32toh(itd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 771 return; 772 } 773 774 /* All descriptor(s) inactive, it's done */ 775 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 776 timeout_del(&xfer->timeout_handle); 777 usb_rem_task(xfer->pipe->device, &xfer->abort_task); 778 ehci_isoc_idone(xfer); 779 } 780 781 void 782 ehci_isoc_idone(struct usbd_xfer *xfer) 783 { 784 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 785 struct ehci_soft_itd *itd; 786 int i, len, uframes, nframes = 0, actlen = 0; 787 uint32_t status = 0; 788 789 if (xfer->status == USBD_CANCELLED || xfer->status == USBD_TIMEOUT) 790 return; 791 792 if (xfer->device->speed == USB_SPEED_HIGH) { 793 switch (xfer->pipe->endpoint->edesc->bInterval) { 794 case 0: 795 panic("isoc xfer suddenly has 0 bInterval, invalid"); 796 case 1: 797 uframes = 1; 798 break; 799 case 2: 800 uframes = 2; 801 break; 802 case 3: 803 uframes = 4; 804 break; 805 default: 806 uframes = 8; 807 break; 808 } 809 810 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 811 usb_syncmem(&itd->dma, 812 itd->offs + offsetof(struct ehci_itd, itd_ctl), 813 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 814 BUS_DMASYNC_POSTREAD); 815 816 for (i = 0; i < 8; i += uframes) { 817 /* XXX - driver didn't fill in the frame full 818 * of uframes. This leads to scheduling 819 * inefficiencies, but working around 820 * this doubles complexity of tracking 821 * an xfer. 822 */ 823 if (nframes >= xfer->nframes) 824 break; 825 826 status = letoh32(itd->itd.itd_ctl[i]); 827 len = EHCI_ITD_GET_LEN(status); 828 if (EHCI_ITD_GET_STATUS(status) != 0) 829 len = 0; /*No valid data on error*/ 830 831 xfer->frlengths[nframes++] = len; 832 actlen += len; 833 } 834 } 835 } else { 836 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 837 usb_syncmem(&itd->dma, 838 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 839 sizeof(itd->sitd.sitd_trans), 840 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 841 842 status = le32toh(itd->sitd.sitd_trans); 843 len = EHCI_SITD_GET_LEN(status); 844 if (xfer->frlengths[nframes] >= len) 845 len = xfer->frlengths[nframes] - len; 846 else 847 len = 0; 848 849 xfer->frlengths[nframes++] = len; 850 actlen += len; 851 } 852 } 853 854 #ifdef DIAGNOSTIC 855 ex->isdone = 1; 856 #endif 857 xfer->actlen = actlen; 858 xfer->status = USBD_NORMAL_COMPLETION; 859 usb_transfer_complete(xfer); 860 } 861 862 void 863 ehci_idone(struct usbd_xfer *xfer) 864 { 865 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 866 struct ehci_soft_qtd *sqtd; 867 u_int32_t status = 0, nstatus = 0; 868 int actlen, cerr; 869 870 #ifdef DIAGNOSTIC 871 { 872 int s = splhigh(); 873 if (ex->isdone) { 874 splx(s); 875 printf("ehci_idone: ex=%p is done!\n", ex); 876 return; 877 } 878 ex->isdone = 1; 879 splx(s); 880 } 881 #endif 882 if (xfer->status == USBD_CANCELLED || xfer->status == USBD_TIMEOUT) 883 return; 884 885 actlen = 0; 886 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) { 887 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 888 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 889 nstatus = letoh32(sqtd->qtd.qtd_status); 890 if (nstatus & EHCI_QTD_ACTIVE) 891 break; 892 893 status = nstatus; 894 /* halt is ok if descriptor is last, and complete */ 895 if (sqtd->qtd.qtd_next == htole32(EHCI_LINK_TERMINATE) && 896 EHCI_QTD_GET_BYTES(status) == 0) 897 status &= ~EHCI_QTD_HALTED; 898 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 899 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 900 } 901 902 cerr = EHCI_QTD_GET_CERR(status); 903 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 904 "status=0x%x\n", xfer->length, actlen, cerr, status)); 905 xfer->actlen = actlen; 906 if ((status & EHCI_QTD_HALTED) != 0) { 907 if ((status & EHCI_QTD_BABBLE) == 0 && cerr > 0) 908 xfer->status = USBD_STALLED; 909 else 910 xfer->status = USBD_IOERROR; /* more info XXX */ 911 } else 912 xfer->status = USBD_NORMAL_COMPLETION; 913 914 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 915 * during this call, before methods->done is called: dma sync required 916 * beforehand? */ 917 usb_transfer_complete(xfer); 918 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 919 } 920 921 /* 922 * Wait here until controller claims to have an interrupt. 923 * Then call ehci_intr and return. Use timeout to avoid waiting 924 * too long. 925 */ 926 void 927 ehci_waitintr(struct ehci_softc *sc, struct usbd_xfer *xfer) 928 { 929 int timo; 930 u_int32_t intrs; 931 932 xfer->status = USBD_IN_PROGRESS; 933 for (timo = xfer->timeout; timo >= 0; timo--) { 934 usb_delay_ms(&sc->sc_bus, 1); 935 if (sc->sc_bus.dying) 936 break; 937 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 938 sc->sc_eintrs; 939 if (intrs) { 940 ehci_intr1(sc); 941 if (xfer->status != USBD_IN_PROGRESS) 942 return; 943 } 944 } 945 946 /* Timeout */ 947 xfer->status = USBD_TIMEOUT; 948 usb_transfer_complete(xfer); 949 /* XXX should free TD */ 950 } 951 952 void 953 ehci_poll(struct usbd_bus *bus) 954 { 955 struct ehci_softc *sc = (struct ehci_softc *)bus; 956 957 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 958 ehci_intr1(sc); 959 } 960 961 int 962 ehci_detach(struct device *self, int flags) 963 { 964 struct ehci_softc *sc = (struct ehci_softc *)self; 965 int rv; 966 967 rv = config_detach_children(self, flags); 968 if (rv != 0) 969 return (rv); 970 971 timeout_del(&sc->sc_tmo_intrlist); 972 973 ehci_reset(sc); 974 975 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 976 977 free(sc->sc_softitds, M_USB, sc->sc_flsize); 978 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 979 /* XXX free other data structures XXX */ 980 981 return (rv); 982 } 983 984 985 int 986 ehci_activate(struct device *self, int act) 987 { 988 struct ehci_softc *sc = (struct ehci_softc *)self; 989 u_int32_t cmd, hcr, cparams; 990 int i, rv = 0; 991 992 switch (act) { 993 case DVACT_SUSPEND: 994 rv = config_activate_children(self, act); 995 996 #ifdef DIAGNOSTIC 997 if (!TAILQ_EMPTY(&sc->sc_intrhead)) { 998 printf("%s: interrupt list not empty\n", 999 sc->sc_bus.bdev.dv_xname); 1000 return (-1); 1001 } 1002 #endif 1003 1004 sc->sc_bus.use_polling++; 1005 1006 for (i = 1; i <= sc->sc_noport; i++) { 1007 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1008 if ((cmd & (EHCI_PS_PO|EHCI_PS_PE)) == EHCI_PS_PE) 1009 EOWRITE4(sc, EHCI_PORTSC(i), 1010 cmd | EHCI_PS_SUSP); 1011 } 1012 1013 /* 1014 * First tell the host to stop processing Asynchronous 1015 * and Periodic schedules. 1016 */ 1017 cmd = EOREAD4(sc, EHCI_USBCMD) & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1018 EOWRITE4(sc, EHCI_USBCMD, cmd); 1019 for (i = 0; i < 100; i++) { 1020 usb_delay_ms(&sc->sc_bus, 1); 1021 hcr = EOREAD4(sc, EHCI_USBSTS) & 1022 (EHCI_STS_ASS | EHCI_STS_PSS); 1023 if (hcr == 0) 1024 break; 1025 } 1026 if (hcr != 0) 1027 printf("%s: disable schedules timeout\n", 1028 sc->sc_bus.bdev.dv_xname); 1029 1030 /* 1031 * Then reset the host as if it was a shutdown. 1032 * 1033 * All USB devices are disconnected/reconnected during 1034 * a suspend/resume cycle so keep it simple. 1035 */ 1036 ehci_reset(sc); 1037 1038 sc->sc_bus.use_polling--; 1039 break; 1040 case DVACT_RESUME: 1041 sc->sc_bus.use_polling++; 1042 1043 ehci_reset(sc); 1044 1045 cparams = EREAD4(sc, EHCI_HCCPARAMS); 1046 /* MUST clear segment register if 64 bit capable. */ 1047 if (EHCI_HCC_64BIT(cparams)) 1048 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1049 1050 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1051 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1052 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1053 1054 hcr = 0; 1055 for (i = 1; i <= sc->sc_noport; i++) { 1056 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1057 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == EHCI_PS_SUSP) { 1058 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1059 hcr = 1; 1060 } 1061 } 1062 1063 if (hcr) { 1064 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1065 for (i = 1; i <= sc->sc_noport; i++) { 1066 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1067 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == 1068 EHCI_PS_SUSP) 1069 EOWRITE4(sc, EHCI_PORTSC(i), 1070 cmd & ~EHCI_PS_FPR); 1071 } 1072 } 1073 1074 /* Turn on controller */ 1075 EOWRITE4(sc, EHCI_USBCMD, 1076 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 1077 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 1078 EHCI_CMD_ASE | 1079 EHCI_CMD_PSE | 1080 EHCI_CMD_RS); 1081 1082 /* Take over port ownership */ 1083 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 1084 for (i = 0; i < 100; i++) { 1085 usb_delay_ms(&sc->sc_bus, 1); 1086 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1087 if (!hcr) 1088 break; 1089 } 1090 1091 if (hcr) { 1092 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 1093 /* XXX should we bail here? */ 1094 } 1095 1096 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1097 1098 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1099 1100 sc->sc_bus.use_polling--; 1101 rv = config_activate_children(self, act); 1102 break; 1103 case DVACT_POWERDOWN: 1104 rv = config_activate_children(self, act); 1105 ehci_reset(sc); 1106 break; 1107 default: 1108 rv = config_activate_children(self, act); 1109 break; 1110 } 1111 return (rv); 1112 } 1113 1114 usbd_status 1115 ehci_reset(struct ehci_softc *sc) 1116 { 1117 u_int32_t hcr, usbmode; 1118 int i; 1119 1120 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1121 for (i = 0; i < 100; i++) { 1122 usb_delay_ms(&sc->sc_bus, 1); 1123 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1124 if (hcr) 1125 break; 1126 } 1127 1128 if (!hcr) 1129 printf("%s: halt timeout\n", sc->sc_bus.bdev.dv_xname); 1130 1131 if (sc->sc_flags & EHCIF_USBMODE) 1132 usbmode = EOREAD4(sc, EHCI_USBMODE); 1133 1134 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1135 for (i = 0; i < 100; i++) { 1136 usb_delay_ms(&sc->sc_bus, 1); 1137 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 1138 if (!hcr) 1139 break; 1140 } 1141 1142 if (hcr) { 1143 printf("%s: reset timeout\n", sc->sc_bus.bdev.dv_xname); 1144 return (USBD_IOERROR); 1145 } 1146 1147 if (sc->sc_flags & EHCIF_USBMODE) 1148 EOWRITE4(sc, EHCI_USBMODE, usbmode); 1149 1150 return (USBD_NORMAL_COMPLETION); 1151 } 1152 1153 struct usbd_xfer * 1154 ehci_allocx(struct usbd_bus *bus) 1155 { 1156 struct ehci_xfer *ex; 1157 1158 ex = pool_get(ehcixfer, PR_NOWAIT | PR_ZERO); 1159 #ifdef DIAGNOSTIC 1160 if (ex != NULL) 1161 ex->isdone = 1; 1162 #endif 1163 return ((struct usbd_xfer *)ex); 1164 } 1165 1166 void 1167 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1168 { 1169 struct ehci_xfer *ex = (struct ehci_xfer*)xfer; 1170 1171 #ifdef DIAGNOSTIC 1172 if (!ex->isdone) { 1173 printf("%s: !isdone\n", __func__); 1174 return; 1175 } 1176 #endif 1177 pool_put(ehcixfer, ex); 1178 } 1179 1180 void 1181 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1182 { 1183 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1184 1185 #ifdef DIAGNOSTIC 1186 if ((epipe->sqh->qh.qh_qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) != 0) 1187 panic("ehci_device_clear_toggle: queue active"); 1188 #endif 1189 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1190 } 1191 1192 #ifdef EHCI_DEBUG 1193 void 1194 ehci_dump_regs(struct ehci_softc *sc) 1195 { 1196 int i; 1197 1198 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1199 EOREAD4(sc, EHCI_USBCMD), 1200 EOREAD4(sc, EHCI_USBSTS), 1201 EOREAD4(sc, EHCI_USBINTR)); 1202 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1203 EOREAD4(sc, EHCI_FRINDEX), 1204 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1205 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1206 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1207 for (i = 1; i <= sc->sc_noport; i++) 1208 printf("port %d status=0x%08x\n", i, 1209 EOREAD4(sc, EHCI_PORTSC(i))); 1210 } 1211 1212 /* 1213 * Unused function - this is meant to be called from a kernel 1214 * debugger. 1215 */ 1216 void 1217 ehci_dump(void) 1218 { 1219 ehci_dump_regs(theehci); 1220 } 1221 1222 void 1223 ehci_dump_link(ehci_link_t link, int type) 1224 { 1225 link = letoh32(link); 1226 printf("0x%08x", link); 1227 if (link & EHCI_LINK_TERMINATE) 1228 printf("<T>"); 1229 else { 1230 printf("<"); 1231 if (type) { 1232 switch (EHCI_LINK_TYPE(link)) { 1233 case EHCI_LINK_ITD: 1234 printf("ITD"); 1235 break; 1236 case EHCI_LINK_QH: 1237 printf("QH"); 1238 break; 1239 case EHCI_LINK_SITD: 1240 printf("SITD"); 1241 break; 1242 case EHCI_LINK_FSTN: 1243 printf("FSTN"); 1244 break; 1245 } 1246 } 1247 printf(">"); 1248 } 1249 } 1250 1251 void 1252 ehci_dump_sqtds(struct ehci_soft_qtd *sqtd) 1253 { 1254 int i; 1255 u_int32_t stop; 1256 1257 stop = 0; 1258 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1259 ehci_dump_sqtd(sqtd); 1260 usb_syncmem(&sqtd->dma, 1261 sqtd->offs + offsetof(struct ehci_qtd, qtd_next), 1262 sizeof(sqtd->qtd), 1263 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1264 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1265 usb_syncmem(&sqtd->dma, 1266 sqtd->offs + offsetof(struct ehci_qtd, qtd_next), 1267 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1268 } 1269 if (!stop) 1270 printf("dump aborted, too many TDs\n"); 1271 } 1272 1273 void 1274 ehci_dump_sqtd(struct ehci_soft_qtd *sqtd) 1275 { 1276 usb_syncmem(&sqtd->dma, sqtd->offs, 1277 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1278 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1279 ehci_dump_qtd(&sqtd->qtd); 1280 usb_syncmem(&sqtd->dma, sqtd->offs, 1281 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1282 } 1283 1284 void 1285 ehci_dump_qtd(struct ehci_qtd *qtd) 1286 { 1287 u_int32_t s; 1288 char sbuf[128]; 1289 1290 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1291 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1292 printf("\n"); 1293 s = letoh32(qtd->qtd_status); 1294 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), "\20\10ACTIVE\7HALTED" 1295 "\6BUFERR\5BABBLE\4XACTERR\3MISSED\2SPLIT\1PING", 1296 sbuf, sizeof(sbuf)); 1297 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1298 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1299 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1300 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1301 EHCI_QTD_GET_PID(s), sbuf); 1302 for (s = 0; s < 5; s++) 1303 printf(" buffer[%d]=0x%08x\n", s, letoh32(qtd->qtd_buffer[s])); 1304 } 1305 1306 void 1307 ehci_dump_sqh(struct ehci_soft_qh *sqh) 1308 { 1309 struct ehci_qh *qh = &sqh->qh; 1310 u_int32_t endp, endphub; 1311 1312 usb_syncmem(&sqh->dma, sqh->offs, 1313 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1314 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1315 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1316 endp = letoh32(qh->qh_endp); 1317 printf(" endp=0x%08x\n", endp); 1318 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1319 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1320 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1321 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1322 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1323 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1324 EHCI_QH_GET_NRL(endp)); 1325 endphub = letoh32(qh->qh_endphub); 1326 printf(" endphub=0x%08x\n", endphub); 1327 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1328 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1329 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1330 EHCI_QH_GET_MULT(endphub)); 1331 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1332 printf("Overlay qTD:\n"); 1333 ehci_dump_qtd(&qh->qh_qtd); 1334 usb_syncmem(&sqh->dma, sqh->offs, 1335 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1336 } 1337 1338 #if notyet 1339 void 1340 ehci_dump_itd(struct ehci_soft_itd *itd) 1341 { 1342 ehci_isoc_trans_t t; 1343 ehci_isoc_bufr_ptr_t b, b2, b3; 1344 int i; 1345 1346 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1347 1348 for (i = 0; i < 8; i++) { 1349 t = letoh32(itd->itd.itd_ctl[i]); 1350 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1351 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1352 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1353 EHCI_ITD_GET_OFFS(t)); 1354 } 1355 printf("ITDbufr: "); 1356 for (i = 0; i < 7; i++) 1357 printf("%X,", EHCI_ITD_GET_BPTR(letoh32(itd->itd.itd_bufr[i]))); 1358 1359 b = letoh32(itd->itd.itd_bufr[0]); 1360 b2 = letoh32(itd->itd.itd_bufr[1]); 1361 b3 = letoh32(itd->itd.itd_bufr[2]); 1362 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1363 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1364 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1365 } 1366 #endif 1367 1368 #ifdef DIAGNOSTIC 1369 void 1370 ehci_dump_exfer(struct ehci_xfer *ex) 1371 { 1372 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p " 1373 "isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, 1374 ex->itdend, ex->isdone); 1375 } 1376 #endif 1377 1378 #endif /* EHCI_DEBUG */ 1379 1380 usbd_status 1381 ehci_open(struct usbd_pipe *pipe) 1382 { 1383 struct usbd_device *dev = pipe->device; 1384 struct ehci_softc *sc = (struct ehci_softc *)dev->bus; 1385 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1386 u_int8_t addr = dev->address; 1387 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1388 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1389 struct ehci_soft_qh *sqh; 1390 usbd_status err; 1391 int s; 1392 int ival, speed, naks; 1393 int hshubaddr, hshubport; 1394 1395 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d\n", 1396 pipe, addr, ed->bEndpointAddress)); 1397 1398 if (sc->sc_bus.dying) 1399 return (USBD_IOERROR); 1400 1401 if (dev->myhsport) { 1402 hshubaddr = dev->myhsport->parent->address; 1403 hshubport = dev->myhsport->portno; 1404 } else { 1405 hshubaddr = 0; 1406 hshubport = 0; 1407 } 1408 1409 /* Root Hub */ 1410 if (pipe->device->depth == 0) { 1411 switch (ed->bEndpointAddress) { 1412 case USB_CONTROL_ENDPOINT: 1413 pipe->methods = &ehci_root_ctrl_methods; 1414 break; 1415 case UE_DIR_IN | EHCI_INTR_ENDPT: 1416 pipe->methods = &ehci_root_intr_methods; 1417 break; 1418 default: 1419 return (USBD_INVAL); 1420 } 1421 return (USBD_NORMAL_COMPLETION); 1422 } 1423 1424 /* XXX All this stuff is only valid for async. */ 1425 switch (dev->speed) { 1426 case USB_SPEED_LOW: 1427 speed = EHCI_QH_SPEED_LOW; 1428 break; 1429 case USB_SPEED_FULL: 1430 speed = EHCI_QH_SPEED_FULL; 1431 break; 1432 case USB_SPEED_HIGH: 1433 speed = EHCI_QH_SPEED_HIGH; 1434 break; 1435 default: 1436 panic("ehci_open: bad device speed %d", dev->speed); 1437 } 1438 1439 naks = 8; /* XXX */ 1440 1441 /* Allocate sqh for everything, save isoc xfers */ 1442 if (xfertype != UE_ISOCHRONOUS) { 1443 sqh = ehci_alloc_sqh(sc); 1444 if (sqh == NULL) 1445 return (USBD_NOMEM); 1446 /* qh_link filled when the QH is added */ 1447 sqh->qh.qh_endp = htole32( 1448 EHCI_QH_SET_ADDR(addr) | 1449 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1450 EHCI_QH_SET_EPS(speed) | 1451 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1452 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1453 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1454 EHCI_QH_CTL : 0) | 1455 EHCI_QH_SET_NRL(naks) 1456 ); 1457 sqh->qh.qh_endphub = htole32( 1458 EHCI_QH_SET_MULT(1) | 1459 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0) 1460 ); 1461 if (speed != EHCI_QH_SPEED_HIGH) { 1462 sqh->qh.qh_endphub |= htole32( 1463 EHCI_QH_SET_HUBA(hshubaddr) | 1464 EHCI_QH_SET_PORT(hshubport) | 1465 EHCI_QH_SET_CMASK(0x1c) /* XXX */ 1466 ); 1467 } 1468 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 1469 /* Fill the overlay qTD */ 1470 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 1471 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1472 sqh->qh.qh_qtd.qtd_status = 1473 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1474 1475 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1476 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1477 epipe->sqh = sqh; 1478 } /*xfertype == UE_ISOC*/ 1479 1480 switch (xfertype) { 1481 case UE_CONTROL: 1482 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1483 0, &epipe->u.ctl.reqdma); 1484 if (err) { 1485 ehci_free_sqh(sc, sqh); 1486 return (err); 1487 } 1488 pipe->methods = &ehci_device_ctrl_methods; 1489 s = splusb(); 1490 ehci_add_qh(sqh, sc->sc_async_head); 1491 splx(s); 1492 break; 1493 case UE_BULK: 1494 pipe->methods = &ehci_device_bulk_methods; 1495 s = splusb(); 1496 ehci_add_qh(sqh, sc->sc_async_head); 1497 splx(s); 1498 break; 1499 case UE_INTERRUPT: 1500 pipe->methods = &ehci_device_intr_methods; 1501 ival = pipe->interval; 1502 if (ival == USBD_DEFAULT_INTERVAL) 1503 ival = ed->bInterval; 1504 s = splusb(); 1505 err = ehci_device_setintr(sc, sqh, ival); 1506 splx(s); 1507 return (err); 1508 case UE_ISOCHRONOUS: 1509 switch (speed) { 1510 case EHCI_QH_SPEED_HIGH: 1511 case EHCI_QH_SPEED_FULL: 1512 pipe->methods = &ehci_device_isoc_methods; 1513 break; 1514 case EHCI_QH_SPEED_LOW: 1515 default: 1516 return (USBD_INVAL); 1517 } 1518 /* Spec page 271 says intervals > 16 are invalid */ 1519 if (ed->bInterval == 0 || ed->bInterval > 16) { 1520 printf("ehci: opening pipe with invalid bInterval\n"); 1521 return (USBD_INVAL); 1522 } 1523 if (UGETW(ed->wMaxPacketSize) == 0) { 1524 printf("ehci: zero length endpoint open request\n"); 1525 return (USBD_INVAL); 1526 } 1527 epipe->u.isoc.next_frame = 0; 1528 epipe->u.isoc.cur_xfers = 0; 1529 break; 1530 default: 1531 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1532 return (USBD_INVAL); 1533 } 1534 return (USBD_NORMAL_COMPLETION); 1535 } 1536 1537 /* 1538 * Add an ED to the schedule. Called at splusb(). 1539 * If in the async schedule, it will always have a next. 1540 * If in the intr schedule it may not. 1541 */ 1542 void 1543 ehci_add_qh(struct ehci_soft_qh *sqh, struct ehci_soft_qh *head) 1544 { 1545 SPLUSBCHECK; 1546 1547 usb_syncmem(&head->dma, head->offs + offsetof(struct ehci_qh, qh_link), 1548 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1549 sqh->next = head->next; 1550 sqh->prev = head; 1551 sqh->qh.qh_link = head->qh.qh_link; 1552 usb_syncmem(&sqh->dma, sqh->offs + offsetof(struct ehci_qh, qh_link), 1553 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1554 head->next = sqh; 1555 if (sqh->next) 1556 sqh->next->prev = sqh; 1557 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1558 usb_syncmem(&head->dma, head->offs + offsetof(struct ehci_qh, qh_link), 1559 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1560 } 1561 1562 /* 1563 * Remove an ED from the schedule. Called at splusb(). 1564 * Will always have a 'next' if it's in the async list as it's circular. 1565 */ 1566 void 1567 ehci_rem_qh(struct ehci_softc *sc, struct ehci_soft_qh *sqh) 1568 { 1569 SPLUSBCHECK; 1570 /* XXX */ 1571 usb_syncmem(&sqh->dma, sqh->offs + offsetof(struct ehci_qh, qh_link), 1572 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1573 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1574 sqh->prev->next = sqh->next; 1575 if (sqh->next) 1576 sqh->next->prev = sqh->prev; 1577 usb_syncmem(&sqh->prev->dma, 1578 sqh->prev->offs + offsetof(struct ehci_qh, qh_link), 1579 sizeof(sqh->prev->qh.qh_link), BUS_DMASYNC_PREWRITE); 1580 1581 ehci_sync_hc(sc); 1582 } 1583 1584 void 1585 ehci_set_qh_qtd(struct ehci_soft_qh *sqh, struct ehci_soft_qtd *sqtd) 1586 { 1587 int i; 1588 u_int32_t status; 1589 1590 /* Save toggle bit and ping status. */ 1591 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1592 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1593 status = sqh->qh.qh_qtd.qtd_status & 1594 htole32(EHCI_QTD_TOGGLE_MASK | 1595 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1596 /* Set HALTED to make hw leave it alone. */ 1597 sqh->qh.qh_qtd.qtd_status = 1598 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1599 usb_syncmem(&sqh->dma, 1600 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 1601 sizeof(sqh->qh.qh_qtd.qtd_status), 1602 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1603 sqh->qh.qh_curqtd = 0; 1604 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1605 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1606 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1607 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1608 sqh->sqtd = sqtd; 1609 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1610 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1611 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1612 sqh->qh.qh_qtd.qtd_status = status; 1613 usb_syncmem(&sqh->dma, 1614 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 1615 sizeof(sqh->qh.qh_qtd.qtd_status), 1616 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1617 } 1618 1619 /* 1620 * Ensure that the HC has released all references to the QH. We do this 1621 * by asking for a Async Advance Doorbell interrupt and then we wait for 1622 * the interrupt. 1623 * To make this easier we first obtain exclusive use of the doorbell. 1624 */ 1625 void 1626 ehci_sync_hc(struct ehci_softc *sc) 1627 { 1628 int s, error; 1629 int tries = 0; 1630 1631 if (sc->sc_bus.dying) { 1632 return; 1633 } 1634 1635 /* get doorbell */ 1636 rw_enter_write(&sc->sc_doorbell_lock); 1637 s = splhardusb(); 1638 do { 1639 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | 1640 EHCI_CMD_IAAD); 1641 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz / 2); 1642 } while (error && ++tries < 10); 1643 splx(s); 1644 /* release doorbell */ 1645 rw_exit_write(&sc->sc_doorbell_lock); 1646 #ifdef DIAGNOSTIC 1647 if (error) 1648 printf("ehci_sync_hc: tsleep() = %d\n", error); 1649 #endif 1650 } 1651 1652 void 1653 ehci_rem_itd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 1654 { 1655 struct ehci_soft_itd *itd, *prev = NULL; 1656 1657 splsoftassert(IPL_SOFTUSB); 1658 1659 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 1660 1661 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1662 prev = itd->u.frame_list.prev; 1663 /* Unlink itd from hardware chain, or frame array */ 1664 if (prev == NULL) { /* We're at the table head */ 1665 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1666 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1667 usb_syncmem(&sc->sc_fldma, 1668 sizeof(uint32_t) * itd->slot, sizeof(uint32_t), 1669 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1670 1671 if (itd->u.frame_list.next != NULL) 1672 itd->u.frame_list.next->u.frame_list.prev = 1673 NULL; 1674 } else { 1675 /* XXX this part is untested... */ 1676 prev->itd.itd_next = itd->itd.itd_next; 1677 usb_syncmem(&itd->dma, 1678 itd->offs + offsetof(struct ehci_itd, itd_next), 1679 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1680 1681 prev->u.frame_list.next = itd->u.frame_list.next; 1682 if (itd->u.frame_list.next != NULL) 1683 itd->u.frame_list.next->u.frame_list.prev = 1684 prev; 1685 } 1686 } 1687 } 1688 1689 void 1690 ehci_free_itd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 1691 { 1692 struct ehci_soft_itd *itd, *prev = NULL; 1693 1694 splsoftassert(IPL_SOFTUSB); 1695 1696 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 1697 1698 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1699 if (prev != NULL) 1700 ehci_free_itd(sc, prev); 1701 prev = itd; 1702 } 1703 if (prev) 1704 ehci_free_itd(sc, prev); 1705 ex->itdstart = NULL; 1706 ex->itdend = NULL; 1707 } 1708 1709 /* 1710 * Data structures and routines to emulate the root hub. 1711 */ 1712 usb_device_descriptor_t ehci_devd = { 1713 USB_DEVICE_DESCRIPTOR_SIZE, 1714 UDESC_DEVICE, /* type */ 1715 {0x00, 0x02}, /* USB version */ 1716 UDCLASS_HUB, /* class */ 1717 UDSUBCLASS_HUB, /* subclass */ 1718 UDPROTO_HSHUBSTT, /* protocol */ 1719 64, /* max packet */ 1720 {0},{0},{0x00,0x01}, /* device id */ 1721 1,2,0, /* string indicies */ 1722 1 /* # of configurations */ 1723 }; 1724 1725 usb_device_qualifier_t ehci_odevd = { 1726 USB_DEVICE_DESCRIPTOR_SIZE, 1727 UDESC_DEVICE_QUALIFIER, /* type */ 1728 {0x00, 0x02}, /* USB version */ 1729 UDCLASS_HUB, /* class */ 1730 UDSUBCLASS_HUB, /* subclass */ 1731 UDPROTO_FSHUB, /* protocol */ 1732 64, /* max packet */ 1733 1, /* # of configurations */ 1734 0 1735 }; 1736 1737 usb_config_descriptor_t ehci_confd = { 1738 USB_CONFIG_DESCRIPTOR_SIZE, 1739 UDESC_CONFIG, 1740 {USB_CONFIG_DESCRIPTOR_SIZE + 1741 USB_INTERFACE_DESCRIPTOR_SIZE + 1742 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1743 1, 1744 1, 1745 0, 1746 UC_SELF_POWERED, 1747 0 /* max power */ 1748 }; 1749 1750 usb_interface_descriptor_t ehci_ifcd = { 1751 USB_INTERFACE_DESCRIPTOR_SIZE, 1752 UDESC_INTERFACE, 1753 0, 1754 0, 1755 1, 1756 UICLASS_HUB, 1757 UISUBCLASS_HUB, 1758 UIPROTO_HSHUBSTT, 1759 0 1760 }; 1761 1762 usb_endpoint_descriptor_t ehci_endpd = { 1763 USB_ENDPOINT_DESCRIPTOR_SIZE, 1764 UDESC_ENDPOINT, 1765 UE_DIR_IN | EHCI_INTR_ENDPT, 1766 UE_INTERRUPT, 1767 {8, 0}, /* max packet */ 1768 12 1769 }; 1770 1771 usb_hub_descriptor_t ehci_hubd = { 1772 USB_HUB_DESCRIPTOR_SIZE, 1773 UDESC_HUB, 1774 0, 1775 {0,0}, 1776 0, 1777 0, 1778 {0}, 1779 }; 1780 1781 /* 1782 * Simulate a hardware hub by handling all the necessary requests. 1783 */ 1784 usbd_status 1785 ehci_root_ctrl_transfer(struct usbd_xfer *xfer) 1786 { 1787 usbd_status err; 1788 1789 /* Insert last in queue. */ 1790 err = usb_insert_transfer(xfer); 1791 if (err) 1792 return (err); 1793 1794 /* Pipe isn't running, start first */ 1795 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1796 } 1797 1798 usbd_status 1799 ehci_root_ctrl_start(struct usbd_xfer *xfer) 1800 { 1801 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1802 usb_device_request_t *req; 1803 void *buf = NULL; 1804 int port, i; 1805 int s, len, value, index, l, totlen = 0; 1806 usb_port_status_t ps; 1807 usb_hub_descriptor_t hubd; 1808 usbd_status err; 1809 u_int32_t v; 1810 1811 if (sc->sc_bus.dying) 1812 return (USBD_IOERROR); 1813 1814 #ifdef DIAGNOSTIC 1815 if (!(xfer->rqflags & URQ_REQUEST)) 1816 /* XXX panic */ 1817 return (USBD_INVAL); 1818 #endif 1819 req = &xfer->request; 1820 1821 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1822 req->bmRequestType, req->bRequest)); 1823 1824 len = UGETW(req->wLength); 1825 value = UGETW(req->wValue); 1826 index = UGETW(req->wIndex); 1827 1828 if (len != 0) 1829 buf = KERNADDR(&xfer->dmabuf, 0); 1830 1831 #define C(x,y) ((x) | ((y) << 8)) 1832 switch(C(req->bRequest, req->bmRequestType)) { 1833 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1834 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1835 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1836 /* 1837 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1838 * for the integrated root hub. 1839 */ 1840 break; 1841 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1842 if (len > 0) { 1843 *(u_int8_t *)buf = sc->sc_conf; 1844 totlen = 1; 1845 } 1846 break; 1847 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1848 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1849 switch(value >> 8) { 1850 case UDESC_DEVICE: 1851 if ((value & 0xff) != 0) { 1852 err = USBD_IOERROR; 1853 goto ret; 1854 } 1855 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1856 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1857 memcpy(buf, &ehci_devd, l); 1858 break; 1859 /* 1860 * We can't really operate at another speed, but the spec says 1861 * we need this descriptor. 1862 */ 1863 case UDESC_DEVICE_QUALIFIER: 1864 if ((value & 0xff) != 0) { 1865 err = USBD_IOERROR; 1866 goto ret; 1867 } 1868 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1869 memcpy(buf, &ehci_odevd, l); 1870 break; 1871 /* 1872 * We can't really operate at another speed, but the spec says 1873 * we need this descriptor. 1874 */ 1875 case UDESC_OTHER_SPEED_CONFIGURATION: 1876 case UDESC_CONFIG: 1877 if ((value & 0xff) != 0) { 1878 err = USBD_IOERROR; 1879 goto ret; 1880 } 1881 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1882 memcpy(buf, &ehci_confd, l); 1883 ((usb_config_descriptor_t *)buf)->bDescriptorType = 1884 value >> 8; 1885 buf = (char *)buf + l; 1886 len -= l; 1887 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1888 totlen += l; 1889 memcpy(buf, &ehci_ifcd, l); 1890 buf = (char *)buf + l; 1891 len -= l; 1892 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1893 totlen += l; 1894 memcpy(buf, &ehci_endpd, l); 1895 break; 1896 case UDESC_STRING: 1897 if (len == 0) 1898 break; 1899 *(u_int8_t *)buf = 0; 1900 totlen = 1; 1901 switch (value & 0xff) { 1902 case 0: /* Language table */ 1903 totlen = usbd_str(buf, len, "\001"); 1904 break; 1905 case 1: /* Vendor */ 1906 totlen = usbd_str(buf, len, sc->sc_vendor); 1907 break; 1908 case 2: /* Product */ 1909 totlen = usbd_str(buf, len, "EHCI root hub"); 1910 break; 1911 } 1912 break; 1913 default: 1914 err = USBD_IOERROR; 1915 goto ret; 1916 } 1917 break; 1918 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1919 if (len > 0) { 1920 *(u_int8_t *)buf = 0; 1921 totlen = 1; 1922 } 1923 break; 1924 case C(UR_GET_STATUS, UT_READ_DEVICE): 1925 if (len > 1) { 1926 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1927 totlen = 2; 1928 } 1929 break; 1930 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1931 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1932 if (len > 1) { 1933 USETW(((usb_status_t *)buf)->wStatus, 0); 1934 totlen = 2; 1935 } 1936 break; 1937 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1938 if (value >= USB_MAX_DEVICES) { 1939 err = USBD_IOERROR; 1940 goto ret; 1941 } 1942 break; 1943 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1944 if (value != 0 && value != 1) { 1945 err = USBD_IOERROR; 1946 goto ret; 1947 } 1948 sc->sc_conf = value; 1949 break; 1950 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1951 break; 1952 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1953 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1954 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1955 err = USBD_IOERROR; 1956 goto ret; 1957 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1958 break; 1959 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1960 break; 1961 /* Hub requests */ 1962 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1963 break; 1964 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1965 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 1966 "port=%d feature=%d\n", index, value)); 1967 if (index < 1 || index > sc->sc_noport) { 1968 err = USBD_IOERROR; 1969 goto ret; 1970 } 1971 port = EHCI_PORTSC(index); 1972 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 1973 switch(value) { 1974 case UHF_PORT_ENABLE: 1975 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 1976 break; 1977 case UHF_PORT_SUSPEND: 1978 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 1979 break; 1980 case UHF_PORT_POWER: 1981 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 1982 break; 1983 case UHF_PORT_TEST: 1984 DPRINTFN(2,("ehci_root_ctrl_start: " 1985 "clear port test %d\n", index)); 1986 break; 1987 case UHF_PORT_INDICATOR: 1988 DPRINTFN(2,("ehci_root_ctrl_start: " 1989 "clear port index %d\n", index)); 1990 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 1991 break; 1992 case UHF_C_PORT_CONNECTION: 1993 EOWRITE4(sc, port, v | EHCI_PS_CSC); 1994 break; 1995 case UHF_C_PORT_ENABLE: 1996 EOWRITE4(sc, port, v | EHCI_PS_PEC); 1997 break; 1998 case UHF_C_PORT_SUSPEND: 1999 /* how? */ 2000 break; 2001 case UHF_C_PORT_OVER_CURRENT: 2002 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2003 break; 2004 case UHF_C_PORT_RESET: 2005 sc->sc_isreset = 0; 2006 break; 2007 default: 2008 err = USBD_IOERROR; 2009 goto ret; 2010 } 2011 break; 2012 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2013 if ((value & 0xff) != 0) { 2014 err = USBD_IOERROR; 2015 goto ret; 2016 } 2017 hubd = ehci_hubd; 2018 hubd.bNbrPorts = sc->sc_noport; 2019 v = EREAD4(sc, EHCI_HCSPARAMS); 2020 USETW(hubd.wHubCharacteristics, 2021 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 2022 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0)); 2023 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2024 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2025 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2026 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2027 l = min(len, hubd.bDescLength); 2028 totlen = l; 2029 memcpy(buf, &hubd, l); 2030 break; 2031 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2032 if (len != 4) { 2033 err = USBD_IOERROR; 2034 goto ret; 2035 } 2036 memset(buf, 0, len); /* ? XXX */ 2037 totlen = len; 2038 break; 2039 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2040 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2041 index)); 2042 if (index < 1 || index > sc->sc_noport) { 2043 err = USBD_IOERROR; 2044 goto ret; 2045 } 2046 if (len != 4) { 2047 err = USBD_IOERROR; 2048 goto ret; 2049 } 2050 v = EOREAD4(sc, EHCI_PORTSC(index)); 2051 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2052 i = UPS_HIGH_SPEED; 2053 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2054 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2055 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2056 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2057 if (v & EHCI_PS_PR) i |= UPS_RESET; 2058 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2059 USETW(ps.wPortStatus, i); 2060 i = 0; 2061 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2062 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2063 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2064 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 2065 USETW(ps.wPortChange, i); 2066 l = min(len, sizeof(ps)); 2067 memcpy(buf, &ps, l); 2068 totlen = l; 2069 break; 2070 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2071 err = USBD_IOERROR; 2072 goto ret; 2073 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2074 break; 2075 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2076 if (index < 1 || index > sc->sc_noport) { 2077 err = USBD_IOERROR; 2078 goto ret; 2079 } 2080 port = EHCI_PORTSC(index); 2081 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2082 switch(value) { 2083 case UHF_PORT_ENABLE: 2084 EOWRITE4(sc, port, v | EHCI_PS_PE); 2085 break; 2086 case UHF_PORT_SUSPEND: 2087 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2088 break; 2089 case UHF_PORT_DISOWN_TO_1_1: 2090 /* enter to Port Reset State */ 2091 v &= ~EHCI_PS_PE; 2092 EOWRITE4(sc, port, v | EHCI_PS_PR); 2093 ehci_disown(sc, index, 0); 2094 break; 2095 case UHF_PORT_RESET: 2096 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2097 index)); 2098 if (EHCI_PS_IS_LOWSPEED(v)) { 2099 /* Low speed device, give up ownership. */ 2100 ehci_disown(sc, index, 1); 2101 break; 2102 } 2103 /* Start reset sequence. */ 2104 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2105 EOWRITE4(sc, port, v | EHCI_PS_PR); 2106 /* Wait for reset to complete. */ 2107 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2108 if (sc->sc_bus.dying) { 2109 err = USBD_IOERROR; 2110 goto ret; 2111 } 2112 /* Terminate reset sequence. */ 2113 v = EOREAD4(sc, port); 2114 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2115 /* Wait for HC to complete reset. */ 2116 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2117 if (sc->sc_bus.dying) { 2118 err = USBD_IOERROR; 2119 goto ret; 2120 } 2121 v = EOREAD4(sc, port); 2122 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2123 if (v & EHCI_PS_PR) { 2124 printf("%s: port reset timeout\n", 2125 sc->sc_bus.bdev.dv_xname); 2126 err = USBD_IOERROR; 2127 goto ret; 2128 } 2129 if (!(v & EHCI_PS_PE)) { 2130 /* Not a high speed device, give up ownership.*/ 2131 ehci_disown(sc, index, 0); 2132 break; 2133 } 2134 sc->sc_isreset = 1; 2135 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2136 index, v)); 2137 break; 2138 case UHF_PORT_POWER: 2139 DPRINTFN(2,("ehci_root_ctrl_start: " 2140 "set port power %d\n", index)); 2141 EOWRITE4(sc, port, v | EHCI_PS_PP); 2142 break; 2143 case UHF_PORT_TEST: 2144 DPRINTFN(2,("ehci_root_ctrl_start: " 2145 "set port test %d\n", index)); 2146 break; 2147 case UHF_PORT_INDICATOR: 2148 DPRINTFN(2,("ehci_root_ctrl_start: " 2149 "set port ind %d\n", index)); 2150 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2151 break; 2152 default: 2153 err = USBD_IOERROR; 2154 goto ret; 2155 } 2156 break; 2157 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2158 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2159 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2160 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2161 break; 2162 default: 2163 err = USBD_IOERROR; 2164 goto ret; 2165 } 2166 xfer->actlen = totlen; 2167 err = USBD_NORMAL_COMPLETION; 2168 ret: 2169 xfer->status = err; 2170 s = splusb(); 2171 usb_transfer_complete(xfer); 2172 splx(s); 2173 return (USBD_IN_PROGRESS); 2174 } 2175 2176 void 2177 ehci_disown(struct ehci_softc *sc, int index, int lowspeed) 2178 { 2179 int port; 2180 u_int32_t v; 2181 2182 port = EHCI_PORTSC(index); 2183 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2184 EOWRITE4(sc, port, v | EHCI_PS_PO); 2185 } 2186 2187 /* Abort a root control request. */ 2188 void 2189 ehci_root_ctrl_abort(struct usbd_xfer *xfer) 2190 { 2191 /* Nothing to do, all transfers are synchronous. */ 2192 } 2193 2194 /* Close the root pipe. */ 2195 void 2196 ehci_root_ctrl_close(struct usbd_pipe *pipe) 2197 { 2198 /* Nothing to do. */ 2199 } 2200 2201 void 2202 ehci_root_intr_done(struct usbd_xfer *xfer) 2203 { 2204 } 2205 2206 usbd_status 2207 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2208 { 2209 usbd_status err; 2210 2211 /* Insert last in queue. */ 2212 err = usb_insert_transfer(xfer); 2213 if (err) 2214 return (err); 2215 2216 /* Pipe isn't running, start first */ 2217 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2218 } 2219 2220 usbd_status 2221 ehci_root_intr_start(struct usbd_xfer *xfer) 2222 { 2223 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2224 2225 if (sc->sc_bus.dying) 2226 return (USBD_IOERROR); 2227 2228 sc->sc_intrxfer = xfer; 2229 2230 return (USBD_IN_PROGRESS); 2231 } 2232 2233 void 2234 ehci_root_intr_abort(struct usbd_xfer *xfer) 2235 { 2236 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2237 int s; 2238 2239 sc->sc_intrxfer = NULL; 2240 2241 xfer->status = USBD_CANCELLED; 2242 s = splusb(); 2243 usb_transfer_complete(xfer); 2244 splx(s); 2245 } 2246 2247 void 2248 ehci_root_intr_close(struct usbd_pipe *pipe) 2249 { 2250 } 2251 2252 void 2253 ehci_root_ctrl_done(struct usbd_xfer *xfer) 2254 { 2255 } 2256 2257 struct ehci_soft_qh * 2258 ehci_alloc_sqh(struct ehci_softc *sc) 2259 { 2260 struct ehci_soft_qh *sqh = NULL; 2261 usbd_status err; 2262 int i, offs; 2263 struct usb_dma dma; 2264 int s; 2265 2266 s = splusb(); 2267 if (sc->sc_freeqhs == NULL) { 2268 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2269 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2270 EHCI_PAGE_SIZE, &dma); 2271 if (err) 2272 goto out; 2273 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2274 offs = i * EHCI_SQH_SIZE; 2275 sqh = KERNADDR(&dma, offs); 2276 sqh->physaddr = DMAADDR(&dma, offs); 2277 sqh->dma = dma; 2278 sqh->offs = offs; 2279 sqh->next = sc->sc_freeqhs; 2280 sc->sc_freeqhs = sqh; 2281 } 2282 } 2283 sqh = sc->sc_freeqhs; 2284 sc->sc_freeqhs = sqh->next; 2285 memset(&sqh->qh, 0, sizeof(struct ehci_qh)); 2286 sqh->next = NULL; 2287 sqh->prev = NULL; 2288 2289 out: 2290 splx(s); 2291 return (sqh); 2292 } 2293 2294 void 2295 ehci_free_sqh(struct ehci_softc *sc, struct ehci_soft_qh *sqh) 2296 { 2297 int s; 2298 2299 s = splusb(); 2300 sqh->next = sc->sc_freeqhs; 2301 sc->sc_freeqhs = sqh; 2302 splx(s); 2303 } 2304 2305 struct ehci_soft_qtd * 2306 ehci_alloc_sqtd(struct ehci_softc *sc) 2307 { 2308 struct ehci_soft_qtd *sqtd = NULL; 2309 usbd_status err; 2310 int i, offs; 2311 struct usb_dma dma; 2312 int s; 2313 2314 s = splusb(); 2315 if (sc->sc_freeqtds == NULL) { 2316 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2317 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2318 EHCI_PAGE_SIZE, &dma); 2319 if (err) 2320 goto out; 2321 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2322 offs = i * EHCI_SQTD_SIZE; 2323 sqtd = KERNADDR(&dma, offs); 2324 sqtd->physaddr = DMAADDR(&dma, offs); 2325 sqtd->dma = dma; 2326 sqtd->offs = offs; 2327 sqtd->nextqtd = sc->sc_freeqtds; 2328 sc->sc_freeqtds = sqtd; 2329 } 2330 } 2331 2332 sqtd = sc->sc_freeqtds; 2333 sc->sc_freeqtds = sqtd->nextqtd; 2334 memset(&sqtd->qtd, 0, sizeof(struct ehci_qtd)); 2335 sqtd->nextqtd = NULL; 2336 2337 out: 2338 splx(s); 2339 return (sqtd); 2340 } 2341 2342 void 2343 ehci_free_sqtd(struct ehci_softc *sc, struct ehci_soft_qtd *sqtd) 2344 { 2345 int s; 2346 2347 s = splusb(); 2348 sqtd->nextqtd = sc->sc_freeqtds; 2349 sc->sc_freeqtds = sqtd; 2350 splx(s); 2351 } 2352 2353 usbd_status 2354 ehci_alloc_sqtd_chain(struct ehci_softc *sc, u_int alen, struct usbd_xfer *xfer, 2355 struct ehci_soft_qtd **sp, struct ehci_soft_qtd **ep) 2356 { 2357 struct ehci_soft_qtd *next, *cur; 2358 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2359 u_int32_t qtdstatus; 2360 u_int len, curlen; 2361 int mps, i, iscontrol, forceshort; 2362 int rd = usbd_xfer_isread(xfer); 2363 struct usb_dma *dma = &xfer->dmabuf; 2364 2365 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2366 2367 len = alen; 2368 iscontrol = (xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) == 2369 UE_CONTROL; 2370 2371 dataphys = DMAADDR(dma, 0); 2372 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2373 qtdstatus = EHCI_QTD_ACTIVE | 2374 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2375 EHCI_QTD_SET_CERR(3); /* IOC and BYTES set below */ 2376 mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize); 2377 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2378 len % mps == 0; 2379 /* 2380 * The control transfer data stage always starts with a toggle of 1. 2381 * For other transfers we let the hardware track the toggle state. 2382 */ 2383 if (iscontrol) 2384 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2385 2386 cur = ehci_alloc_sqtd(sc); 2387 *sp = cur; 2388 if (cur == NULL) 2389 goto nomem; 2390 2391 usb_syncmem(dma, 0, alen, 2392 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2393 for (;;) { 2394 dataphyspage = EHCI_PAGE(dataphys); 2395 /* The EHCI hardware can handle at most 5 pages. */ 2396 if (dataphyslastpage - dataphyspage < 2397 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2398 /* we can handle it in this QTD */ 2399 curlen = len; 2400 } else { 2401 /* must use multiple TDs, fill as much as possible. */ 2402 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2403 EHCI_PAGE_OFFSET(dataphys); 2404 #ifdef DIAGNOSTIC 2405 if (curlen > len) { 2406 printf("ehci_alloc_sqtd_chain: curlen=%u " 2407 "len=%u offs=0x%x\n", curlen, len, 2408 EHCI_PAGE_OFFSET(dataphys)); 2409 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2410 dataphyslastpage, dataphyspage, dataphys); 2411 curlen = len; 2412 } 2413 #endif 2414 /* the length must be a multiple of the max size */ 2415 curlen -= curlen % mps; 2416 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2417 "curlen=%u\n", curlen)); 2418 #ifdef DIAGNOSTIC 2419 if (curlen == 0) 2420 panic("ehci_alloc_std: curlen == 0"); 2421 #endif 2422 } 2423 2424 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2425 "dataphyslastpage=0x%08x len=%u curlen=%u\n", 2426 dataphys, dataphyslastpage, len, curlen)); 2427 len -= curlen; 2428 2429 /* 2430 * Allocate another transfer if there's more data left, 2431 * or if force last short transfer flag is set and we're 2432 * allocating a multiple of the max packet size. 2433 */ 2434 if (len != 0 || forceshort) { 2435 next = ehci_alloc_sqtd(sc); 2436 if (next == NULL) 2437 goto nomem; 2438 nextphys = htole32(next->physaddr); 2439 } else { 2440 next = NULL; 2441 nextphys = htole32(EHCI_LINK_TERMINATE); 2442 } 2443 2444 for (i = 0; i * EHCI_PAGE_SIZE < 2445 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2446 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2447 if (i != 0) /* use offset only in first buffer */ 2448 a = EHCI_PAGE(a); 2449 #ifdef DIAGNOSTIC 2450 if (i >= EHCI_QTD_NBUFFERS) { 2451 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2452 goto nomem; 2453 } 2454 #endif 2455 cur->qtd.qtd_buffer[i] = htole32(a); 2456 cur->qtd.qtd_buffer_hi[i] = 0; 2457 } 2458 cur->nextqtd = next; 2459 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2460 cur->qtd.qtd_status = htole32(qtdstatus | 2461 EHCI_QTD_SET_BYTES(curlen)); 2462 cur->len = curlen; 2463 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2464 dataphys, dataphys + curlen)); 2465 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%u\n", curlen)); 2466 if (iscontrol) { 2467 /* 2468 * adjust the toggle based on the number of packets 2469 * in this qtd 2470 */ 2471 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2472 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2473 } 2474 if (len == 0) { 2475 if (! forceshort) 2476 break; 2477 forceshort = 0; 2478 } 2479 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2480 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2481 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2482 dataphys += curlen; 2483 cur = next; 2484 } 2485 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2486 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2487 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2488 *ep = cur; 2489 2490 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2491 *sp, *ep)); 2492 2493 return (USBD_NORMAL_COMPLETION); 2494 2495 nomem: 2496 /* XXX free chain */ 2497 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2498 return (USBD_NOMEM); 2499 } 2500 2501 void 2502 ehci_free_sqtd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 2503 { 2504 struct ehci_pipe *epipe = (struct ehci_pipe *)ex->xfer.pipe; 2505 struct ehci_soft_qtd *sqtd, *next; 2506 2507 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p\n", ex->sqtdstart)); 2508 2509 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = next) { 2510 next = sqtd->nextqtd; 2511 ehci_free_sqtd(sc, sqtd); 2512 } 2513 ex->sqtdstart = ex->sqtdend = NULL; 2514 epipe->sqh->sqtd = NULL; 2515 } 2516 2517 struct ehci_soft_itd * 2518 ehci_alloc_itd(struct ehci_softc *sc) 2519 { 2520 struct ehci_soft_itd *itd, *freeitd; 2521 usbd_status err; 2522 int i, s, offs, frindex, previndex; 2523 struct usb_dma dma; 2524 2525 s = splusb(); 2526 2527 /* Find an itd that wasn't freed this frame or last frame. This can 2528 * discard itds that were freed before frindex wrapped around 2529 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2530 * interrupt and fiddling with list when that happens */ 2531 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2532 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2533 2534 freeitd = NULL; 2535 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2536 if (itd == NULL) 2537 break; 2538 if (itd->slot != frindex && itd->slot != previndex) { 2539 freeitd = itd; 2540 break; 2541 } 2542 } 2543 2544 if (freeitd == NULL) { 2545 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2546 EHCI_PAGE_SIZE, &dma); 2547 if (err) { 2548 splx(s); 2549 return (NULL); 2550 } 2551 2552 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2553 offs = i * EHCI_ITD_SIZE; 2554 itd = KERNADDR(&dma, offs); 2555 itd->physaddr = DMAADDR(&dma, offs); 2556 itd->dma = dma; 2557 itd->offs = offs; 2558 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2559 } 2560 freeitd = LIST_FIRST(&sc->sc_freeitds); 2561 } 2562 2563 itd = freeitd; 2564 LIST_REMOVE(itd, u.free_list); 2565 memset(&itd->itd, 0, sizeof(struct ehci_itd)); 2566 usb_syncmem(&itd->dma, itd->offs + offsetof(struct ehci_itd, itd_next), 2567 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2568 BUS_DMASYNC_PREREAD); 2569 2570 itd->u.frame_list.next = NULL; 2571 itd->u.frame_list.prev = NULL; 2572 itd->xfer_next = NULL; 2573 itd->slot = 0; 2574 splx(s); 2575 2576 return (itd); 2577 } 2578 2579 void 2580 ehci_free_itd(struct ehci_softc *sc, struct ehci_soft_itd *itd) 2581 { 2582 int s; 2583 2584 s = splusb(); 2585 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2586 splx(s); 2587 } 2588 2589 /* 2590 * Close a reqular pipe. 2591 * Assumes that there are no pending transactions. 2592 */ 2593 void 2594 ehci_close_pipe(struct usbd_pipe *pipe) 2595 { 2596 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2597 struct ehci_softc *sc = (struct ehci_softc *)pipe->device->bus; 2598 struct ehci_soft_qh *sqh = epipe->sqh; 2599 int s; 2600 2601 s = splusb(); 2602 ehci_rem_qh(sc, sqh); 2603 splx(s); 2604 pipe->endpoint->savedtoggle = 2605 EHCI_QTD_GET_TOGGLE(letoh32(sqh->qh.qh_qtd.qtd_status)); 2606 ehci_free_sqh(sc, epipe->sqh); 2607 } 2608 2609 /* 2610 * Abort a device request. 2611 * If this routine is called at splusb() it guarantees that the request 2612 * will be removed from the hardware scheduling and that the callback 2613 * for it will be called with USBD_CANCELLED status. 2614 * It's impossible to guarantee that the requested transfer will not 2615 * have happened since the hardware runs concurrently. 2616 * If the transaction has already happened we rely on the ordinary 2617 * interrupt processing to process it. 2618 */ 2619 void 2620 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2621 { 2622 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2623 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2624 struct ehci_xfer *ex = (struct ehci_xfer*)xfer; 2625 struct ehci_soft_qh *sqh = epipe->sqh; 2626 struct ehci_soft_qtd *sqtd; 2627 int s; 2628 2629 if (sc->sc_bus.dying || xfer->status == USBD_NOT_STARTED) { 2630 s = splusb(); 2631 if (xfer->status != USBD_NOT_STARTED) 2632 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2633 xfer->status = status; /* make software ignore it */ 2634 timeout_del(&xfer->timeout_handle); 2635 usb_rem_task(xfer->device, &xfer->abort_task); 2636 #ifdef DIAGNOSTIC 2637 ex->isdone = 1; 2638 #endif 2639 usb_transfer_complete(xfer); 2640 splx(s); 2641 return; 2642 } 2643 2644 if (xfer->device->bus->intr_context) 2645 panic("ehci_abort_xfer: not in process context"); 2646 2647 /* 2648 * If an abort is already in progress then just wait for it to 2649 * complete and return. 2650 */ 2651 if (ex->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2652 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2653 /* No need to wait if we're aborting from a timeout. */ 2654 if (status == USBD_TIMEOUT) 2655 return; 2656 /* Override the status which might be USBD_TIMEOUT. */ 2657 xfer->status = status; 2658 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2659 ex->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 2660 while (ex->ehci_xfer_flags & EHCI_XFER_ABORTING) 2661 tsleep(&ex->ehci_xfer_flags, PZERO, "ehciaw", 0); 2662 return; 2663 } 2664 2665 /* 2666 * Step 1: Make interrupt routine and timeouts ignore xfer. 2667 */ 2668 s = splusb(); 2669 ex->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2670 xfer->status = status; /* make software ignore it */ 2671 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2672 timeout_del(&xfer->timeout_handle); 2673 usb_rem_task(xfer->device, &xfer->abort_task); 2674 splx(s); 2675 2676 /* 2677 * Step 2: Deactivate all of the qTDs that we will be removing, 2678 * otherwise the queue head may go active again. 2679 */ 2680 usb_syncmem(&sqh->dma, 2681 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 2682 sizeof(sqh->qh.qh_qtd.qtd_status), 2683 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2684 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2685 usb_syncmem(&sqh->dma, 2686 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 2687 sizeof(sqh->qh.qh_qtd.qtd_status), 2688 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2689 2690 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) { 2691 usb_syncmem(&sqtd->dma, 2692 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 2693 sizeof(sqtd->qtd.qtd_status), 2694 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2695 sqtd->qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2696 usb_syncmem(&sqtd->dma, 2697 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 2698 sizeof(sqtd->qtd.qtd_status), 2699 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2700 } 2701 ehci_sync_hc(sc); 2702 2703 /* 2704 * Step 3: Make sure the soft interrupt routine has run. This 2705 * should remove any completed items off the queue. 2706 * The hardware has no reference to completed items (TDs). 2707 * It's safe to remove them at any time. 2708 */ 2709 s = splusb(); 2710 sc->sc_softwake = 1; 2711 usb_schedsoftintr(&sc->sc_bus); 2712 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2713 2714 #ifdef DIAGNOSTIC 2715 ex->isdone = 1; 2716 #endif 2717 /* Do the wakeup first to avoid touching the xfer after the callback. */ 2718 ex->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 2719 if (ex->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 2720 ex->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 2721 wakeup(&ex->ehci_xfer_flags); 2722 } 2723 usb_transfer_complete(xfer); 2724 2725 splx(s); 2726 } 2727 2728 void 2729 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 2730 { 2731 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2732 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2733 ehci_isoc_trans_t trans_status; 2734 struct ehci_soft_itd *itd; 2735 int i; 2736 2737 splsoftassert(IPL_SOFTUSB); 2738 2739 if (sc->sc_bus.dying || xfer->status == USBD_NOT_STARTED) { 2740 if (xfer->status != USBD_NOT_STARTED) 2741 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2742 xfer->status = status; 2743 timeout_del(&xfer->timeout_handle); 2744 usb_rem_task(xfer->device, &xfer->abort_task); 2745 usb_transfer_complete(xfer); 2746 return; 2747 } 2748 2749 /* Transfer is already done. */ 2750 if (xfer->status != USBD_IN_PROGRESS) { 2751 DPRINTF(("%s: already done \n", __func__)); 2752 return; 2753 } 2754 2755 2756 #ifdef DIAGNOSTIC 2757 ex->isdone = 1; 2758 #endif 2759 xfer->status = status; 2760 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2761 timeout_del(&xfer->timeout_handle); 2762 usb_rem_task(xfer->device, &xfer->abort_task); 2763 2764 if (xfer->device->speed == USB_SPEED_HIGH) { 2765 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 2766 usb_syncmem(&itd->dma, 2767 itd->offs + offsetof(struct ehci_itd, itd_ctl), 2768 sizeof(itd->itd.itd_ctl), 2769 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2770 2771 for (i = 0; i < 8; i++) { 2772 trans_status = le32toh(itd->itd.itd_ctl[i]); 2773 trans_status &= ~EHCI_ITD_ACTIVE; 2774 itd->itd.itd_ctl[i] = htole32(trans_status); 2775 } 2776 2777 usb_syncmem(&itd->dma, 2778 itd->offs + offsetof(struct ehci_itd, itd_ctl), 2779 sizeof(itd->itd.itd_ctl), 2780 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2781 } 2782 } else { 2783 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 2784 usb_syncmem(&itd->dma, 2785 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 2786 sizeof(itd->sitd.sitd_trans), 2787 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2788 2789 trans_status = le32toh(itd->sitd.sitd_trans); 2790 trans_status &= ~EHCI_SITD_ACTIVE; 2791 itd->sitd.sitd_trans = htole32(trans_status); 2792 2793 usb_syncmem(&itd->dma, 2794 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 2795 sizeof(itd->sitd.sitd_trans), 2796 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2797 } 2798 } 2799 2800 sc->sc_softwake = 1; 2801 usb_schedsoftintr(&sc->sc_bus); 2802 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2803 2804 usb_transfer_complete(xfer); 2805 } 2806 2807 void 2808 ehci_timeout(void *addr) 2809 { 2810 struct usbd_xfer *xfer = addr; 2811 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2812 2813 if (sc->sc_bus.dying) { 2814 ehci_timeout_task(addr); 2815 return; 2816 } 2817 2818 usb_init_task(&xfer->abort_task, ehci_timeout_task, addr, 2819 USB_TASK_TYPE_ABORT); 2820 usb_add_task(xfer->device, &xfer->abort_task); 2821 } 2822 2823 void 2824 ehci_timeout_task(void *addr) 2825 { 2826 struct usbd_xfer *xfer = addr; 2827 int s; 2828 2829 s = splusb(); 2830 ehci_abort_xfer(xfer, USBD_TIMEOUT); 2831 splx(s); 2832 } 2833 2834 /* 2835 * Some EHCI chips from VIA / ATI seem to trigger interrupts before writing 2836 * back the qTD status, or miss signalling occasionally under heavy load. 2837 * If the host machine is too fast, we can miss transaction completion - when 2838 * we scan the active list the transaction still seems to be active. This 2839 * generally exhibits itself as a umass stall that never recovers. 2840 * 2841 * We work around this behaviour by setting up this callback after any softintr 2842 * that completes with transactions still pending, giving us another chance to 2843 * check for completion after the writeback has taken place. 2844 */ 2845 void 2846 ehci_intrlist_timeout(void *arg) 2847 { 2848 struct ehci_softc *sc = arg; 2849 int s; 2850 2851 if (sc->sc_bus.dying) 2852 return; 2853 2854 s = splusb(); 2855 DPRINTFN(1, ("ehci_intrlist_timeout\n")); 2856 usb_schedsoftintr(&sc->sc_bus); 2857 splx(s); 2858 } 2859 2860 usbd_status 2861 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 2862 { 2863 usbd_status err; 2864 2865 /* Insert last in queue. */ 2866 err = usb_insert_transfer(xfer); 2867 if (err) 2868 return (err); 2869 2870 /* Pipe isn't running, start first */ 2871 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2872 } 2873 2874 usbd_status 2875 ehci_device_ctrl_start(struct usbd_xfer *xfer) 2876 { 2877 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2878 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2879 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2880 usb_device_request_t *req = &xfer->request; 2881 struct ehci_soft_qtd *setup, *stat, *next; 2882 struct ehci_soft_qh *sqh; 2883 u_int len = UGETW(req->wLength); 2884 usbd_status err; 2885 int s; 2886 2887 KASSERT(xfer->rqflags & URQ_REQUEST); 2888 2889 if (sc->sc_bus.dying) 2890 return (USBD_IOERROR); 2891 2892 setup = ehci_alloc_sqtd(sc); 2893 if (setup == NULL) { 2894 err = USBD_NOMEM; 2895 goto bad1; 2896 } 2897 stat = ehci_alloc_sqtd(sc); 2898 if (stat == NULL) { 2899 err = USBD_NOMEM; 2900 goto bad2; 2901 } 2902 2903 sqh = epipe->sqh; 2904 2905 /* Set up data transaction */ 2906 if (len != 0) { 2907 struct ehci_soft_qtd *end; 2908 2909 err = ehci_alloc_sqtd_chain(sc, len, xfer, &next, &end); 2910 if (err) 2911 goto bad3; 2912 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 2913 end->nextqtd = stat; 2914 end->qtd.qtd_next = 2915 end->qtd.qtd_altnext = htole32(stat->physaddr); 2916 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 2917 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2918 } else { 2919 next = stat; 2920 } 2921 2922 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 2923 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2924 2925 /* Clear toggle */ 2926 setup->qtd.qtd_status = htole32( 2927 EHCI_QTD_ACTIVE | 2928 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 2929 EHCI_QTD_SET_CERR(3) | 2930 EHCI_QTD_SET_TOGGLE(0) | 2931 EHCI_QTD_SET_BYTES(sizeof(*req))); 2932 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 2933 setup->qtd.qtd_buffer_hi[0] = 0; 2934 setup->nextqtd = next; 2935 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 2936 setup->len = sizeof(*req); 2937 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 2938 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2939 2940 stat->qtd.qtd_status = htole32( 2941 EHCI_QTD_ACTIVE | 2942 EHCI_QTD_SET_PID(usbd_xfer_isread(xfer) ? 2943 EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 2944 EHCI_QTD_SET_CERR(3) | 2945 EHCI_QTD_SET_TOGGLE(1) | 2946 EHCI_QTD_IOC); 2947 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 2948 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 2949 stat->nextqtd = NULL; 2950 stat->qtd.qtd_next = stat->qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 2951 stat->len = 0; 2952 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 2953 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2954 2955 ex->sqtdstart = setup; 2956 ex->sqtdend = stat; 2957 #ifdef DIAGNOSTIC 2958 if (!ex->isdone) { 2959 printf("%s: not done, ex=%p\n", __func__, ex); 2960 } 2961 ex->isdone = 0; 2962 #endif 2963 2964 /* Insert qTD in QH list. */ 2965 s = splusb(); 2966 ehci_set_qh_qtd(sqh, setup); 2967 if (xfer->timeout && !sc->sc_bus.use_polling) { 2968 timeout_del(&xfer->timeout_handle); 2969 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 2970 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 2971 } 2972 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 2973 xfer->status = USBD_IN_PROGRESS; 2974 splx(s); 2975 2976 if (sc->sc_bus.use_polling) 2977 ehci_waitintr(sc, xfer); 2978 2979 return (USBD_IN_PROGRESS); 2980 2981 bad3: 2982 ehci_free_sqtd(sc, stat); 2983 bad2: 2984 ehci_free_sqtd(sc, setup); 2985 bad1: 2986 xfer->status = err; 2987 usb_transfer_complete(xfer); 2988 return (err); 2989 } 2990 2991 void 2992 ehci_device_ctrl_done(struct usbd_xfer *xfer) 2993 { 2994 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2995 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2996 2997 KASSERT(xfer->rqflags & URQ_REQUEST); 2998 2999 if (xfer->status != USBD_NOMEM) { 3000 ehci_free_sqtd_chain(sc, ex); 3001 } 3002 } 3003 3004 void 3005 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3006 { 3007 ehci_abort_xfer(xfer, USBD_CANCELLED); 3008 } 3009 3010 void 3011 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3012 { 3013 ehci_close_pipe(pipe); 3014 } 3015 3016 usbd_status 3017 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3018 { 3019 usbd_status err; 3020 3021 /* Insert last in queue. */ 3022 err = usb_insert_transfer(xfer); 3023 if (err) 3024 return (err); 3025 3026 /* Pipe isn't running, start first */ 3027 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3028 } 3029 3030 usbd_status 3031 ehci_device_bulk_start(struct usbd_xfer *xfer) 3032 { 3033 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3034 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3035 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3036 struct ehci_soft_qtd *data, *dataend; 3037 struct ehci_soft_qh *sqh; 3038 usbd_status err; 3039 int s; 3040 3041 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3042 3043 if (sc->sc_bus.dying) 3044 return (USBD_IOERROR); 3045 3046 sqh = epipe->sqh; 3047 3048 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3049 if (err) { 3050 xfer->status = err; 3051 usb_transfer_complete(xfer); 3052 return (err); 3053 } 3054 3055 /* Set up interrupt info. */ 3056 ex->sqtdstart = data; 3057 ex->sqtdend = dataend; 3058 #ifdef DIAGNOSTIC 3059 if (!ex->isdone) { 3060 printf("ehci_device_bulk_start: not done, ex=%p\n", ex); 3061 } 3062 ex->isdone = 0; 3063 #endif 3064 3065 s = splusb(); 3066 ehci_set_qh_qtd(sqh, data); 3067 if (xfer->timeout && !sc->sc_bus.use_polling) { 3068 timeout_del(&xfer->timeout_handle); 3069 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3070 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3071 } 3072 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3073 xfer->status = USBD_IN_PROGRESS; 3074 splx(s); 3075 3076 if (sc->sc_bus.use_polling) 3077 ehci_waitintr(sc, xfer); 3078 3079 return (USBD_IN_PROGRESS); 3080 } 3081 3082 void 3083 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3084 { 3085 ehci_abort_xfer(xfer, USBD_CANCELLED); 3086 } 3087 3088 /* 3089 * Close a device bulk pipe. 3090 */ 3091 void 3092 ehci_device_bulk_close(struct usbd_pipe *pipe) 3093 { 3094 ehci_close_pipe(pipe); 3095 } 3096 3097 void 3098 ehci_device_bulk_done(struct usbd_xfer *xfer) 3099 { 3100 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3101 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3102 3103 if (xfer->status != USBD_NOMEM) { 3104 ehci_free_sqtd_chain(sc, ex); 3105 } 3106 } 3107 3108 usbd_status 3109 ehci_device_setintr(struct ehci_softc *sc, struct ehci_soft_qh *sqh, int ival) 3110 { 3111 struct ehci_soft_islot *isp; 3112 int islot, lev; 3113 3114 /* Find a poll rate that is large enough. */ 3115 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3116 if (EHCI_ILEV_IVAL(lev) <= ival) 3117 break; 3118 3119 /* Pick an interrupt slot at the right level. */ 3120 /* XXX could do better than picking at random */ 3121 islot = EHCI_IQHIDX(lev, arc4random()); 3122 3123 sqh->islot = islot; 3124 isp = &sc->sc_islots[islot]; 3125 ehci_add_qh(sqh, isp->sqh); 3126 3127 return (USBD_NORMAL_COMPLETION); 3128 } 3129 3130 usbd_status 3131 ehci_device_intr_transfer(struct usbd_xfer *xfer) 3132 { 3133 usbd_status err; 3134 3135 /* Insert last in queue. */ 3136 err = usb_insert_transfer(xfer); 3137 if (err) 3138 return (err); 3139 3140 /* 3141 * Pipe isn't running (otherwise err would be USBD_INPROG), 3142 * so start it first. 3143 */ 3144 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3145 } 3146 3147 usbd_status 3148 ehci_device_intr_start(struct usbd_xfer *xfer) 3149 { 3150 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3151 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3152 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3153 struct ehci_soft_qtd *data, *dataend; 3154 struct ehci_soft_qh *sqh; 3155 usbd_status err; 3156 int s; 3157 3158 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3159 3160 if (sc->sc_bus.dying) 3161 return (USBD_IOERROR); 3162 3163 sqh = epipe->sqh; 3164 3165 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3166 if (err) { 3167 xfer->status = err; 3168 usb_transfer_complete(xfer); 3169 return (err); 3170 } 3171 3172 /* Set up interrupt info. */ 3173 ex->sqtdstart = data; 3174 ex->sqtdend = dataend; 3175 #ifdef DIAGNOSTIC 3176 if (!ex->isdone) 3177 printf("ehci_device_intr_start: not done, ex=%p\n", ex); 3178 ex->isdone = 0; 3179 #endif 3180 3181 s = splusb(); 3182 ehci_set_qh_qtd(sqh, data); 3183 if (xfer->timeout && !sc->sc_bus.use_polling) { 3184 timeout_del(&xfer->timeout_handle); 3185 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3186 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3187 } 3188 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3189 xfer->status = USBD_IN_PROGRESS; 3190 splx(s); 3191 3192 if (sc->sc_bus.use_polling) 3193 ehci_waitintr(sc, xfer); 3194 3195 return (USBD_IN_PROGRESS); 3196 } 3197 3198 void 3199 ehci_device_intr_abort(struct usbd_xfer *xfer) 3200 { 3201 KASSERT(!xfer->pipe->repeat || xfer->pipe->intrxfer == xfer); 3202 3203 /* 3204 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3205 * async doorbell. That's dependant on the async list, wheras 3206 * intr xfers are periodic, should not use this? 3207 */ 3208 ehci_abort_xfer(xfer, USBD_CANCELLED); 3209 } 3210 3211 void 3212 ehci_device_intr_close(struct usbd_pipe *pipe) 3213 { 3214 ehci_close_pipe(pipe); 3215 } 3216 3217 void 3218 ehci_device_intr_done(struct usbd_xfer *xfer) 3219 { 3220 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3221 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3222 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3223 struct ehci_soft_qtd *data, *dataend; 3224 struct ehci_soft_qh *sqh; 3225 usbd_status err; 3226 int s; 3227 3228 if (xfer->pipe->repeat) { 3229 ehci_free_sqtd_chain(sc, ex); 3230 3231 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3232 usbd_xfer_isread(xfer) ? 3233 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3234 sqh = epipe->sqh; 3235 3236 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3237 if (err) { 3238 xfer->status = err; 3239 return; 3240 } 3241 3242 /* Set up interrupt info. */ 3243 ex->sqtdstart = data; 3244 ex->sqtdend = dataend; 3245 #ifdef DIAGNOSTIC 3246 if (!ex->isdone) { 3247 printf("ehci_device_intr_done: not done, ex=%p\n", 3248 ex); 3249 } 3250 ex->isdone = 0; 3251 #endif 3252 3253 s = splusb(); 3254 ehci_set_qh_qtd(sqh, data); 3255 if (xfer->timeout && !sc->sc_bus.use_polling) { 3256 timeout_del(&xfer->timeout_handle); 3257 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3258 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3259 } 3260 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3261 xfer->status = USBD_IN_PROGRESS; 3262 splx(s); 3263 } else if (xfer->status != USBD_NOMEM) { 3264 ehci_free_sqtd_chain(sc, ex); 3265 } 3266 } 3267 3268 usbd_status 3269 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 3270 { 3271 usbd_status err; 3272 3273 err = usb_insert_transfer(xfer); 3274 if (err && err != USBD_IN_PROGRESS) 3275 return (err); 3276 3277 return (ehci_device_isoc_start(xfer)); 3278 } 3279 3280 usbd_status 3281 ehci_device_isoc_start(struct usbd_xfer *xfer) 3282 { 3283 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3284 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3285 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3286 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3287 uint8_t ival = ed->bInterval; 3288 struct ehci_soft_itd *itd; 3289 int s, frindex; 3290 uint32_t link; 3291 3292 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3293 KASSERT(ival > 0 && ival <= 16); 3294 3295 /* 3296 * To allow continuous transfers, above we start all transfers 3297 * immediately. However, we're still going to get usbd_start_next call 3298 * this when another xfer completes. So, check if this is already 3299 * in progress or not 3300 */ 3301 if (ex->itdstart != NULL) 3302 return (USBD_IN_PROGRESS); 3303 3304 if (sc->sc_bus.dying) 3305 return (USBD_IOERROR); 3306 3307 /* Why would you do that anyway? */ 3308 if (sc->sc_bus.use_polling) 3309 return (USBD_INVAL); 3310 3311 /* 3312 * To avoid complication, don't allow a request right now that'll span 3313 * the entire frame table. To within 4 frames, to allow some leeway 3314 * on either side of where the hc currently is. 3315 */ 3316 if ((1 << (ival - 1)) * xfer->nframes >= (sc->sc_flsize - 4) * 8) 3317 return (USBD_INVAL); 3318 3319 /* 3320 * Step 1: Allocate and initialize itds. 3321 */ 3322 if (xfer->device->speed == USB_SPEED_HIGH) { 3323 if (ehci_alloc_itd_chain(sc, xfer)) 3324 return (USBD_INVAL); 3325 3326 link = EHCI_LINK_ITD; 3327 } else { 3328 if (ehci_alloc_sitd_chain(sc, xfer)) 3329 return (USBD_INVAL); 3330 3331 link = EHCI_LINK_SITD; 3332 } 3333 3334 #ifdef DIAGNOSTIC 3335 if (!ex->isdone) { 3336 printf("%s: not done, ex=%p\n", __func__, ex); 3337 } 3338 ex->isdone = 0; 3339 #endif 3340 3341 /* 3342 * Part 2: Transfer descriptors have now been set up, now they must 3343 * be scheduled into the period frame list. Erk. Not wanting to 3344 * complicate matters, transfer is denied if the transfer spans 3345 * more than the period frame list. 3346 */ 3347 s = splusb(); 3348 3349 /* Start inserting frames */ 3350 if (epipe->u.isoc.cur_xfers > 0) { 3351 frindex = epipe->u.isoc.next_frame; 3352 } else { 3353 frindex = EOREAD4(sc, EHCI_FRINDEX); 3354 frindex = frindex >> 3; /* Erase microframe index */ 3355 frindex += 2; 3356 } 3357 3358 if (frindex >= sc->sc_flsize) 3359 frindex &= (sc->sc_flsize - 1); 3360 3361 /* What's the frame interval? */ 3362 ival = (1 << (ival - 1)); 3363 if (ival / 8 == 0) 3364 ival = 1; 3365 else 3366 ival /= 8; 3367 3368 /* Abuse the fact that itd_next == sitd_next. */ 3369 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 3370 itd->itd.itd_next = sc->sc_flist[frindex]; 3371 if (itd->itd.itd_next == 0) 3372 itd->itd.itd_next = htole32(EHCI_LINK_TERMINATE); 3373 3374 sc->sc_flist[frindex] = htole32(link | itd->physaddr); 3375 itd->u.frame_list.next = sc->sc_softitds[frindex]; 3376 sc->sc_softitds[frindex] = itd; 3377 if (itd->u.frame_list.next != NULL) 3378 itd->u.frame_list.next->u.frame_list.prev = itd; 3379 itd->slot = frindex; 3380 itd->u.frame_list.prev = NULL; 3381 3382 frindex += ival; 3383 if (frindex >= sc->sc_flsize) 3384 frindex -= sc->sc_flsize; 3385 } 3386 3387 epipe->u.isoc.cur_xfers++; 3388 epipe->u.isoc.next_frame = frindex; 3389 3390 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3391 xfer->status = USBD_IN_PROGRESS; 3392 xfer->done = 0; 3393 splx(s); 3394 3395 return (USBD_IN_PROGRESS); 3396 } 3397 3398 int 3399 ehci_alloc_itd_chain(struct ehci_softc *sc, struct usbd_xfer *xfer) 3400 { 3401 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3402 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3403 const uint32_t mps = UGETW(ed->wMaxPacketSize); 3404 struct ehci_soft_itd *itd = NULL, *pitd = NULL; 3405 int i, j, nframes, uframes, ufrperframe; 3406 int offs = 0, trans_count = 0; 3407 3408 /* 3409 * How many itds do we need? One per transfer if interval >= 8 3410 * microframes, fewer if we use multiple microframes per frame. 3411 */ 3412 switch (ed->bInterval) { 3413 case 1: 3414 ufrperframe = 8; 3415 break; 3416 case 2: 3417 ufrperframe = 4; 3418 break; 3419 case 3: 3420 ufrperframe = 2; 3421 break; 3422 default: 3423 ufrperframe = 1; 3424 break; 3425 } 3426 nframes = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3427 uframes = 8 / ufrperframe; 3428 if (nframes == 0) 3429 return (1); 3430 3431 for (i = 0; i < nframes; i++) { 3432 uint32_t froffs = offs; 3433 3434 itd = ehci_alloc_itd(sc); 3435 if (itd == NULL) { 3436 ehci_free_itd_chain(sc, ex); 3437 return (1); 3438 } 3439 3440 if (pitd != NULL) 3441 pitd->xfer_next = itd; 3442 else 3443 ex->itdstart = itd; 3444 3445 /* 3446 * Step 1.5, initialize uframes 3447 */ 3448 for (j = 0; j < 8; j += uframes) { 3449 /* Calculate which page in the list this starts in */ 3450 int addr = DMAADDR(&xfer->dmabuf, froffs); 3451 addr = EHCI_PAGE_OFFSET(addr) + (offs - froffs); 3452 addr = EHCI_PAGE(addr) / EHCI_PAGE_SIZE; 3453 3454 /* This gets the initial offset into the first page, 3455 * looks how far further along the current uframe 3456 * offset is. Works out how many pages that is. 3457 */ 3458 itd->itd.itd_ctl[j] = htole32( 3459 EHCI_ITD_ACTIVE | 3460 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3461 EHCI_ITD_SET_PG(addr) | 3462 EHCI_ITD_SET_OFFS(DMAADDR(&xfer->dmabuf, offs)) 3463 ); 3464 3465 offs += xfer->frlengths[trans_count]; 3466 trans_count++; 3467 3468 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3469 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3470 break; 3471 } 3472 } 3473 3474 /* Step 1.75, set buffer pointers. To simplify matters, all 3475 * pointers are filled out for the next 7 hardware pages in 3476 * the dma block, so no need to worry what pages to cover 3477 * and what to not. 3478 */ 3479 3480 for (j = 0; j < 7; j++) { 3481 /* 3482 * Don't try to lookup a page that's past the end 3483 * of buffer 3484 */ 3485 int page_offs = EHCI_PAGE(froffs + 3486 (EHCI_PAGE_SIZE * j)); 3487 3488 if (page_offs >= xfer->dmabuf.block->size) 3489 break; 3490 3491 long long page = DMAADDR(&xfer->dmabuf, page_offs); 3492 page = EHCI_PAGE(page); 3493 itd->itd.itd_bufr[j] = htole32(page); 3494 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 3495 } 3496 3497 /* 3498 * Other special values 3499 */ 3500 itd->itd.itd_bufr[0] |= htole32( 3501 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 3502 EHCI_ITD_SET_DADDR(xfer->pipe->device->address) 3503 ); 3504 3505 itd->itd.itd_bufr[1] |= htole32( 3506 (usbd_xfer_isread(xfer) ? EHCI_ITD_SET_DIR(1) : 0) | 3507 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(mps)) 3508 ); 3509 /* FIXME: handle invalid trans */ 3510 itd->itd.itd_bufr[2] |= htole32( 3511 EHCI_ITD_SET_MULTI(UE_GET_TRANS(mps)+1) 3512 ); 3513 3514 pitd = itd; 3515 } 3516 3517 ex->itdend = itd; 3518 3519 return (0); 3520 } 3521 3522 int 3523 ehci_alloc_sitd_chain(struct ehci_softc *sc, struct usbd_xfer *xfer) 3524 { 3525 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3526 struct usbd_device *hshub = xfer->device->myhsport->parent; 3527 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3528 struct ehci_soft_itd *itd = NULL, *pitd = NULL; 3529 uint8_t smask, cmask, tp, uf; 3530 int i, nframes, offs = 0; 3531 uint32_t endp; 3532 3533 nframes = xfer->nframes; 3534 if (nframes == 0) 3535 return (1); 3536 3537 endp = EHCI_SITD_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 3538 EHCI_SITD_SET_ADDR(xfer->device->address) | 3539 EHCI_SITD_SET_PORT(xfer->device->myhsport->portno) | 3540 EHCI_SITD_SET_HUBA(hshub->address); 3541 3542 if (usbd_xfer_isread(xfer)) 3543 endp |= EHCI_SITD_SET_DIR(1); 3544 3545 for (i = 0; i < nframes; i++) { 3546 uint32_t addr = DMAADDR(&xfer->dmabuf, offs); 3547 uint32_t page = EHCI_PAGE(addr + xfer->frlengths[i] - 1); 3548 3549 itd = ehci_alloc_itd(sc); 3550 if (itd == NULL) { 3551 ehci_free_itd_chain(sc, ex); 3552 return (1); 3553 } 3554 if (pitd) 3555 pitd->xfer_next = itd; 3556 else 3557 ex->itdstart = itd; 3558 3559 itd->sitd.sitd_endp = htole32(endp); 3560 itd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 3561 itd->sitd.sitd_trans = htole32( 3562 EHCI_SITD_ACTIVE | 3563 EHCI_SITD_SET_LEN(xfer->frlengths[i]) | 3564 ((i == nframes - 1) ? EHCI_SITD_IOC : 0) 3565 ); 3566 3567 uf = max(1, ((xfer->frlengths[i] + 187) / 188)); 3568 3569 /* 3570 * Since we do not yet budget and schedule micro-frames 3571 * we assume there is no other transfer using the same 3572 * TT. 3573 */ 3574 if (usbd_xfer_isread(xfer)) { 3575 smask = 0x01; 3576 cmask = ((1 << (uf + 2)) - 1) << 2; 3577 } else { 3578 /* Is the payload is greater than 188 bytes? */ 3579 if (uf == 1) 3580 tp = EHCI_SITD_TP_ALL; 3581 else 3582 tp = EHCI_SITD_TP_BEGIN; 3583 3584 page |= EHCI_SITD_SET_TCOUNT(uf) | EHCI_SITD_SET_TP(tp); 3585 smask = (1 << uf) - 1; 3586 cmask = 0x00; 3587 } 3588 3589 itd->sitd.sitd_sched = htole32( 3590 EHCI_SITD_SET_SMASK(smask) | EHCI_SITD_SET_CMASK(cmask) 3591 ); 3592 itd->sitd.sitd_bufr[0] = htole32(addr); 3593 itd->sitd.sitd_bufr[1] = htole32(page); 3594 3595 offs += xfer->frlengths[i]; 3596 pitd = itd; 3597 } 3598 3599 ex->itdend = itd; 3600 3601 return (0); 3602 } 3603 3604 void 3605 ehci_device_isoc_abort(struct usbd_xfer *xfer) 3606 { 3607 int s; 3608 3609 s = splusb(); 3610 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 3611 splx(s); 3612 } 3613 3614 void 3615 ehci_device_isoc_close(struct usbd_pipe *pipe) 3616 { 3617 } 3618 3619 void 3620 ehci_device_isoc_done(struct usbd_xfer *xfer) 3621 { 3622 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3623 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3624 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3625 int s; 3626 3627 s = splusb(); 3628 epipe->u.isoc.cur_xfers--; 3629 if (xfer->status != USBD_NOMEM) { 3630 ehci_rem_itd_chain(sc, ex); 3631 ehci_free_itd_chain(sc, ex); 3632 } 3633 splx(s); 3634 } 3635