1 /* $OpenBSD: ehci.c,v 1.201 2019/01/08 13:49:47 uaa Exp $ */ 2 /* $NetBSD: ehci.c,v 1.66 2004/06/30 03:11:56 mycroft Exp $ */ 3 4 /* 5 * Copyright (c) 2014-2015 Martin Pieuchot 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 /* 20 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 21 * All rights reserved. 22 * 23 * This code is derived from software contributed to The NetBSD Foundation 24 * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and 25 * Jeremy Morse (jeremy.morse@gmail.com). 26 * 27 * Redistribution and use in source and binary forms, with or without 28 * modification, are permitted provided that the following conditions 29 * are met: 30 * 1. Redistributions of source code must retain the above copyright 31 * notice, this list of conditions and the following disclaimer. 32 * 2. Redistributions in binary form must reproduce the above copyright 33 * notice, this list of conditions and the following disclaimer in the 34 * documentation and/or other materials provided with the distribution. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 37 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 38 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 39 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 40 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 41 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 42 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 43 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 44 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 45 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 46 * POSSIBILITY OF SUCH DAMAGE. 47 */ 48 49 /* 50 * TODO: 51 * 1) The hub driver needs to handle and schedule the transaction translator, 52 * to assign place in frame where different devices get to go. See chapter 53 * on hubs in USB 2.0 for details. 54 * 55 * 2) Command failures are not recovered correctly. 56 */ 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/kernel.h> 61 #include <sys/rwlock.h> 62 #include <sys/malloc.h> 63 #include <sys/device.h> 64 #include <sys/queue.h> 65 #include <sys/timeout.h> 66 #include <sys/pool.h> 67 #include <sys/endian.h> 68 #include <sys/atomic.h> 69 70 #include <machine/bus.h> 71 72 #include <dev/usb/usb.h> 73 #include <dev/usb/usbdi.h> 74 #include <dev/usb/usbdivar.h> 75 #include <dev/usb/usb_mem.h> 76 77 #include <dev/usb/ehcireg.h> 78 #include <dev/usb/ehcivar.h> 79 80 struct cfdriver ehci_cd = { 81 NULL, "ehci", DV_DULL 82 }; 83 84 #ifdef EHCI_DEBUG 85 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 86 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 87 int ehcidebug = 0; 88 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 89 #else 90 #define DPRINTF(x) 91 #define DPRINTFN(n,x) 92 #endif 93 94 struct pool *ehcixfer; 95 96 struct ehci_pipe { 97 struct usbd_pipe pipe; 98 99 struct ehci_soft_qh *sqh; 100 union { 101 /* Control pipe */ 102 struct { 103 struct usb_dma reqdma; 104 } ctl; 105 /* Iso pipe */ 106 struct { 107 u_int next_frame; 108 u_int cur_xfers; 109 } isoc; 110 } u; 111 }; 112 113 u_int8_t ehci_reverse_bits(u_int8_t, int); 114 115 usbd_status ehci_open(struct usbd_pipe *); 116 int ehci_setaddr(struct usbd_device *, int); 117 void ehci_poll(struct usbd_bus *); 118 void ehci_softintr(void *); 119 int ehci_intr1(struct ehci_softc *); 120 void ehci_check_intr(struct ehci_softc *, struct usbd_xfer *); 121 void ehci_check_qh_intr(struct ehci_softc *, struct usbd_xfer *); 122 void ehci_check_itd_intr(struct ehci_softc *, struct usbd_xfer *); 123 void ehci_idone(struct usbd_xfer *); 124 void ehci_isoc_idone(struct usbd_xfer *); 125 void ehci_timeout(void *); 126 void ehci_timeout_task(void *); 127 void ehci_intrlist_timeout(void *); 128 129 struct usbd_xfer *ehci_allocx(struct usbd_bus *); 130 void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 131 132 usbd_status ehci_root_ctrl_transfer(struct usbd_xfer *); 133 usbd_status ehci_root_ctrl_start(struct usbd_xfer *); 134 void ehci_root_ctrl_abort(struct usbd_xfer *); 135 void ehci_root_ctrl_close(struct usbd_pipe *); 136 void ehci_root_ctrl_done(struct usbd_xfer *); 137 138 usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 139 usbd_status ehci_root_intr_start(struct usbd_xfer *); 140 void ehci_root_intr_abort(struct usbd_xfer *); 141 void ehci_root_intr_close(struct usbd_pipe *); 142 void ehci_root_intr_done(struct usbd_xfer *); 143 144 usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 145 usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 146 void ehci_device_ctrl_abort(struct usbd_xfer *); 147 void ehci_device_ctrl_close(struct usbd_pipe *); 148 void ehci_device_ctrl_done(struct usbd_xfer *); 149 150 usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 151 usbd_status ehci_device_bulk_start(struct usbd_xfer *); 152 void ehci_device_bulk_abort(struct usbd_xfer *); 153 void ehci_device_bulk_close(struct usbd_pipe *); 154 void ehci_device_bulk_done(struct usbd_xfer *); 155 156 usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 157 usbd_status ehci_device_intr_start(struct usbd_xfer *); 158 void ehci_device_intr_abort(struct usbd_xfer *); 159 void ehci_device_intr_close(struct usbd_pipe *); 160 void ehci_device_intr_done(struct usbd_xfer *); 161 162 usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 163 usbd_status ehci_device_isoc_start(struct usbd_xfer *); 164 void ehci_device_isoc_abort(struct usbd_xfer *); 165 void ehci_device_isoc_close(struct usbd_pipe *); 166 void ehci_device_isoc_done(struct usbd_xfer *); 167 168 void ehci_device_clear_toggle(struct usbd_pipe *pipe); 169 170 void ehci_pcd(struct ehci_softc *, struct usbd_xfer *); 171 void ehci_disown(struct ehci_softc *, int, int); 172 173 struct ehci_soft_qh *ehci_alloc_sqh(struct ehci_softc *); 174 void ehci_free_sqh(struct ehci_softc *, struct ehci_soft_qh *); 175 176 struct ehci_soft_qtd *ehci_alloc_sqtd(struct ehci_softc *); 177 void ehci_free_sqtd(struct ehci_softc *, struct ehci_soft_qtd *); 178 usbd_status ehci_alloc_sqtd_chain(struct ehci_softc *, u_int, 179 struct usbd_xfer *, struct ehci_soft_qtd **, struct ehci_soft_qtd **); 180 void ehci_free_sqtd_chain(struct ehci_softc *, struct ehci_xfer *); 181 182 struct ehci_soft_itd *ehci_alloc_itd(struct ehci_softc *); 183 void ehci_free_itd(struct ehci_softc *, struct ehci_soft_itd *); 184 void ehci_rem_itd_chain(struct ehci_softc *, struct ehci_xfer *); 185 void ehci_free_itd_chain(struct ehci_softc *, struct ehci_xfer *); 186 int ehci_alloc_itd_chain(struct ehci_softc *, struct usbd_xfer *); 187 int ehci_alloc_sitd_chain(struct ehci_softc *, struct usbd_xfer *); 188 void ehci_abort_isoc_xfer(struct usbd_xfer *xfer, 189 usbd_status status); 190 191 usbd_status ehci_device_setintr(struct ehci_softc *, struct ehci_soft_qh *, 192 int ival); 193 194 void ehci_add_qh(struct ehci_soft_qh *, struct ehci_soft_qh *); 195 void ehci_rem_qh(struct ehci_softc *, struct ehci_soft_qh *); 196 void ehci_set_qh_qtd(struct ehci_soft_qh *, struct ehci_soft_qtd *); 197 void ehci_sync_hc(struct ehci_softc *); 198 199 void ehci_close_pipe(struct usbd_pipe *); 200 void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 201 202 #ifdef EHCI_DEBUG 203 void ehci_dump_regs(struct ehci_softc *); 204 void ehci_dump(void); 205 struct ehci_softc *theehci; 206 void ehci_dump_link(ehci_link_t, int); 207 void ehci_dump_sqtds(struct ehci_soft_qtd *); 208 void ehci_dump_sqtd(struct ehci_soft_qtd *); 209 void ehci_dump_qtd(struct ehci_qtd *); 210 void ehci_dump_sqh(struct ehci_soft_qh *); 211 #if notyet 212 void ehci_dump_itd(struct ehci_soft_itd *); 213 #endif 214 #ifdef DIAGNOSTIC 215 void ehci_dump_exfer(struct ehci_xfer *); 216 #endif 217 #endif 218 219 #define EHCI_INTR_ENDPT 1 220 221 struct usbd_bus_methods ehci_bus_methods = { 222 .open_pipe = ehci_open, 223 .dev_setaddr = ehci_setaddr, 224 .soft_intr = ehci_softintr, 225 .do_poll = ehci_poll, 226 .allocx = ehci_allocx, 227 .freex = ehci_freex, 228 }; 229 230 struct usbd_pipe_methods ehci_root_ctrl_methods = { 231 .transfer = ehci_root_ctrl_transfer, 232 .start = ehci_root_ctrl_start, 233 .abort = ehci_root_ctrl_abort, 234 .close = ehci_root_ctrl_close, 235 .done = ehci_root_ctrl_done, 236 }; 237 238 struct usbd_pipe_methods ehci_root_intr_methods = { 239 .transfer = ehci_root_intr_transfer, 240 .start = ehci_root_intr_start, 241 .abort = ehci_root_intr_abort, 242 .close = ehci_root_intr_close, 243 .done = ehci_root_intr_done, 244 }; 245 246 struct usbd_pipe_methods ehci_device_ctrl_methods = { 247 .transfer = ehci_device_ctrl_transfer, 248 .start = ehci_device_ctrl_start, 249 .abort = ehci_device_ctrl_abort, 250 .close = ehci_device_ctrl_close, 251 .done = ehci_device_ctrl_done, 252 }; 253 254 struct usbd_pipe_methods ehci_device_intr_methods = { 255 .transfer = ehci_device_intr_transfer, 256 .start = ehci_device_intr_start, 257 .abort = ehci_device_intr_abort, 258 .close = ehci_device_intr_close, 259 .cleartoggle = ehci_device_clear_toggle, 260 .done = ehci_device_intr_done, 261 }; 262 263 struct usbd_pipe_methods ehci_device_bulk_methods = { 264 .transfer = ehci_device_bulk_transfer, 265 .start = ehci_device_bulk_start, 266 .abort = ehci_device_bulk_abort, 267 .close = ehci_device_bulk_close, 268 .cleartoggle = ehci_device_clear_toggle, 269 .done = ehci_device_bulk_done, 270 }; 271 272 struct usbd_pipe_methods ehci_device_isoc_methods = { 273 .transfer = ehci_device_isoc_transfer, 274 .start = ehci_device_isoc_start, 275 .abort = ehci_device_isoc_abort, 276 .close = ehci_device_isoc_close, 277 .done = ehci_device_isoc_done, 278 }; 279 280 /* 281 * Reverse a number with nbits bits. Used to evenly distribute lower-level 282 * interrupt heads in the periodic schedule. 283 * Suitable for use with EHCI_IPOLLRATES <= 9. 284 */ 285 u_int8_t 286 ehci_reverse_bits(u_int8_t c, int nbits) 287 { 288 c = ((c >> 1) & 0x55) | ((c << 1) & 0xaa); 289 c = ((c >> 2) & 0x33) | ((c << 2) & 0xcc); 290 c = ((c >> 4) & 0x0f) | ((c << 4) & 0xf0); 291 292 return c >> (8 - nbits); 293 } 294 295 usbd_status 296 ehci_init(struct ehci_softc *sc) 297 { 298 u_int32_t sparams, cparams, hcr; 299 u_int i, j; 300 usbd_status err; 301 struct ehci_soft_qh *sqh; 302 303 #ifdef EHCI_DEBUG 304 u_int32_t vers; 305 theehci = sc; 306 307 DPRINTF(("ehci_init: start\n")); 308 309 vers = EREAD2(sc, EHCI_HCIVERSION); 310 DPRINTF(("%s: EHCI version %x.%x\n", sc->sc_bus.bdev.dv_xname, 311 vers >> 8, vers & 0xff)); 312 #endif 313 314 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 315 316 sparams = EREAD4(sc, EHCI_HCSPARAMS); 317 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 318 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 319 cparams = EREAD4(sc, EHCI_HCCPARAMS); 320 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 321 322 /* MUST clear segment register if 64 bit capable. */ 323 if (EHCI_HCC_64BIT(cparams)) 324 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 325 326 sc->sc_bus.usbrev = USBREV_2_0; 327 328 DPRINTF(("%s: resetting\n", sc->sc_bus.bdev.dv_xname)); 329 err = ehci_reset(sc); 330 if (err) 331 return (err); 332 333 if (ehcixfer == NULL) { 334 ehcixfer = malloc(sizeof(struct pool), M_DEVBUF, M_NOWAIT); 335 if (ehcixfer == NULL) { 336 printf("%s: unable to allocate pool descriptor\n", 337 sc->sc_bus.bdev.dv_xname); 338 return (ENOMEM); 339 } 340 pool_init(ehcixfer, sizeof(struct ehci_xfer), 0, IPL_SOFTUSB, 341 0, "ehcixfer", NULL); 342 } 343 344 /* frame list size at default, read back what we got and use that */ 345 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 346 case 0: 347 sc->sc_flsize = 1024; 348 break; 349 case 1: 350 sc->sc_flsize = 512; 351 break; 352 case 2: 353 sc->sc_flsize = 256; 354 break; 355 case 3: 356 return (USBD_IOERROR); 357 } 358 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 359 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 360 if (err) 361 return (err); 362 DPRINTF(("%s: flsize=%d\n", sc->sc_bus.bdev.dv_xname,sc->sc_flsize)); 363 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 364 365 for (i = 0; i < sc->sc_flsize; i++) 366 sc->sc_flist[i] = htole32(EHCI_LINK_TERMINATE); 367 368 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 369 370 sc->sc_softitds = mallocarray(sc->sc_flsize, 371 sizeof(struct ehci_soft_itd *), M_USB, M_NOWAIT | M_ZERO); 372 if (sc->sc_softitds == NULL) { 373 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 374 return (ENOMEM); 375 } 376 LIST_INIT(&sc->sc_freeitds); 377 TAILQ_INIT(&sc->sc_intrhead); 378 379 /* Set up the bus struct. */ 380 sc->sc_bus.methods = &ehci_bus_methods; 381 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 382 383 sc->sc_eintrs = EHCI_NORMAL_INTRS; 384 385 /* 386 * Allocate the interrupt dummy QHs. These are arranged to give poll 387 * intervals that are powers of 2 times 1ms. 388 */ 389 for (i = 0; i < EHCI_INTRQHS; i++) { 390 sqh = ehci_alloc_sqh(sc); 391 if (sqh == NULL) { 392 err = USBD_NOMEM; 393 goto bad1; 394 } 395 sc->sc_islots[i].sqh = sqh; 396 } 397 for (i = 0; i < EHCI_INTRQHS; i++) { 398 sqh = sc->sc_islots[i].sqh; 399 if (i == 0) { 400 /* The last (1ms) QH terminates. */ 401 sqh->qh.qh_link = htole32(EHCI_LINK_TERMINATE); 402 sqh->next = NULL; 403 } else { 404 /* Otherwise the next QH has half the poll interval */ 405 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 406 sqh->qh.qh_link = htole32(sqh->next->physaddr | 407 EHCI_LINK_QH); 408 } 409 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 410 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 411 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 412 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 413 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 414 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 415 sqh->sqtd = NULL; 416 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 417 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 418 } 419 /* Point the frame list at the last level (128ms). */ 420 for (i = 0; i < (1 << (EHCI_IPOLLRATES - 1)); i++) 421 for (j = i; j < sc->sc_flsize; j += 1 << (EHCI_IPOLLRATES - 1)) 422 sc->sc_flist[j] = htole32(EHCI_LINK_QH | sc->sc_islots[ 423 EHCI_IQHIDX(EHCI_IPOLLRATES - 1, ehci_reverse_bits( 424 i, EHCI_IPOLLRATES - 1))].sqh->physaddr); 425 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 426 BUS_DMASYNC_PREWRITE); 427 428 /* Allocate dummy QH that starts the async list. */ 429 sqh = ehci_alloc_sqh(sc); 430 if (sqh == NULL) { 431 err = USBD_NOMEM; 432 goto bad1; 433 } 434 /* Fill the QH */ 435 sqh->qh.qh_endp = 436 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 437 sqh->qh.qh_link = 438 htole32(sqh->physaddr | EHCI_LINK_QH); 439 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 440 sqh->prev = sqh; /*It's a circular list.. */ 441 sqh->next = sqh; 442 /* Fill the overlay qTD */ 443 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 444 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 445 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 446 sqh->sqtd = NULL; 447 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 448 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 449 450 /* Point to async list */ 451 sc->sc_async_head = sqh; 452 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 453 454 timeout_set(&sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 455 456 rw_init(&sc->sc_doorbell_lock, "ehcidb"); 457 458 /* Turn on controller */ 459 EOWRITE4(sc, EHCI_USBCMD, 460 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 461 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 462 EHCI_CMD_ASE | 463 EHCI_CMD_PSE | 464 EHCI_CMD_RS); 465 466 /* Take over port ownership */ 467 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 468 469 for (i = 0; i < 100; i++) { 470 usb_delay_ms(&sc->sc_bus, 1); 471 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 472 if (!hcr) 473 break; 474 } 475 if (hcr) { 476 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 477 return (USBD_IOERROR); 478 } 479 480 /* Enable interrupts */ 481 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 482 483 return (USBD_NORMAL_COMPLETION); 484 485 #if 0 486 bad2: 487 ehci_free_sqh(sc, sc->sc_async_head); 488 #endif 489 bad1: 490 free(sc->sc_softitds, M_USB, 491 sc->sc_flsize * sizeof(struct ehci_soft_itd *)); 492 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 493 return (err); 494 } 495 496 int 497 ehci_intr(void *v) 498 { 499 struct ehci_softc *sc = v; 500 501 if (sc == NULL || sc->sc_bus.dying) 502 return (0); 503 504 /* If we get an interrupt while polling, then just ignore it. */ 505 if (sc->sc_bus.use_polling) { 506 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 507 508 if (intrs) 509 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 510 return (0); 511 } 512 513 return (ehci_intr1(sc)); 514 } 515 516 int 517 ehci_intr1(struct ehci_softc *sc) 518 { 519 u_int32_t intrs, eintrs; 520 521 /* In case the interrupt occurs before initialization has completed. */ 522 if (sc == NULL) { 523 #ifdef DIAGNOSTIC 524 printf("ehci_intr1: sc == NULL\n"); 525 #endif 526 return (0); 527 } 528 529 intrs = EOREAD4(sc, EHCI_USBSTS); 530 if (intrs == 0xffffffff) { 531 sc->sc_bus.dying = 1; 532 return (0); 533 } 534 intrs = EHCI_STS_INTRS(intrs); 535 if (!intrs) 536 return (0); 537 538 eintrs = intrs & sc->sc_eintrs; 539 if (!eintrs) 540 return (0); 541 542 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 543 sc->sc_bus.no_intrs++; 544 545 if (eintrs & EHCI_STS_HSE) { 546 printf("%s: unrecoverable error, controller halted\n", 547 sc->sc_bus.bdev.dv_xname); 548 sc->sc_bus.dying = 1; 549 return (1); 550 } 551 if (eintrs & EHCI_STS_IAA) { 552 wakeup(&sc->sc_async_head); 553 eintrs &= ~EHCI_STS_IAA; 554 } 555 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 556 usb_schedsoftintr(&sc->sc_bus); 557 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 558 } 559 if (eintrs & EHCI_STS_PCD) { 560 atomic_setbits_int(&sc->sc_flags, EHCIF_PCB_INTR); 561 usb_schedsoftintr(&sc->sc_bus); 562 eintrs &= ~EHCI_STS_PCD; 563 } 564 565 if (eintrs != 0) { 566 /* Block unprocessed interrupts. */ 567 sc->sc_eintrs &= ~eintrs; 568 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 569 printf("%s: blocking intrs 0x%x\n", 570 sc->sc_bus.bdev.dv_xname, eintrs); 571 } 572 573 return (1); 574 } 575 576 void 577 ehci_pcd(struct ehci_softc *sc, struct usbd_xfer *xfer) 578 { 579 u_char *p; 580 int i, m; 581 582 if (xfer == NULL) { 583 /* Just ignore the change. */ 584 return; 585 } 586 587 p = KERNADDR(&xfer->dmabuf, 0); 588 m = min(sc->sc_noport, xfer->length * 8 - 1); 589 memset(p, 0, xfer->length); 590 for (i = 1; i <= m; i++) { 591 /* Pick out CHANGE bits from the status reg. */ 592 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 593 p[i / 8] |= 1 << (i % 8); 594 } 595 xfer->actlen = xfer->length; 596 xfer->status = USBD_NORMAL_COMPLETION; 597 598 usb_transfer_complete(xfer); 599 } 600 601 /* 602 * Work around the half configured control (default) pipe when setting 603 * the address of a device. 604 * 605 * Because a single QH is setup per endpoint in ehci_open(), and the 606 * control pipe is configured before we could have set the address 607 * of the device or read the wMaxPacketSize of the endpoint, we have 608 * to re-open the pipe twice here. 609 */ 610 int 611 ehci_setaddr(struct usbd_device *dev, int addr) 612 { 613 /* Root Hub */ 614 if (dev->depth == 0) 615 return (0); 616 617 /* Re-establish the default pipe with the new max packet size. */ 618 ehci_close_pipe(dev->default_pipe); 619 if (ehci_open(dev->default_pipe)) 620 return (EINVAL); 621 622 if (usbd_set_address(dev, addr)) 623 return (1); 624 625 dev->address = addr; 626 627 /* Re-establish the default pipe with the new address. */ 628 ehci_close_pipe(dev->default_pipe); 629 if (ehci_open(dev->default_pipe)) 630 return (EINVAL); 631 632 return (0); 633 } 634 635 void 636 ehci_softintr(void *v) 637 { 638 struct ehci_softc *sc = v; 639 struct ehci_xfer *ex, *nextex; 640 641 if (sc->sc_bus.dying) 642 return; 643 644 sc->sc_bus.intr_context++; 645 646 if (sc->sc_flags & EHCIF_PCB_INTR) { 647 atomic_clearbits_int(&sc->sc_flags, EHCIF_PCB_INTR); 648 ehci_pcd(sc, sc->sc_intrxfer); 649 } 650 651 /* 652 * The only explanation I can think of for why EHCI is as brain dead 653 * as UHCI interrupt-wise is that Intel was involved in both. 654 * An interrupt just tells us that something is done, we have no 655 * clue what, so we need to scan through all active transfers. :-( 656 */ 657 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 658 nextex = TAILQ_NEXT(ex, inext); 659 ehci_check_intr(sc, &ex->xfer); 660 } 661 662 /* Schedule a callout to catch any dropped transactions. */ 663 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 664 !TAILQ_EMPTY(&sc->sc_intrhead)) { 665 timeout_add_sec(&sc->sc_tmo_intrlist, 1); 666 } 667 668 if (sc->sc_softwake) { 669 sc->sc_softwake = 0; 670 wakeup(&sc->sc_softwake); 671 } 672 673 sc->sc_bus.intr_context--; 674 } 675 676 void 677 ehci_check_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 678 { 679 int attr = xfer->pipe->endpoint->edesc->bmAttributes; 680 681 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 682 ehci_check_itd_intr(sc, xfer); 683 else 684 ehci_check_qh_intr(sc, xfer); 685 } 686 687 void 688 ehci_check_qh_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 689 { 690 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 691 struct ehci_soft_qtd *sqtd, *lsqtd = ex->sqtdend; 692 uint32_t status; 693 694 KASSERT(ex->sqtdstart != NULL && ex->sqtdend != NULL); 695 696 usb_syncmem(&lsqtd->dma, 697 lsqtd->offs + offsetof(struct ehci_qtd, qtd_status), 698 sizeof(lsqtd->qtd.qtd_status), 699 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 700 701 /* 702 * If the last TD is still active we need to check whether there 703 * is a an error somewhere in the middle, or whether there was a 704 * short packet (SPD and not ACTIVE). 705 */ 706 if (letoh32(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 707 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 708 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 709 usb_syncmem(&sqtd->dma, 710 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 711 sizeof(sqtd->qtd.qtd_status), 712 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 713 status = letoh32(sqtd->qtd.qtd_status); 714 usb_syncmem(&sqtd->dma, 715 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 716 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 717 /* If there's an active QTD the xfer isn't done. */ 718 if (status & EHCI_QTD_ACTIVE) 719 break; 720 /* Any kind of error makes the xfer done. */ 721 if (status & EHCI_QTD_HALTED) 722 goto done; 723 /* We want short packets, and it is short: it's done */ 724 if (EHCI_QTD_GET_BYTES(status) != 0) 725 goto done; 726 } 727 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 728 ex, ex->sqtdstart)); 729 usb_syncmem(&lsqtd->dma, 730 lsqtd->offs + offsetof(struct ehci_qtd, qtd_status), 731 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 732 return; 733 } 734 done: 735 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 736 timeout_del(&xfer->timeout_handle); 737 usb_rem_task(xfer->pipe->device, &xfer->abort_task); 738 ehci_idone(xfer); 739 } 740 741 void 742 ehci_check_itd_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 743 { 744 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 745 struct ehci_soft_itd *itd = ex->itdend; 746 int i; 747 748 if (xfer != SIMPLEQ_FIRST(&xfer->pipe->queue)) 749 return; 750 751 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 752 753 /* Check no active transfers in last itd, meaning we're finished */ 754 if (xfer->device->speed == USB_SPEED_HIGH) { 755 usb_syncmem(&itd->dma, 756 itd->offs + offsetof(struct ehci_itd, itd_ctl), 757 sizeof(itd->itd.itd_ctl), 758 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 759 760 for (i = 0; i < 8; i++) { 761 if (letoh32(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 762 return; 763 } 764 } else { 765 usb_syncmem(&itd->dma, 766 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 767 sizeof(itd->sitd.sitd_trans), 768 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 769 770 if (le32toh(itd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 771 return; 772 } 773 774 /* All descriptor(s) inactive, it's done */ 775 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 776 timeout_del(&xfer->timeout_handle); 777 usb_rem_task(xfer->pipe->device, &xfer->abort_task); 778 ehci_isoc_idone(xfer); 779 } 780 781 void 782 ehci_isoc_idone(struct usbd_xfer *xfer) 783 { 784 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 785 struct ehci_soft_itd *itd; 786 int i, len, uframes, nframes = 0, actlen = 0; 787 uint32_t status = 0; 788 789 if (xfer->status == USBD_CANCELLED || xfer->status == USBD_TIMEOUT) 790 return; 791 792 if (xfer->device->speed == USB_SPEED_HIGH) { 793 switch (xfer->pipe->endpoint->edesc->bInterval) { 794 case 0: 795 panic("isoc xfer suddenly has 0 bInterval, invalid"); 796 case 1: 797 uframes = 1; 798 break; 799 case 2: 800 uframes = 2; 801 break; 802 case 3: 803 uframes = 4; 804 break; 805 default: 806 uframes = 8; 807 break; 808 } 809 810 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 811 usb_syncmem(&itd->dma, 812 itd->offs + offsetof(struct ehci_itd, itd_ctl), 813 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 814 BUS_DMASYNC_POSTREAD); 815 816 for (i = 0; i < 8; i += uframes) { 817 /* XXX - driver didn't fill in the frame full 818 * of uframes. This leads to scheduling 819 * inefficiencies, but working around 820 * this doubles complexity of tracking 821 * an xfer. 822 */ 823 if (nframes >= xfer->nframes) 824 break; 825 826 status = letoh32(itd->itd.itd_ctl[i]); 827 len = EHCI_ITD_GET_LEN(status); 828 if (EHCI_ITD_GET_STATUS(status) != 0) 829 len = 0; /*No valid data on error*/ 830 831 xfer->frlengths[nframes++] = len; 832 actlen += len; 833 } 834 } 835 } else { 836 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 837 usb_syncmem(&itd->dma, 838 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 839 sizeof(itd->sitd.sitd_trans), 840 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 841 842 status = le32toh(itd->sitd.sitd_trans); 843 len = EHCI_SITD_GET_LEN(status); 844 if (xfer->frlengths[nframes] >= len) 845 len = xfer->frlengths[nframes] - len; 846 else 847 len = 0; 848 849 xfer->frlengths[nframes++] = len; 850 actlen += len; 851 } 852 } 853 854 #ifdef DIAGNOSTIC 855 ex->isdone = 1; 856 #endif 857 xfer->actlen = actlen; 858 xfer->status = USBD_NORMAL_COMPLETION; 859 usb_transfer_complete(xfer); 860 } 861 862 void 863 ehci_idone(struct usbd_xfer *xfer) 864 { 865 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 866 struct ehci_soft_qtd *sqtd; 867 u_int32_t status = 0, nstatus = 0; 868 int actlen, cerr; 869 870 #ifdef DIAGNOSTIC 871 { 872 int s = splhigh(); 873 if (ex->isdone) { 874 splx(s); 875 printf("ehci_idone: ex=%p is done!\n", ex); 876 return; 877 } 878 ex->isdone = 1; 879 splx(s); 880 } 881 #endif 882 if (xfer->status == USBD_CANCELLED || xfer->status == USBD_TIMEOUT) 883 return; 884 885 actlen = 0; 886 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) { 887 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 888 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 889 nstatus = letoh32(sqtd->qtd.qtd_status); 890 if (nstatus & EHCI_QTD_ACTIVE) 891 break; 892 893 status = nstatus; 894 /* halt is ok if descriptor is last, and complete */ 895 if (sqtd->qtd.qtd_next == htole32(EHCI_LINK_TERMINATE) && 896 EHCI_QTD_GET_BYTES(status) == 0) 897 status &= ~EHCI_QTD_HALTED; 898 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 899 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 900 } 901 902 cerr = EHCI_QTD_GET_CERR(status); 903 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 904 "status=0x%x\n", xfer->length, actlen, cerr, status)); 905 xfer->actlen = actlen; 906 if ((status & EHCI_QTD_HALTED) != 0) { 907 if ((status & EHCI_QTD_BABBLE) == 0 && cerr > 0) 908 xfer->status = USBD_STALLED; 909 else 910 xfer->status = USBD_IOERROR; /* more info XXX */ 911 } else 912 xfer->status = USBD_NORMAL_COMPLETION; 913 914 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 915 * during this call, before methods->done is called: dma sync required 916 * beforehand? */ 917 usb_transfer_complete(xfer); 918 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 919 } 920 921 void 922 ehci_poll(struct usbd_bus *bus) 923 { 924 struct ehci_softc *sc = (struct ehci_softc *)bus; 925 926 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 927 ehci_intr1(sc); 928 } 929 930 int 931 ehci_detach(struct device *self, int flags) 932 { 933 struct ehci_softc *sc = (struct ehci_softc *)self; 934 int rv; 935 936 rv = config_detach_children(self, flags); 937 if (rv != 0) 938 return (rv); 939 940 timeout_del(&sc->sc_tmo_intrlist); 941 942 ehci_reset(sc); 943 944 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 945 946 free(sc->sc_softitds, M_USB, 947 sc->sc_flsize * sizeof(struct ehci_soft_itd *)); 948 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 949 /* XXX free other data structures XXX */ 950 951 return (rv); 952 } 953 954 955 int 956 ehci_activate(struct device *self, int act) 957 { 958 struct ehci_softc *sc = (struct ehci_softc *)self; 959 u_int32_t cmd, hcr, cparams; 960 int i, rv = 0; 961 962 switch (act) { 963 case DVACT_SUSPEND: 964 rv = config_activate_children(self, act); 965 966 #ifdef DIAGNOSTIC 967 if (!TAILQ_EMPTY(&sc->sc_intrhead)) { 968 printf("%s: interrupt list not empty\n", 969 sc->sc_bus.bdev.dv_xname); 970 return (-1); 971 } 972 #endif 973 974 sc->sc_bus.use_polling++; 975 976 for (i = 1; i <= sc->sc_noport; i++) { 977 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 978 if ((cmd & (EHCI_PS_PO|EHCI_PS_PE)) == EHCI_PS_PE) 979 EOWRITE4(sc, EHCI_PORTSC(i), 980 cmd | EHCI_PS_SUSP); 981 } 982 983 /* 984 * First tell the host to stop processing Asynchronous 985 * and Periodic schedules. 986 */ 987 cmd = EOREAD4(sc, EHCI_USBCMD) & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 988 EOWRITE4(sc, EHCI_USBCMD, cmd); 989 for (i = 0; i < 100; i++) { 990 usb_delay_ms(&sc->sc_bus, 1); 991 hcr = EOREAD4(sc, EHCI_USBSTS) & 992 (EHCI_STS_ASS | EHCI_STS_PSS); 993 if (hcr == 0) 994 break; 995 } 996 if (hcr != 0) 997 printf("%s: disable schedules timeout\n", 998 sc->sc_bus.bdev.dv_xname); 999 1000 /* 1001 * Then reset the host as if it was a shutdown. 1002 * 1003 * All USB devices are disconnected/reconnected during 1004 * a suspend/resume cycle so keep it simple. 1005 */ 1006 ehci_reset(sc); 1007 1008 sc->sc_bus.use_polling--; 1009 break; 1010 case DVACT_RESUME: 1011 sc->sc_bus.use_polling++; 1012 1013 ehci_reset(sc); 1014 1015 cparams = EREAD4(sc, EHCI_HCCPARAMS); 1016 /* MUST clear segment register if 64 bit capable. */ 1017 if (EHCI_HCC_64BIT(cparams)) 1018 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1019 1020 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1021 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1022 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1023 1024 hcr = 0; 1025 for (i = 1; i <= sc->sc_noport; i++) { 1026 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1027 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == EHCI_PS_SUSP) { 1028 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1029 hcr = 1; 1030 } 1031 } 1032 1033 if (hcr) { 1034 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1035 for (i = 1; i <= sc->sc_noport; i++) { 1036 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1037 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == 1038 EHCI_PS_SUSP) 1039 EOWRITE4(sc, EHCI_PORTSC(i), 1040 cmd & ~EHCI_PS_FPR); 1041 } 1042 } 1043 1044 /* Turn on controller */ 1045 EOWRITE4(sc, EHCI_USBCMD, 1046 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 1047 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 1048 EHCI_CMD_ASE | 1049 EHCI_CMD_PSE | 1050 EHCI_CMD_RS); 1051 1052 /* Take over port ownership */ 1053 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 1054 for (i = 0; i < 100; i++) { 1055 usb_delay_ms(&sc->sc_bus, 1); 1056 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1057 if (!hcr) 1058 break; 1059 } 1060 1061 if (hcr) { 1062 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 1063 /* XXX should we bail here? */ 1064 } 1065 1066 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1067 1068 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1069 1070 sc->sc_bus.use_polling--; 1071 rv = config_activate_children(self, act); 1072 break; 1073 case DVACT_POWERDOWN: 1074 rv = config_activate_children(self, act); 1075 ehci_reset(sc); 1076 break; 1077 default: 1078 rv = config_activate_children(self, act); 1079 break; 1080 } 1081 return (rv); 1082 } 1083 1084 usbd_status 1085 ehci_reset(struct ehci_softc *sc) 1086 { 1087 u_int32_t hcr, usbmode; 1088 int i; 1089 1090 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1091 for (i = 0; i < 100; i++) { 1092 usb_delay_ms(&sc->sc_bus, 1); 1093 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1094 if (hcr) 1095 break; 1096 } 1097 1098 if (!hcr) 1099 printf("%s: halt timeout\n", sc->sc_bus.bdev.dv_xname); 1100 1101 if (sc->sc_flags & EHCIF_USBMODE) 1102 usbmode = EOREAD4(sc, EHCI_USBMODE); 1103 1104 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1105 for (i = 0; i < 100; i++) { 1106 usb_delay_ms(&sc->sc_bus, 1); 1107 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 1108 if (!hcr) 1109 break; 1110 } 1111 1112 if (hcr) { 1113 printf("%s: reset timeout\n", sc->sc_bus.bdev.dv_xname); 1114 return (USBD_IOERROR); 1115 } 1116 1117 if (sc->sc_flags & EHCIF_USBMODE) 1118 EOWRITE4(sc, EHCI_USBMODE, usbmode); 1119 1120 return (USBD_NORMAL_COMPLETION); 1121 } 1122 1123 struct usbd_xfer * 1124 ehci_allocx(struct usbd_bus *bus) 1125 { 1126 struct ehci_xfer *ex; 1127 1128 ex = pool_get(ehcixfer, PR_NOWAIT | PR_ZERO); 1129 #ifdef DIAGNOSTIC 1130 if (ex != NULL) 1131 ex->isdone = 1; 1132 #endif 1133 return ((struct usbd_xfer *)ex); 1134 } 1135 1136 void 1137 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1138 { 1139 struct ehci_xfer *ex = (struct ehci_xfer*)xfer; 1140 1141 #ifdef DIAGNOSTIC 1142 if (!ex->isdone) { 1143 printf("%s: !isdone\n", __func__); 1144 return; 1145 } 1146 #endif 1147 pool_put(ehcixfer, ex); 1148 } 1149 1150 void 1151 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1152 { 1153 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1154 1155 #ifdef DIAGNOSTIC 1156 if ((epipe->sqh->qh.qh_qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) != 0) 1157 panic("ehci_device_clear_toggle: queue active"); 1158 #endif 1159 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1160 } 1161 1162 #ifdef EHCI_DEBUG 1163 void 1164 ehci_dump_regs(struct ehci_softc *sc) 1165 { 1166 int i; 1167 1168 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1169 EOREAD4(sc, EHCI_USBCMD), 1170 EOREAD4(sc, EHCI_USBSTS), 1171 EOREAD4(sc, EHCI_USBINTR)); 1172 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1173 EOREAD4(sc, EHCI_FRINDEX), 1174 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1175 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1176 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1177 for (i = 1; i <= sc->sc_noport; i++) 1178 printf("port %d status=0x%08x\n", i, 1179 EOREAD4(sc, EHCI_PORTSC(i))); 1180 } 1181 1182 /* 1183 * Unused function - this is meant to be called from a kernel 1184 * debugger. 1185 */ 1186 void 1187 ehci_dump(void) 1188 { 1189 ehci_dump_regs(theehci); 1190 } 1191 1192 void 1193 ehci_dump_link(ehci_link_t link, int type) 1194 { 1195 link = letoh32(link); 1196 printf("0x%08x", link); 1197 if (link & EHCI_LINK_TERMINATE) 1198 printf("<T>"); 1199 else { 1200 printf("<"); 1201 if (type) { 1202 switch (EHCI_LINK_TYPE(link)) { 1203 case EHCI_LINK_ITD: 1204 printf("ITD"); 1205 break; 1206 case EHCI_LINK_QH: 1207 printf("QH"); 1208 break; 1209 case EHCI_LINK_SITD: 1210 printf("SITD"); 1211 break; 1212 case EHCI_LINK_FSTN: 1213 printf("FSTN"); 1214 break; 1215 } 1216 } 1217 printf(">"); 1218 } 1219 } 1220 1221 void 1222 ehci_dump_sqtds(struct ehci_soft_qtd *sqtd) 1223 { 1224 int i; 1225 u_int32_t stop; 1226 1227 stop = 0; 1228 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1229 ehci_dump_sqtd(sqtd); 1230 usb_syncmem(&sqtd->dma, 1231 sqtd->offs + offsetof(struct ehci_qtd, qtd_next), 1232 sizeof(sqtd->qtd), 1233 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1234 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1235 usb_syncmem(&sqtd->dma, 1236 sqtd->offs + offsetof(struct ehci_qtd, qtd_next), 1237 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1238 } 1239 if (!stop) 1240 printf("dump aborted, too many TDs\n"); 1241 } 1242 1243 void 1244 ehci_dump_sqtd(struct ehci_soft_qtd *sqtd) 1245 { 1246 usb_syncmem(&sqtd->dma, sqtd->offs, 1247 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1248 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1249 ehci_dump_qtd(&sqtd->qtd); 1250 usb_syncmem(&sqtd->dma, sqtd->offs, 1251 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1252 } 1253 1254 void 1255 ehci_dump_qtd(struct ehci_qtd *qtd) 1256 { 1257 u_int32_t s; 1258 char sbuf[128]; 1259 1260 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1261 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1262 printf("\n"); 1263 s = letoh32(qtd->qtd_status); 1264 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), "\20\10ACTIVE\7HALTED" 1265 "\6BUFERR\5BABBLE\4XACTERR\3MISSED\2SPLIT\1PING", 1266 sbuf, sizeof(sbuf)); 1267 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1268 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1269 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1270 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1271 EHCI_QTD_GET_PID(s), sbuf); 1272 for (s = 0; s < 5; s++) 1273 printf(" buffer[%d]=0x%08x\n", s, letoh32(qtd->qtd_buffer[s])); 1274 } 1275 1276 void 1277 ehci_dump_sqh(struct ehci_soft_qh *sqh) 1278 { 1279 struct ehci_qh *qh = &sqh->qh; 1280 u_int32_t endp, endphub; 1281 1282 usb_syncmem(&sqh->dma, sqh->offs, 1283 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1284 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1285 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1286 endp = letoh32(qh->qh_endp); 1287 printf(" endp=0x%08x\n", endp); 1288 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1289 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1290 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1291 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1292 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1293 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1294 EHCI_QH_GET_NRL(endp)); 1295 endphub = letoh32(qh->qh_endphub); 1296 printf(" endphub=0x%08x\n", endphub); 1297 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1298 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1299 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1300 EHCI_QH_GET_MULT(endphub)); 1301 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1302 printf("Overlay qTD:\n"); 1303 ehci_dump_qtd(&qh->qh_qtd); 1304 usb_syncmem(&sqh->dma, sqh->offs, 1305 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1306 } 1307 1308 #if notyet 1309 void 1310 ehci_dump_itd(struct ehci_soft_itd *itd) 1311 { 1312 ehci_isoc_trans_t t; 1313 ehci_isoc_bufr_ptr_t b, b2, b3; 1314 int i; 1315 1316 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1317 1318 for (i = 0; i < 8; i++) { 1319 t = letoh32(itd->itd.itd_ctl[i]); 1320 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1321 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1322 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1323 EHCI_ITD_GET_OFFS(t)); 1324 } 1325 printf("ITDbufr: "); 1326 for (i = 0; i < 7; i++) 1327 printf("%X,", EHCI_ITD_GET_BPTR(letoh32(itd->itd.itd_bufr[i]))); 1328 1329 b = letoh32(itd->itd.itd_bufr[0]); 1330 b2 = letoh32(itd->itd.itd_bufr[1]); 1331 b3 = letoh32(itd->itd.itd_bufr[2]); 1332 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1333 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1334 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1335 } 1336 #endif 1337 1338 #ifdef DIAGNOSTIC 1339 void 1340 ehci_dump_exfer(struct ehci_xfer *ex) 1341 { 1342 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p " 1343 "isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, 1344 ex->itdend, ex->isdone); 1345 } 1346 #endif 1347 1348 #endif /* EHCI_DEBUG */ 1349 1350 usbd_status 1351 ehci_open(struct usbd_pipe *pipe) 1352 { 1353 struct usbd_device *dev = pipe->device; 1354 struct ehci_softc *sc = (struct ehci_softc *)dev->bus; 1355 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1356 u_int8_t addr = dev->address; 1357 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1358 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1359 struct ehci_soft_qh *sqh; 1360 usbd_status err; 1361 int s; 1362 int ival, speed, naks; 1363 int hshubaddr, hshubport; 1364 1365 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d\n", 1366 pipe, addr, ed->bEndpointAddress)); 1367 1368 if (sc->sc_bus.dying) 1369 return (USBD_IOERROR); 1370 1371 if (dev->myhsport) { 1372 hshubaddr = dev->myhsport->parent->address; 1373 hshubport = dev->myhsport->portno; 1374 } else { 1375 hshubaddr = 0; 1376 hshubport = 0; 1377 } 1378 1379 /* Root Hub */ 1380 if (pipe->device->depth == 0) { 1381 switch (ed->bEndpointAddress) { 1382 case USB_CONTROL_ENDPOINT: 1383 pipe->methods = &ehci_root_ctrl_methods; 1384 break; 1385 case UE_DIR_IN | EHCI_INTR_ENDPT: 1386 pipe->methods = &ehci_root_intr_methods; 1387 break; 1388 default: 1389 return (USBD_INVAL); 1390 } 1391 return (USBD_NORMAL_COMPLETION); 1392 } 1393 1394 /* XXX All this stuff is only valid for async. */ 1395 switch (dev->speed) { 1396 case USB_SPEED_LOW: 1397 speed = EHCI_QH_SPEED_LOW; 1398 break; 1399 case USB_SPEED_FULL: 1400 speed = EHCI_QH_SPEED_FULL; 1401 break; 1402 case USB_SPEED_HIGH: 1403 speed = EHCI_QH_SPEED_HIGH; 1404 break; 1405 default: 1406 panic("ehci_open: bad device speed %d", dev->speed); 1407 } 1408 1409 /* 1410 * NAK reload count: 1411 * must be zero with using periodic transfer. 1412 * Linux 4.20's driver (ehci-q.c) sets 4, we use same value. 1413 */ 1414 naks = ((xfertype == UE_CONTROL) || (xfertype == UE_BULK)) ? 4 : 0; 1415 1416 /* Allocate sqh for everything, save isoc xfers */ 1417 if (xfertype != UE_ISOCHRONOUS) { 1418 sqh = ehci_alloc_sqh(sc); 1419 if (sqh == NULL) 1420 return (USBD_NOMEM); 1421 /* qh_link filled when the QH is added */ 1422 sqh->qh.qh_endp = htole32( 1423 EHCI_QH_SET_ADDR(addr) | 1424 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1425 EHCI_QH_SET_EPS(speed) | 1426 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1427 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1428 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1429 EHCI_QH_CTL : 0) | 1430 EHCI_QH_SET_NRL(naks) 1431 ); 1432 sqh->qh.qh_endphub = htole32( 1433 EHCI_QH_SET_MULT(1) | 1434 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0) 1435 ); 1436 if (speed != EHCI_QH_SPEED_HIGH) { 1437 sqh->qh.qh_endphub |= htole32( 1438 EHCI_QH_SET_HUBA(hshubaddr) | 1439 EHCI_QH_SET_PORT(hshubport) | 1440 EHCI_QH_SET_CMASK(0x1c) /* XXX */ 1441 ); 1442 } 1443 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 1444 /* Fill the overlay qTD */ 1445 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 1446 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1447 sqh->qh.qh_qtd.qtd_status = 1448 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1449 1450 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1451 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1452 epipe->sqh = sqh; 1453 } /*xfertype == UE_ISOC*/ 1454 1455 switch (xfertype) { 1456 case UE_CONTROL: 1457 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1458 0, &epipe->u.ctl.reqdma); 1459 if (err) { 1460 ehci_free_sqh(sc, sqh); 1461 return (err); 1462 } 1463 pipe->methods = &ehci_device_ctrl_methods; 1464 s = splusb(); 1465 ehci_add_qh(sqh, sc->sc_async_head); 1466 splx(s); 1467 break; 1468 case UE_BULK: 1469 pipe->methods = &ehci_device_bulk_methods; 1470 s = splusb(); 1471 ehci_add_qh(sqh, sc->sc_async_head); 1472 splx(s); 1473 break; 1474 case UE_INTERRUPT: 1475 pipe->methods = &ehci_device_intr_methods; 1476 ival = pipe->interval; 1477 if (ival == USBD_DEFAULT_INTERVAL) 1478 ival = ed->bInterval; 1479 s = splusb(); 1480 err = ehci_device_setintr(sc, sqh, ival); 1481 splx(s); 1482 return (err); 1483 case UE_ISOCHRONOUS: 1484 switch (speed) { 1485 case EHCI_QH_SPEED_HIGH: 1486 case EHCI_QH_SPEED_FULL: 1487 pipe->methods = &ehci_device_isoc_methods; 1488 break; 1489 case EHCI_QH_SPEED_LOW: 1490 default: 1491 return (USBD_INVAL); 1492 } 1493 /* Spec page 271 says intervals > 16 are invalid */ 1494 if (ed->bInterval == 0 || ed->bInterval > 16) { 1495 printf("ehci: opening pipe with invalid bInterval\n"); 1496 return (USBD_INVAL); 1497 } 1498 if (UGETW(ed->wMaxPacketSize) == 0) { 1499 printf("ehci: zero length endpoint open request\n"); 1500 return (USBD_INVAL); 1501 } 1502 epipe->u.isoc.next_frame = 0; 1503 epipe->u.isoc.cur_xfers = 0; 1504 break; 1505 default: 1506 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1507 return (USBD_INVAL); 1508 } 1509 return (USBD_NORMAL_COMPLETION); 1510 } 1511 1512 /* 1513 * Add an ED to the schedule. Called at splusb(). 1514 * If in the async schedule, it will always have a next. 1515 * If in the intr schedule it may not. 1516 */ 1517 void 1518 ehci_add_qh(struct ehci_soft_qh *sqh, struct ehci_soft_qh *head) 1519 { 1520 splsoftassert(IPL_SOFTUSB); 1521 1522 usb_syncmem(&head->dma, head->offs + offsetof(struct ehci_qh, qh_link), 1523 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1524 sqh->next = head->next; 1525 sqh->prev = head; 1526 sqh->qh.qh_link = head->qh.qh_link; 1527 usb_syncmem(&sqh->dma, sqh->offs + offsetof(struct ehci_qh, qh_link), 1528 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1529 head->next = sqh; 1530 if (sqh->next) 1531 sqh->next->prev = sqh; 1532 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1533 usb_syncmem(&head->dma, head->offs + offsetof(struct ehci_qh, qh_link), 1534 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1535 } 1536 1537 /* 1538 * Remove an ED from the schedule. Called at splusb(). 1539 * Will always have a 'next' if it's in the async list as it's circular. 1540 */ 1541 void 1542 ehci_rem_qh(struct ehci_softc *sc, struct ehci_soft_qh *sqh) 1543 { 1544 splsoftassert(IPL_SOFTUSB); 1545 /* XXX */ 1546 usb_syncmem(&sqh->dma, sqh->offs + offsetof(struct ehci_qh, qh_link), 1547 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1548 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1549 sqh->prev->next = sqh->next; 1550 if (sqh->next) 1551 sqh->next->prev = sqh->prev; 1552 usb_syncmem(&sqh->prev->dma, 1553 sqh->prev->offs + offsetof(struct ehci_qh, qh_link), 1554 sizeof(sqh->prev->qh.qh_link), BUS_DMASYNC_PREWRITE); 1555 1556 ehci_sync_hc(sc); 1557 } 1558 1559 void 1560 ehci_set_qh_qtd(struct ehci_soft_qh *sqh, struct ehci_soft_qtd *sqtd) 1561 { 1562 int i; 1563 u_int32_t status; 1564 1565 /* Save toggle bit and ping status. */ 1566 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1567 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1568 status = sqh->qh.qh_qtd.qtd_status & 1569 htole32(EHCI_QTD_TOGGLE_MASK | 1570 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1571 /* Set HALTED to make hw leave it alone. */ 1572 sqh->qh.qh_qtd.qtd_status = 1573 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1574 usb_syncmem(&sqh->dma, 1575 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 1576 sizeof(sqh->qh.qh_qtd.qtd_status), 1577 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1578 sqh->qh.qh_curqtd = 0; 1579 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1580 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1581 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1582 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1583 sqh->sqtd = sqtd; 1584 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1585 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1586 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1587 sqh->qh.qh_qtd.qtd_status = status; 1588 usb_syncmem(&sqh->dma, 1589 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 1590 sizeof(sqh->qh.qh_qtd.qtd_status), 1591 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1592 } 1593 1594 /* 1595 * Ensure that the HC has released all references to the QH. We do this 1596 * by asking for a Async Advance Doorbell interrupt and then we wait for 1597 * the interrupt. 1598 * To make this easier we first obtain exclusive use of the doorbell. 1599 */ 1600 void 1601 ehci_sync_hc(struct ehci_softc *sc) 1602 { 1603 int s, error; 1604 int tries = 0; 1605 1606 if (sc->sc_bus.dying) { 1607 return; 1608 } 1609 1610 /* get doorbell */ 1611 rw_enter_write(&sc->sc_doorbell_lock); 1612 s = splhardusb(); 1613 do { 1614 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | 1615 EHCI_CMD_IAAD); 1616 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz / 2); 1617 } while (error && ++tries < 10); 1618 splx(s); 1619 /* release doorbell */ 1620 rw_exit_write(&sc->sc_doorbell_lock); 1621 #ifdef DIAGNOSTIC 1622 if (error) 1623 printf("ehci_sync_hc: tsleep() = %d\n", error); 1624 #endif 1625 } 1626 1627 void 1628 ehci_rem_itd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 1629 { 1630 struct ehci_soft_itd *itd, *prev = NULL; 1631 1632 splsoftassert(IPL_SOFTUSB); 1633 1634 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 1635 1636 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1637 prev = itd->u.frame_list.prev; 1638 /* Unlink itd from hardware chain, or frame array */ 1639 if (prev == NULL) { /* We're at the table head */ 1640 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1641 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1642 usb_syncmem(&sc->sc_fldma, 1643 sizeof(uint32_t) * itd->slot, sizeof(uint32_t), 1644 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1645 1646 if (itd->u.frame_list.next != NULL) 1647 itd->u.frame_list.next->u.frame_list.prev = 1648 NULL; 1649 } else { 1650 /* XXX this part is untested... */ 1651 prev->itd.itd_next = itd->itd.itd_next; 1652 usb_syncmem(&itd->dma, 1653 itd->offs + offsetof(struct ehci_itd, itd_next), 1654 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1655 1656 prev->u.frame_list.next = itd->u.frame_list.next; 1657 if (itd->u.frame_list.next != NULL) 1658 itd->u.frame_list.next->u.frame_list.prev = 1659 prev; 1660 } 1661 } 1662 } 1663 1664 void 1665 ehci_free_itd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 1666 { 1667 struct ehci_soft_itd *itd, *prev = NULL; 1668 1669 splsoftassert(IPL_SOFTUSB); 1670 1671 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 1672 1673 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1674 if (prev != NULL) 1675 ehci_free_itd(sc, prev); 1676 prev = itd; 1677 } 1678 if (prev) 1679 ehci_free_itd(sc, prev); 1680 ex->itdstart = NULL; 1681 ex->itdend = NULL; 1682 } 1683 1684 /* 1685 * Data structures and routines to emulate the root hub. 1686 */ 1687 usb_device_descriptor_t ehci_devd = { 1688 USB_DEVICE_DESCRIPTOR_SIZE, 1689 UDESC_DEVICE, /* type */ 1690 {0x00, 0x02}, /* USB version */ 1691 UDCLASS_HUB, /* class */ 1692 UDSUBCLASS_HUB, /* subclass */ 1693 UDPROTO_HSHUBSTT, /* protocol */ 1694 64, /* max packet */ 1695 {0},{0},{0x00,0x01}, /* device id */ 1696 1,2,0, /* string indicies */ 1697 1 /* # of configurations */ 1698 }; 1699 1700 usb_device_qualifier_t ehci_odevd = { 1701 USB_DEVICE_DESCRIPTOR_SIZE, 1702 UDESC_DEVICE_QUALIFIER, /* type */ 1703 {0x00, 0x02}, /* USB version */ 1704 UDCLASS_HUB, /* class */ 1705 UDSUBCLASS_HUB, /* subclass */ 1706 UDPROTO_FSHUB, /* protocol */ 1707 64, /* max packet */ 1708 1, /* # of configurations */ 1709 0 1710 }; 1711 1712 usb_config_descriptor_t ehci_confd = { 1713 USB_CONFIG_DESCRIPTOR_SIZE, 1714 UDESC_CONFIG, 1715 {USB_CONFIG_DESCRIPTOR_SIZE + 1716 USB_INTERFACE_DESCRIPTOR_SIZE + 1717 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1718 1, 1719 1, 1720 0, 1721 UC_SELF_POWERED, 1722 0 /* max power */ 1723 }; 1724 1725 usb_interface_descriptor_t ehci_ifcd = { 1726 USB_INTERFACE_DESCRIPTOR_SIZE, 1727 UDESC_INTERFACE, 1728 0, 1729 0, 1730 1, 1731 UICLASS_HUB, 1732 UISUBCLASS_HUB, 1733 UIPROTO_HSHUBSTT, 1734 0 1735 }; 1736 1737 usb_endpoint_descriptor_t ehci_endpd = { 1738 USB_ENDPOINT_DESCRIPTOR_SIZE, 1739 UDESC_ENDPOINT, 1740 UE_DIR_IN | EHCI_INTR_ENDPT, 1741 UE_INTERRUPT, 1742 {8, 0}, /* max packet */ 1743 12 1744 }; 1745 1746 usb_hub_descriptor_t ehci_hubd = { 1747 USB_HUB_DESCRIPTOR_SIZE, 1748 UDESC_HUB, 1749 0, 1750 {0,0}, 1751 0, 1752 0, 1753 {0}, 1754 }; 1755 1756 /* 1757 * Simulate a hardware hub by handling all the necessary requests. 1758 */ 1759 usbd_status 1760 ehci_root_ctrl_transfer(struct usbd_xfer *xfer) 1761 { 1762 usbd_status err; 1763 1764 /* Insert last in queue. */ 1765 err = usb_insert_transfer(xfer); 1766 if (err) 1767 return (err); 1768 1769 /* Pipe isn't running, start first */ 1770 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1771 } 1772 1773 usbd_status 1774 ehci_root_ctrl_start(struct usbd_xfer *xfer) 1775 { 1776 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1777 usb_device_request_t *req; 1778 void *buf = NULL; 1779 int port, i; 1780 int s, len, value, index, l, totlen = 0; 1781 usb_port_status_t ps; 1782 usb_hub_descriptor_t hubd; 1783 usbd_status err; 1784 u_int32_t v; 1785 1786 if (sc->sc_bus.dying) 1787 return (USBD_IOERROR); 1788 1789 #ifdef DIAGNOSTIC 1790 if (!(xfer->rqflags & URQ_REQUEST)) 1791 /* XXX panic */ 1792 return (USBD_INVAL); 1793 #endif 1794 req = &xfer->request; 1795 1796 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1797 req->bmRequestType, req->bRequest)); 1798 1799 len = UGETW(req->wLength); 1800 value = UGETW(req->wValue); 1801 index = UGETW(req->wIndex); 1802 1803 if (len != 0) 1804 buf = KERNADDR(&xfer->dmabuf, 0); 1805 1806 #define C(x,y) ((x) | ((y) << 8)) 1807 switch(C(req->bRequest, req->bmRequestType)) { 1808 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1809 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1810 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1811 /* 1812 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1813 * for the integrated root hub. 1814 */ 1815 break; 1816 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1817 if (len > 0) { 1818 *(u_int8_t *)buf = sc->sc_conf; 1819 totlen = 1; 1820 } 1821 break; 1822 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1823 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1824 switch(value >> 8) { 1825 case UDESC_DEVICE: 1826 if ((value & 0xff) != 0) { 1827 err = USBD_IOERROR; 1828 goto ret; 1829 } 1830 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1831 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1832 memcpy(buf, &ehci_devd, l); 1833 break; 1834 /* 1835 * We can't really operate at another speed, but the spec says 1836 * we need this descriptor. 1837 */ 1838 case UDESC_DEVICE_QUALIFIER: 1839 if ((value & 0xff) != 0) { 1840 err = USBD_IOERROR; 1841 goto ret; 1842 } 1843 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1844 memcpy(buf, &ehci_odevd, l); 1845 break; 1846 /* 1847 * We can't really operate at another speed, but the spec says 1848 * we need this descriptor. 1849 */ 1850 case UDESC_OTHER_SPEED_CONFIGURATION: 1851 case UDESC_CONFIG: 1852 if ((value & 0xff) != 0) { 1853 err = USBD_IOERROR; 1854 goto ret; 1855 } 1856 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1857 memcpy(buf, &ehci_confd, l); 1858 ((usb_config_descriptor_t *)buf)->bDescriptorType = 1859 value >> 8; 1860 buf = (char *)buf + l; 1861 len -= l; 1862 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1863 totlen += l; 1864 memcpy(buf, &ehci_ifcd, l); 1865 buf = (char *)buf + l; 1866 len -= l; 1867 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1868 totlen += l; 1869 memcpy(buf, &ehci_endpd, l); 1870 break; 1871 case UDESC_STRING: 1872 if (len == 0) 1873 break; 1874 *(u_int8_t *)buf = 0; 1875 totlen = 1; 1876 switch (value & 0xff) { 1877 case 0: /* Language table */ 1878 totlen = usbd_str(buf, len, "\001"); 1879 break; 1880 case 1: /* Vendor */ 1881 totlen = usbd_str(buf, len, sc->sc_vendor); 1882 break; 1883 case 2: /* Product */ 1884 totlen = usbd_str(buf, len, "EHCI root hub"); 1885 break; 1886 } 1887 break; 1888 default: 1889 err = USBD_IOERROR; 1890 goto ret; 1891 } 1892 break; 1893 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1894 if (len > 0) { 1895 *(u_int8_t *)buf = 0; 1896 totlen = 1; 1897 } 1898 break; 1899 case C(UR_GET_STATUS, UT_READ_DEVICE): 1900 if (len > 1) { 1901 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1902 totlen = 2; 1903 } 1904 break; 1905 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1906 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1907 if (len > 1) { 1908 USETW(((usb_status_t *)buf)->wStatus, 0); 1909 totlen = 2; 1910 } 1911 break; 1912 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1913 if (value >= USB_MAX_DEVICES) { 1914 err = USBD_IOERROR; 1915 goto ret; 1916 } 1917 break; 1918 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1919 if (value != 0 && value != 1) { 1920 err = USBD_IOERROR; 1921 goto ret; 1922 } 1923 sc->sc_conf = value; 1924 break; 1925 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1926 break; 1927 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1928 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1929 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1930 err = USBD_IOERROR; 1931 goto ret; 1932 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1933 break; 1934 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1935 break; 1936 /* Hub requests */ 1937 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1938 break; 1939 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1940 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 1941 "port=%d feature=%d\n", index, value)); 1942 if (index < 1 || index > sc->sc_noport) { 1943 err = USBD_IOERROR; 1944 goto ret; 1945 } 1946 port = EHCI_PORTSC(index); 1947 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 1948 switch(value) { 1949 case UHF_PORT_ENABLE: 1950 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 1951 break; 1952 case UHF_PORT_SUSPEND: 1953 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 1954 break; 1955 case UHF_PORT_POWER: 1956 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 1957 break; 1958 case UHF_PORT_TEST: 1959 DPRINTFN(2,("ehci_root_ctrl_start: " 1960 "clear port test %d\n", index)); 1961 break; 1962 case UHF_PORT_INDICATOR: 1963 DPRINTFN(2,("ehci_root_ctrl_start: " 1964 "clear port index %d\n", index)); 1965 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 1966 break; 1967 case UHF_C_PORT_CONNECTION: 1968 EOWRITE4(sc, port, v | EHCI_PS_CSC); 1969 break; 1970 case UHF_C_PORT_ENABLE: 1971 EOWRITE4(sc, port, v | EHCI_PS_PEC); 1972 break; 1973 case UHF_C_PORT_SUSPEND: 1974 /* how? */ 1975 break; 1976 case UHF_C_PORT_OVER_CURRENT: 1977 EOWRITE4(sc, port, v | EHCI_PS_OCC); 1978 break; 1979 case UHF_C_PORT_RESET: 1980 sc->sc_isreset = 0; 1981 break; 1982 default: 1983 err = USBD_IOERROR; 1984 goto ret; 1985 } 1986 break; 1987 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1988 if ((value & 0xff) != 0) { 1989 err = USBD_IOERROR; 1990 goto ret; 1991 } 1992 hubd = ehci_hubd; 1993 hubd.bNbrPorts = sc->sc_noport; 1994 v = EREAD4(sc, EHCI_HCSPARAMS); 1995 USETW(hubd.wHubCharacteristics, 1996 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 1997 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0)); 1998 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 1999 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2000 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2001 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2002 l = min(len, hubd.bDescLength); 2003 totlen = l; 2004 memcpy(buf, &hubd, l); 2005 break; 2006 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2007 if (len != 4) { 2008 err = USBD_IOERROR; 2009 goto ret; 2010 } 2011 memset(buf, 0, len); /* ? XXX */ 2012 totlen = len; 2013 break; 2014 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2015 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2016 index)); 2017 if (index < 1 || index > sc->sc_noport) { 2018 err = USBD_IOERROR; 2019 goto ret; 2020 } 2021 if (len != 4) { 2022 err = USBD_IOERROR; 2023 goto ret; 2024 } 2025 v = EOREAD4(sc, EHCI_PORTSC(index)); 2026 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2027 i = UPS_HIGH_SPEED; 2028 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2029 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2030 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2031 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2032 if (v & EHCI_PS_PR) i |= UPS_RESET; 2033 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2034 USETW(ps.wPortStatus, i); 2035 i = 0; 2036 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2037 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2038 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2039 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 2040 USETW(ps.wPortChange, i); 2041 l = min(len, sizeof(ps)); 2042 memcpy(buf, &ps, l); 2043 totlen = l; 2044 break; 2045 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2046 err = USBD_IOERROR; 2047 goto ret; 2048 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2049 break; 2050 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2051 if (index < 1 || index > sc->sc_noport) { 2052 err = USBD_IOERROR; 2053 goto ret; 2054 } 2055 port = EHCI_PORTSC(index); 2056 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2057 switch(value) { 2058 case UHF_PORT_ENABLE: 2059 EOWRITE4(sc, port, v | EHCI_PS_PE); 2060 break; 2061 case UHF_PORT_SUSPEND: 2062 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2063 break; 2064 case UHF_PORT_DISOWN_TO_1_1: 2065 /* enter to Port Reset State */ 2066 v &= ~EHCI_PS_PE; 2067 EOWRITE4(sc, port, v | EHCI_PS_PR); 2068 ehci_disown(sc, index, 0); 2069 break; 2070 case UHF_PORT_RESET: 2071 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2072 index)); 2073 if (EHCI_PS_IS_LOWSPEED(v)) { 2074 /* Low speed device, give up ownership. */ 2075 ehci_disown(sc, index, 1); 2076 break; 2077 } 2078 /* Start reset sequence. */ 2079 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2080 EOWRITE4(sc, port, v | EHCI_PS_PR); 2081 /* Wait for reset to complete. */ 2082 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2083 if (sc->sc_bus.dying) { 2084 err = USBD_IOERROR; 2085 goto ret; 2086 } 2087 /* Terminate reset sequence. */ 2088 v = EOREAD4(sc, port); 2089 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2090 /* Wait for HC to complete reset. */ 2091 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2092 if (sc->sc_bus.dying) { 2093 err = USBD_IOERROR; 2094 goto ret; 2095 } 2096 v = EOREAD4(sc, port); 2097 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2098 if (v & EHCI_PS_PR) { 2099 printf("%s: port reset timeout\n", 2100 sc->sc_bus.bdev.dv_xname); 2101 err = USBD_IOERROR; 2102 goto ret; 2103 } 2104 if (!(v & EHCI_PS_PE)) { 2105 /* Not a high speed device, give up ownership.*/ 2106 ehci_disown(sc, index, 0); 2107 break; 2108 } 2109 sc->sc_isreset = 1; 2110 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2111 index, v)); 2112 break; 2113 case UHF_PORT_POWER: 2114 DPRINTFN(2,("ehci_root_ctrl_start: " 2115 "set port power %d\n", index)); 2116 EOWRITE4(sc, port, v | EHCI_PS_PP); 2117 break; 2118 case UHF_PORT_TEST: 2119 DPRINTFN(2,("ehci_root_ctrl_start: " 2120 "set port test %d\n", index)); 2121 break; 2122 case UHF_PORT_INDICATOR: 2123 DPRINTFN(2,("ehci_root_ctrl_start: " 2124 "set port ind %d\n", index)); 2125 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2126 break; 2127 default: 2128 err = USBD_IOERROR; 2129 goto ret; 2130 } 2131 break; 2132 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2133 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2134 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2135 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2136 break; 2137 default: 2138 err = USBD_IOERROR; 2139 goto ret; 2140 } 2141 xfer->actlen = totlen; 2142 err = USBD_NORMAL_COMPLETION; 2143 ret: 2144 xfer->status = err; 2145 s = splusb(); 2146 usb_transfer_complete(xfer); 2147 splx(s); 2148 return (err); 2149 } 2150 2151 void 2152 ehci_disown(struct ehci_softc *sc, int index, int lowspeed) 2153 { 2154 int port; 2155 u_int32_t v; 2156 2157 port = EHCI_PORTSC(index); 2158 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2159 EOWRITE4(sc, port, v | EHCI_PS_PO); 2160 } 2161 2162 /* Abort a root control request. */ 2163 void 2164 ehci_root_ctrl_abort(struct usbd_xfer *xfer) 2165 { 2166 /* Nothing to do, all transfers are synchronous. */ 2167 } 2168 2169 /* Close the root pipe. */ 2170 void 2171 ehci_root_ctrl_close(struct usbd_pipe *pipe) 2172 { 2173 /* Nothing to do. */ 2174 } 2175 2176 void 2177 ehci_root_intr_done(struct usbd_xfer *xfer) 2178 { 2179 } 2180 2181 usbd_status 2182 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2183 { 2184 usbd_status err; 2185 2186 /* Insert last in queue. */ 2187 err = usb_insert_transfer(xfer); 2188 if (err) 2189 return (err); 2190 2191 /* Pipe isn't running, start first */ 2192 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2193 } 2194 2195 usbd_status 2196 ehci_root_intr_start(struct usbd_xfer *xfer) 2197 { 2198 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2199 2200 if (sc->sc_bus.dying) 2201 return (USBD_IOERROR); 2202 2203 sc->sc_intrxfer = xfer; 2204 2205 return (USBD_IN_PROGRESS); 2206 } 2207 2208 void 2209 ehci_root_intr_abort(struct usbd_xfer *xfer) 2210 { 2211 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2212 int s; 2213 2214 sc->sc_intrxfer = NULL; 2215 2216 xfer->status = USBD_CANCELLED; 2217 s = splusb(); 2218 usb_transfer_complete(xfer); 2219 splx(s); 2220 } 2221 2222 void 2223 ehci_root_intr_close(struct usbd_pipe *pipe) 2224 { 2225 } 2226 2227 void 2228 ehci_root_ctrl_done(struct usbd_xfer *xfer) 2229 { 2230 } 2231 2232 struct ehci_soft_qh * 2233 ehci_alloc_sqh(struct ehci_softc *sc) 2234 { 2235 struct ehci_soft_qh *sqh = NULL; 2236 usbd_status err; 2237 int i, offs; 2238 struct usb_dma dma; 2239 int s; 2240 2241 s = splusb(); 2242 if (sc->sc_freeqhs == NULL) { 2243 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2244 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2245 EHCI_PAGE_SIZE, &dma); 2246 if (err) 2247 goto out; 2248 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2249 offs = i * EHCI_SQH_SIZE; 2250 sqh = KERNADDR(&dma, offs); 2251 sqh->physaddr = DMAADDR(&dma, offs); 2252 sqh->dma = dma; 2253 sqh->offs = offs; 2254 sqh->next = sc->sc_freeqhs; 2255 sc->sc_freeqhs = sqh; 2256 } 2257 } 2258 sqh = sc->sc_freeqhs; 2259 sc->sc_freeqhs = sqh->next; 2260 memset(&sqh->qh, 0, sizeof(struct ehci_qh)); 2261 sqh->next = NULL; 2262 sqh->prev = NULL; 2263 2264 out: 2265 splx(s); 2266 return (sqh); 2267 } 2268 2269 void 2270 ehci_free_sqh(struct ehci_softc *sc, struct ehci_soft_qh *sqh) 2271 { 2272 int s; 2273 2274 s = splusb(); 2275 sqh->next = sc->sc_freeqhs; 2276 sc->sc_freeqhs = sqh; 2277 splx(s); 2278 } 2279 2280 struct ehci_soft_qtd * 2281 ehci_alloc_sqtd(struct ehci_softc *sc) 2282 { 2283 struct ehci_soft_qtd *sqtd = NULL; 2284 usbd_status err; 2285 int i, offs; 2286 struct usb_dma dma; 2287 int s; 2288 2289 s = splusb(); 2290 if (sc->sc_freeqtds == NULL) { 2291 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2292 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2293 EHCI_PAGE_SIZE, &dma); 2294 if (err) 2295 goto out; 2296 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2297 offs = i * EHCI_SQTD_SIZE; 2298 sqtd = KERNADDR(&dma, offs); 2299 sqtd->physaddr = DMAADDR(&dma, offs); 2300 sqtd->dma = dma; 2301 sqtd->offs = offs; 2302 sqtd->nextqtd = sc->sc_freeqtds; 2303 sc->sc_freeqtds = sqtd; 2304 } 2305 } 2306 2307 sqtd = sc->sc_freeqtds; 2308 sc->sc_freeqtds = sqtd->nextqtd; 2309 memset(&sqtd->qtd, 0, sizeof(struct ehci_qtd)); 2310 sqtd->nextqtd = NULL; 2311 2312 out: 2313 splx(s); 2314 return (sqtd); 2315 } 2316 2317 void 2318 ehci_free_sqtd(struct ehci_softc *sc, struct ehci_soft_qtd *sqtd) 2319 { 2320 int s; 2321 2322 s = splusb(); 2323 sqtd->nextqtd = sc->sc_freeqtds; 2324 sc->sc_freeqtds = sqtd; 2325 splx(s); 2326 } 2327 2328 usbd_status 2329 ehci_alloc_sqtd_chain(struct ehci_softc *sc, u_int alen, struct usbd_xfer *xfer, 2330 struct ehci_soft_qtd **sp, struct ehci_soft_qtd **ep) 2331 { 2332 struct ehci_soft_qtd *next, *cur; 2333 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2334 u_int32_t qtdstatus; 2335 u_int len, curlen; 2336 int mps, i, iscontrol, forceshort; 2337 int rd = usbd_xfer_isread(xfer); 2338 struct usb_dma *dma = &xfer->dmabuf; 2339 2340 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2341 2342 len = alen; 2343 iscontrol = (xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) == 2344 UE_CONTROL; 2345 2346 dataphys = DMAADDR(dma, 0); 2347 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2348 qtdstatus = EHCI_QTD_ACTIVE | 2349 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2350 EHCI_QTD_SET_CERR(3); /* IOC and BYTES set below */ 2351 mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize); 2352 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2353 len % mps == 0; 2354 /* 2355 * The control transfer data stage always starts with a toggle of 1. 2356 * For other transfers we let the hardware track the toggle state. 2357 */ 2358 if (iscontrol) 2359 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2360 2361 cur = ehci_alloc_sqtd(sc); 2362 *sp = cur; 2363 if (cur == NULL) 2364 goto nomem; 2365 2366 usb_syncmem(dma, 0, alen, 2367 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2368 for (;;) { 2369 dataphyspage = EHCI_PAGE(dataphys); 2370 /* The EHCI hardware can handle at most 5 pages. */ 2371 if (dataphyslastpage - dataphyspage < 2372 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2373 /* we can handle it in this QTD */ 2374 curlen = len; 2375 } else { 2376 /* must use multiple TDs, fill as much as possible. */ 2377 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2378 EHCI_PAGE_OFFSET(dataphys); 2379 #ifdef DIAGNOSTIC 2380 if (curlen > len) { 2381 printf("ehci_alloc_sqtd_chain: curlen=%u " 2382 "len=%u offs=0x%x\n", curlen, len, 2383 EHCI_PAGE_OFFSET(dataphys)); 2384 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2385 dataphyslastpage, dataphyspage, dataphys); 2386 curlen = len; 2387 } 2388 #endif 2389 /* the length must be a multiple of the max size */ 2390 curlen -= curlen % mps; 2391 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2392 "curlen=%u\n", curlen)); 2393 #ifdef DIAGNOSTIC 2394 if (curlen == 0) 2395 panic("ehci_alloc_std: curlen == 0"); 2396 #endif 2397 } 2398 2399 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2400 "dataphyslastpage=0x%08x len=%u curlen=%u\n", 2401 dataphys, dataphyslastpage, len, curlen)); 2402 len -= curlen; 2403 2404 /* 2405 * Allocate another transfer if there's more data left, 2406 * or if force last short transfer flag is set and we're 2407 * allocating a multiple of the max packet size. 2408 */ 2409 if (len != 0 || forceshort) { 2410 next = ehci_alloc_sqtd(sc); 2411 if (next == NULL) 2412 goto nomem; 2413 nextphys = htole32(next->physaddr); 2414 } else { 2415 next = NULL; 2416 nextphys = htole32(EHCI_LINK_TERMINATE); 2417 } 2418 2419 for (i = 0; i * EHCI_PAGE_SIZE < 2420 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2421 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2422 if (i != 0) /* use offset only in first buffer */ 2423 a = EHCI_PAGE(a); 2424 #ifdef DIAGNOSTIC 2425 if (i >= EHCI_QTD_NBUFFERS) { 2426 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2427 goto nomem; 2428 } 2429 #endif 2430 cur->qtd.qtd_buffer[i] = htole32(a); 2431 cur->qtd.qtd_buffer_hi[i] = 0; 2432 } 2433 cur->nextqtd = next; 2434 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2435 cur->qtd.qtd_status = htole32(qtdstatus | 2436 EHCI_QTD_SET_BYTES(curlen)); 2437 cur->len = curlen; 2438 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2439 dataphys, dataphys + curlen)); 2440 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%u\n", curlen)); 2441 if (iscontrol) { 2442 /* 2443 * adjust the toggle based on the number of packets 2444 * in this qtd 2445 */ 2446 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2447 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2448 } 2449 if (len == 0) { 2450 if (! forceshort) 2451 break; 2452 forceshort = 0; 2453 } 2454 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2455 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2456 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2457 dataphys += curlen; 2458 cur = next; 2459 } 2460 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2461 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2462 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2463 *ep = cur; 2464 2465 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2466 *sp, *ep)); 2467 2468 return (USBD_NORMAL_COMPLETION); 2469 2470 nomem: 2471 /* XXX free chain */ 2472 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2473 return (USBD_NOMEM); 2474 } 2475 2476 void 2477 ehci_free_sqtd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 2478 { 2479 struct ehci_pipe *epipe = (struct ehci_pipe *)ex->xfer.pipe; 2480 struct ehci_soft_qtd *sqtd, *next; 2481 2482 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p\n", ex->sqtdstart)); 2483 2484 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = next) { 2485 next = sqtd->nextqtd; 2486 ehci_free_sqtd(sc, sqtd); 2487 } 2488 ex->sqtdstart = ex->sqtdend = NULL; 2489 epipe->sqh->sqtd = NULL; 2490 } 2491 2492 struct ehci_soft_itd * 2493 ehci_alloc_itd(struct ehci_softc *sc) 2494 { 2495 struct ehci_soft_itd *itd, *freeitd; 2496 usbd_status err; 2497 int i, s, offs, frindex, previndex; 2498 struct usb_dma dma; 2499 2500 s = splusb(); 2501 2502 /* Find an itd that wasn't freed this frame or last frame. This can 2503 * discard itds that were freed before frindex wrapped around 2504 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2505 * interrupt and fiddling with list when that happens */ 2506 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2507 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2508 2509 freeitd = NULL; 2510 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2511 if (itd == NULL) 2512 break; 2513 if (itd->slot != frindex && itd->slot != previndex) { 2514 freeitd = itd; 2515 break; 2516 } 2517 } 2518 2519 if (freeitd == NULL) { 2520 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2521 EHCI_PAGE_SIZE, &dma); 2522 if (err) { 2523 splx(s); 2524 return (NULL); 2525 } 2526 2527 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2528 offs = i * EHCI_ITD_SIZE; 2529 itd = KERNADDR(&dma, offs); 2530 itd->physaddr = DMAADDR(&dma, offs); 2531 itd->dma = dma; 2532 itd->offs = offs; 2533 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2534 } 2535 freeitd = LIST_FIRST(&sc->sc_freeitds); 2536 } 2537 2538 itd = freeitd; 2539 LIST_REMOVE(itd, u.free_list); 2540 memset(&itd->itd, 0, sizeof(struct ehci_itd)); 2541 usb_syncmem(&itd->dma, itd->offs + offsetof(struct ehci_itd, itd_next), 2542 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2543 BUS_DMASYNC_PREREAD); 2544 2545 itd->u.frame_list.next = NULL; 2546 itd->u.frame_list.prev = NULL; 2547 itd->xfer_next = NULL; 2548 itd->slot = 0; 2549 splx(s); 2550 2551 return (itd); 2552 } 2553 2554 void 2555 ehci_free_itd(struct ehci_softc *sc, struct ehci_soft_itd *itd) 2556 { 2557 int s; 2558 2559 s = splusb(); 2560 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2561 splx(s); 2562 } 2563 2564 /* 2565 * Close a reqular pipe. 2566 * Assumes that there are no pending transactions. 2567 */ 2568 void 2569 ehci_close_pipe(struct usbd_pipe *pipe) 2570 { 2571 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2572 struct ehci_softc *sc = (struct ehci_softc *)pipe->device->bus; 2573 struct ehci_soft_qh *sqh = epipe->sqh; 2574 int s; 2575 2576 s = splusb(); 2577 ehci_rem_qh(sc, sqh); 2578 splx(s); 2579 pipe->endpoint->savedtoggle = 2580 EHCI_QTD_GET_TOGGLE(letoh32(sqh->qh.qh_qtd.qtd_status)); 2581 ehci_free_sqh(sc, epipe->sqh); 2582 } 2583 2584 /* 2585 * Abort a device request. 2586 * If this routine is called at splusb() it guarantees that the request 2587 * will be removed from the hardware scheduling and that the callback 2588 * for it will be called with USBD_CANCELLED status. 2589 * It's impossible to guarantee that the requested transfer will not 2590 * have happened since the hardware runs concurrently. 2591 * If the transaction has already happened we rely on the ordinary 2592 * interrupt processing to process it. 2593 */ 2594 void 2595 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2596 { 2597 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2598 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2599 struct ehci_xfer *ex = (struct ehci_xfer*)xfer; 2600 struct ehci_soft_qh *sqh = epipe->sqh; 2601 struct ehci_soft_qtd *sqtd; 2602 int s; 2603 2604 if (sc->sc_bus.dying || xfer->status == USBD_NOT_STARTED) { 2605 s = splusb(); 2606 if (xfer->status != USBD_NOT_STARTED) 2607 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2608 xfer->status = status; /* make software ignore it */ 2609 timeout_del(&xfer->timeout_handle); 2610 usb_rem_task(xfer->device, &xfer->abort_task); 2611 #ifdef DIAGNOSTIC 2612 ex->isdone = 1; 2613 #endif 2614 usb_transfer_complete(xfer); 2615 splx(s); 2616 return; 2617 } 2618 2619 if (xfer->device->bus->intr_context) 2620 panic("ehci_abort_xfer: not in process context"); 2621 2622 /* 2623 * If an abort is already in progress then just wait for it to 2624 * complete and return. 2625 */ 2626 if (ex->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2627 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2628 /* No need to wait if we're aborting from a timeout. */ 2629 if (status == USBD_TIMEOUT) 2630 return; 2631 /* Override the status which might be USBD_TIMEOUT. */ 2632 xfer->status = status; 2633 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2634 ex->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 2635 while (ex->ehci_xfer_flags & EHCI_XFER_ABORTING) 2636 tsleep(&ex->ehci_xfer_flags, PZERO, "ehciaw", 0); 2637 return; 2638 } 2639 2640 /* 2641 * Step 1: Make interrupt routine and timeouts ignore xfer. 2642 */ 2643 s = splusb(); 2644 ex->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2645 xfer->status = status; /* make software ignore it */ 2646 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2647 timeout_del(&xfer->timeout_handle); 2648 usb_rem_task(xfer->device, &xfer->abort_task); 2649 splx(s); 2650 2651 /* 2652 * Step 2: Deactivate all of the qTDs that we will be removing, 2653 * otherwise the queue head may go active again. 2654 */ 2655 usb_syncmem(&sqh->dma, 2656 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 2657 sizeof(sqh->qh.qh_qtd.qtd_status), 2658 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2659 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2660 usb_syncmem(&sqh->dma, 2661 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 2662 sizeof(sqh->qh.qh_qtd.qtd_status), 2663 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2664 2665 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) { 2666 usb_syncmem(&sqtd->dma, 2667 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 2668 sizeof(sqtd->qtd.qtd_status), 2669 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2670 sqtd->qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2671 usb_syncmem(&sqtd->dma, 2672 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 2673 sizeof(sqtd->qtd.qtd_status), 2674 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2675 } 2676 ehci_sync_hc(sc); 2677 2678 /* 2679 * Step 3: Make sure the soft interrupt routine has run. This 2680 * should remove any completed items off the queue. 2681 * The hardware has no reference to completed items (TDs). 2682 * It's safe to remove them at any time. 2683 */ 2684 s = splusb(); 2685 sc->sc_softwake = 1; 2686 usb_schedsoftintr(&sc->sc_bus); 2687 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2688 2689 #ifdef DIAGNOSTIC 2690 ex->isdone = 1; 2691 #endif 2692 /* Do the wakeup first to avoid touching the xfer after the callback. */ 2693 ex->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 2694 if (ex->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 2695 ex->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 2696 wakeup(&ex->ehci_xfer_flags); 2697 } 2698 usb_transfer_complete(xfer); 2699 2700 splx(s); 2701 } 2702 2703 void 2704 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 2705 { 2706 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2707 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2708 ehci_isoc_trans_t trans_status; 2709 struct ehci_soft_itd *itd; 2710 int i; 2711 2712 splsoftassert(IPL_SOFTUSB); 2713 2714 if (sc->sc_bus.dying || xfer->status == USBD_NOT_STARTED) { 2715 if (xfer->status != USBD_NOT_STARTED) 2716 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2717 xfer->status = status; 2718 timeout_del(&xfer->timeout_handle); 2719 usb_rem_task(xfer->device, &xfer->abort_task); 2720 usb_transfer_complete(xfer); 2721 return; 2722 } 2723 2724 /* Transfer is already done. */ 2725 if (xfer->status != USBD_IN_PROGRESS) { 2726 DPRINTF(("%s: already done \n", __func__)); 2727 return; 2728 } 2729 2730 2731 #ifdef DIAGNOSTIC 2732 ex->isdone = 1; 2733 #endif 2734 xfer->status = status; 2735 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2736 timeout_del(&xfer->timeout_handle); 2737 usb_rem_task(xfer->device, &xfer->abort_task); 2738 2739 if (xfer->device->speed == USB_SPEED_HIGH) { 2740 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 2741 usb_syncmem(&itd->dma, 2742 itd->offs + offsetof(struct ehci_itd, itd_ctl), 2743 sizeof(itd->itd.itd_ctl), 2744 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2745 2746 for (i = 0; i < 8; i++) { 2747 trans_status = le32toh(itd->itd.itd_ctl[i]); 2748 trans_status &= ~EHCI_ITD_ACTIVE; 2749 itd->itd.itd_ctl[i] = htole32(trans_status); 2750 } 2751 2752 usb_syncmem(&itd->dma, 2753 itd->offs + offsetof(struct ehci_itd, itd_ctl), 2754 sizeof(itd->itd.itd_ctl), 2755 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2756 } 2757 } else { 2758 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 2759 usb_syncmem(&itd->dma, 2760 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 2761 sizeof(itd->sitd.sitd_trans), 2762 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2763 2764 trans_status = le32toh(itd->sitd.sitd_trans); 2765 trans_status &= ~EHCI_SITD_ACTIVE; 2766 itd->sitd.sitd_trans = htole32(trans_status); 2767 2768 usb_syncmem(&itd->dma, 2769 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 2770 sizeof(itd->sitd.sitd_trans), 2771 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2772 } 2773 } 2774 2775 sc->sc_softwake = 1; 2776 usb_schedsoftintr(&sc->sc_bus); 2777 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2778 2779 usb_transfer_complete(xfer); 2780 } 2781 2782 void 2783 ehci_timeout(void *addr) 2784 { 2785 struct usbd_xfer *xfer = addr; 2786 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2787 2788 if (sc->sc_bus.dying) { 2789 ehci_timeout_task(addr); 2790 return; 2791 } 2792 2793 usb_init_task(&xfer->abort_task, ehci_timeout_task, addr, 2794 USB_TASK_TYPE_ABORT); 2795 usb_add_task(xfer->device, &xfer->abort_task); 2796 } 2797 2798 void 2799 ehci_timeout_task(void *addr) 2800 { 2801 struct usbd_xfer *xfer = addr; 2802 int s; 2803 2804 s = splusb(); 2805 ehci_abort_xfer(xfer, USBD_TIMEOUT); 2806 splx(s); 2807 } 2808 2809 /* 2810 * Some EHCI chips from VIA / ATI seem to trigger interrupts before writing 2811 * back the qTD status, or miss signalling occasionally under heavy load. 2812 * If the host machine is too fast, we can miss transaction completion - when 2813 * we scan the active list the transaction still seems to be active. This 2814 * generally exhibits itself as a umass stall that never recovers. 2815 * 2816 * We work around this behaviour by setting up this callback after any softintr 2817 * that completes with transactions still pending, giving us another chance to 2818 * check for completion after the writeback has taken place. 2819 */ 2820 void 2821 ehci_intrlist_timeout(void *arg) 2822 { 2823 struct ehci_softc *sc = arg; 2824 int s; 2825 2826 if (sc->sc_bus.dying) 2827 return; 2828 2829 s = splusb(); 2830 DPRINTFN(1, ("ehci_intrlist_timeout\n")); 2831 usb_schedsoftintr(&sc->sc_bus); 2832 splx(s); 2833 } 2834 2835 usbd_status 2836 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 2837 { 2838 usbd_status err; 2839 2840 /* Insert last in queue. */ 2841 err = usb_insert_transfer(xfer); 2842 if (err) 2843 return (err); 2844 2845 /* Pipe isn't running, start first */ 2846 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2847 } 2848 2849 usbd_status 2850 ehci_device_ctrl_start(struct usbd_xfer *xfer) 2851 { 2852 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2853 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2854 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2855 usb_device_request_t *req = &xfer->request; 2856 struct ehci_soft_qtd *setup, *stat, *next; 2857 struct ehci_soft_qh *sqh; 2858 u_int len = UGETW(req->wLength); 2859 usbd_status err; 2860 int s; 2861 2862 KASSERT(xfer->rqflags & URQ_REQUEST); 2863 2864 if (sc->sc_bus.dying) 2865 return (USBD_IOERROR); 2866 2867 setup = ehci_alloc_sqtd(sc); 2868 if (setup == NULL) { 2869 err = USBD_NOMEM; 2870 goto bad1; 2871 } 2872 stat = ehci_alloc_sqtd(sc); 2873 if (stat == NULL) { 2874 err = USBD_NOMEM; 2875 goto bad2; 2876 } 2877 2878 sqh = epipe->sqh; 2879 2880 /* Set up data transaction */ 2881 if (len != 0) { 2882 struct ehci_soft_qtd *end; 2883 2884 err = ehci_alloc_sqtd_chain(sc, len, xfer, &next, &end); 2885 if (err) 2886 goto bad3; 2887 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 2888 end->nextqtd = stat; 2889 end->qtd.qtd_next = 2890 end->qtd.qtd_altnext = htole32(stat->physaddr); 2891 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 2892 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2893 } else { 2894 next = stat; 2895 } 2896 2897 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 2898 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2899 2900 /* Clear toggle */ 2901 setup->qtd.qtd_status = htole32( 2902 EHCI_QTD_ACTIVE | 2903 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 2904 EHCI_QTD_SET_CERR(3) | 2905 EHCI_QTD_SET_TOGGLE(0) | 2906 EHCI_QTD_SET_BYTES(sizeof(*req))); 2907 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 2908 setup->qtd.qtd_buffer_hi[0] = 0; 2909 setup->nextqtd = next; 2910 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 2911 setup->len = sizeof(*req); 2912 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 2913 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2914 2915 stat->qtd.qtd_status = htole32( 2916 EHCI_QTD_ACTIVE | 2917 EHCI_QTD_SET_PID(usbd_xfer_isread(xfer) ? 2918 EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 2919 EHCI_QTD_SET_CERR(3) | 2920 EHCI_QTD_SET_TOGGLE(1) | 2921 EHCI_QTD_IOC); 2922 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 2923 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 2924 stat->nextqtd = NULL; 2925 stat->qtd.qtd_next = stat->qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 2926 stat->len = 0; 2927 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 2928 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2929 2930 ex->sqtdstart = setup; 2931 ex->sqtdend = stat; 2932 #ifdef DIAGNOSTIC 2933 if (!ex->isdone) { 2934 printf("%s: not done, ex=%p\n", __func__, ex); 2935 } 2936 ex->isdone = 0; 2937 #endif 2938 2939 /* Insert qTD in QH list. */ 2940 s = splusb(); 2941 ehci_set_qh_qtd(sqh, setup); 2942 if (xfer->timeout && !sc->sc_bus.use_polling) { 2943 timeout_del(&xfer->timeout_handle); 2944 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 2945 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 2946 } 2947 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 2948 xfer->status = USBD_IN_PROGRESS; 2949 splx(s); 2950 2951 return (USBD_IN_PROGRESS); 2952 2953 bad3: 2954 ehci_free_sqtd(sc, stat); 2955 bad2: 2956 ehci_free_sqtd(sc, setup); 2957 bad1: 2958 xfer->status = err; 2959 usb_transfer_complete(xfer); 2960 return (err); 2961 } 2962 2963 void 2964 ehci_device_ctrl_done(struct usbd_xfer *xfer) 2965 { 2966 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2967 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2968 2969 KASSERT(xfer->rqflags & URQ_REQUEST); 2970 2971 if (xfer->status != USBD_NOMEM) { 2972 ehci_free_sqtd_chain(sc, ex); 2973 } 2974 } 2975 2976 void 2977 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 2978 { 2979 ehci_abort_xfer(xfer, USBD_CANCELLED); 2980 } 2981 2982 void 2983 ehci_device_ctrl_close(struct usbd_pipe *pipe) 2984 { 2985 ehci_close_pipe(pipe); 2986 } 2987 2988 usbd_status 2989 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 2990 { 2991 usbd_status err; 2992 2993 /* Insert last in queue. */ 2994 err = usb_insert_transfer(xfer); 2995 if (err) 2996 return (err); 2997 2998 /* Pipe isn't running, start first */ 2999 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3000 } 3001 3002 usbd_status 3003 ehci_device_bulk_start(struct usbd_xfer *xfer) 3004 { 3005 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3006 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3007 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3008 struct ehci_soft_qtd *data, *dataend; 3009 struct ehci_soft_qh *sqh; 3010 usbd_status err; 3011 int s; 3012 3013 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3014 3015 if (sc->sc_bus.dying) 3016 return (USBD_IOERROR); 3017 3018 sqh = epipe->sqh; 3019 3020 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3021 if (err) { 3022 xfer->status = err; 3023 usb_transfer_complete(xfer); 3024 return (err); 3025 } 3026 3027 /* Set up interrupt info. */ 3028 ex->sqtdstart = data; 3029 ex->sqtdend = dataend; 3030 #ifdef DIAGNOSTIC 3031 if (!ex->isdone) { 3032 printf("ehci_device_bulk_start: not done, ex=%p\n", ex); 3033 } 3034 ex->isdone = 0; 3035 #endif 3036 3037 s = splusb(); 3038 ehci_set_qh_qtd(sqh, data); 3039 if (xfer->timeout && !sc->sc_bus.use_polling) { 3040 timeout_del(&xfer->timeout_handle); 3041 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3042 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3043 } 3044 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3045 xfer->status = USBD_IN_PROGRESS; 3046 splx(s); 3047 3048 return (USBD_IN_PROGRESS); 3049 } 3050 3051 void 3052 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3053 { 3054 ehci_abort_xfer(xfer, USBD_CANCELLED); 3055 } 3056 3057 /* 3058 * Close a device bulk pipe. 3059 */ 3060 void 3061 ehci_device_bulk_close(struct usbd_pipe *pipe) 3062 { 3063 ehci_close_pipe(pipe); 3064 } 3065 3066 void 3067 ehci_device_bulk_done(struct usbd_xfer *xfer) 3068 { 3069 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3070 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3071 3072 if (xfer->status != USBD_NOMEM) { 3073 ehci_free_sqtd_chain(sc, ex); 3074 } 3075 } 3076 3077 usbd_status 3078 ehci_device_setintr(struct ehci_softc *sc, struct ehci_soft_qh *sqh, int ival) 3079 { 3080 struct ehci_soft_islot *isp; 3081 int islot, lev; 3082 3083 /* Find a poll rate that is large enough. */ 3084 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3085 if (EHCI_ILEV_IVAL(lev) <= ival) 3086 break; 3087 3088 /* Pick an interrupt slot at the right level. */ 3089 /* XXX could do better than picking at random */ 3090 islot = EHCI_IQHIDX(lev, arc4random()); 3091 3092 sqh->islot = islot; 3093 isp = &sc->sc_islots[islot]; 3094 ehci_add_qh(sqh, isp->sqh); 3095 3096 return (USBD_NORMAL_COMPLETION); 3097 } 3098 3099 usbd_status 3100 ehci_device_intr_transfer(struct usbd_xfer *xfer) 3101 { 3102 usbd_status err; 3103 3104 /* Insert last in queue. */ 3105 err = usb_insert_transfer(xfer); 3106 if (err) 3107 return (err); 3108 3109 /* 3110 * Pipe isn't running (otherwise err would be USBD_INPROG), 3111 * so start it first. 3112 */ 3113 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3114 } 3115 3116 usbd_status 3117 ehci_device_intr_start(struct usbd_xfer *xfer) 3118 { 3119 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3120 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3121 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3122 struct ehci_soft_qtd *data, *dataend; 3123 struct ehci_soft_qh *sqh; 3124 usbd_status err; 3125 int s; 3126 3127 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3128 3129 if (sc->sc_bus.dying) 3130 return (USBD_IOERROR); 3131 3132 sqh = epipe->sqh; 3133 3134 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3135 if (err) { 3136 xfer->status = err; 3137 usb_transfer_complete(xfer); 3138 return (err); 3139 } 3140 3141 /* Set up interrupt info. */ 3142 ex->sqtdstart = data; 3143 ex->sqtdend = dataend; 3144 #ifdef DIAGNOSTIC 3145 if (!ex->isdone) 3146 printf("ehci_device_intr_start: not done, ex=%p\n", ex); 3147 ex->isdone = 0; 3148 #endif 3149 3150 s = splusb(); 3151 ehci_set_qh_qtd(sqh, data); 3152 if (xfer->timeout && !sc->sc_bus.use_polling) { 3153 timeout_del(&xfer->timeout_handle); 3154 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3155 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3156 } 3157 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3158 xfer->status = USBD_IN_PROGRESS; 3159 splx(s); 3160 3161 return (USBD_IN_PROGRESS); 3162 } 3163 3164 void 3165 ehci_device_intr_abort(struct usbd_xfer *xfer) 3166 { 3167 KASSERT(!xfer->pipe->repeat || xfer->pipe->intrxfer == xfer); 3168 3169 /* 3170 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3171 * async doorbell. That's dependant on the async list, wheras 3172 * intr xfers are periodic, should not use this? 3173 */ 3174 ehci_abort_xfer(xfer, USBD_CANCELLED); 3175 } 3176 3177 void 3178 ehci_device_intr_close(struct usbd_pipe *pipe) 3179 { 3180 ehci_close_pipe(pipe); 3181 } 3182 3183 void 3184 ehci_device_intr_done(struct usbd_xfer *xfer) 3185 { 3186 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3187 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3188 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3189 struct ehci_soft_qtd *data, *dataend; 3190 struct ehci_soft_qh *sqh; 3191 usbd_status err; 3192 int s; 3193 3194 if (xfer->pipe->repeat) { 3195 ehci_free_sqtd_chain(sc, ex); 3196 3197 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3198 usbd_xfer_isread(xfer) ? 3199 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3200 sqh = epipe->sqh; 3201 3202 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3203 if (err) { 3204 xfer->status = err; 3205 return; 3206 } 3207 3208 /* Set up interrupt info. */ 3209 ex->sqtdstart = data; 3210 ex->sqtdend = dataend; 3211 #ifdef DIAGNOSTIC 3212 if (!ex->isdone) { 3213 printf("ehci_device_intr_done: not done, ex=%p\n", 3214 ex); 3215 } 3216 ex->isdone = 0; 3217 #endif 3218 3219 s = splusb(); 3220 ehci_set_qh_qtd(sqh, data); 3221 if (xfer->timeout && !sc->sc_bus.use_polling) { 3222 timeout_del(&xfer->timeout_handle); 3223 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3224 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3225 } 3226 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3227 xfer->status = USBD_IN_PROGRESS; 3228 splx(s); 3229 } else if (xfer->status != USBD_NOMEM) { 3230 ehci_free_sqtd_chain(sc, ex); 3231 } 3232 } 3233 3234 usbd_status 3235 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 3236 { 3237 usbd_status err; 3238 3239 err = usb_insert_transfer(xfer); 3240 if (err && err != USBD_IN_PROGRESS) 3241 return (err); 3242 3243 return (ehci_device_isoc_start(xfer)); 3244 } 3245 3246 usbd_status 3247 ehci_device_isoc_start(struct usbd_xfer *xfer) 3248 { 3249 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3250 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3251 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3252 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3253 uint8_t ival = ed->bInterval; 3254 struct ehci_soft_itd *itd; 3255 int s, frindex; 3256 uint32_t link; 3257 3258 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3259 KASSERT(ival > 0 && ival <= 16); 3260 3261 /* 3262 * To allow continuous transfers, above we start all transfers 3263 * immediately. However, we're still going to get usbd_start_next call 3264 * this when another xfer completes. So, check if this is already 3265 * in progress or not 3266 */ 3267 if (ex->itdstart != NULL) 3268 return (USBD_IN_PROGRESS); 3269 3270 if (sc->sc_bus.dying) 3271 return (USBD_IOERROR); 3272 3273 /* Why would you do that anyway? */ 3274 if (sc->sc_bus.use_polling) 3275 return (USBD_INVAL); 3276 3277 /* 3278 * To avoid complication, don't allow a request right now that'll span 3279 * the entire frame table. To within 4 frames, to allow some leeway 3280 * on either side of where the hc currently is. 3281 */ 3282 if ((1 << (ival - 1)) * xfer->nframes >= (sc->sc_flsize - 4) * 8) 3283 return (USBD_INVAL); 3284 3285 /* 3286 * Step 1: Allocate and initialize itds. 3287 */ 3288 if (xfer->device->speed == USB_SPEED_HIGH) { 3289 if (ehci_alloc_itd_chain(sc, xfer)) 3290 return (USBD_INVAL); 3291 3292 link = EHCI_LINK_ITD; 3293 } else { 3294 if (ehci_alloc_sitd_chain(sc, xfer)) 3295 return (USBD_INVAL); 3296 3297 link = EHCI_LINK_SITD; 3298 } 3299 3300 #ifdef DIAGNOSTIC 3301 if (!ex->isdone) { 3302 printf("%s: not done, ex=%p\n", __func__, ex); 3303 } 3304 ex->isdone = 0; 3305 #endif 3306 3307 /* 3308 * Part 2: Transfer descriptors have now been set up, now they must 3309 * be scheduled into the period frame list. Erk. Not wanting to 3310 * complicate matters, transfer is denied if the transfer spans 3311 * more than the period frame list. 3312 */ 3313 s = splusb(); 3314 3315 /* Start inserting frames */ 3316 if (epipe->u.isoc.cur_xfers > 0) { 3317 frindex = epipe->u.isoc.next_frame; 3318 } else { 3319 frindex = EOREAD4(sc, EHCI_FRINDEX); 3320 frindex = frindex >> 3; /* Erase microframe index */ 3321 frindex += 2; 3322 } 3323 3324 if (frindex >= sc->sc_flsize) 3325 frindex &= (sc->sc_flsize - 1); 3326 3327 /* What's the frame interval? */ 3328 ival = (1 << (ival - 1)); 3329 if (ival / 8 == 0) 3330 ival = 1; 3331 else 3332 ival /= 8; 3333 3334 /* Abuse the fact that itd_next == sitd_next. */ 3335 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 3336 itd->itd.itd_next = sc->sc_flist[frindex]; 3337 if (itd->itd.itd_next == 0) 3338 itd->itd.itd_next = htole32(EHCI_LINK_TERMINATE); 3339 3340 sc->sc_flist[frindex] = htole32(link | itd->physaddr); 3341 itd->u.frame_list.next = sc->sc_softitds[frindex]; 3342 sc->sc_softitds[frindex] = itd; 3343 if (itd->u.frame_list.next != NULL) 3344 itd->u.frame_list.next->u.frame_list.prev = itd; 3345 itd->slot = frindex; 3346 itd->u.frame_list.prev = NULL; 3347 3348 frindex += ival; 3349 if (frindex >= sc->sc_flsize) 3350 frindex -= sc->sc_flsize; 3351 } 3352 3353 epipe->u.isoc.cur_xfers++; 3354 epipe->u.isoc.next_frame = frindex; 3355 3356 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3357 xfer->status = USBD_IN_PROGRESS; 3358 xfer->done = 0; 3359 splx(s); 3360 3361 return (USBD_IN_PROGRESS); 3362 } 3363 3364 int 3365 ehci_alloc_itd_chain(struct ehci_softc *sc, struct usbd_xfer *xfer) 3366 { 3367 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3368 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3369 const uint32_t mps = UGETW(ed->wMaxPacketSize); 3370 struct ehci_soft_itd *itd = NULL, *pitd = NULL; 3371 int i, j, nframes, uframes, ufrperframe; 3372 int offs = 0, trans_count = 0; 3373 3374 /* 3375 * How many itds do we need? One per transfer if interval >= 8 3376 * microframes, fewer if we use multiple microframes per frame. 3377 */ 3378 switch (ed->bInterval) { 3379 case 1: 3380 ufrperframe = 8; 3381 break; 3382 case 2: 3383 ufrperframe = 4; 3384 break; 3385 case 3: 3386 ufrperframe = 2; 3387 break; 3388 default: 3389 ufrperframe = 1; 3390 break; 3391 } 3392 nframes = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3393 uframes = 8 / ufrperframe; 3394 if (nframes == 0) 3395 return (1); 3396 3397 for (i = 0; i < nframes; i++) { 3398 uint32_t froffs = offs; 3399 3400 itd = ehci_alloc_itd(sc); 3401 if (itd == NULL) { 3402 ehci_free_itd_chain(sc, ex); 3403 return (1); 3404 } 3405 3406 if (pitd != NULL) 3407 pitd->xfer_next = itd; 3408 else 3409 ex->itdstart = itd; 3410 3411 /* 3412 * Step 1.5, initialize uframes 3413 */ 3414 for (j = 0; j < 8; j += uframes) { 3415 /* Calculate which page in the list this starts in */ 3416 int addr = DMAADDR(&xfer->dmabuf, froffs); 3417 addr = EHCI_PAGE_OFFSET(addr) + (offs - froffs); 3418 addr = EHCI_PAGE(addr) / EHCI_PAGE_SIZE; 3419 3420 /* This gets the initial offset into the first page, 3421 * looks how far further along the current uframe 3422 * offset is. Works out how many pages that is. 3423 */ 3424 itd->itd.itd_ctl[j] = htole32( 3425 EHCI_ITD_ACTIVE | 3426 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3427 EHCI_ITD_SET_PG(addr) | 3428 EHCI_ITD_SET_OFFS(DMAADDR(&xfer->dmabuf, offs)) 3429 ); 3430 3431 offs += xfer->frlengths[trans_count]; 3432 trans_count++; 3433 3434 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3435 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3436 break; 3437 } 3438 } 3439 3440 /* Step 1.75, set buffer pointers. To simplify matters, all 3441 * pointers are filled out for the next 7 hardware pages in 3442 * the dma block, so no need to worry what pages to cover 3443 * and what to not. 3444 */ 3445 3446 for (j = 0; j < 7; j++) { 3447 /* 3448 * Don't try to lookup a page that's past the end 3449 * of buffer 3450 */ 3451 int page_offs = EHCI_PAGE(froffs + 3452 (EHCI_PAGE_SIZE * j)); 3453 3454 if (page_offs >= xfer->dmabuf.block->size) 3455 break; 3456 3457 long long page = DMAADDR(&xfer->dmabuf, page_offs); 3458 page = EHCI_PAGE(page); 3459 itd->itd.itd_bufr[j] = htole32(page); 3460 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 3461 } 3462 3463 /* 3464 * Other special values 3465 */ 3466 itd->itd.itd_bufr[0] |= htole32( 3467 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 3468 EHCI_ITD_SET_DADDR(xfer->pipe->device->address) 3469 ); 3470 3471 itd->itd.itd_bufr[1] |= htole32( 3472 (usbd_xfer_isread(xfer) ? EHCI_ITD_SET_DIR(1) : 0) | 3473 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(mps)) 3474 ); 3475 /* FIXME: handle invalid trans */ 3476 itd->itd.itd_bufr[2] |= htole32( 3477 EHCI_ITD_SET_MULTI(UE_GET_TRANS(mps)+1) 3478 ); 3479 3480 pitd = itd; 3481 } 3482 3483 ex->itdend = itd; 3484 3485 return (0); 3486 } 3487 3488 int 3489 ehci_alloc_sitd_chain(struct ehci_softc *sc, struct usbd_xfer *xfer) 3490 { 3491 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3492 struct usbd_device *hshub = xfer->device->myhsport->parent; 3493 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3494 struct ehci_soft_itd *itd = NULL, *pitd = NULL; 3495 uint8_t smask, cmask, tp, uf; 3496 int i, nframes, offs = 0; 3497 uint32_t endp; 3498 3499 nframes = xfer->nframes; 3500 if (nframes == 0) 3501 return (1); 3502 3503 endp = EHCI_SITD_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 3504 EHCI_SITD_SET_ADDR(xfer->device->address) | 3505 EHCI_SITD_SET_PORT(xfer->device->myhsport->portno) | 3506 EHCI_SITD_SET_HUBA(hshub->address); 3507 3508 if (usbd_xfer_isread(xfer)) 3509 endp |= EHCI_SITD_SET_DIR(1); 3510 3511 for (i = 0; i < nframes; i++) { 3512 uint32_t addr = DMAADDR(&xfer->dmabuf, offs); 3513 uint32_t page = EHCI_PAGE(addr + xfer->frlengths[i] - 1); 3514 3515 itd = ehci_alloc_itd(sc); 3516 if (itd == NULL) { 3517 ehci_free_itd_chain(sc, ex); 3518 return (1); 3519 } 3520 if (pitd) 3521 pitd->xfer_next = itd; 3522 else 3523 ex->itdstart = itd; 3524 3525 itd->sitd.sitd_endp = htole32(endp); 3526 itd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 3527 itd->sitd.sitd_trans = htole32( 3528 EHCI_SITD_ACTIVE | 3529 EHCI_SITD_SET_LEN(xfer->frlengths[i]) | 3530 ((i == nframes - 1) ? EHCI_SITD_IOC : 0) 3531 ); 3532 3533 uf = max(1, ((xfer->frlengths[i] + 187) / 188)); 3534 3535 /* 3536 * Since we do not yet budget and schedule micro-frames 3537 * we assume there is no other transfer using the same 3538 * TT. 3539 */ 3540 if (usbd_xfer_isread(xfer)) { 3541 smask = 0x01; 3542 cmask = ((1 << (uf + 2)) - 1) << 2; 3543 } else { 3544 /* Is the payload is greater than 188 bytes? */ 3545 if (uf == 1) 3546 tp = EHCI_SITD_TP_ALL; 3547 else 3548 tp = EHCI_SITD_TP_BEGIN; 3549 3550 page |= EHCI_SITD_SET_TCOUNT(uf) | EHCI_SITD_SET_TP(tp); 3551 smask = (1 << uf) - 1; 3552 cmask = 0x00; 3553 } 3554 3555 itd->sitd.sitd_sched = htole32( 3556 EHCI_SITD_SET_SMASK(smask) | EHCI_SITD_SET_CMASK(cmask) 3557 ); 3558 itd->sitd.sitd_bufr[0] = htole32(addr); 3559 itd->sitd.sitd_bufr[1] = htole32(page); 3560 3561 offs += xfer->frlengths[i]; 3562 pitd = itd; 3563 } 3564 3565 ex->itdend = itd; 3566 3567 return (0); 3568 } 3569 3570 void 3571 ehci_device_isoc_abort(struct usbd_xfer *xfer) 3572 { 3573 int s; 3574 3575 s = splusb(); 3576 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 3577 splx(s); 3578 } 3579 3580 void 3581 ehci_device_isoc_close(struct usbd_pipe *pipe) 3582 { 3583 } 3584 3585 void 3586 ehci_device_isoc_done(struct usbd_xfer *xfer) 3587 { 3588 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3589 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3590 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3591 int s; 3592 3593 s = splusb(); 3594 epipe->u.isoc.cur_xfers--; 3595 if (xfer->status != USBD_NOMEM) { 3596 ehci_rem_itd_chain(sc, ex); 3597 ehci_free_itd_chain(sc, ex); 3598 } 3599 splx(s); 3600 } 3601