1 /* $OpenBSD: ehci.c,v 1.99 2009/04/20 14:11:57 reyk Exp $ */ 2 /* $NetBSD: ehci.c,v 1.66 2004/06/30 03:11:56 mycroft Exp $ */ 3 4 /* 5 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and 10 * Jeremy Morse (jeremy.morse@gmail.com). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/usb_20.zip 41 */ 42 43 /* 44 * TODO: 45 * 1) The hub driver needs to handle and schedule the transaction translator, 46 * to assign place in frame where different devices get to go. See chapter 47 * on hubs in USB 2.0 for details. 48 * 49 * 2) Command failures are not recovered correctly. 50 */ 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/rwlock.h> 56 #include <sys/malloc.h> 57 #include <sys/device.h> 58 #include <sys/selinfo.h> 59 #include <sys/proc.h> 60 #include <sys/queue.h> 61 #include <sys/timeout.h> 62 63 #include <machine/bus.h> 64 #include <machine/endian.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 #include <dev/usb/usbdivar.h> 69 #include <dev/usb/usb_mem.h> 70 #include <dev/usb/usb_quirks.h> 71 72 #include <dev/usb/ehcireg.h> 73 #include <dev/usb/ehcivar.h> 74 75 #include <dev/rndvar.h> 76 77 struct cfdriver ehci_cd = { 78 NULL, "ehci", DV_DULL 79 }; 80 81 #ifdef EHCI_DEBUG 82 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 83 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 84 int ehcidebug = 0; 85 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n,x) 89 #endif 90 91 #define mstohz(ms) ((ms) * hz / 1000) 92 93 struct ehci_pipe { 94 struct usbd_pipe pipe; 95 96 ehci_soft_qh_t *sqh; 97 union { 98 ehci_soft_qtd_t *qtd; 99 /* ehci_soft_itd_t *itd; */ 100 } tail; 101 union { 102 /* Control pipe */ 103 struct { 104 usb_dma_t reqdma; 105 u_int length; 106 /*ehci_soft_qtd_t *setup, *data, *stat;*/ 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 u_int length; 111 } intr; 112 /* Bulk pipe */ 113 struct { 114 u_int length; 115 } bulk; 116 /* Iso pipe */ 117 struct { 118 u_int next_frame; 119 u_int cur_xfers; 120 } isoc; 121 } u; 122 }; 123 124 u_int8_t ehci_reverse_bits(u_int8_t, int); 125 126 void ehci_power(int, void *); 127 128 usbd_status ehci_open(usbd_pipe_handle); 129 void ehci_poll(struct usbd_bus *); 130 void ehci_softintr(void *); 131 int ehci_intr1(ehci_softc_t *); 132 void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 133 void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 134 void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 135 void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 136 void ehci_idone(struct ehci_xfer *); 137 void ehci_timeout(void *); 138 void ehci_timeout_task(void *); 139 void ehci_intrlist_timeout(void *); 140 141 usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 142 void ehci_freem(struct usbd_bus *, usb_dma_t *); 143 144 usbd_xfer_handle ehci_allocx(struct usbd_bus *); 145 void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 146 147 usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 148 usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 149 void ehci_root_ctrl_abort(usbd_xfer_handle); 150 void ehci_root_ctrl_close(usbd_pipe_handle); 151 void ehci_root_ctrl_done(usbd_xfer_handle); 152 153 usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 154 usbd_status ehci_root_intr_start(usbd_xfer_handle); 155 void ehci_root_intr_abort(usbd_xfer_handle); 156 void ehci_root_intr_close(usbd_pipe_handle); 157 void ehci_root_intr_done(usbd_xfer_handle); 158 159 usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 160 usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 161 void ehci_device_ctrl_abort(usbd_xfer_handle); 162 void ehci_device_ctrl_close(usbd_pipe_handle); 163 void ehci_device_ctrl_done(usbd_xfer_handle); 164 165 usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 166 usbd_status ehci_device_bulk_start(usbd_xfer_handle); 167 void ehci_device_bulk_abort(usbd_xfer_handle); 168 void ehci_device_bulk_close(usbd_pipe_handle); 169 void ehci_device_bulk_done(usbd_xfer_handle); 170 171 usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 172 usbd_status ehci_device_intr_start(usbd_xfer_handle); 173 void ehci_device_intr_abort(usbd_xfer_handle); 174 void ehci_device_intr_close(usbd_pipe_handle); 175 void ehci_device_intr_done(usbd_xfer_handle); 176 177 usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 178 usbd_status ehci_device_isoc_start(usbd_xfer_handle); 179 void ehci_device_isoc_abort(usbd_xfer_handle); 180 void ehci_device_isoc_close(usbd_pipe_handle); 181 void ehci_device_isoc_done(usbd_xfer_handle); 182 183 void ehci_device_clear_toggle(usbd_pipe_handle pipe); 184 void ehci_noop(usbd_pipe_handle pipe); 185 186 int ehci_str(usb_string_descriptor_t *, int, const char *); 187 void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 188 void ehci_disown(ehci_softc_t *, int, int); 189 190 ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 191 void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 192 193 ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 194 void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 195 usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 196 ehci_softc_t *, int, int, usbd_xfer_handle, 197 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 198 void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 199 ehci_soft_qtd_t *); 200 201 ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 202 void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 203 void ehci_rem_free_itd_chain(ehci_softc_t *sc, 204 struct ehci_xfer *exfer); 205 void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 206 usbd_status status); 207 208 usbd_status ehci_device_request(usbd_xfer_handle xfer); 209 210 usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 211 int ival); 212 213 void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 214 void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 215 ehci_soft_qh_t *); 216 void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 217 void ehci_sync_hc(ehci_softc_t *); 218 219 void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 220 void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 221 222 #ifdef EHCI_DEBUG 223 void ehci_dump_regs(ehci_softc_t *); 224 void ehci_dump(void); 225 ehci_softc_t *theehci; 226 void ehci_dump_link(ehci_link_t, int); 227 void ehci_dump_sqtds(ehci_soft_qtd_t *); 228 void ehci_dump_sqtd(ehci_soft_qtd_t *); 229 void ehci_dump_qtd(ehci_qtd_t *); 230 void ehci_dump_sqh(ehci_soft_qh_t *); 231 #if notyet 232 void ehci_dump_sitd(struct ehci_soft_itd *itd); 233 void ehci_dump_itd(struct ehci_soft_itd *); 234 #endif 235 #ifdef DIAGNOSTIC 236 void ehci_dump_exfer(struct ehci_xfer *); 237 #endif 238 #endif 239 240 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 241 242 #define EHCI_INTR_ENDPT 1 243 244 #define ehci_add_intr_list(sc, ex) \ 245 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 246 #define ehci_del_intr_list(sc, ex) \ 247 do { \ 248 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 249 (ex)->inext.tqe_prev = NULL; \ 250 } while (0) 251 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 252 253 struct usbd_bus_methods ehci_bus_methods = { 254 ehci_open, 255 ehci_softintr, 256 ehci_poll, 257 ehci_allocm, 258 ehci_freem, 259 ehci_allocx, 260 ehci_freex, 261 }; 262 263 struct usbd_pipe_methods ehci_root_ctrl_methods = { 264 ehci_root_ctrl_transfer, 265 ehci_root_ctrl_start, 266 ehci_root_ctrl_abort, 267 ehci_root_ctrl_close, 268 ehci_noop, 269 ehci_root_ctrl_done, 270 }; 271 272 struct usbd_pipe_methods ehci_root_intr_methods = { 273 ehci_root_intr_transfer, 274 ehci_root_intr_start, 275 ehci_root_intr_abort, 276 ehci_root_intr_close, 277 ehci_noop, 278 ehci_root_intr_done, 279 }; 280 281 struct usbd_pipe_methods ehci_device_ctrl_methods = { 282 ehci_device_ctrl_transfer, 283 ehci_device_ctrl_start, 284 ehci_device_ctrl_abort, 285 ehci_device_ctrl_close, 286 ehci_noop, 287 ehci_device_ctrl_done, 288 }; 289 290 struct usbd_pipe_methods ehci_device_intr_methods = { 291 ehci_device_intr_transfer, 292 ehci_device_intr_start, 293 ehci_device_intr_abort, 294 ehci_device_intr_close, 295 ehci_device_clear_toggle, 296 ehci_device_intr_done, 297 }; 298 299 struct usbd_pipe_methods ehci_device_bulk_methods = { 300 ehci_device_bulk_transfer, 301 ehci_device_bulk_start, 302 ehci_device_bulk_abort, 303 ehci_device_bulk_close, 304 ehci_device_clear_toggle, 305 ehci_device_bulk_done, 306 }; 307 308 struct usbd_pipe_methods ehci_device_isoc_methods = { 309 ehci_device_isoc_transfer, 310 ehci_device_isoc_start, 311 ehci_device_isoc_abort, 312 ehci_device_isoc_close, 313 ehci_noop, 314 ehci_device_isoc_done, 315 }; 316 317 /* 318 * Reverse a number with nbits bits. Used to evenly distribute lower-level 319 * interrupt heads in the periodic schedule. 320 * Suitable for use with EHCI_IPOLLRATES <= 9. 321 */ 322 u_int8_t 323 ehci_reverse_bits(u_int8_t c, int nbits) 324 { 325 c = ((c >> 1) & 0x55) | ((c << 1) & 0xaa); 326 c = ((c >> 2) & 0x33) | ((c << 2) & 0xcc); 327 c = ((c >> 4) & 0x0f) | ((c << 4) & 0xf0); 328 329 return c >> (8 - nbits); 330 } 331 332 usbd_status 333 ehci_init(ehci_softc_t *sc) 334 { 335 u_int32_t sparams, cparams, hcr; 336 u_int i, j; 337 usbd_status err; 338 ehci_soft_qh_t *sqh; 339 340 #ifdef EHCI_DEBUG 341 u_int32_t vers; 342 theehci = sc; 343 344 DPRINTF(("ehci_init: start\n")); 345 346 vers = EREAD2(sc, EHCI_HCIVERSION); 347 DPRINTF(("%s: EHCI version %x.%x\n", sc->sc_bus.bdev.dv_xname, 348 vers >> 8, vers & 0xff)); 349 #endif 350 351 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 352 353 sparams = EREAD4(sc, EHCI_HCSPARAMS); 354 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 355 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 356 cparams = EREAD4(sc, EHCI_HCCPARAMS); 357 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 358 359 /* MUST clear segment register if 64 bit capable. */ 360 if (EHCI_HCC_64BIT(cparams)) 361 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 362 363 sc->sc_bus.usbrev = USBREV_2_0; 364 365 /* Reset the controller */ 366 DPRINTF(("%s: resetting\n", sc->sc_bus.bdev.dv_xname)); 367 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 368 usb_delay_ms(&sc->sc_bus, 1); 369 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 370 for (i = 0; i < 100; i++) { 371 usb_delay_ms(&sc->sc_bus, 1); 372 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 373 if (!hcr) 374 break; 375 } 376 if (hcr) { 377 printf("%s: reset timeout\n", 378 sc->sc_bus.bdev.dv_xname); 379 return (USBD_IOERROR); 380 } 381 382 /* XXX need proper intr scheduling */ 383 sc->sc_rand = 96; 384 385 /* frame list size at default, read back what we got and use that */ 386 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 387 case 0: 388 sc->sc_flsize = 1024; 389 break; 390 case 1: 391 sc->sc_flsize = 512; 392 break; 393 case 2: 394 sc->sc_flsize = 256; 395 break; 396 case 3: 397 return (USBD_IOERROR); 398 } 399 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 400 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 401 if (err) 402 return (err); 403 DPRINTF(("%s: flsize=%d\n", sc->sc_bus.bdev.dv_xname,sc->sc_flsize)); 404 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 405 406 for (i = 0; i < sc->sc_flsize; i++) 407 sc->sc_flist[i] = EHCI_NULL; 408 409 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 410 411 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 412 M_USB, M_NOWAIT | M_ZERO); 413 if (sc->sc_softitds == NULL) 414 return (ENOMEM); 415 LIST_INIT(&sc->sc_freeitds); 416 TAILQ_INIT(&sc->sc_intrhead); 417 418 /* Set up the bus struct. */ 419 sc->sc_bus.methods = &ehci_bus_methods; 420 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 421 422 sc->sc_powerhook = powerhook_establish(ehci_power, sc); 423 424 sc->sc_eintrs = EHCI_NORMAL_INTRS; 425 426 /* 427 * Allocate the interrupt dummy QHs. These are arranged to give poll 428 * intervals that are powers of 2 times 1ms. 429 */ 430 for (i = 0; i < EHCI_INTRQHS; i++) { 431 sqh = ehci_alloc_sqh(sc); 432 if (sqh == NULL) { 433 err = USBD_NOMEM; 434 goto bad1; 435 } 436 sc->sc_islots[i].sqh = sqh; 437 } 438 for (i = 0; i < EHCI_INTRQHS; i++) { 439 sqh = sc->sc_islots[i].sqh; 440 if (i == 0) { 441 /* The last (1ms) QH terminates. */ 442 sqh->qh.qh_link = EHCI_NULL; 443 sqh->next = NULL; 444 } else { 445 /* Otherwise the next QH has half the poll interval */ 446 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 447 sqh->qh.qh_link = htole32(sqh->next->physaddr | 448 EHCI_LINK_QH); 449 } 450 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 451 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 452 sqh->qh.qh_curqtd = EHCI_NULL; 453 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 454 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 455 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 456 sqh->sqtd = NULL; 457 } 458 /* Point the frame list at the last level (128ms). */ 459 for (i = 0; i < (1 << (EHCI_IPOLLRATES - 1)); i++) 460 for (j = i; j < sc->sc_flsize; j += 1 << (EHCI_IPOLLRATES - 1)) 461 sc->sc_flist[j] = htole32(EHCI_LINK_QH | sc->sc_islots[ 462 EHCI_IQHIDX(EHCI_IPOLLRATES - 1, ehci_reverse_bits( 463 i, EHCI_IPOLLRATES - 1))].sqh->physaddr); 464 465 /* Allocate dummy QH that starts the async list. */ 466 sqh = ehci_alloc_sqh(sc); 467 if (sqh == NULL) { 468 err = USBD_NOMEM; 469 goto bad1; 470 } 471 /* Fill the QH */ 472 sqh->qh.qh_endp = 473 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 474 sqh->qh.qh_link = 475 htole32(sqh->physaddr | EHCI_LINK_QH); 476 sqh->qh.qh_curqtd = EHCI_NULL; 477 sqh->prev = sqh; /*It's a circular list.. */ 478 sqh->next = sqh; 479 /* Fill the overlay qTD */ 480 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 481 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 482 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 483 sqh->sqtd = NULL; 484 #ifdef EHCI_DEBUG 485 if (ehcidebug) 486 ehci_dump_sqh(sqh); 487 #endif 488 489 /* Point to async list */ 490 sc->sc_async_head = sqh; 491 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 492 493 timeout_set(&sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 494 495 rw_init(&sc->sc_doorbell_lock, "ehcidb"); 496 497 /* Turn on controller */ 498 EOWRITE4(sc, EHCI_USBCMD, 499 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 500 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 501 EHCI_CMD_ASE | 502 EHCI_CMD_PSE | 503 EHCI_CMD_RS); 504 505 /* Take over port ownership */ 506 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 507 508 for (i = 0; i < 100; i++) { 509 usb_delay_ms(&sc->sc_bus, 1); 510 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 511 if (!hcr) 512 break; 513 } 514 if (hcr) { 515 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 516 return (USBD_IOERROR); 517 } 518 519 /* Enable interrupts */ 520 DPRINTFN(1,("ehci_init: enabling\n")); 521 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 522 523 return (USBD_NORMAL_COMPLETION); 524 525 #if 0 526 bad2: 527 ehci_free_sqh(sc, sc->sc_async_head); 528 #endif 529 bad1: 530 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 531 return (err); 532 } 533 534 int 535 ehci_intr(void *v) 536 { 537 ehci_softc_t *sc = v; 538 539 if (sc == NULL || sc->sc_dying) 540 return (0); 541 542 /* If we get an interrupt while polling, then just ignore it. */ 543 if (sc->sc_bus.use_polling) { 544 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 545 546 if (intrs) 547 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 548 return (0); 549 } 550 551 return (ehci_intr1(sc)); 552 } 553 554 int 555 ehci_intr1(ehci_softc_t *sc) 556 { 557 u_int32_t intrs, eintrs; 558 559 DPRINTFN(20,("ehci_intr1: enter\n")); 560 561 /* In case the interrupt occurs before initialization has completed. */ 562 if (sc == NULL) { 563 #ifdef DIAGNOSTIC 564 printf("ehci_intr1: sc == NULL\n"); 565 #endif 566 return (0); 567 } 568 569 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 570 if (intrs == 0xffffffff) { 571 sc->sc_dying = 1; 572 return (0); 573 } 574 if (!intrs) 575 return (0); 576 577 eintrs = intrs & sc->sc_eintrs; 578 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 579 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), (u_int)eintrs)); 580 if (!eintrs) 581 return (0); 582 583 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 584 sc->sc_bus.intr_context++; 585 sc->sc_bus.no_intrs++; 586 if (eintrs & EHCI_STS_IAA) { 587 DPRINTF(("ehci_intr1: door bell\n")); 588 wakeup(&sc->sc_async_head); 589 eintrs &= ~EHCI_STS_IAA; 590 } 591 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 592 DPRINTFN(5,("ehci_intr1: %s %s\n", 593 eintrs & EHCI_STS_INT ? "INT" : "", 594 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 595 usb_schedsoftintr(&sc->sc_bus); 596 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 597 } 598 if (eintrs & EHCI_STS_HSE) { 599 printf("%s: unrecoverable error, controller halted\n", 600 sc->sc_bus.bdev.dv_xname); 601 /* XXX what else */ 602 } 603 if (eintrs & EHCI_STS_PCD) { 604 ehci_pcd(sc, sc->sc_intrxfer); 605 eintrs &= ~EHCI_STS_PCD; 606 } 607 608 sc->sc_bus.intr_context--; 609 610 if (eintrs != 0) { 611 /* Block unprocessed interrupts. */ 612 sc->sc_eintrs &= ~eintrs; 613 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 614 printf("%s: blocking intrs 0x%x\n", 615 sc->sc_bus.bdev.dv_xname, eintrs); 616 } 617 618 return (1); 619 } 620 621 void 622 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 623 { 624 u_char *p; 625 int i, m; 626 627 if (xfer == NULL) { 628 /* Just ignore the change. */ 629 return; 630 } 631 632 p = KERNADDR(&xfer->dmabuf, 0); 633 m = min(sc->sc_noport, xfer->length * 8 - 1); 634 memset(p, 0, xfer->length); 635 for (i = 1; i <= m; i++) { 636 /* Pick out CHANGE bits from the status reg. */ 637 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 638 p[i/8] |= 1 << (i%8); 639 } 640 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 641 xfer->actlen = xfer->length; 642 xfer->status = USBD_NORMAL_COMPLETION; 643 644 usb_transfer_complete(xfer); 645 } 646 647 void 648 ehci_softintr(void *v) 649 { 650 ehci_softc_t *sc = v; 651 struct ehci_xfer *ex, *nextex; 652 653 DPRINTFN(10,("%s: ehci_softintr (%d)\n", sc->sc_bus.bdev.dv_xname, 654 sc->sc_bus.intr_context)); 655 656 sc->sc_bus.intr_context++; 657 658 /* 659 * The only explanation I can think of for why EHCI is as brain dead 660 * as UHCI interrupt-wise is that Intel was involved in both. 661 * An interrupt just tells us that something is done, we have no 662 * clue what, so we need to scan through all active transfers. :-( 663 */ 664 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 665 nextex = TAILQ_NEXT(ex, inext); 666 ehci_check_intr(sc, ex); 667 } 668 669 /* Schedule a callout to catch any dropped transactions. */ 670 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 671 !TAILQ_EMPTY(&sc->sc_intrhead)) { 672 timeout_add_sec(&sc->sc_tmo_intrlist, 1); 673 } 674 675 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 676 if (sc->sc_softwake) { 677 sc->sc_softwake = 0; 678 wakeup(&sc->sc_softwake); 679 } 680 #endif /* __HAVE_GENERIC_SOFT_INTERRUPTS */ 681 682 sc->sc_bus.intr_context--; 683 } 684 685 /* Check for an interrupt. */ 686 void 687 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 688 { 689 int attr; 690 691 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 692 693 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 694 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 695 ehci_check_itd_intr(sc, ex); 696 else 697 ehci_check_qh_intr(sc, ex); 698 699 return; 700 } 701 702 void 703 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 704 { 705 ehci_soft_qtd_t *sqtd, *lsqtd; 706 __uint32_t status; 707 708 if (ex->sqtdstart == NULL) { 709 printf("ehci_check_qh_intr: not valid sqtd\n"); 710 return; 711 } 712 713 lsqtd = ex->sqtdend; 714 #ifdef DIAGNOSTIC 715 if (lsqtd == NULL) { 716 printf("ehci_check_qh_intr: lsqtd==0\n"); 717 return; 718 } 719 #endif 720 /* 721 * If the last TD is still active we need to check whether there 722 * is a an error somewhere in the middle, or whether there was a 723 * short packet (SPD and not ACTIVE). 724 */ 725 if (letoh32(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 726 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 727 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 728 status = letoh32(sqtd->qtd.qtd_status); 729 /* If there's an active QTD the xfer isn't done. */ 730 if (status & EHCI_QTD_ACTIVE) 731 break; 732 /* Any kind of error makes the xfer done. */ 733 if (status & EHCI_QTD_HALTED) 734 goto done; 735 /* We want short packets, and it is short: it's done */ 736 if (EHCI_QTD_GET_BYTES(status) != 0) 737 goto done; 738 } 739 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 740 ex, ex->sqtdstart)); 741 return; 742 } 743 done: 744 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 745 timeout_del(&ex->xfer.timeout_handle); 746 usb_rem_task(ex->xfer.pipe->device, &ex->abort_task); 747 ehci_idone(ex); 748 } 749 750 void 751 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 752 ehci_soft_itd_t *itd; 753 int i; 754 755 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 756 return; 757 758 if (ex->itdstart == NULL) { 759 printf("ehci_check_itd_intr: not valid itd\n"); 760 return; 761 } 762 763 itd = ex->itdend; 764 #ifdef DIAGNOSTIC 765 if (itd == NULL) { 766 printf("ehci_check_itd_intr: itdend == 0\n"); 767 return; 768 } 769 #endif 770 771 /* 772 * Step 1, check no active transfers in last itd, meaning we're finished 773 * check no active transfers in last itd, meaning we're finished 774 */ 775 for (i = 0; i < 8; i++) { 776 if (letoh32(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 777 break; 778 } 779 780 if (i == 8) { 781 goto done; /* All 8 descriptors inactive, it's done */ 782 } 783 784 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 785 ex->itdstart)); 786 return; 787 done: 788 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 789 timeout_del(&ex->xfer.timeout_handle); 790 ehci_idone(ex); 791 } 792 793 void 794 ehci_idone(struct ehci_xfer *ex) 795 { 796 usbd_xfer_handle xfer = &ex->xfer; 797 #ifdef EHCI_DEBUG 798 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 799 #endif 800 ehci_soft_qtd_t *sqtd, *lsqtd; 801 u_int32_t status = 0, nstatus = 0; 802 int actlen, cerr; 803 804 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 805 #ifdef DIAGNOSTIC 806 { 807 int s = splhigh(); 808 if (ex->isdone) { 809 splx(s); 810 #ifdef EHCI_DEBUG 811 printf("ehci_idone: ex is done!\n "); 812 ehci_dump_exfer(ex); 813 #else 814 printf("ehci_idone: ex=%p is done!\n", ex); 815 #endif 816 return; 817 } 818 ex->isdone = 1; 819 splx(s); 820 } 821 #endif 822 if (xfer->status == USBD_CANCELLED || 823 xfer->status == USBD_TIMEOUT) { 824 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 825 return; 826 } 827 828 #ifdef EHCI_DEBUG 829 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 830 if (ehcidebug > 10) 831 ehci_dump_sqtds(ex->sqtdstart); 832 #endif 833 834 /* The transfer is done, compute actual length and status. */ 835 836 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 837 == UE_ISOCHRONOUS) { 838 /* Isoc transfer */ 839 struct ehci_soft_itd *itd; 840 int i, nframes, len, uframes; 841 842 nframes = 0; 843 actlen = 0; 844 845 switch (xfer->pipe->endpoint->edesc->bInterval) { 846 case 0: 847 panic("ehci: isoc xfer suddenly has 0 bInterval, " 848 "invalid"); 849 case 1: 850 uframes = 1; 851 break; 852 case 2: 853 uframes = 2; 854 break; 855 case 3: 856 uframes = 4; 857 break; 858 default: 859 uframes = 8; 860 break; 861 } 862 863 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 864 for (i = 0; i < 8; i += uframes) { 865 /* XXX - driver didn't fill in the frame full 866 * of uframes. This leads to scheduling 867 * inefficiencies, but working around 868 * this doubles complexity of tracking 869 * an xfer. 870 */ 871 if (nframes >= xfer->nframes) 872 break; 873 874 status = letoh32(itd->itd.itd_ctl[i]); 875 len = EHCI_ITD_GET_LEN(status); 876 if (EHCI_ITD_GET_STATUS(status) != 0) 877 len = 0; /*No valid data on error*/ 878 879 xfer->frlengths[nframes++] = len; 880 actlen += len; 881 } 882 883 if (nframes >= xfer->nframes) 884 break; 885 } 886 887 xfer->actlen = actlen; 888 xfer->status = USBD_NORMAL_COMPLETION; 889 890 goto end; 891 } 892 893 /* Continue processing xfers using queue heads */ 894 895 lsqtd = ex->sqtdend; 896 actlen = 0; 897 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; 898 sqtd = sqtd->nextqtd) { 899 nstatus = letoh32(sqtd->qtd.qtd_status); 900 if (nstatus & EHCI_QTD_ACTIVE) 901 break; 902 903 status = nstatus; 904 /* halt is ok if descriptor is last, and complete */ 905 if (sqtd->qtd.qtd_next == EHCI_NULL && 906 EHCI_QTD_GET_BYTES(status) == 0) 907 status &= ~EHCI_QTD_HALTED; 908 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 909 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 910 } 911 912 cerr = EHCI_QTD_GET_CERR(status); 913 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 914 "status=0x%x\n", xfer->length, actlen, cerr, status)); 915 xfer->actlen = actlen; 916 if ((status & EHCI_QTD_HALTED) != 0) { 917 #ifdef EHCI_DEBUG 918 char sbuf[128]; 919 920 bitmask_snprintf((u_int32_t)status, 921 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 922 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 923 924 DPRINTFN(2, 925 ("ehci_idone: error, addr=%d, endpt=0x%02x, " 926 "status 0x%s\n", 927 xfer->pipe->device->address, 928 xfer->pipe->endpoint->edesc->bEndpointAddress, 929 sbuf)); 930 if (ehcidebug > 2) { 931 ehci_dump_sqh(epipe->sqh); 932 ehci_dump_sqtds(ex->sqtdstart); 933 } 934 #endif 935 if ((status & EHCI_QTD_BABBLE) == 0 && cerr > 0) 936 xfer->status = USBD_STALLED; 937 else 938 xfer->status = USBD_IOERROR; /* more info XXX */ 939 } else 940 xfer->status = USBD_NORMAL_COMPLETION; 941 end: 942 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 943 * during this call, before methods->done is called: dma sync required 944 * beforehand? */ 945 usb_transfer_complete(xfer); 946 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 947 } 948 949 /* 950 * Wait here until controller claims to have an interrupt. 951 * Then call ehci_intr and return. Use timeout to avoid waiting 952 * too long. 953 */ 954 void 955 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 956 { 957 int timo; 958 u_int32_t intrs; 959 960 xfer->status = USBD_IN_PROGRESS; 961 for (timo = xfer->timeout; timo >= 0; timo--) { 962 usb_delay_ms(&sc->sc_bus, 1); 963 if (sc->sc_dying) 964 break; 965 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 966 sc->sc_eintrs; 967 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 968 #ifdef EHCI_DEBUG 969 if (ehcidebug > 15) 970 ehci_dump_regs(sc); 971 #endif 972 if (intrs) { 973 ehci_intr1(sc); 974 if (xfer->status != USBD_IN_PROGRESS) 975 return; 976 } 977 } 978 979 /* Timeout */ 980 DPRINTF(("ehci_waitintr: timeout\n")); 981 xfer->status = USBD_TIMEOUT; 982 usb_transfer_complete(xfer); 983 /* XXX should free TD */ 984 } 985 986 void 987 ehci_poll(struct usbd_bus *bus) 988 { 989 ehci_softc_t *sc = (ehci_softc_t *)bus; 990 #ifdef EHCI_DEBUG 991 static int last; 992 int new; 993 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 994 if (new != last) { 995 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 996 last = new; 997 } 998 #endif 999 1000 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1001 ehci_intr1(sc); 1002 } 1003 1004 int 1005 ehci_detach(struct ehci_softc *sc, int flags) 1006 { 1007 int rv = 0; 1008 1009 if (sc->sc_child != NULL) 1010 rv = config_detach(sc->sc_child, flags); 1011 1012 if (rv != 0) 1013 return (rv); 1014 1015 timeout_del(&sc->sc_tmo_intrlist); 1016 1017 if (sc->sc_powerhook != NULL) 1018 powerhook_disestablish(sc->sc_powerhook); 1019 if (sc->sc_shutdownhook != NULL) 1020 shutdownhook_disestablish(sc->sc_shutdownhook); 1021 1022 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1023 1024 /* XXX free other data structures XXX */ 1025 1026 return (rv); 1027 } 1028 1029 1030 int 1031 ehci_activate(struct device *self, enum devact act) 1032 { 1033 struct ehci_softc *sc = (struct ehci_softc *)self; 1034 int rv = 0; 1035 1036 switch (act) { 1037 case DVACT_ACTIVATE: 1038 break; 1039 1040 case DVACT_DEACTIVATE: 1041 if (sc->sc_child != NULL) 1042 rv = config_deactivate(sc->sc_child); 1043 sc->sc_dying = 1; 1044 break; 1045 } 1046 return (rv); 1047 } 1048 1049 /* 1050 * Handle suspend/resume. 1051 * 1052 * We need to switch to polling mode here, because this routine is 1053 * called from an interrupt context. This is all right since we 1054 * are almost suspended anyway. 1055 */ 1056 void 1057 ehci_power(int why, void *v) 1058 { 1059 ehci_softc_t *sc = v; 1060 u_int32_t cmd, hcr; 1061 int s, i; 1062 1063 #ifdef EHCI_DEBUG 1064 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why)); 1065 if (ehcidebug > 0) 1066 ehci_dump_regs(sc); 1067 #endif 1068 1069 s = splhardusb(); 1070 switch (why) { 1071 case PWR_SUSPEND: 1072 case PWR_STANDBY: 1073 sc->sc_bus.use_polling++; 1074 1075 for (i = 1; i <= sc->sc_noport; i++) { 1076 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1077 if ((cmd & (EHCI_PS_PO|EHCI_PS_PE)) == EHCI_PS_PE) 1078 EOWRITE4(sc, EHCI_PORTSC(i), 1079 cmd | EHCI_PS_SUSP); 1080 } 1081 1082 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1083 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1084 EOWRITE4(sc, EHCI_USBCMD, cmd); 1085 1086 for (i = 0; i < 100; i++) { 1087 hcr = EOREAD4(sc, EHCI_USBSTS) & 1088 (EHCI_STS_ASS | EHCI_STS_PSS); 1089 if (hcr == 0) 1090 break; 1091 1092 usb_delay_ms(&sc->sc_bus, 1); 1093 } 1094 if (hcr != 0) 1095 printf("%s: reset timeout\n", 1096 sc->sc_bus.bdev.dv_xname); 1097 1098 cmd &= ~EHCI_CMD_RS; 1099 EOWRITE4(sc, EHCI_USBCMD, cmd); 1100 1101 for (i = 0; i < 100; i++) { 1102 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1103 if (hcr == EHCI_STS_HCH) 1104 break; 1105 1106 usb_delay_ms(&sc->sc_bus, 1); 1107 } 1108 if (hcr != EHCI_STS_HCH) 1109 printf("%s: config timeout\n", 1110 sc->sc_bus.bdev.dv_xname); 1111 1112 sc->sc_bus.use_polling--; 1113 break; 1114 1115 case PWR_RESUME: 1116 sc->sc_bus.use_polling++; 1117 1118 /* restore things in case the bios sucks */ 1119 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1120 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1121 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1122 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1123 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1124 1125 hcr = 0; 1126 for (i = 1; i <= sc->sc_noport; i++) { 1127 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1128 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == EHCI_PS_SUSP) { 1129 EOWRITE4(sc, EHCI_PORTSC(i), 1130 cmd | EHCI_PS_FPR); 1131 hcr = 1; 1132 } 1133 } 1134 1135 if (hcr) { 1136 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1137 for (i = 1; i <= sc->sc_noport; i++) { 1138 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1139 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == 1140 EHCI_PS_SUSP) 1141 EOWRITE4(sc, EHCI_PORTSC(i), 1142 cmd & ~EHCI_PS_FPR); 1143 } 1144 } 1145 1146 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1147 1148 /* Take over port ownership */ 1149 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 1150 1151 for (i = 0; i < 100; i++) { 1152 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1153 if (hcr != EHCI_STS_HCH) 1154 break; 1155 1156 usb_delay_ms(&sc->sc_bus, 1); 1157 } 1158 if (hcr == EHCI_STS_HCH) 1159 printf("%s: config timeout\n", 1160 sc->sc_bus.bdev.dv_xname); 1161 1162 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1163 1164 sc->sc_bus.use_polling--; 1165 break; 1166 } 1167 splx(s); 1168 1169 #ifdef EHCI_DEBUG 1170 DPRINTF(("ehci_power: sc=%p\n", sc)); 1171 if (ehcidebug > 0) 1172 ehci_dump_regs(sc); 1173 #endif 1174 } 1175 1176 /* 1177 * Shut down the controller when the system is going down. 1178 */ 1179 void 1180 ehci_shutdown(void *v) 1181 { 1182 ehci_softc_t *sc = v; 1183 1184 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1185 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1186 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1187 } 1188 1189 usbd_status 1190 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1191 { 1192 struct ehci_softc *sc = (struct ehci_softc *)bus; 1193 usbd_status err; 1194 1195 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1196 #ifdef EHCI_DEBUG 1197 if (err) 1198 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1199 #endif 1200 return (err); 1201 } 1202 1203 void 1204 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1205 { 1206 struct ehci_softc *sc = (struct ehci_softc *)bus; 1207 1208 usb_freemem(&sc->sc_bus, dma); 1209 } 1210 1211 usbd_xfer_handle 1212 ehci_allocx(struct usbd_bus *bus) 1213 { 1214 struct ehci_softc *sc = (struct ehci_softc *)bus; 1215 usbd_xfer_handle xfer; 1216 1217 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1218 if (xfer != NULL) { 1219 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1220 #ifdef DIAGNOSTIC 1221 if (xfer->busy_free != XFER_FREE) 1222 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", 1223 xfer, xfer->busy_free); 1224 #endif 1225 } else 1226 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1227 1228 if (xfer != NULL) { 1229 memset(xfer, 0, sizeof(struct ehci_xfer)); 1230 usb_init_task(&EXFER(xfer)->abort_task, ehci_timeout_task, 1231 xfer); 1232 EXFER(xfer)->ehci_xfer_flags = 0; 1233 #ifdef DIAGNOSTIC 1234 EXFER(xfer)->isdone = 1; 1235 xfer->busy_free = XFER_BUSY; 1236 #endif 1237 } 1238 return (xfer); 1239 } 1240 1241 void 1242 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1243 { 1244 struct ehci_softc *sc = (struct ehci_softc *)bus; 1245 1246 #ifdef DIAGNOSTIC 1247 if (xfer->busy_free != XFER_BUSY) { 1248 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1249 xfer->busy_free); 1250 return; 1251 } 1252 xfer->busy_free = XFER_FREE; 1253 if (!EXFER(xfer)->isdone) { 1254 printf("ehci_freex: !isdone\n"); 1255 return; 1256 } 1257 #endif 1258 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1259 } 1260 1261 void 1262 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1263 { 1264 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1265 1266 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1267 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1268 #if defined(EHCI_DEBUG) && defined(USB_DEBUG) 1269 if (ehcidebug) 1270 usbd_dump_pipe(pipe); 1271 #endif 1272 #ifdef DIAGNOSTIC 1273 if ((epipe->sqh->qh.qh_qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) != 0) 1274 panic("ehci_device_clear_toggle: queue active"); 1275 #endif 1276 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1277 } 1278 1279 void 1280 ehci_noop(usbd_pipe_handle pipe) 1281 { 1282 } 1283 1284 #ifdef EHCI_DEBUG 1285 void 1286 ehci_dump_regs(ehci_softc_t *sc) 1287 { 1288 int i; 1289 1290 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1291 EOREAD4(sc, EHCI_USBCMD), 1292 EOREAD4(sc, EHCI_USBSTS), 1293 EOREAD4(sc, EHCI_USBINTR)); 1294 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1295 EOREAD4(sc, EHCI_FRINDEX), 1296 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1297 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1298 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1299 for (i = 1; i <= sc->sc_noport; i++) 1300 printf("port %d status=0x%08x\n", i, 1301 EOREAD4(sc, EHCI_PORTSC(i))); 1302 } 1303 1304 /* 1305 * Unused function - this is meant to be called from a kernel 1306 * debugger. 1307 */ 1308 void 1309 ehci_dump() 1310 { 1311 ehci_dump_regs(theehci); 1312 } 1313 1314 void 1315 ehci_dump_link(ehci_link_t link, int type) 1316 { 1317 link = letoh32(link); 1318 printf("0x%08x", link); 1319 if (link & EHCI_LINK_TERMINATE) 1320 printf("<T>"); 1321 else { 1322 printf("<"); 1323 if (type) { 1324 switch (EHCI_LINK_TYPE(link)) { 1325 case EHCI_LINK_ITD: 1326 printf("ITD"); 1327 break; 1328 case EHCI_LINK_QH: 1329 printf("QH"); 1330 break; 1331 case EHCI_LINK_SITD: 1332 printf("SITD"); 1333 break; 1334 case EHCI_LINK_FSTN: 1335 printf("FSTN"); 1336 break; 1337 } 1338 } 1339 printf(">"); 1340 } 1341 } 1342 1343 void 1344 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1345 { 1346 int i; 1347 u_int32_t stop; 1348 1349 stop = 0; 1350 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1351 ehci_dump_sqtd(sqtd); 1352 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1353 } 1354 if (!stop) 1355 printf("dump aborted, too many TDs\n"); 1356 } 1357 1358 void 1359 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1360 { 1361 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1362 ehci_dump_qtd(&sqtd->qtd); 1363 } 1364 1365 void 1366 ehci_dump_qtd(ehci_qtd_t *qtd) 1367 { 1368 u_int32_t s; 1369 char sbuf[128]; 1370 1371 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1372 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1373 printf("\n"); 1374 s = letoh32(qtd->qtd_status); 1375 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), "\20\10ACTIVE\7HALTED" 1376 "\6BUFERR\5BABBLE\4XACTERR\3MISSED\2SPLIT\1PING", 1377 sbuf, sizeof(sbuf)); 1378 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1379 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1380 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1381 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1382 EHCI_QTD_GET_PID(s), sbuf); 1383 for (s = 0; s < 5; s++) 1384 printf(" buffer[%d]=0x%08x\n", s, letoh32(qtd->qtd_buffer[s])); 1385 } 1386 1387 void 1388 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1389 { 1390 ehci_qh_t *qh = &sqh->qh; 1391 u_int32_t endp, endphub; 1392 1393 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1394 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1395 endp = letoh32(qh->qh_endp); 1396 printf(" endp=0x%08x\n", endp); 1397 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1398 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1399 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1400 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1401 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1402 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1403 EHCI_QH_GET_NRL(endp)); 1404 endphub = letoh32(qh->qh_endphub); 1405 printf(" endphub=0x%08x\n", endphub); 1406 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1407 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1408 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1409 EHCI_QH_GET_MULT(endphub)); 1410 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1411 printf("Overlay qTD:\n"); 1412 ehci_dump_qtd(&qh->qh_qtd); 1413 } 1414 1415 #if notyet 1416 void 1417 ehci_dump_itd(struct ehci_soft_itd *itd) 1418 { 1419 ehci_isoc_trans_t t; 1420 ehci_isoc_bufr_ptr_t b, b2, b3; 1421 int i; 1422 1423 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1424 1425 for (i = 0; i < 8;i++) { 1426 t = letoh32(itd->itd.itd_ctl[i]); 1427 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1428 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1429 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1430 EHCI_ITD_GET_OFFS(t)); 1431 } 1432 printf("ITDbufr: "); 1433 for (i = 0; i < 7; i++) 1434 printf("%X,", EHCI_ITD_GET_BPTR(letoh32(itd->itd.itd_bufr[i]))); 1435 1436 b = letoh32(itd->itd.itd_bufr[0]); 1437 b2 = letoh32(itd->itd.itd_bufr[1]); 1438 b3 = letoh32(itd->itd.itd_bufr[2]); 1439 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1440 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1441 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1442 } 1443 1444 void 1445 ehci_dump_sitd(struct ehci_soft_itd *itd) 1446 { 1447 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1448 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1449 itd->xfer_next, itd->physaddr, itd->slot); 1450 } 1451 #endif 1452 1453 #ifdef DIAGNOSTIC 1454 void 1455 ehci_dump_exfer(struct ehci_xfer *ex) 1456 { 1457 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p " 1458 "isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, 1459 ex->itdend, ex->isdone); 1460 } 1461 #endif 1462 1463 #endif /* EHCI_DEBUG */ 1464 1465 usbd_status 1466 ehci_open(usbd_pipe_handle pipe) 1467 { 1468 usbd_device_handle dev = pipe->device; 1469 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1470 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1471 u_int8_t addr = dev->address; 1472 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1473 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1474 ehci_soft_qh_t *sqh; 1475 usbd_status err; 1476 int s; 1477 int ival, speed, naks; 1478 int hshubaddr, hshubport; 1479 1480 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1481 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1482 1483 if (sc->sc_dying) 1484 return (USBD_IOERROR); 1485 1486 if (dev->myhsport) { 1487 hshubaddr = dev->myhsport->parent->address; 1488 hshubport = dev->myhsport->portno; 1489 } else { 1490 hshubaddr = 0; 1491 hshubport = 0; 1492 } 1493 1494 if (addr == sc->sc_addr) { 1495 switch (ed->bEndpointAddress) { 1496 case USB_CONTROL_ENDPOINT: 1497 pipe->methods = &ehci_root_ctrl_methods; 1498 break; 1499 case UE_DIR_IN | EHCI_INTR_ENDPT: 1500 pipe->methods = &ehci_root_intr_methods; 1501 break; 1502 default: 1503 return (USBD_INVAL); 1504 } 1505 return (USBD_NORMAL_COMPLETION); 1506 } 1507 1508 /* XXX All this stuff is only valid for async. */ 1509 switch (dev->speed) { 1510 case USB_SPEED_LOW: 1511 speed = EHCI_QH_SPEED_LOW; 1512 break; 1513 case USB_SPEED_FULL: 1514 speed = EHCI_QH_SPEED_FULL; 1515 break; 1516 case USB_SPEED_HIGH: 1517 speed = EHCI_QH_SPEED_HIGH; 1518 break; 1519 default: 1520 panic("ehci_open: bad device speed %d", dev->speed); 1521 } 1522 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1523 printf("%s: Error opening low/full speed isoc endpoint.\n" 1524 "A low/full speed device is attached to a USB2 hub, and " 1525 "transaction translations are not yet supported.\n" 1526 "Reattach the device to the root hub instead.\n", 1527 sc->sc_bus.bdev.dv_xname); 1528 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1529 hshubaddr, hshubport)); 1530 return (USBD_INVAL); 1531 } 1532 1533 naks = 8; /* XXX */ 1534 1535 /* Allocate sqh for everything, save isoc xfers */ 1536 if (xfertype != UE_ISOCHRONOUS) { 1537 sqh = ehci_alloc_sqh(sc); 1538 if (sqh == NULL) 1539 return (USBD_NOMEM); 1540 /* qh_link filled when the QH is added */ 1541 sqh->qh.qh_endp = htole32( 1542 EHCI_QH_SET_ADDR(addr) | 1543 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1544 EHCI_QH_SET_EPS(speed) | 1545 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1546 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1547 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1548 EHCI_QH_CTL : 0) | 1549 EHCI_QH_SET_NRL(naks) 1550 ); 1551 sqh->qh.qh_endphub = htole32( 1552 EHCI_QH_SET_MULT(1) | 1553 EHCI_QH_SET_HUBA(hshubaddr) | 1554 EHCI_QH_SET_PORT(hshubport) | 1555 EHCI_QH_SET_CMASK(0x1c) | /* XXX */ 1556 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0) 1557 ); 1558 sqh->qh.qh_curqtd = EHCI_NULL; 1559 /* Fill the overlay qTD */ 1560 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1561 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1562 sqh->qh.qh_qtd.qtd_status = 1563 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1564 epipe->sqh = sqh; 1565 } else { 1566 sqh = NULL; 1567 } /*xfertype == UE_ISOC*/ 1568 1569 switch (xfertype) { 1570 case UE_CONTROL: 1571 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1572 0, &epipe->u.ctl.reqdma); 1573 #ifdef EHCI_DEBUG 1574 if (err) 1575 printf("ehci_open: usb_allocmem()=%d\n", err); 1576 #endif 1577 if (err) 1578 goto bad; 1579 pipe->methods = &ehci_device_ctrl_methods; 1580 s = splusb(); 1581 ehci_add_qh(sqh, sc->sc_async_head); 1582 splx(s); 1583 break; 1584 case UE_BULK: 1585 pipe->methods = &ehci_device_bulk_methods; 1586 s = splusb(); 1587 ehci_add_qh(sqh, sc->sc_async_head); 1588 splx(s); 1589 break; 1590 case UE_INTERRUPT: 1591 pipe->methods = &ehci_device_intr_methods; 1592 ival = pipe->interval; 1593 if (ival == USBD_DEFAULT_INTERVAL) 1594 ival = ed->bInterval; 1595 return (ehci_device_setintr(sc, sqh, ival)); 1596 case UE_ISOCHRONOUS: 1597 pipe->methods = &ehci_device_isoc_methods; 1598 if (ed->bInterval == 0 || ed->bInterval > 16) { 1599 printf("ehci: opening pipe with invalid bInterval\n"); 1600 err = USBD_INVAL; 1601 goto bad; 1602 } 1603 if (UGETW(ed->wMaxPacketSize) == 0) { 1604 printf("ehci: zero length endpoint open request\n"); 1605 err = USBD_INVAL; 1606 goto bad; 1607 } 1608 epipe->u.isoc.next_frame = 0; 1609 epipe->u.isoc.cur_xfers = 0; 1610 break; 1611 default: 1612 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1613 return (USBD_INVAL); 1614 } 1615 return (USBD_NORMAL_COMPLETION); 1616 1617 bad: 1618 if (sqh != NULL) 1619 ehci_free_sqh(sc, sqh); 1620 return (err); 1621 } 1622 1623 /* 1624 * Add an ED to the schedule. Called at splusb(). 1625 * If in the async schedule, it will always have a next. 1626 * If in the intr schedule it may not. 1627 */ 1628 void 1629 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1630 { 1631 SPLUSBCHECK; 1632 1633 sqh->next = head->next; 1634 sqh->prev = head; 1635 sqh->qh.qh_link = head->qh.qh_link; 1636 head->next = sqh; 1637 if (sqh->next) 1638 sqh->next->prev = sqh; 1639 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1640 1641 #ifdef EHCI_DEBUG 1642 if (ehcidebug > 5) { 1643 printf("ehci_add_qh:\n"); 1644 ehci_dump_sqh(sqh); 1645 } 1646 #endif 1647 } 1648 1649 /* 1650 * Remove an ED from the schedule. Called at splusb(). 1651 * Will always have a 'next' if it's in the async list as it's circular. 1652 */ 1653 void 1654 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1655 { 1656 SPLUSBCHECK; 1657 /* XXX */ 1658 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1659 sqh->prev->next = sqh->next; 1660 if (sqh->next) 1661 sqh->next->prev = sqh->prev; 1662 ehci_sync_hc(sc); 1663 } 1664 1665 void 1666 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1667 { 1668 int i; 1669 u_int32_t status; 1670 1671 /* Save toggle bit and ping status. */ 1672 status = sqh->qh.qh_qtd.qtd_status & 1673 htole32(EHCI_QTD_TOGGLE_MASK | 1674 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1675 /* Set HALTED to make hw leave it alone. */ 1676 sqh->qh.qh_qtd.qtd_status = 1677 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1678 sqh->qh.qh_curqtd = 0; 1679 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1680 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1681 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1682 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1683 sqh->sqtd = sqtd; 1684 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1685 sqh->qh.qh_qtd.qtd_status = status; 1686 } 1687 1688 /* 1689 * Ensure that the HC has released all references to the QH. We do this 1690 * by asking for a Async Advance Doorbell interrupt and then we wait for 1691 * the interrupt. 1692 * To make this easier we first obtain exclusive use of the doorbell. 1693 */ 1694 void 1695 ehci_sync_hc(ehci_softc_t *sc) 1696 { 1697 int s, error; 1698 int tries = 0; 1699 1700 if (sc->sc_dying) { 1701 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1702 return; 1703 } 1704 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1705 /* get doorbell */ 1706 rw_enter_write(&sc->sc_doorbell_lock); 1707 s = splhardusb(); 1708 do { 1709 /* ask for doorbell */ 1710 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | 1711 EHCI_CMD_IAAD); 1712 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1713 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1714 /* bell wait */ 1715 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz / 2); 1716 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1717 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1718 } while (error && ++tries < 10); 1719 splx(s); 1720 /* release doorbell */ 1721 rw_exit_write(&sc->sc_doorbell_lock); 1722 #ifdef DIAGNOSTIC 1723 if (error) 1724 printf("ehci_sync_hc: tsleep() = %d\n", error); 1725 #endif 1726 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1727 } 1728 1729 /*Call at splusb*/ 1730 void 1731 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1732 { 1733 struct ehci_soft_itd *itd, *prev; 1734 1735 prev = NULL; 1736 1737 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1738 panic("ehci isoc xfer being freed, but with no itd chain"); 1739 1740 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1741 prev = itd->u.frame_list.prev; 1742 /* Unlink itd from hardware chain, or frame array */ 1743 if (prev == NULL) { /* We're at the table head */ 1744 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1745 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1746 1747 if (itd->u.frame_list.next != NULL) 1748 itd->u.frame_list.next->u.frame_list.prev = 1749 NULL; 1750 } else { 1751 /* XXX this part is untested... */ 1752 prev->itd.itd_next = itd->itd.itd_next; 1753 prev->u.frame_list.next = itd->u.frame_list.next; 1754 if (itd->u.frame_list.next != NULL) 1755 itd->u.frame_list.next->u.frame_list.prev = 1756 prev; 1757 } 1758 } 1759 1760 prev = NULL; 1761 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1762 if (prev != NULL) 1763 ehci_free_itd(sc, prev); 1764 prev = itd; 1765 } 1766 if (prev) 1767 ehci_free_itd(sc, prev); 1768 exfer->itdstart = NULL; 1769 exfer->itdend = NULL; 1770 } 1771 1772 /***********/ 1773 1774 /* 1775 * Data structures and routines to emulate the root hub. 1776 */ 1777 usb_device_descriptor_t ehci_devd = { 1778 USB_DEVICE_DESCRIPTOR_SIZE, 1779 UDESC_DEVICE, /* type */ 1780 {0x00, 0x02}, /* USB version */ 1781 UDCLASS_HUB, /* class */ 1782 UDSUBCLASS_HUB, /* subclass */ 1783 UDPROTO_HSHUBSTT, /* protocol */ 1784 64, /* max packet */ 1785 {0},{0},{0x00,0x01}, /* device id */ 1786 1,2,0, /* string indicies */ 1787 1 /* # of configurations */ 1788 }; 1789 1790 usb_device_qualifier_t ehci_odevd = { 1791 USB_DEVICE_DESCRIPTOR_SIZE, 1792 UDESC_DEVICE_QUALIFIER, /* type */ 1793 {0x00, 0x02}, /* USB version */ 1794 UDCLASS_HUB, /* class */ 1795 UDSUBCLASS_HUB, /* subclass */ 1796 UDPROTO_FSHUB, /* protocol */ 1797 64, /* max packet */ 1798 1, /* # of configurations */ 1799 0 1800 }; 1801 1802 usb_config_descriptor_t ehci_confd = { 1803 USB_CONFIG_DESCRIPTOR_SIZE, 1804 UDESC_CONFIG, 1805 {USB_CONFIG_DESCRIPTOR_SIZE + 1806 USB_INTERFACE_DESCRIPTOR_SIZE + 1807 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1808 1, 1809 1, 1810 0, 1811 UC_SELF_POWERED, 1812 0 /* max power */ 1813 }; 1814 1815 usb_interface_descriptor_t ehci_ifcd = { 1816 USB_INTERFACE_DESCRIPTOR_SIZE, 1817 UDESC_INTERFACE, 1818 0, 1819 0, 1820 1, 1821 UICLASS_HUB, 1822 UISUBCLASS_HUB, 1823 UIPROTO_HSHUBSTT, 1824 0 1825 }; 1826 1827 usb_endpoint_descriptor_t ehci_endpd = { 1828 USB_ENDPOINT_DESCRIPTOR_SIZE, 1829 UDESC_ENDPOINT, 1830 UE_DIR_IN | EHCI_INTR_ENDPT, 1831 UE_INTERRUPT, 1832 {8, 0}, /* max packet */ 1833 255 1834 }; 1835 1836 usb_hub_descriptor_t ehci_hubd = { 1837 USB_HUB_DESCRIPTOR_SIZE, 1838 UDESC_HUB, 1839 0, 1840 {0,0}, 1841 0, 1842 0, 1843 {0}, 1844 }; 1845 1846 int 1847 ehci_str(usb_string_descriptor_t *p, int l, const char *s) 1848 { 1849 int i; 1850 1851 if (l == 0) 1852 return (0); 1853 p->bLength = 2 * strlen(s) + 2; 1854 if (l == 1) 1855 return (1); 1856 p->bDescriptorType = UDESC_STRING; 1857 l -= 2; 1858 for (i = 0; s[i] && l > 1; i++, l -= 2) 1859 USETW2(p->bString[i], 0, s[i]); 1860 return (2*i+2); 1861 } 1862 1863 /* 1864 * Simulate a hardware hub by handling all the necessary requests. 1865 */ 1866 usbd_status 1867 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1868 { 1869 usbd_status err; 1870 1871 /* Insert last in queue. */ 1872 err = usb_insert_transfer(xfer); 1873 if (err) 1874 return (err); 1875 1876 /* Pipe isn't running, start first */ 1877 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1878 } 1879 1880 usbd_status 1881 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1882 { 1883 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 1884 usb_device_request_t *req; 1885 void *buf = NULL; 1886 int port, i; 1887 int s, len, value, index, l, totlen = 0; 1888 usb_port_status_t ps; 1889 usb_hub_descriptor_t hubd; 1890 usbd_status err; 1891 u_int32_t v; 1892 1893 if (sc->sc_dying) 1894 return (USBD_IOERROR); 1895 1896 #ifdef DIAGNOSTIC 1897 if (!(xfer->rqflags & URQ_REQUEST)) 1898 /* XXX panic */ 1899 return (USBD_INVAL); 1900 #endif 1901 req = &xfer->request; 1902 1903 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1904 req->bmRequestType, req->bRequest)); 1905 1906 len = UGETW(req->wLength); 1907 value = UGETW(req->wValue); 1908 index = UGETW(req->wIndex); 1909 1910 if (len != 0) 1911 buf = KERNADDR(&xfer->dmabuf, 0); 1912 1913 #define C(x,y) ((x) | ((y) << 8)) 1914 switch(C(req->bRequest, req->bmRequestType)) { 1915 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1916 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1917 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1918 /* 1919 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1920 * for the integrated root hub. 1921 */ 1922 break; 1923 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1924 if (len > 0) { 1925 *(u_int8_t *)buf = sc->sc_conf; 1926 totlen = 1; 1927 } 1928 break; 1929 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1930 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1931 switch(value >> 8) { 1932 case UDESC_DEVICE: 1933 if ((value & 0xff) != 0) { 1934 err = USBD_IOERROR; 1935 goto ret; 1936 } 1937 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1938 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1939 memcpy(buf, &ehci_devd, l); 1940 break; 1941 /* 1942 * We can't really operate at another speed, but the spec says 1943 * we need this descriptor. 1944 */ 1945 case UDESC_DEVICE_QUALIFIER: 1946 if ((value & 0xff) != 0) { 1947 err = USBD_IOERROR; 1948 goto ret; 1949 } 1950 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1951 memcpy(buf, &ehci_odevd, l); 1952 break; 1953 /* 1954 * We can't really operate at another speed, but the spec says 1955 * we need this descriptor. 1956 */ 1957 case UDESC_OTHER_SPEED_CONFIGURATION: 1958 case UDESC_CONFIG: 1959 if ((value & 0xff) != 0) { 1960 err = USBD_IOERROR; 1961 goto ret; 1962 } 1963 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1964 memcpy(buf, &ehci_confd, l); 1965 ((usb_config_descriptor_t *)buf)->bDescriptorType = 1966 value >> 8; 1967 buf = (char *)buf + l; 1968 len -= l; 1969 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1970 totlen += l; 1971 memcpy(buf, &ehci_ifcd, l); 1972 buf = (char *)buf + l; 1973 len -= l; 1974 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1975 totlen += l; 1976 memcpy(buf, &ehci_endpd, l); 1977 break; 1978 case UDESC_STRING: 1979 if (len == 0) 1980 break; 1981 *(u_int8_t *)buf = 0; 1982 totlen = 1; 1983 switch (value & 0xff) { 1984 case 0: /* Language table */ 1985 totlen = ehci_str(buf, len, "\001"); 1986 break; 1987 case 1: /* Vendor */ 1988 totlen = ehci_str(buf, len, sc->sc_vendor); 1989 break; 1990 case 2: /* Product */ 1991 totlen = ehci_str(buf, len, "EHCI root hub"); 1992 break; 1993 } 1994 break; 1995 default: 1996 err = USBD_IOERROR; 1997 goto ret; 1998 } 1999 break; 2000 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2001 if (len > 0) { 2002 *(u_int8_t *)buf = 0; 2003 totlen = 1; 2004 } 2005 break; 2006 case C(UR_GET_STATUS, UT_READ_DEVICE): 2007 if (len > 1) { 2008 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2009 totlen = 2; 2010 } 2011 break; 2012 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2013 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2014 if (len > 1) { 2015 USETW(((usb_status_t *)buf)->wStatus, 0); 2016 totlen = 2; 2017 } 2018 break; 2019 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2020 if (value >= USB_MAX_DEVICES) { 2021 err = USBD_IOERROR; 2022 goto ret; 2023 } 2024 sc->sc_addr = value; 2025 break; 2026 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2027 if (value != 0 && value != 1) { 2028 err = USBD_IOERROR; 2029 goto ret; 2030 } 2031 sc->sc_conf = value; 2032 break; 2033 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2034 break; 2035 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2036 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2037 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2038 err = USBD_IOERROR; 2039 goto ret; 2040 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2041 break; 2042 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2043 break; 2044 /* Hub requests */ 2045 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2046 break; 2047 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2048 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2049 "port=%d feature=%d\n", index, value)); 2050 if (index < 1 || index > sc->sc_noport) { 2051 err = USBD_IOERROR; 2052 goto ret; 2053 } 2054 port = EHCI_PORTSC(index); 2055 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2056 switch(value) { 2057 case UHF_PORT_ENABLE: 2058 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2059 break; 2060 case UHF_PORT_SUSPEND: 2061 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 2062 break; 2063 case UHF_PORT_POWER: 2064 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2065 break; 2066 case UHF_PORT_TEST: 2067 DPRINTFN(2,("ehci_root_ctrl_start: " 2068 "clear port test %d\n", index)); 2069 break; 2070 case UHF_PORT_INDICATOR: 2071 DPRINTFN(2,("ehci_root_ctrl_start: " 2072 "clear port index %d\n", index)); 2073 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2074 break; 2075 case UHF_C_PORT_CONNECTION: 2076 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2077 break; 2078 case UHF_C_PORT_ENABLE: 2079 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2080 break; 2081 case UHF_C_PORT_SUSPEND: 2082 /* how? */ 2083 break; 2084 case UHF_C_PORT_OVER_CURRENT: 2085 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2086 break; 2087 case UHF_C_PORT_RESET: 2088 sc->sc_isreset = 0; 2089 break; 2090 default: 2091 err = USBD_IOERROR; 2092 goto ret; 2093 } 2094 break; 2095 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2096 if ((value & 0xff) != 0) { 2097 err = USBD_IOERROR; 2098 goto ret; 2099 } 2100 hubd = ehci_hubd; 2101 hubd.bNbrPorts = sc->sc_noport; 2102 v = EOREAD4(sc, EHCI_HCSPARAMS); 2103 USETW(hubd.wHubCharacteristics, 2104 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2105 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2106 ? UHD_PORT_IND : 0); 2107 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2108 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2109 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2110 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2111 l = min(len, hubd.bDescLength); 2112 totlen = l; 2113 memcpy(buf, &hubd, l); 2114 break; 2115 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2116 if (len != 4) { 2117 err = USBD_IOERROR; 2118 goto ret; 2119 } 2120 memset(buf, 0, len); /* ? XXX */ 2121 totlen = len; 2122 break; 2123 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2124 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2125 index)); 2126 if (index < 1 || index > sc->sc_noport) { 2127 err = USBD_IOERROR; 2128 goto ret; 2129 } 2130 if (len != 4) { 2131 err = USBD_IOERROR; 2132 goto ret; 2133 } 2134 v = EOREAD4(sc, EHCI_PORTSC(index)); 2135 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2136 i = UPS_HIGH_SPEED; 2137 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2138 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2139 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2140 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2141 if (v & EHCI_PS_PR) i |= UPS_RESET; 2142 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2143 USETW(ps.wPortStatus, i); 2144 i = 0; 2145 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2146 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2147 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2148 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 2149 USETW(ps.wPortChange, i); 2150 l = min(len, sizeof(ps)); 2151 memcpy(buf, &ps, l); 2152 totlen = l; 2153 break; 2154 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2155 err = USBD_IOERROR; 2156 goto ret; 2157 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2158 break; 2159 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2160 if (index < 1 || index > sc->sc_noport) { 2161 err = USBD_IOERROR; 2162 goto ret; 2163 } 2164 port = EHCI_PORTSC(index); 2165 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2166 switch(value) { 2167 case UHF_PORT_ENABLE: 2168 EOWRITE4(sc, port, v | EHCI_PS_PE); 2169 break; 2170 case UHF_PORT_SUSPEND: 2171 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2172 break; 2173 case UHF_PORT_DISOWN_TO_1_1: 2174 /* enter to Port Reset State */ 2175 v &= ~EHCI_PS_PE; 2176 EOWRITE4(sc, port, v | EHCI_PS_PR); 2177 ehci_disown(sc, index, 0); 2178 break; 2179 case UHF_PORT_RESET: 2180 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2181 index)); 2182 if (EHCI_PS_IS_LOWSPEED(v)) { 2183 /* Low speed device, give up ownership. */ 2184 ehci_disown(sc, index, 1); 2185 break; 2186 } 2187 /* Start reset sequence. */ 2188 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2189 EOWRITE4(sc, port, v | EHCI_PS_PR); 2190 /* Wait for reset to complete. */ 2191 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2192 if (sc->sc_dying) { 2193 err = USBD_IOERROR; 2194 goto ret; 2195 } 2196 /* Terminate reset sequence. */ 2197 v = EOREAD4(sc, port); 2198 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2199 /* Wait for HC to complete reset. */ 2200 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2201 if (sc->sc_dying) { 2202 err = USBD_IOERROR; 2203 goto ret; 2204 } 2205 v = EOREAD4(sc, port); 2206 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2207 if (v & EHCI_PS_PR) { 2208 printf("%s: port reset timeout\n", 2209 sc->sc_bus.bdev.dv_xname); 2210 return (USBD_TIMEOUT); 2211 } 2212 if (!(v & EHCI_PS_PE)) { 2213 /* Not a high speed device, give up ownership.*/ 2214 ehci_disown(sc, index, 0); 2215 break; 2216 } 2217 sc->sc_isreset = 1; 2218 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2219 index, v)); 2220 break; 2221 case UHF_PORT_POWER: 2222 DPRINTFN(2,("ehci_root_ctrl_start: " 2223 "set port power %d\n", index)); 2224 EOWRITE4(sc, port, v | EHCI_PS_PP); 2225 break; 2226 case UHF_PORT_TEST: 2227 DPRINTFN(2,("ehci_root_ctrl_start: " 2228 "set port test %d\n", index)); 2229 break; 2230 case UHF_PORT_INDICATOR: 2231 DPRINTFN(2,("ehci_root_ctrl_start: " 2232 "set port ind %d\n", index)); 2233 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2234 break; 2235 default: 2236 err = USBD_IOERROR; 2237 goto ret; 2238 } 2239 break; 2240 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2241 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2242 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2243 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2244 break; 2245 default: 2246 err = USBD_IOERROR; 2247 goto ret; 2248 } 2249 xfer->actlen = totlen; 2250 err = USBD_NORMAL_COMPLETION; 2251 ret: 2252 xfer->status = err; 2253 s = splusb(); 2254 usb_transfer_complete(xfer); 2255 splx(s); 2256 return (USBD_IN_PROGRESS); 2257 } 2258 2259 void 2260 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2261 { 2262 int port; 2263 u_int32_t v; 2264 2265 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2266 2267 port = EHCI_PORTSC(index); 2268 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2269 EOWRITE4(sc, port, v | EHCI_PS_PO); 2270 } 2271 2272 /* Abort a root control request. */ 2273 void 2274 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2275 { 2276 /* Nothing to do, all transfers are synchronous. */ 2277 } 2278 2279 /* Close the root pipe. */ 2280 void 2281 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2282 { 2283 DPRINTF(("ehci_root_ctrl_close\n")); 2284 /* Nothing to do. */ 2285 } 2286 2287 void 2288 ehci_root_intr_done(usbd_xfer_handle xfer) 2289 { 2290 } 2291 2292 usbd_status 2293 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2294 { 2295 usbd_status err; 2296 2297 /* Insert last in queue. */ 2298 err = usb_insert_transfer(xfer); 2299 if (err) 2300 return (err); 2301 2302 /* Pipe isn't running, start first */ 2303 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2304 } 2305 2306 usbd_status 2307 ehci_root_intr_start(usbd_xfer_handle xfer) 2308 { 2309 usbd_pipe_handle pipe = xfer->pipe; 2310 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2311 2312 if (sc->sc_dying) 2313 return (USBD_IOERROR); 2314 2315 sc->sc_intrxfer = xfer; 2316 2317 return (USBD_IN_PROGRESS); 2318 } 2319 2320 /* Abort a root interrupt request. */ 2321 void 2322 ehci_root_intr_abort(usbd_xfer_handle xfer) 2323 { 2324 int s; 2325 2326 if (xfer->pipe->intrxfer == xfer) { 2327 DPRINTF(("ehci_root_intr_abort: remove\n")); 2328 xfer->pipe->intrxfer = NULL; 2329 } 2330 xfer->status = USBD_CANCELLED; 2331 s = splusb(); 2332 usb_transfer_complete(xfer); 2333 splx(s); 2334 } 2335 2336 /* Close the root pipe. */ 2337 void 2338 ehci_root_intr_close(usbd_pipe_handle pipe) 2339 { 2340 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2341 2342 DPRINTF(("ehci_root_intr_close\n")); 2343 2344 sc->sc_intrxfer = NULL; 2345 } 2346 2347 void 2348 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2349 { 2350 } 2351 2352 /************************/ 2353 2354 ehci_soft_qh_t * 2355 ehci_alloc_sqh(ehci_softc_t *sc) 2356 { 2357 ehci_soft_qh_t *sqh; 2358 usbd_status err; 2359 int i, offs; 2360 usb_dma_t dma; 2361 2362 if (sc->sc_freeqhs == NULL) { 2363 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2364 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2365 EHCI_PAGE_SIZE, &dma); 2366 #ifdef EHCI_DEBUG 2367 if (err) 2368 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2369 #endif 2370 if (err) 2371 return (NULL); 2372 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2373 offs = i * EHCI_SQH_SIZE; 2374 sqh = KERNADDR(&dma, offs); 2375 sqh->physaddr = DMAADDR(&dma, offs); 2376 sqh->next = sc->sc_freeqhs; 2377 sc->sc_freeqhs = sqh; 2378 } 2379 } 2380 sqh = sc->sc_freeqhs; 2381 sc->sc_freeqhs = sqh->next; 2382 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2383 sqh->next = NULL; 2384 sqh->prev = NULL; 2385 return (sqh); 2386 } 2387 2388 void 2389 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2390 { 2391 sqh->next = sc->sc_freeqhs; 2392 sc->sc_freeqhs = sqh; 2393 } 2394 2395 ehci_soft_qtd_t * 2396 ehci_alloc_sqtd(ehci_softc_t *sc) 2397 { 2398 ehci_soft_qtd_t *sqtd; 2399 usbd_status err; 2400 int i, offs; 2401 usb_dma_t dma; 2402 int s; 2403 2404 if (sc->sc_freeqtds == NULL) { 2405 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2406 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2407 EHCI_PAGE_SIZE, &dma); 2408 #ifdef EHCI_DEBUG 2409 if (err) 2410 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2411 #endif 2412 if (err) 2413 return (NULL); 2414 s = splusb(); 2415 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2416 offs = i * EHCI_SQTD_SIZE; 2417 sqtd = KERNADDR(&dma, offs); 2418 sqtd->physaddr = DMAADDR(&dma, offs); 2419 sqtd->nextqtd = sc->sc_freeqtds; 2420 sc->sc_freeqtds = sqtd; 2421 } 2422 splx(s); 2423 } 2424 2425 s = splusb(); 2426 sqtd = sc->sc_freeqtds; 2427 sc->sc_freeqtds = sqtd->nextqtd; 2428 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2429 sqtd->nextqtd = NULL; 2430 sqtd->xfer = NULL; 2431 splx(s); 2432 2433 return (sqtd); 2434 } 2435 2436 void 2437 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2438 { 2439 int s; 2440 2441 s = splusb(); 2442 sqtd->nextqtd = sc->sc_freeqtds; 2443 sc->sc_freeqtds = sqtd; 2444 splx(s); 2445 } 2446 2447 usbd_status 2448 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, int alen, 2449 int rd, usbd_xfer_handle xfer, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2450 { 2451 ehci_soft_qtd_t *next, *cur; 2452 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2453 u_int32_t qtdstatus; 2454 int len, curlen, mps; 2455 int i, iscontrol, forceshort; 2456 usb_dma_t *dma = &xfer->dmabuf; 2457 2458 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2459 2460 len = alen; 2461 iscontrol = (epipe->pipe.endpoint->edesc->bmAttributes & UE_XFERTYPE) == 2462 UE_CONTROL; 2463 2464 dataphys = DMAADDR(dma, 0); 2465 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2466 qtdstatus = EHCI_QTD_ACTIVE | 2467 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2468 EHCI_QTD_SET_CERR(3); /* IOC and BYTES set below */ 2469 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2470 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2471 len % mps == 0; 2472 /* 2473 * The control transfer data stage always starts with a toggle of 1. 2474 * For other transfers we let the hardware track the toggle state. 2475 */ 2476 if (iscontrol) 2477 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2478 2479 cur = ehci_alloc_sqtd(sc); 2480 *sp = cur; 2481 if (cur == NULL) 2482 goto nomem; 2483 for (;;) { 2484 dataphyspage = EHCI_PAGE(dataphys); 2485 /* The EHCI hardware can handle at most 5 pages. */ 2486 if (dataphyslastpage - dataphyspage < 2487 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2488 /* we can handle it in this QTD */ 2489 curlen = len; 2490 } else { 2491 /* must use multiple TDs, fill as much as possible. */ 2492 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2493 EHCI_PAGE_OFFSET(dataphys); 2494 #ifdef DIAGNOSTIC 2495 if (curlen > len) { 2496 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2497 "len=0x%x offs=0x%x\n", curlen, len, 2498 EHCI_PAGE_OFFSET(dataphys)); 2499 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2500 dataphyslastpage, dataphyspage, dataphys); 2501 curlen = len; 2502 } 2503 #endif 2504 /* the length must be a multiple of the max size */ 2505 curlen -= curlen % mps; 2506 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2507 "curlen=%d\n", curlen)); 2508 #ifdef DIAGNOSTIC 2509 if (curlen == 0) 2510 panic("ehci_alloc_std: curlen == 0"); 2511 #endif 2512 } 2513 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2514 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2515 dataphys, dataphyslastpage, len, curlen)); 2516 len -= curlen; 2517 2518 /* 2519 * Allocate another transfer if there's more data left, 2520 * or if force last short transfer flag is set and we're 2521 * allocating a multiple of the max packet size. 2522 */ 2523 if (len != 0 || forceshort) { 2524 next = ehci_alloc_sqtd(sc); 2525 if (next == NULL) 2526 goto nomem; 2527 nextphys = htole32(next->physaddr); 2528 } else { 2529 next = NULL; 2530 nextphys = EHCI_NULL; 2531 } 2532 2533 for (i = 0; i * EHCI_PAGE_SIZE < 2534 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2535 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2536 if (i != 0) /* use offset only in first buffer */ 2537 a = EHCI_PAGE(a); 2538 cur->qtd.qtd_buffer[i] = htole32(a); 2539 cur->qtd.qtd_buffer_hi[i] = 0; 2540 #ifdef DIAGNOSTIC 2541 if (i >= EHCI_QTD_NBUFFERS) { 2542 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2543 goto nomem; 2544 } 2545 #endif 2546 } 2547 cur->nextqtd = next; 2548 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2549 cur->qtd.qtd_status = htole32(qtdstatus | 2550 EHCI_QTD_SET_BYTES(curlen)); 2551 cur->xfer = xfer; 2552 cur->len = curlen; 2553 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2554 dataphys, dataphys + curlen)); 2555 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%d\n", curlen)); 2556 if (iscontrol) { 2557 /* 2558 * adjust the toggle based on the number of packets 2559 * in this qtd 2560 */ 2561 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2562 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2563 } 2564 if (len == 0) { 2565 if (! forceshort) 2566 break; 2567 forceshort = 0; 2568 } 2569 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2570 dataphys += curlen; 2571 cur = next; 2572 } 2573 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2574 *ep = cur; 2575 2576 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2577 *sp, *ep)); 2578 2579 return (USBD_NORMAL_COMPLETION); 2580 2581 nomem: 2582 /* XXX free chain */ 2583 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2584 return (USBD_NOMEM); 2585 } 2586 2587 void 2588 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2589 ehci_soft_qtd_t *sqtdend) 2590 { 2591 ehci_soft_qtd_t *p; 2592 int i; 2593 2594 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2595 sqtd, sqtdend)); 2596 2597 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2598 p = sqtd->nextqtd; 2599 ehci_free_sqtd(sc, sqtd); 2600 } 2601 } 2602 2603 ehci_soft_itd_t * 2604 ehci_alloc_itd(ehci_softc_t *sc) 2605 { 2606 struct ehci_soft_itd *itd, *freeitd; 2607 usbd_status err; 2608 int i, s, offs, frindex, previndex; 2609 usb_dma_t dma; 2610 2611 s = splusb(); 2612 2613 /* Find an itd that wasn't freed this frame or last frame. This can 2614 * discard itds that were freed before frindex wrapped around 2615 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2616 * interrupt and fiddling with list when that happens */ 2617 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2618 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2619 2620 freeitd = NULL; 2621 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2622 if (itd == NULL) 2623 break; 2624 if (itd->slot != frindex && itd->slot != previndex) { 2625 freeitd = itd; 2626 break; 2627 } 2628 } 2629 2630 if (freeitd == NULL) { 2631 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2632 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2633 EHCI_PAGE_SIZE, &dma); 2634 2635 if (err) { 2636 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2637 return (NULL); 2638 } 2639 2640 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2641 offs = i * EHCI_ITD_SIZE; 2642 itd = KERNADDR(&dma, offs); 2643 itd->physaddr = DMAADDR(&dma, offs); 2644 itd->dma = dma; 2645 itd->offs = offs; 2646 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2647 } 2648 freeitd = LIST_FIRST(&sc->sc_freeitds); 2649 } 2650 2651 itd = freeitd; 2652 LIST_REMOVE(itd, u.free_list); 2653 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2654 itd->u.frame_list.next = NULL; 2655 itd->u.frame_list.prev = NULL; 2656 itd->xfer_next = NULL; 2657 itd->slot = 0; 2658 splx(s); 2659 2660 return (itd); 2661 } 2662 2663 void 2664 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2665 { 2666 int s; 2667 2668 s = splusb(); 2669 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2670 splx(s); 2671 } 2672 2673 /****************/ 2674 2675 /* 2676 * Close a reqular pipe. 2677 * Assumes that there are no pending transactions. 2678 */ 2679 void 2680 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2681 { 2682 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2683 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2684 ehci_soft_qh_t *sqh = epipe->sqh; 2685 int s; 2686 2687 s = splusb(); 2688 ehci_rem_qh(sc, sqh, head); 2689 splx(s); 2690 pipe->endpoint->savedtoggle = 2691 EHCI_QTD_GET_TOGGLE(letoh32(sqh->qh.qh_qtd.qtd_status)); 2692 ehci_free_sqh(sc, epipe->sqh); 2693 } 2694 2695 /* 2696 * Abort a device request. 2697 * If this routine is called at splusb() it guarantees that the request 2698 * will be removed from the hardware scheduling and that the callback 2699 * for it will be called with USBD_CANCELLED status. 2700 * It's impossible to guarantee that the requested transfer will not 2701 * have happened since the hardware runs concurrently. 2702 * If the transaction has already happened we rely on the ordinary 2703 * interrupt processing to process it. 2704 */ 2705 void 2706 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2707 { 2708 #define exfer EXFER(xfer) 2709 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2710 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2711 ehci_soft_qh_t *sqh = epipe->sqh; 2712 ehci_soft_qtd_t *sqtd, *snext, **psqtd; 2713 ehci_physaddr_t cur, us, next; 2714 int s; 2715 int hit; 2716 ehci_soft_qh_t *psqh; 2717 2718 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2719 2720 if (sc->sc_dying) { 2721 /* If we're dying, just do the software part. */ 2722 s = splusb(); 2723 xfer->status = status; /* make software ignore it */ 2724 timeout_del(&xfer->timeout_handle); 2725 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 2726 usb_transfer_complete(xfer); 2727 splx(s); 2728 return; 2729 } 2730 2731 if (xfer->device->bus->intr_context) 2732 panic("ehci_abort_xfer: not in process context"); 2733 2734 /* 2735 * If an abort is already in progress then just wait for it to 2736 * complete and return. 2737 */ 2738 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2739 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2740 /* No need to wait if we're aborting from a timeout. */ 2741 if (status == USBD_TIMEOUT) 2742 return; 2743 /* Override the status which might be USBD_TIMEOUT. */ 2744 xfer->status = status; 2745 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2746 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 2747 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 2748 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciaw", 0); 2749 return; 2750 } 2751 2752 /* 2753 * Step 1: Make interrupt routine and timeouts ignore xfer. 2754 */ 2755 s = splusb(); 2756 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2757 xfer->status = status; /* make software ignore it */ 2758 timeout_del(&xfer->timeout_handle); 2759 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 2760 splx(s); 2761 2762 /* 2763 * Step 2: Wait until we know hardware has finished any possible 2764 * use of the xfer. We do this by removing the entire 2765 * queue from the async schedule and waiting for the doorbell. 2766 * Nothing else should be touching the queue now. 2767 */ 2768 psqh = sqh->prev; 2769 ehci_rem_qh(sc, sqh, psqh); 2770 2771 /* 2772 * Step 3: Deactivate all of the qTDs that we will be removing, 2773 * otherwise the queue head may go active again. The EHCI spec 2774 * suggests we should perform the deactivation before removing the 2775 * queue head from the schedule, however the VT6202 (at least) only 2776 * behaves correctly when we deactivate them afterwards. 2777 */ 2778 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2779 sqtd->qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2780 if (sqtd == exfer->sqtdend) 2781 break; 2782 } 2783 ehci_sync_hc(sc); 2784 2785 /* 2786 * Step 4: make sure the soft interrupt routine 2787 * has run. This should remove any completed items off the queue. 2788 * The hardware has no reference to completed items (TDs). 2789 * It's safe to remove them at any time. 2790 * use of the xfer. Also make sure the soft interrupt routine 2791 * has run. 2792 */ 2793 s = splusb(); 2794 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 2795 sc->sc_softwake = 1; 2796 #endif /* __HAVE_GENERIC_SOFT_INTERRUPTS */ 2797 usb_schedsoftintr(&sc->sc_bus); 2798 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 2799 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2800 #endif /* __HAVE_GENERIC_SOFT_INTERRUPTS */ 2801 2802 /* 2803 * Step 5: Remove any vestiges of the xfer from the hardware. 2804 * The complication here is that the hardware may have executed 2805 * into or even beyond the xfer we're trying to abort. 2806 * So as we're scanning the TDs of this xfer we check if 2807 * the hardware points to any of them. 2808 * 2809 * first we need to see if there are any transfers 2810 * on this queue before the xfer we are aborting.. we need 2811 * to update any pointers that point to us to point past 2812 * the aborting xfer. (If there is something past us). 2813 * Hardware and software. 2814 */ 2815 cur = EHCI_LINK_ADDR(letoh32(sqh->qh.qh_curqtd)); 2816 hit = 0; 2817 2818 /* If they initially point here. */ 2819 us = exfer->sqtdstart->physaddr; 2820 2821 /* We will change them to point here */ 2822 snext = exfer->sqtdend->nextqtd; 2823 next = snext ? snext->physaddr : EHCI_NULL; 2824 2825 /* 2826 * Now loop through any qTDs before us and keep track of the pointer 2827 * that points to us for the end. 2828 */ 2829 psqtd = &sqh->sqtd; 2830 sqtd = sqh->sqtd; 2831 while (sqtd && sqtd != exfer->sqtdstart) { 2832 hit |= (cur == sqtd->physaddr); 2833 if (EHCI_LINK_ADDR(letoh32(sqtd->qtd.qtd_next)) == us) 2834 sqtd->qtd.qtd_next = next; 2835 if (EHCI_LINK_ADDR(letoh32(sqtd->qtd.qtd_altnext)) == us) 2836 sqtd->qtd.qtd_altnext = next; 2837 psqtd = &sqtd->nextqtd; 2838 sqtd = sqtd->nextqtd; 2839 } 2840 /* make the software pointer bypass us too */ 2841 *psqtd = exfer->sqtdend->nextqtd; 2842 2843 /* 2844 * If we already saw the active one then we are pretty much done. 2845 * We've done all the relinking we need to do. 2846 */ 2847 if (!hit) { 2848 2849 /* 2850 * Now reinitialise the QH to point to the next qTD 2851 * (if there is one). We only need to do this if 2852 * it was previously pointing to us. 2853 * XXX Not quite sure what to do about the data toggle. 2854 */ 2855 sqtd = exfer->sqtdstart; 2856 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2857 if (cur == sqtd->physaddr) { 2858 hit++; 2859 } 2860 if (sqtd == exfer->sqtdend) 2861 break; 2862 } 2863 /* 2864 * Only need to alter the QH if it was pointing at a qTD 2865 * that we are removing. 2866 */ 2867 if (hit) { 2868 if (snext) { 2869 ehci_set_qh_qtd(sqh, snext); 2870 } else { 2871 2872 sqh->qh.qh_curqtd = 0; /* unlink qTDs */ 2873 sqh->qh.qh_qtd.qtd_status = 0; 2874 sqh->qh.qh_qtd.qtd_next = 2875 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2876 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2877 } 2878 } 2879 } 2880 ehci_add_qh(sqh, psqh); 2881 2882 /* 2883 * Step 6: Execute callback. 2884 */ 2885 #ifdef DIAGNOSTIC 2886 exfer->isdone = 1; 2887 #endif 2888 /* Do the wakeup first to avoid touching the xfer after the callback. */ 2889 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 2890 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 2891 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 2892 wakeup(&exfer->ehci_xfer_flags); 2893 } 2894 usb_transfer_complete(xfer); 2895 2896 splx(s); 2897 #undef exfer 2898 } 2899 2900 void 2901 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 2902 { 2903 ehci_isoc_trans_t trans_status; 2904 struct ehci_pipe *epipe; 2905 struct ehci_xfer *exfer; 2906 ehci_softc_t *sc; 2907 struct ehci_soft_itd *itd; 2908 int s, i, wake; 2909 2910 epipe = (struct ehci_pipe *) xfer->pipe; 2911 exfer = EXFER(xfer); 2912 sc = (ehci_softc_t *)epipe->pipe.device->bus; 2913 2914 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 2915 2916 if (sc->sc_dying) { 2917 s = splusb(); 2918 xfer->status = status; 2919 timeout_del(&xfer->timeout_handle); 2920 usb_transfer_complete(xfer); 2921 splx(s); 2922 return; 2923 } 2924 2925 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2926 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 2927 2928 #ifdef DIAGNOSTIC 2929 if (status == USBD_TIMEOUT) 2930 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2931 #endif 2932 2933 xfer->status = status; 2934 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2935 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2936 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 2937 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciiaw", 0); 2938 return; 2939 } 2940 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2941 2942 xfer->status = status; 2943 timeout_del(&xfer->timeout_handle); 2944 2945 s = splusb(); 2946 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2947 for (i = 0; i < 8; i++) { 2948 trans_status = letoh32(itd->itd.itd_ctl[i]); 2949 trans_status &= ~EHCI_ITD_ACTIVE; 2950 itd->itd.itd_ctl[i] = htole32(trans_status); 2951 } 2952 } 2953 splx(s); 2954 2955 s = splusb(); 2956 #ifdef USB_USE_SOFTINTR 2957 sc->sc_softwake = 1; 2958 #endif /* USB_USE_SOFTINTR */ 2959 usb_schedsoftintr(&sc->sc_bus); 2960 #ifdef USB_USE_SOFTINTR 2961 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2962 #endif /* USB_USE_SOFTINTR */ 2963 splx(s); 2964 2965 #ifdef DIAGNOSTIC 2966 exfer->isdone = 1; 2967 #endif 2968 wake = exfer->ehci_xfer_flags & EHCI_XFER_ABORTING; 2969 exfer->ehci_xfer_flags &= ~(EHCI_XFER_ABORTING | EHCI_XFER_ABORTWAIT); 2970 usb_transfer_complete(xfer); 2971 if (wake) 2972 wakeup(&exfer->ehci_xfer_flags); 2973 2974 return; 2975 } 2976 2977 void 2978 ehci_timeout(void *addr) 2979 { 2980 struct ehci_xfer *exfer = addr; 2981 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 2982 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2983 2984 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 2985 #if defined(EHCI_DEBUG) && defined(USB_DEBUG) 2986 if (ehcidebug > 1) 2987 usbd_dump_pipe(exfer->xfer.pipe); 2988 #endif 2989 2990 if (sc->sc_dying) { 2991 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 2992 return; 2993 } 2994 2995 /* Execute the abort in a process context. */ 2996 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task); 2997 } 2998 2999 void 3000 ehci_timeout_task(void *addr) 3001 { 3002 usbd_xfer_handle xfer = addr; 3003 int s; 3004 3005 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3006 3007 s = splusb(); 3008 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3009 splx(s); 3010 } 3011 3012 /* 3013 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3014 * qTD status, or miss signalling occasionally under heavy load. If the host 3015 * machine is too fast, we we can miss transaction completion - when we scan 3016 * the active list the transaction still seems to be active. This generally 3017 * exhibits itself as a umass stall that never recovers. 3018 * 3019 * We work around this behaviour by setting up this callback after any softintr 3020 * that completes with transactions still pending, giving us another chance to 3021 * check for completion after the writeback has taken place. 3022 */ 3023 void 3024 ehci_intrlist_timeout(void *arg) 3025 { 3026 ehci_softc_t *sc = arg; 3027 int s = splusb(); 3028 3029 DPRINTFN(1, ("ehci_intrlist_timeout\n")); 3030 usb_schedsoftintr(&sc->sc_bus); 3031 3032 splx(s); 3033 } 3034 3035 /************************/ 3036 3037 usbd_status 3038 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3039 { 3040 usbd_status err; 3041 3042 /* Insert last in queue. */ 3043 err = usb_insert_transfer(xfer); 3044 if (err) 3045 return (err); 3046 3047 /* Pipe isn't running, start first */ 3048 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3049 } 3050 3051 usbd_status 3052 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3053 { 3054 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3055 usbd_status err; 3056 3057 if (sc->sc_dying) 3058 return (USBD_IOERROR); 3059 3060 #ifdef DIAGNOSTIC 3061 if (!(xfer->rqflags & URQ_REQUEST)) { 3062 /* XXX panic */ 3063 printf("ehci_device_ctrl_transfer: not a request\n"); 3064 return (USBD_INVAL); 3065 } 3066 #endif 3067 3068 err = ehci_device_request(xfer); 3069 if (err) 3070 return (err); 3071 3072 if (sc->sc_bus.use_polling) 3073 ehci_waitintr(sc, xfer); 3074 return (USBD_IN_PROGRESS); 3075 } 3076 3077 void 3078 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3079 { 3080 struct ehci_xfer *ex = EXFER(xfer); 3081 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3082 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 3083 3084 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3085 3086 #ifdef DIAGNOSTIC 3087 if (!(xfer->rqflags & URQ_REQUEST)) { 3088 panic("ehci_ctrl_done: not a request"); 3089 } 3090 #endif 3091 3092 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3093 ehci_del_intr_list(sc, ex); /* remove from active list */ 3094 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3095 } 3096 3097 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3098 } 3099 3100 /* Abort a device control request. */ 3101 void 3102 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3103 { 3104 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3105 ehci_abort_xfer(xfer, USBD_CANCELLED); 3106 } 3107 3108 /* Close a device control pipe. */ 3109 void 3110 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3111 { 3112 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3113 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3114 3115 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3116 ehci_close_pipe(pipe, sc->sc_async_head); 3117 } 3118 3119 usbd_status 3120 ehci_device_request(usbd_xfer_handle xfer) 3121 { 3122 #define exfer EXFER(xfer) 3123 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3124 usb_device_request_t *req = &xfer->request; 3125 usbd_device_handle dev = epipe->pipe.device; 3126 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3127 int addr = dev->address; 3128 ehci_soft_qtd_t *setup, *stat, *next; 3129 ehci_soft_qh_t *sqh; 3130 int isread; 3131 int len; 3132 usbd_status err; 3133 int s; 3134 3135 isread = req->bmRequestType & UT_READ; 3136 len = UGETW(req->wLength); 3137 3138 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3139 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3140 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3141 UGETW(req->wIndex), len, addr, 3142 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3143 3144 setup = ehci_alloc_sqtd(sc); 3145 if (setup == NULL) { 3146 err = USBD_NOMEM; 3147 goto bad1; 3148 } 3149 stat = ehci_alloc_sqtd(sc); 3150 if (stat == NULL) { 3151 err = USBD_NOMEM; 3152 goto bad2; 3153 } 3154 3155 sqh = epipe->sqh; 3156 epipe->u.ctl.length = len; 3157 3158 /* Update device address and length since they may have changed 3159 during the setup of the control pipe in usbd_new_device(). */ 3160 /* XXX This only needs to be done once, but it's too early in open. */ 3161 /* XXXX Should not touch ED here! */ 3162 sqh->qh.qh_endp = 3163 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3164 htole32( 3165 EHCI_QH_SET_ADDR(addr) | 3166 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3167 ); 3168 3169 /* Set up data transaction */ 3170 if (len != 0) { 3171 ehci_soft_qtd_t *end; 3172 3173 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3174 &next, &end); 3175 if (err) 3176 goto bad3; 3177 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3178 end->nextqtd = stat; 3179 end->qtd.qtd_next = 3180 end->qtd.qtd_altnext = htole32(stat->physaddr); 3181 } else { 3182 next = stat; 3183 } 3184 3185 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 3186 3187 /* Clear toggle */ 3188 setup->qtd.qtd_status = htole32( 3189 EHCI_QTD_ACTIVE | 3190 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3191 EHCI_QTD_SET_CERR(3) | 3192 EHCI_QTD_SET_TOGGLE(0) | 3193 EHCI_QTD_SET_BYTES(sizeof(*req))); 3194 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3195 setup->qtd.qtd_buffer_hi[0] = 0; 3196 setup->nextqtd = next; 3197 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3198 setup->xfer = xfer; 3199 setup->len = sizeof(*req); 3200 3201 stat->qtd.qtd_status = htole32( 3202 EHCI_QTD_ACTIVE | 3203 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3204 EHCI_QTD_SET_CERR(3) | 3205 EHCI_QTD_SET_TOGGLE(1) | 3206 EHCI_QTD_IOC); 3207 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3208 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3209 stat->nextqtd = NULL; 3210 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3211 stat->xfer = xfer; 3212 stat->len = 0; 3213 3214 #ifdef EHCI_DEBUG 3215 if (ehcidebug > 5) { 3216 DPRINTF(("ehci_device_request:\n")); 3217 ehci_dump_sqh(sqh); 3218 ehci_dump_sqtds(setup); 3219 } 3220 #endif 3221 3222 exfer->sqtdstart = setup; 3223 exfer->sqtdend = stat; 3224 #ifdef DIAGNOSTIC 3225 if (!exfer->isdone) { 3226 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3227 } 3228 exfer->isdone = 0; 3229 #endif 3230 3231 /* Insert qTD in QH list. */ 3232 s = splusb(); 3233 ehci_set_qh_qtd(sqh, setup); 3234 if (xfer->timeout && !sc->sc_bus.use_polling) { 3235 timeout_del(&xfer->timeout_handle); 3236 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3237 timeout_add(&xfer->timeout_handle, mstohz(xfer->timeout)); 3238 } 3239 ehci_add_intr_list(sc, exfer); 3240 xfer->status = USBD_IN_PROGRESS; 3241 splx(s); 3242 3243 #ifdef EHCI_DEBUG 3244 if (ehcidebug > 10) { 3245 DPRINTF(("ehci_device_request: status=%x\n", 3246 EOREAD4(sc, EHCI_USBSTS))); 3247 delay(10000); 3248 ehci_dump_regs(sc); 3249 ehci_dump_sqh(sc->sc_async_head); 3250 ehci_dump_sqh(sqh); 3251 ehci_dump_sqtds(setup); 3252 } 3253 #endif 3254 3255 return (USBD_NORMAL_COMPLETION); 3256 3257 bad3: 3258 ehci_free_sqtd(sc, stat); 3259 bad2: 3260 ehci_free_sqtd(sc, setup); 3261 bad1: 3262 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3263 xfer->status = err; 3264 usb_transfer_complete(xfer); 3265 return (err); 3266 #undef exfer 3267 } 3268 3269 /************************/ 3270 3271 usbd_status 3272 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3273 { 3274 usbd_status err; 3275 3276 /* Insert last in queue. */ 3277 err = usb_insert_transfer(xfer); 3278 if (err) 3279 return (err); 3280 3281 /* Pipe isn't running, start first */ 3282 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3283 } 3284 3285 usbd_status 3286 ehci_device_bulk_start(usbd_xfer_handle xfer) 3287 { 3288 #define exfer EXFER(xfer) 3289 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3290 usbd_device_handle dev = epipe->pipe.device; 3291 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3292 ehci_soft_qtd_t *data, *dataend; 3293 ehci_soft_qh_t *sqh; 3294 usbd_status err; 3295 int len, isread, endpt; 3296 int s; 3297 3298 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3299 xfer, xfer->length, xfer->flags)); 3300 3301 if (sc->sc_dying) 3302 return (USBD_IOERROR); 3303 3304 #ifdef DIAGNOSTIC 3305 if (xfer->rqflags & URQ_REQUEST) 3306 panic("ehci_device_bulk_start: a request"); 3307 #endif 3308 3309 len = xfer->length; 3310 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3311 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3312 sqh = epipe->sqh; 3313 3314 epipe->u.bulk.length = len; 3315 3316 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3317 &dataend); 3318 if (err) { 3319 DPRINTFN(-1,("ehci_device_bulk_start: no memory\n")); 3320 xfer->status = err; 3321 usb_transfer_complete(xfer); 3322 return (err); 3323 } 3324 3325 #ifdef EHCI_DEBUG 3326 if (ehcidebug > 5) { 3327 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3328 ehci_dump_sqh(sqh); 3329 ehci_dump_sqtds(data); 3330 } 3331 #endif 3332 3333 /* Set up interrupt info. */ 3334 exfer->sqtdstart = data; 3335 exfer->sqtdend = dataend; 3336 #ifdef DIAGNOSTIC 3337 if (!exfer->isdone) { 3338 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3339 } 3340 exfer->isdone = 0; 3341 #endif 3342 3343 s = splusb(); 3344 ehci_set_qh_qtd(sqh, data); 3345 if (xfer->timeout && !sc->sc_bus.use_polling) { 3346 timeout_del(&xfer->timeout_handle); 3347 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3348 timeout_add(&xfer->timeout_handle, mstohz(xfer->timeout)); 3349 } 3350 ehci_add_intr_list(sc, exfer); 3351 xfer->status = USBD_IN_PROGRESS; 3352 splx(s); 3353 3354 #ifdef EHCI_DEBUG 3355 if (ehcidebug > 10) { 3356 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3357 delay(10000); 3358 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3359 ehci_dump_regs(sc); 3360 #if 0 3361 printf("async_head:\n"); 3362 ehci_dump_sqh(sc->sc_async_head); 3363 #endif 3364 printf("sqh:\n"); 3365 ehci_dump_sqh(sqh); 3366 ehci_dump_sqtds(data); 3367 } 3368 #endif 3369 3370 if (sc->sc_bus.use_polling) 3371 ehci_waitintr(sc, xfer); 3372 3373 return (USBD_IN_PROGRESS); 3374 #undef exfer 3375 } 3376 3377 void 3378 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3379 { 3380 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3381 ehci_abort_xfer(xfer, USBD_CANCELLED); 3382 } 3383 3384 /* 3385 * Close a device bulk pipe. 3386 */ 3387 void 3388 ehci_device_bulk_close(usbd_pipe_handle pipe) 3389 { 3390 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3391 3392 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3393 ehci_close_pipe(pipe, sc->sc_async_head); 3394 } 3395 3396 void 3397 ehci_device_bulk_done(usbd_xfer_handle xfer) 3398 { 3399 struct ehci_xfer *ex = EXFER(xfer); 3400 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3401 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 3402 3403 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3404 xfer, xfer->actlen)); 3405 3406 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3407 ehci_del_intr_list(sc, ex); /* remove from active list */ 3408 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3409 } 3410 3411 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3412 } 3413 3414 /************************/ 3415 3416 usbd_status 3417 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3418 { 3419 struct ehci_soft_islot *isp; 3420 int islot, lev; 3421 3422 /* Find a poll rate that is large enough. */ 3423 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3424 if (EHCI_ILEV_IVAL(lev) <= ival) 3425 break; 3426 3427 /* Pick an interrupt slot at the right level. */ 3428 /* XXX could do better than picking at random */ 3429 if (cold) { 3430 /* XXX prevent panics at boot by not using arc4random */ 3431 sc->sc_rand = (sc->sc_rand + 192) % sc->sc_flsize; 3432 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3433 } else 3434 islot = EHCI_IQHIDX(lev, arc4random()); 3435 3436 sqh->islot = islot; 3437 isp = &sc->sc_islots[islot]; 3438 ehci_add_qh(sqh, isp->sqh); 3439 3440 return (USBD_NORMAL_COMPLETION); 3441 } 3442 3443 usbd_status 3444 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3445 { 3446 usbd_status err; 3447 3448 /* Insert last in queue. */ 3449 err = usb_insert_transfer(xfer); 3450 if (err) 3451 return (err); 3452 3453 /* 3454 * Pipe isn't running (otherwise err would be USBD_INPROG), 3455 * so start it first. 3456 */ 3457 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3458 } 3459 3460 usbd_status 3461 ehci_device_intr_start(usbd_xfer_handle xfer) 3462 { 3463 #define exfer EXFER(xfer) 3464 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3465 usbd_device_handle dev = xfer->pipe->device; 3466 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3467 ehci_soft_qtd_t *data, *dataend; 3468 ehci_soft_qh_t *sqh; 3469 usbd_status err; 3470 int len, isread, endpt; 3471 int s; 3472 3473 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3474 xfer, xfer->length, xfer->flags)); 3475 3476 if (sc->sc_dying) 3477 return (USBD_IOERROR); 3478 3479 #ifdef DIAGNOSTIC 3480 if (xfer->rqflags & URQ_REQUEST) 3481 panic("ehci_device_intr_start: a request"); 3482 #endif 3483 3484 len = xfer->length; 3485 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3486 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3487 sqh = epipe->sqh; 3488 3489 epipe->u.intr.length = len; 3490 3491 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3492 &dataend); 3493 if (err) { 3494 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3495 xfer->status = err; 3496 usb_transfer_complete(xfer); 3497 return (err); 3498 } 3499 3500 #ifdef EHCI_DEBUG 3501 if (ehcidebug > 5) { 3502 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3503 ehci_dump_sqh(sqh); 3504 ehci_dump_sqtds(data); 3505 } 3506 #endif 3507 3508 /* Set up interrupt info. */ 3509 exfer->sqtdstart = data; 3510 exfer->sqtdend = dataend; 3511 #ifdef DIAGNOSTIC 3512 if (!exfer->isdone) 3513 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3514 exfer->isdone = 0; 3515 #endif 3516 3517 s = splusb(); 3518 ehci_set_qh_qtd(sqh, data); 3519 if (xfer->timeout && !sc->sc_bus.use_polling) { 3520 timeout_del(&xfer->timeout_handle); 3521 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3522 timeout_add(&xfer->timeout_handle, mstohz(xfer->timeout)); 3523 } 3524 ehci_add_intr_list(sc, exfer); 3525 xfer->status = USBD_IN_PROGRESS; 3526 splx(s); 3527 3528 #ifdef EHCI_DEBUG 3529 if (ehcidebug > 10) { 3530 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3531 delay(10000); 3532 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3533 ehci_dump_regs(sc); 3534 printf("sqh:\n"); 3535 ehci_dump_sqh(sqh); 3536 ehci_dump_sqtds(data); 3537 } 3538 #endif 3539 3540 if (sc->sc_bus.use_polling) 3541 ehci_waitintr(sc, xfer); 3542 3543 return (USBD_IN_PROGRESS); 3544 #undef exfer 3545 } 3546 3547 void 3548 ehci_device_intr_abort(usbd_xfer_handle xfer) 3549 { 3550 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3551 if (xfer->pipe->intrxfer == xfer) { 3552 DPRINTFN(1, ("ehci_device_intr_abort: remove\n")); 3553 xfer->pipe->intrxfer = NULL; 3554 } 3555 /* 3556 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3557 * async doorbell. That's dependant on the async list, wheras 3558 * intr xfers are periodic, should not use this? 3559 */ 3560 ehci_abort_xfer(xfer, USBD_CANCELLED); 3561 } 3562 3563 void 3564 ehci_device_intr_close(usbd_pipe_handle pipe) 3565 { 3566 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3567 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3568 struct ehci_soft_islot *isp; 3569 3570 isp = &sc->sc_islots[epipe->sqh->islot]; 3571 ehci_close_pipe(pipe, isp->sqh); 3572 } 3573 3574 void 3575 ehci_device_intr_done(usbd_xfer_handle xfer) 3576 { 3577 #define exfer EXFER(xfer) 3578 struct ehci_xfer *ex = EXFER(xfer); 3579 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3580 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3581 ehci_soft_qtd_t *data, *dataend; 3582 ehci_soft_qh_t *sqh; 3583 usbd_status err; 3584 int len, isread, endpt, s; 3585 3586 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3587 xfer, xfer->actlen)); 3588 3589 if (xfer->pipe->repeat) { 3590 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3591 3592 len = epipe->u.intr.length; 3593 xfer->length = len; 3594 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3595 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3596 sqh = epipe->sqh; 3597 3598 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3599 &data, &dataend); 3600 if (err) { 3601 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3602 xfer->status = err; 3603 return; 3604 } 3605 3606 /* Set up interrupt info. */ 3607 exfer->sqtdstart = data; 3608 exfer->sqtdend = dataend; 3609 #ifdef DIAGNOSTIC 3610 if (!exfer->isdone) { 3611 printf("ehci_device_intr_done: not done, ex=%p\n", 3612 exfer); 3613 } 3614 exfer->isdone = 0; 3615 #endif 3616 3617 s = splusb(); 3618 ehci_set_qh_qtd(sqh, data); 3619 if (xfer->timeout && !sc->sc_bus.use_polling) { 3620 timeout_del(&xfer->timeout_handle); 3621 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3622 timeout_add(&xfer->timeout_handle, 3623 mstohz(xfer->timeout)); 3624 } 3625 splx(s); 3626 3627 xfer->status = USBD_IN_PROGRESS; 3628 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3629 ehci_del_intr_list(sc, ex); /* remove from active list */ 3630 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3631 } 3632 #undef exfer 3633 } 3634 3635 /************************/ 3636 3637 usbd_status 3638 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3639 { 3640 usbd_status err; 3641 3642 err = usb_insert_transfer(xfer); 3643 if (err && err != USBD_IN_PROGRESS) 3644 return (err); 3645 3646 return (ehci_device_isoc_start(xfer)); 3647 } 3648 3649 usbd_status 3650 ehci_device_isoc_start(usbd_xfer_handle xfer) 3651 { 3652 struct ehci_pipe *epipe; 3653 ehci_softc_t *sc; 3654 struct ehci_xfer *exfer; 3655 ehci_soft_itd_t *itd, *prev, *start, *stop; 3656 usb_dma_t *dma_buf; 3657 int i, j, k, frames, uframes, ufrperframe; 3658 int s, trans_count, offs, total_length; 3659 int frindex; 3660 3661 start = NULL; 3662 prev = NULL; 3663 itd = NULL; 3664 trans_count = 0; 3665 total_length = 0; 3666 exfer = (struct ehci_xfer *) xfer; 3667 sc = (ehci_softc_t *)xfer->pipe->device->bus; 3668 epipe = (struct ehci_pipe *)xfer->pipe; 3669 3670 /* 3671 * To allow continuous transfers, above we start all transfers 3672 * immediately. However, we're still going to get usbd_start_next call 3673 * this when another xfer completes. So, check if this is already 3674 * in progress or not 3675 */ 3676 3677 if (exfer->itdstart != NULL) 3678 return (USBD_IN_PROGRESS); 3679 3680 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3681 xfer, xfer->length, xfer->flags)); 3682 3683 if (sc->sc_dying) 3684 return (USBD_IOERROR); 3685 3686 /* 3687 * To avoid complication, don't allow a request right now that'll span 3688 * the entire frame table. To within 4 frames, to allow some leeway 3689 * on either side of where the hc currently is. 3690 */ 3691 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3692 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3693 printf("ehci: isoc descriptor requested that spans the entire " 3694 "frametable, too many frames\n"); 3695 return (USBD_INVAL); 3696 } 3697 3698 #ifdef DIAGNOSTIC 3699 if (xfer->rqflags & URQ_REQUEST) 3700 panic("ehci_device_isoc_start: request"); 3701 3702 if (!exfer->isdone) 3703 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3704 exfer->isdone = 0; 3705 #endif 3706 3707 /* 3708 * Step 1: Allocate and initialize itds, how many do we need? 3709 * One per transfer if interval >= 8 microframes, fewer if we use 3710 * multiple microframes per frame. 3711 */ 3712 3713 i = epipe->pipe.endpoint->edesc->bInterval; 3714 if (i > 16 || i == 0) { 3715 /* Spec page 271 says intervals > 16 are invalid */ 3716 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3717 return (USBD_INVAL); 3718 } 3719 3720 switch (i) { 3721 case 1: 3722 ufrperframe = 8; 3723 break; 3724 case 2: 3725 ufrperframe = 4; 3726 break; 3727 case 3: 3728 ufrperframe = 2; 3729 break; 3730 default: 3731 ufrperframe = 1; 3732 break; 3733 } 3734 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3735 uframes = 8 / ufrperframe; 3736 3737 if (frames == 0) { 3738 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3739 return (USBD_INVAL); 3740 } 3741 3742 dma_buf = &xfer->dmabuf; 3743 offs = 0; 3744 3745 for (i = 0; i < frames; i++) { 3746 int froffs = offs; 3747 itd = ehci_alloc_itd(sc); 3748 3749 if (prev != NULL) { 3750 prev->itd.itd_next = 3751 htole32(itd->physaddr | EHCI_LINK_ITD); 3752 prev->xfer_next = itd; 3753 } else { 3754 start = itd; 3755 } 3756 3757 /* 3758 * Step 1.5, initialize uframes 3759 */ 3760 for (j = 0; j < 8; j += uframes) { 3761 /* Calculate which page in the list this starts in */ 3762 int addr = DMAADDR(dma_buf, froffs); 3763 addr = EHCI_PAGE_OFFSET(addr); 3764 addr += (offs - froffs); 3765 addr = EHCI_PAGE(addr); 3766 addr /= EHCI_PAGE_SIZE; 3767 3768 /* This gets the initial offset into the first page, 3769 * looks how far further along the current uframe 3770 * offset is. Works out how many pages that is. 3771 */ 3772 3773 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3774 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3775 EHCI_ITD_SET_PG(addr) | 3776 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf, 3777 offs)))); 3778 3779 total_length += xfer->frlengths[trans_count]; 3780 offs += xfer->frlengths[trans_count]; 3781 trans_count++; 3782 3783 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3784 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3785 break; 3786 } 3787 } 3788 3789 /* Step 1.75, set buffer pointers. To simplify matters, all 3790 * pointers are filled out for the next 7 hardware pages in 3791 * the dma block, so no need to worry what pages to cover 3792 * and what to not. 3793 */ 3794 3795 for (j=0; j < 7; j++) { 3796 /* 3797 * Don't try to lookup a page that's past the end 3798 * of buffer 3799 */ 3800 int page_offs = EHCI_PAGE(froffs + 3801 (EHCI_PAGE_SIZE * j)); 3802 3803 if (page_offs >= dma_buf->block->size) 3804 break; 3805 3806 long long page = DMAADDR(dma_buf, page_offs); 3807 page = EHCI_PAGE(page); 3808 itd->itd.itd_bufr[j] = 3809 htole32(EHCI_ITD_SET_BPTR(page)); 3810 itd->itd.itd_bufr_hi[j] = 3811 htole32(page >> 32); 3812 } 3813 3814 /* 3815 * Other special values 3816 */ 3817 3818 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3819 itd->itd.itd_bufr[0] |= 3820 htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3821 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3822 3823 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3824 ? 1 : 0; 3825 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3826 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3827 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3828 3829 /* FIXME: handle invalid trans */ 3830 itd->itd.itd_bufr[2] |= 3831 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3832 prev = itd; 3833 } /* End of frame */ 3834 3835 stop = itd; 3836 stop->xfer_next = NULL; 3837 exfer->isoc_len = total_length; 3838 3839 /* 3840 * Part 2: Transfer descriptors have now been set up, now they must 3841 * be scheduled into the period frame list. Erk. Not wanting to 3842 * complicate matters, transfer is denied if the transfer spans 3843 * more than the period frame list. 3844 */ 3845 3846 s = splusb(); 3847 3848 /* Start inserting frames */ 3849 if (epipe->u.isoc.cur_xfers > 0) { 3850 frindex = epipe->u.isoc.next_frame; 3851 } else { 3852 frindex = EOREAD4(sc, EHCI_FRINDEX); 3853 frindex = frindex >> 3; /* Erase microframe index */ 3854 frindex += 2; 3855 } 3856 3857 if (frindex >= sc->sc_flsize) 3858 frindex &= (sc->sc_flsize - 1); 3859 3860 /* Whats the frame interval? */ 3861 i = (1 << epipe->pipe.endpoint->edesc->bInterval); 3862 if (i / 8 == 0) 3863 i = 1; 3864 else 3865 i /= 8; 3866 3867 itd = start; 3868 for (j = 0; j < frames; j++) { 3869 if (itd == NULL) 3870 panic("ehci: unexpectedly ran out of isoc itds, " 3871 "isoc_start"); 3872 3873 itd->itd.itd_next = sc->sc_flist[frindex]; 3874 if (itd->itd.itd_next == 0) 3875 /* FIXME: frindex table gets initialized to NULL 3876 * or EHCI_NULL? */ 3877 itd->itd.itd_next = htole32(EHCI_NULL); 3878 3879 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 3880 itd->u.frame_list.next = sc->sc_softitds[frindex]; 3881 sc->sc_softitds[frindex] = itd; 3882 if (itd->u.frame_list.next != NULL) 3883 itd->u.frame_list.next->u.frame_list.prev = itd; 3884 itd->slot = frindex; 3885 itd->u.frame_list.prev = NULL; 3886 3887 frindex += i; 3888 if (frindex >= sc->sc_flsize) 3889 frindex -= sc->sc_flsize; 3890 3891 itd = itd->xfer_next; 3892 } 3893 3894 epipe->u.isoc.cur_xfers++; 3895 epipe->u.isoc.next_frame = frindex; 3896 3897 exfer->itdstart = start; 3898 exfer->itdend = stop; 3899 exfer->sqtdstart = NULL; 3900 exfer->sqtdstart = NULL; 3901 3902 ehci_add_intr_list(sc, exfer); 3903 xfer->status = USBD_IN_PROGRESS; 3904 xfer->done = 0; 3905 splx(s); 3906 3907 if (sc->sc_bus.use_polling) { 3908 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 3909 ehci_waitintr(sc, xfer); 3910 } 3911 3912 return (USBD_IN_PROGRESS); 3913 } 3914 3915 void 3916 ehci_device_isoc_abort(usbd_xfer_handle xfer) 3917 { 3918 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 3919 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 3920 } 3921 3922 void 3923 ehci_device_isoc_close(usbd_pipe_handle pipe) 3924 { 3925 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 3926 } 3927 3928 void 3929 ehci_device_isoc_done(usbd_xfer_handle xfer) 3930 { 3931 struct ehci_xfer *exfer; 3932 ehci_softc_t *sc; 3933 struct ehci_pipe *epipe; 3934 int s; 3935 3936 exfer = EXFER(xfer); 3937 sc = (ehci_softc_t *)xfer->pipe->device->bus; 3938 epipe = (struct ehci_pipe *) xfer->pipe; 3939 3940 s = splusb(); 3941 epipe->u.isoc.cur_xfers--; 3942 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 3943 ehci_del_intr_list(sc, exfer); 3944 ehci_rem_free_itd_chain(sc, exfer); 3945 } 3946 splx(s); 3947 } 3948