1 /* $OpenBSD: ehci.c,v 1.210 2020/04/03 20:11:47 patrick Exp $ */ 2 /* $NetBSD: ehci.c,v 1.66 2004/06/30 03:11:56 mycroft Exp $ */ 3 4 /* 5 * Copyright (c) 2014-2015 Martin Pieuchot 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 /* 20 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 21 * All rights reserved. 22 * 23 * This code is derived from software contributed to The NetBSD Foundation 24 * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and 25 * Jeremy Morse (jeremy.morse@gmail.com). 26 * 27 * Redistribution and use in source and binary forms, with or without 28 * modification, are permitted provided that the following conditions 29 * are met: 30 * 1. Redistributions of source code must retain the above copyright 31 * notice, this list of conditions and the following disclaimer. 32 * 2. Redistributions in binary form must reproduce the above copyright 33 * notice, this list of conditions and the following disclaimer in the 34 * documentation and/or other materials provided with the distribution. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 37 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 38 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 39 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 40 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 41 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 42 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 43 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 44 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 45 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 46 * POSSIBILITY OF SUCH DAMAGE. 47 */ 48 49 /* 50 * TODO: 51 * 1) The hub driver needs to handle and schedule the transaction translator, 52 * to assign place in frame where different devices get to go. See chapter 53 * on hubs in USB 2.0 for details. 54 * 55 * 2) Command failures are not recovered correctly. 56 */ 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/kernel.h> 61 #include <sys/rwlock.h> 62 #include <sys/malloc.h> 63 #include <sys/device.h> 64 #include <sys/queue.h> 65 #include <sys/timeout.h> 66 #include <sys/pool.h> 67 #include <sys/endian.h> 68 #include <sys/atomic.h> 69 70 #include <machine/bus.h> 71 72 #include <dev/usb/usb.h> 73 #include <dev/usb/usbdi.h> 74 #include <dev/usb/usbdivar.h> 75 #include <dev/usb/usb_mem.h> 76 77 #include <dev/usb/ehcireg.h> 78 #include <dev/usb/ehcivar.h> 79 80 struct cfdriver ehci_cd = { 81 NULL, "ehci", DV_DULL 82 }; 83 84 #ifdef EHCI_DEBUG 85 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 86 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 87 int ehcidebug = 0; 88 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 89 #else 90 #define DPRINTF(x) 91 #define DPRINTFN(n,x) 92 #endif 93 94 struct pool *ehcixfer; 95 96 struct ehci_pipe { 97 struct usbd_pipe pipe; 98 99 struct ehci_soft_qh *sqh; 100 union { 101 /* Control pipe */ 102 struct { 103 struct usb_dma reqdma; 104 } ctl; 105 /* Iso pipe */ 106 struct { 107 u_int next_frame; 108 u_int cur_xfers; 109 } isoc; 110 } u; 111 }; 112 113 u_int8_t ehci_reverse_bits(u_int8_t, int); 114 115 usbd_status ehci_open(struct usbd_pipe *); 116 int ehci_setaddr(struct usbd_device *, int); 117 void ehci_poll(struct usbd_bus *); 118 void ehci_softintr(void *); 119 int ehci_intr1(struct ehci_softc *); 120 void ehci_check_intr(struct ehci_softc *, struct usbd_xfer *); 121 void ehci_check_qh_intr(struct ehci_softc *, struct usbd_xfer *); 122 void ehci_check_itd_intr(struct ehci_softc *, struct usbd_xfer *); 123 void ehci_idone(struct usbd_xfer *); 124 void ehci_isoc_idone(struct usbd_xfer *); 125 void ehci_timeout(void *); 126 void ehci_timeout_task(void *); 127 void ehci_intrlist_timeout(void *); 128 129 struct usbd_xfer *ehci_allocx(struct usbd_bus *); 130 void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 131 132 usbd_status ehci_root_ctrl_transfer(struct usbd_xfer *); 133 usbd_status ehci_root_ctrl_start(struct usbd_xfer *); 134 void ehci_root_ctrl_abort(struct usbd_xfer *); 135 void ehci_root_ctrl_close(struct usbd_pipe *); 136 void ehci_root_ctrl_done(struct usbd_xfer *); 137 138 usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 139 usbd_status ehci_root_intr_start(struct usbd_xfer *); 140 void ehci_root_intr_abort(struct usbd_xfer *); 141 void ehci_root_intr_close(struct usbd_pipe *); 142 void ehci_root_intr_done(struct usbd_xfer *); 143 144 usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 145 usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 146 void ehci_device_ctrl_abort(struct usbd_xfer *); 147 void ehci_device_ctrl_close(struct usbd_pipe *); 148 void ehci_device_ctrl_done(struct usbd_xfer *); 149 150 usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 151 usbd_status ehci_device_bulk_start(struct usbd_xfer *); 152 void ehci_device_bulk_abort(struct usbd_xfer *); 153 void ehci_device_bulk_close(struct usbd_pipe *); 154 void ehci_device_bulk_done(struct usbd_xfer *); 155 156 usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 157 usbd_status ehci_device_intr_start(struct usbd_xfer *); 158 void ehci_device_intr_abort(struct usbd_xfer *); 159 void ehci_device_intr_close(struct usbd_pipe *); 160 void ehci_device_intr_done(struct usbd_xfer *); 161 162 usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 163 usbd_status ehci_device_isoc_start(struct usbd_xfer *); 164 void ehci_device_isoc_abort(struct usbd_xfer *); 165 void ehci_device_isoc_close(struct usbd_pipe *); 166 void ehci_device_isoc_done(struct usbd_xfer *); 167 168 void ehci_device_clear_toggle(struct usbd_pipe *pipe); 169 170 void ehci_pcd(struct ehci_softc *, struct usbd_xfer *); 171 void ehci_disown(struct ehci_softc *, int, int); 172 173 struct ehci_soft_qh *ehci_alloc_sqh(struct ehci_softc *); 174 void ehci_free_sqh(struct ehci_softc *, struct ehci_soft_qh *); 175 176 struct ehci_soft_qtd *ehci_alloc_sqtd(struct ehci_softc *); 177 void ehci_free_sqtd(struct ehci_softc *, struct ehci_soft_qtd *); 178 usbd_status ehci_alloc_sqtd_chain(struct ehci_softc *, u_int, 179 struct usbd_xfer *, struct ehci_soft_qtd **, struct ehci_soft_qtd **); 180 void ehci_free_sqtd_chain(struct ehci_softc *, struct ehci_xfer *); 181 182 struct ehci_soft_itd *ehci_alloc_itd(struct ehci_softc *); 183 void ehci_free_itd(struct ehci_softc *, struct ehci_soft_itd *); 184 void ehci_rem_itd_chain(struct ehci_softc *, struct ehci_xfer *); 185 void ehci_free_itd_chain(struct ehci_softc *, struct ehci_xfer *); 186 int ehci_alloc_itd_chain(struct ehci_softc *, struct usbd_xfer *); 187 int ehci_alloc_sitd_chain(struct ehci_softc *, struct usbd_xfer *); 188 void ehci_abort_isoc_xfer(struct usbd_xfer *xfer, 189 usbd_status status); 190 191 usbd_status ehci_device_setintr(struct ehci_softc *, struct ehci_soft_qh *, 192 int ival); 193 194 void ehci_add_qh(struct ehci_soft_qh *, struct ehci_soft_qh *); 195 void ehci_rem_qh(struct ehci_softc *, struct ehci_soft_qh *); 196 void ehci_set_qh_qtd(struct ehci_soft_qh *, struct ehci_soft_qtd *); 197 void ehci_sync_hc(struct ehci_softc *); 198 199 void ehci_close_pipe(struct usbd_pipe *); 200 void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 201 202 #ifdef EHCI_DEBUG 203 void ehci_dump_regs(struct ehci_softc *); 204 void ehci_dump(void); 205 struct ehci_softc *theehci; 206 void ehci_dump_link(ehci_link_t, int); 207 void ehci_dump_sqtds(struct ehci_soft_qtd *); 208 void ehci_dump_sqtd(struct ehci_soft_qtd *); 209 void ehci_dump_qtd(struct ehci_qtd *); 210 void ehci_dump_sqh(struct ehci_soft_qh *); 211 #if notyet 212 void ehci_dump_itd(struct ehci_soft_itd *); 213 #endif 214 #ifdef DIAGNOSTIC 215 void ehci_dump_exfer(struct ehci_xfer *); 216 #endif 217 #endif 218 219 #define EHCI_INTR_ENDPT 1 220 221 struct usbd_bus_methods ehci_bus_methods = { 222 .open_pipe = ehci_open, 223 .dev_setaddr = ehci_setaddr, 224 .soft_intr = ehci_softintr, 225 .do_poll = ehci_poll, 226 .allocx = ehci_allocx, 227 .freex = ehci_freex, 228 }; 229 230 struct usbd_pipe_methods ehci_root_ctrl_methods = { 231 .transfer = ehci_root_ctrl_transfer, 232 .start = ehci_root_ctrl_start, 233 .abort = ehci_root_ctrl_abort, 234 .close = ehci_root_ctrl_close, 235 .done = ehci_root_ctrl_done, 236 }; 237 238 struct usbd_pipe_methods ehci_root_intr_methods = { 239 .transfer = ehci_root_intr_transfer, 240 .start = ehci_root_intr_start, 241 .abort = ehci_root_intr_abort, 242 .close = ehci_root_intr_close, 243 .done = ehci_root_intr_done, 244 }; 245 246 struct usbd_pipe_methods ehci_device_ctrl_methods = { 247 .transfer = ehci_device_ctrl_transfer, 248 .start = ehci_device_ctrl_start, 249 .abort = ehci_device_ctrl_abort, 250 .close = ehci_device_ctrl_close, 251 .done = ehci_device_ctrl_done, 252 }; 253 254 struct usbd_pipe_methods ehci_device_intr_methods = { 255 .transfer = ehci_device_intr_transfer, 256 .start = ehci_device_intr_start, 257 .abort = ehci_device_intr_abort, 258 .close = ehci_device_intr_close, 259 .cleartoggle = ehci_device_clear_toggle, 260 .done = ehci_device_intr_done, 261 }; 262 263 struct usbd_pipe_methods ehci_device_bulk_methods = { 264 .transfer = ehci_device_bulk_transfer, 265 .start = ehci_device_bulk_start, 266 .abort = ehci_device_bulk_abort, 267 .close = ehci_device_bulk_close, 268 .cleartoggle = ehci_device_clear_toggle, 269 .done = ehci_device_bulk_done, 270 }; 271 272 struct usbd_pipe_methods ehci_device_isoc_methods = { 273 .transfer = ehci_device_isoc_transfer, 274 .start = ehci_device_isoc_start, 275 .abort = ehci_device_isoc_abort, 276 .close = ehci_device_isoc_close, 277 .done = ehci_device_isoc_done, 278 }; 279 280 /* 281 * Reverse a number with nbits bits. Used to evenly distribute lower-level 282 * interrupt heads in the periodic schedule. 283 * Suitable for use with EHCI_IPOLLRATES <= 9. 284 */ 285 u_int8_t 286 ehci_reverse_bits(u_int8_t c, int nbits) 287 { 288 c = ((c >> 1) & 0x55) | ((c << 1) & 0xaa); 289 c = ((c >> 2) & 0x33) | ((c << 2) & 0xcc); 290 c = ((c >> 4) & 0x0f) | ((c << 4) & 0xf0); 291 292 return c >> (8 - nbits); 293 } 294 295 usbd_status 296 ehci_init(struct ehci_softc *sc) 297 { 298 u_int32_t sparams, cparams, hcr; 299 u_int i, j; 300 usbd_status err; 301 struct ehci_soft_qh *sqh; 302 303 #ifdef EHCI_DEBUG 304 u_int32_t vers; 305 theehci = sc; 306 307 DPRINTF(("ehci_init: start\n")); 308 309 vers = EREAD2(sc, EHCI_HCIVERSION); 310 DPRINTF(("%s: EHCI version %x.%x\n", sc->sc_bus.bdev.dv_xname, 311 vers >> 8, vers & 0xff)); 312 #endif 313 314 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 315 316 sparams = EREAD4(sc, EHCI_HCSPARAMS); 317 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 318 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 319 cparams = EREAD4(sc, EHCI_HCCPARAMS); 320 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 321 322 /* MUST clear segment register if 64 bit capable. */ 323 if (EHCI_HCC_64BIT(cparams)) 324 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 325 326 sc->sc_bus.usbrev = USBREV_2_0; 327 328 DPRINTF(("%s: resetting\n", sc->sc_bus.bdev.dv_xname)); 329 err = ehci_reset(sc); 330 if (err) 331 return (err); 332 333 if (ehcixfer == NULL) { 334 ehcixfer = malloc(sizeof(struct pool), M_DEVBUF, M_NOWAIT); 335 if (ehcixfer == NULL) { 336 printf("%s: unable to allocate pool descriptor\n", 337 sc->sc_bus.bdev.dv_xname); 338 return (ENOMEM); 339 } 340 pool_init(ehcixfer, sizeof(struct ehci_xfer), 0, IPL_SOFTUSB, 341 0, "ehcixfer", NULL); 342 } 343 344 /* frame list size at default, read back what we got and use that */ 345 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 346 case 0: 347 sc->sc_flsize = 1024; 348 break; 349 case 1: 350 sc->sc_flsize = 512; 351 break; 352 case 2: 353 sc->sc_flsize = 256; 354 break; 355 case 3: 356 return (USBD_IOERROR); 357 } 358 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 359 EHCI_FLALIGN_ALIGN, USB_DMA_COHERENT, &sc->sc_fldma); 360 if (err) 361 return (err); 362 DPRINTF(("%s: flsize=%d\n", sc->sc_bus.bdev.dv_xname,sc->sc_flsize)); 363 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 364 365 for (i = 0; i < sc->sc_flsize; i++) 366 sc->sc_flist[i] = htole32(EHCI_LINK_TERMINATE); 367 368 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 369 370 sc->sc_softitds = mallocarray(sc->sc_flsize, 371 sizeof(struct ehci_soft_itd *), M_USB, M_NOWAIT | M_ZERO); 372 if (sc->sc_softitds == NULL) { 373 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 374 return (ENOMEM); 375 } 376 LIST_INIT(&sc->sc_freeitds); 377 TAILQ_INIT(&sc->sc_intrhead); 378 379 /* Set up the bus struct. */ 380 sc->sc_bus.methods = &ehci_bus_methods; 381 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 382 383 sc->sc_eintrs = EHCI_NORMAL_INTRS; 384 385 /* 386 * Allocate the interrupt dummy QHs. These are arranged to give poll 387 * intervals that are powers of 2 times 1ms. 388 */ 389 for (i = 0; i < EHCI_INTRQHS; i++) { 390 sqh = ehci_alloc_sqh(sc); 391 if (sqh == NULL) { 392 err = USBD_NOMEM; 393 goto bad1; 394 } 395 sc->sc_islots[i].sqh = sqh; 396 } 397 for (i = 0; i < EHCI_INTRQHS; i++) { 398 sqh = sc->sc_islots[i].sqh; 399 if (i == 0) { 400 /* The last (1ms) QH terminates. */ 401 sqh->qh.qh_link = htole32(EHCI_LINK_TERMINATE); 402 sqh->next = NULL; 403 } else { 404 /* Otherwise the next QH has half the poll interval */ 405 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 406 sqh->qh.qh_link = htole32(sqh->next->physaddr | 407 EHCI_LINK_QH); 408 } 409 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 410 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 411 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 412 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 413 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 414 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 415 sqh->sqtd = NULL; 416 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 417 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 418 } 419 /* Point the frame list at the last level (128ms). */ 420 for (i = 0; i < (1 << (EHCI_IPOLLRATES - 1)); i++) 421 for (j = i; j < sc->sc_flsize; j += 1 << (EHCI_IPOLLRATES - 1)) 422 sc->sc_flist[j] = htole32(EHCI_LINK_QH | sc->sc_islots[ 423 EHCI_IQHIDX(EHCI_IPOLLRATES - 1, ehci_reverse_bits( 424 i, EHCI_IPOLLRATES - 1))].sqh->physaddr); 425 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 426 BUS_DMASYNC_PREWRITE); 427 428 /* Allocate dummy QH that starts the async list. */ 429 sqh = ehci_alloc_sqh(sc); 430 if (sqh == NULL) { 431 err = USBD_NOMEM; 432 goto bad1; 433 } 434 /* Fill the QH */ 435 sqh->qh.qh_endp = 436 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 437 sqh->qh.qh_link = 438 htole32(sqh->physaddr | EHCI_LINK_QH); 439 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 440 sqh->prev = sqh; /*It's a circular list.. */ 441 sqh->next = sqh; 442 /* Fill the overlay qTD */ 443 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 444 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 445 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 446 sqh->sqtd = NULL; 447 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 448 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 449 450 /* Point to async list */ 451 sc->sc_async_head = sqh; 452 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 453 454 timeout_set(&sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 455 456 rw_init(&sc->sc_doorbell_lock, "ehcidb"); 457 458 /* Turn on controller */ 459 EOWRITE4(sc, EHCI_USBCMD, 460 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 461 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 462 EHCI_CMD_ASE | 463 EHCI_CMD_PSE | 464 EHCI_CMD_RS); 465 466 /* Take over port ownership */ 467 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 468 469 for (i = 0; i < 100; i++) { 470 usb_delay_ms(&sc->sc_bus, 1); 471 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 472 if (!hcr) 473 break; 474 } 475 if (hcr) { 476 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 477 return (USBD_IOERROR); 478 } 479 480 /* Enable interrupts */ 481 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 482 483 return (USBD_NORMAL_COMPLETION); 484 485 #if 0 486 bad2: 487 ehci_free_sqh(sc, sc->sc_async_head); 488 #endif 489 bad1: 490 free(sc->sc_softitds, M_USB, 491 sc->sc_flsize * sizeof(struct ehci_soft_itd *)); 492 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 493 return (err); 494 } 495 496 int 497 ehci_intr(void *v) 498 { 499 struct ehci_softc *sc = v; 500 501 if (sc == NULL || sc->sc_bus.dying) 502 return (0); 503 504 /* If we get an interrupt while polling, then just ignore it. */ 505 if (sc->sc_bus.use_polling) { 506 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 507 508 if (intrs) 509 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 510 return (0); 511 } 512 513 return (ehci_intr1(sc)); 514 } 515 516 int 517 ehci_intr1(struct ehci_softc *sc) 518 { 519 u_int32_t intrs, eintrs; 520 521 /* In case the interrupt occurs before initialization has completed. */ 522 if (sc == NULL) { 523 #ifdef DIAGNOSTIC 524 printf("ehci_intr1: sc == NULL\n"); 525 #endif 526 return (0); 527 } 528 529 intrs = EOREAD4(sc, EHCI_USBSTS); 530 if (intrs == 0xffffffff) { 531 sc->sc_bus.dying = 1; 532 return (0); 533 } 534 intrs = EHCI_STS_INTRS(intrs); 535 if (!intrs) 536 return (0); 537 538 eintrs = intrs & sc->sc_eintrs; 539 if (!eintrs) 540 return (0); 541 542 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 543 sc->sc_bus.no_intrs++; 544 545 if (eintrs & EHCI_STS_HSE) { 546 printf("%s: unrecoverable error, controller halted\n", 547 sc->sc_bus.bdev.dv_xname); 548 sc->sc_bus.dying = 1; 549 return (1); 550 } 551 if (eintrs & EHCI_STS_IAA) { 552 wakeup(&sc->sc_async_head); 553 eintrs &= ~EHCI_STS_IAA; 554 } 555 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 556 usb_schedsoftintr(&sc->sc_bus); 557 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 558 } 559 if (eintrs & EHCI_STS_PCD) { 560 atomic_setbits_int(&sc->sc_flags, EHCIF_PCB_INTR); 561 usb_schedsoftintr(&sc->sc_bus); 562 eintrs &= ~EHCI_STS_PCD; 563 } 564 565 if (eintrs != 0) { 566 /* Block unprocessed interrupts. */ 567 sc->sc_eintrs &= ~eintrs; 568 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 569 printf("%s: blocking intrs 0x%x\n", 570 sc->sc_bus.bdev.dv_xname, eintrs); 571 } 572 573 return (1); 574 } 575 576 void 577 ehci_pcd(struct ehci_softc *sc, struct usbd_xfer *xfer) 578 { 579 u_char *p; 580 int i, m; 581 582 if (xfer == NULL) { 583 /* Just ignore the change. */ 584 return; 585 } 586 587 p = KERNADDR(&xfer->dmabuf, 0); 588 m = min(sc->sc_noport, xfer->length * 8 - 1); 589 memset(p, 0, xfer->length); 590 for (i = 1; i <= m; i++) { 591 /* Pick out CHANGE bits from the status reg. */ 592 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 593 p[i / 8] |= 1 << (i % 8); 594 } 595 xfer->actlen = xfer->length; 596 xfer->status = USBD_NORMAL_COMPLETION; 597 598 usb_transfer_complete(xfer); 599 } 600 601 /* 602 * Work around the half configured control (default) pipe when setting 603 * the address of a device. 604 * 605 * Because a single QH is setup per endpoint in ehci_open(), and the 606 * control pipe is configured before we could have set the address 607 * of the device or read the wMaxPacketSize of the endpoint, we have 608 * to re-open the pipe twice here. 609 */ 610 int 611 ehci_setaddr(struct usbd_device *dev, int addr) 612 { 613 /* Root Hub */ 614 if (dev->depth == 0) 615 return (0); 616 617 /* Re-establish the default pipe with the new max packet size. */ 618 ehci_close_pipe(dev->default_pipe); 619 if (ehci_open(dev->default_pipe)) 620 return (EINVAL); 621 622 if (usbd_set_address(dev, addr)) 623 return (1); 624 625 dev->address = addr; 626 627 /* Re-establish the default pipe with the new address. */ 628 ehci_close_pipe(dev->default_pipe); 629 if (ehci_open(dev->default_pipe)) 630 return (EINVAL); 631 632 return (0); 633 } 634 635 void 636 ehci_softintr(void *v) 637 { 638 struct ehci_softc *sc = v; 639 struct ehci_xfer *ex, *nextex; 640 641 if (sc->sc_bus.dying) 642 return; 643 644 sc->sc_bus.intr_context++; 645 646 if (sc->sc_flags & EHCIF_PCB_INTR) { 647 atomic_clearbits_int(&sc->sc_flags, EHCIF_PCB_INTR); 648 ehci_pcd(sc, sc->sc_intrxfer); 649 } 650 651 /* 652 * The only explanation I can think of for why EHCI is as brain dead 653 * as UHCI interrupt-wise is that Intel was involved in both. 654 * An interrupt just tells us that something is done, we have no 655 * clue what, so we need to scan through all active transfers. :-( 656 */ 657 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 658 nextex = TAILQ_NEXT(ex, inext); 659 ehci_check_intr(sc, &ex->xfer); 660 } 661 662 /* Schedule a callout to catch any dropped transactions. */ 663 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 664 !TAILQ_EMPTY(&sc->sc_intrhead)) { 665 timeout_add_sec(&sc->sc_tmo_intrlist, 1); 666 } 667 668 if (sc->sc_softwake) { 669 sc->sc_softwake = 0; 670 wakeup(&sc->sc_softwake); 671 } 672 673 sc->sc_bus.intr_context--; 674 } 675 676 void 677 ehci_check_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 678 { 679 int attr = xfer->pipe->endpoint->edesc->bmAttributes; 680 681 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 682 ehci_check_itd_intr(sc, xfer); 683 else 684 ehci_check_qh_intr(sc, xfer); 685 } 686 687 void 688 ehci_check_qh_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 689 { 690 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 691 struct ehci_soft_qtd *sqtd, *lsqtd = ex->sqtdend; 692 uint32_t status; 693 694 KASSERT(ex->sqtdstart != NULL && ex->sqtdend != NULL); 695 696 usb_syncmem(&lsqtd->dma, 697 lsqtd->offs + offsetof(struct ehci_qtd, qtd_status), 698 sizeof(lsqtd->qtd.qtd_status), 699 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 700 701 /* 702 * If the last TD is still active we need to check whether there 703 * is a an error somewhere in the middle, or whether there was a 704 * short packet (SPD and not ACTIVE). 705 */ 706 if (letoh32(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 707 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 708 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 709 usb_syncmem(&sqtd->dma, 710 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 711 sizeof(sqtd->qtd.qtd_status), 712 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 713 status = letoh32(sqtd->qtd.qtd_status); 714 usb_syncmem(&sqtd->dma, 715 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 716 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 717 /* If there's an active QTD the xfer isn't done. */ 718 if (status & EHCI_QTD_ACTIVE) 719 break; 720 /* Any kind of error makes the xfer done. */ 721 if (status & EHCI_QTD_HALTED) 722 goto done; 723 /* We want short packets, and it is short: it's done */ 724 if (EHCI_QTD_GET_BYTES(status) != 0) 725 goto done; 726 } 727 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 728 ex, ex->sqtdstart)); 729 usb_syncmem(&lsqtd->dma, 730 lsqtd->offs + offsetof(struct ehci_qtd, qtd_status), 731 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 732 return; 733 } 734 done: 735 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 736 timeout_del(&xfer->timeout_handle); 737 usb_rem_task(xfer->pipe->device, &xfer->abort_task); 738 ehci_idone(xfer); 739 } 740 741 void 742 ehci_check_itd_intr(struct ehci_softc *sc, struct usbd_xfer *xfer) 743 { 744 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 745 struct ehci_soft_itd *itd = ex->itdend; 746 int i; 747 748 if (xfer != SIMPLEQ_FIRST(&xfer->pipe->queue)) 749 return; 750 751 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 752 753 /* Check no active transfers in last itd, meaning we're finished */ 754 if (xfer->device->speed == USB_SPEED_HIGH) { 755 usb_syncmem(&itd->dma, 756 itd->offs + offsetof(struct ehci_itd, itd_ctl), 757 sizeof(itd->itd.itd_ctl), 758 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 759 760 for (i = 0; i < 8; i++) { 761 if (letoh32(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 762 return; 763 } 764 } else { 765 usb_syncmem(&itd->dma, 766 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 767 sizeof(itd->sitd.sitd_trans), 768 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 769 770 if (le32toh(itd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 771 return; 772 } 773 774 /* All descriptor(s) inactive, it's done */ 775 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 776 timeout_del(&xfer->timeout_handle); 777 usb_rem_task(xfer->pipe->device, &xfer->abort_task); 778 ehci_isoc_idone(xfer); 779 } 780 781 void 782 ehci_isoc_idone(struct usbd_xfer *xfer) 783 { 784 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 785 struct ehci_soft_itd *itd; 786 int i, len, uframes, nframes = 0, actlen = 0; 787 uint32_t status = 0; 788 789 if (xfer->status == USBD_CANCELLED || xfer->status == USBD_TIMEOUT) 790 return; 791 792 if (xfer->device->speed == USB_SPEED_HIGH) { 793 switch (xfer->pipe->endpoint->edesc->bInterval) { 794 case 0: 795 panic("isoc xfer suddenly has 0 bInterval, invalid"); 796 case 1: 797 uframes = 1; 798 break; 799 case 2: 800 uframes = 2; 801 break; 802 case 3: 803 uframes = 4; 804 break; 805 default: 806 uframes = 8; 807 break; 808 } 809 810 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 811 usb_syncmem(&itd->dma, 812 itd->offs + offsetof(struct ehci_itd, itd_ctl), 813 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 814 BUS_DMASYNC_POSTREAD); 815 816 for (i = 0; i < 8; i += uframes) { 817 /* XXX - driver didn't fill in the frame full 818 * of uframes. This leads to scheduling 819 * inefficiencies, but working around 820 * this doubles complexity of tracking 821 * an xfer. 822 */ 823 if (nframes >= xfer->nframes) 824 break; 825 826 status = letoh32(itd->itd.itd_ctl[i]); 827 len = EHCI_ITD_GET_LEN(status); 828 if (EHCI_ITD_GET_STATUS(status) != 0) 829 len = 0; /*No valid data on error*/ 830 831 xfer->frlengths[nframes++] = len; 832 actlen += len; 833 } 834 } 835 } else { 836 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 837 usb_syncmem(&itd->dma, 838 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 839 sizeof(itd->sitd.sitd_trans), 840 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 841 842 status = le32toh(itd->sitd.sitd_trans); 843 len = EHCI_SITD_GET_LEN(status); 844 if (xfer->frlengths[nframes] >= len) 845 len = xfer->frlengths[nframes] - len; 846 else 847 len = 0; 848 849 xfer->frlengths[nframes++] = len; 850 actlen += len; 851 } 852 } 853 854 #ifdef DIAGNOSTIC 855 ex->isdone = 1; 856 #endif 857 xfer->actlen = actlen; 858 xfer->status = USBD_NORMAL_COMPLETION; 859 860 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 861 usbd_xfer_isread(xfer) ? 862 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 863 usb_transfer_complete(xfer); 864 } 865 866 void 867 ehci_idone(struct usbd_xfer *xfer) 868 { 869 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 870 struct ehci_soft_qtd *sqtd; 871 u_int32_t status = 0, nstatus = 0; 872 int actlen, cerr; 873 874 #ifdef DIAGNOSTIC 875 { 876 int s = splhigh(); 877 if (ex->isdone) { 878 splx(s); 879 printf("ehci_idone: ex=%p is done!\n", ex); 880 return; 881 } 882 ex->isdone = 1; 883 splx(s); 884 } 885 #endif 886 if (xfer->status == USBD_CANCELLED || xfer->status == USBD_TIMEOUT) 887 return; 888 889 actlen = 0; 890 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) { 891 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 892 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 893 nstatus = letoh32(sqtd->qtd.qtd_status); 894 if (nstatus & EHCI_QTD_ACTIVE) 895 break; 896 897 status = nstatus; 898 /* halt is ok if descriptor is last, and complete */ 899 if (sqtd->qtd.qtd_next == htole32(EHCI_LINK_TERMINATE) && 900 EHCI_QTD_GET_BYTES(status) == 0) 901 status &= ~EHCI_QTD_HALTED; 902 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 903 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 904 } 905 906 cerr = EHCI_QTD_GET_CERR(status); 907 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 908 "status=0x%x\n", xfer->length, actlen, cerr, status)); 909 xfer->actlen = actlen; 910 if ((status & EHCI_QTD_HALTED) != 0) { 911 if ((status & EHCI_QTD_BABBLE) == 0 && cerr > 0) 912 xfer->status = USBD_STALLED; 913 else 914 xfer->status = USBD_IOERROR; /* more info XXX */ 915 } else 916 xfer->status = USBD_NORMAL_COMPLETION; 917 918 if (xfer->actlen) 919 usb_syncmem(&xfer->dmabuf, 0, xfer->actlen, 920 usbd_xfer_isread(xfer) ? 921 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 922 usb_transfer_complete(xfer); 923 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 924 } 925 926 void 927 ehci_poll(struct usbd_bus *bus) 928 { 929 struct ehci_softc *sc = (struct ehci_softc *)bus; 930 931 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 932 ehci_intr1(sc); 933 } 934 935 int 936 ehci_detach(struct device *self, int flags) 937 { 938 struct ehci_softc *sc = (struct ehci_softc *)self; 939 int rv; 940 941 rv = config_detach_children(self, flags); 942 if (rv != 0) 943 return (rv); 944 945 timeout_del(&sc->sc_tmo_intrlist); 946 947 ehci_reset(sc); 948 949 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 950 951 free(sc->sc_softitds, M_USB, 952 sc->sc_flsize * sizeof(struct ehci_soft_itd *)); 953 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 954 /* XXX free other data structures XXX */ 955 956 return (rv); 957 } 958 959 960 int 961 ehci_activate(struct device *self, int act) 962 { 963 struct ehci_softc *sc = (struct ehci_softc *)self; 964 u_int32_t cmd, hcr, cparams; 965 int i, rv = 0; 966 967 switch (act) { 968 case DVACT_SUSPEND: 969 rv = config_activate_children(self, act); 970 971 #ifdef DIAGNOSTIC 972 if (!TAILQ_EMPTY(&sc->sc_intrhead)) { 973 printf("%s: interrupt list not empty\n", 974 sc->sc_bus.bdev.dv_xname); 975 return (-1); 976 } 977 #endif 978 979 sc->sc_bus.use_polling++; 980 981 for (i = 1; i <= sc->sc_noport; i++) { 982 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 983 if ((cmd & (EHCI_PS_PO|EHCI_PS_PE)) == EHCI_PS_PE) 984 EOWRITE4(sc, EHCI_PORTSC(i), 985 cmd | EHCI_PS_SUSP); 986 } 987 988 /* 989 * First tell the host to stop processing Asynchronous 990 * and Periodic schedules. 991 */ 992 cmd = EOREAD4(sc, EHCI_USBCMD) & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 993 EOWRITE4(sc, EHCI_USBCMD, cmd); 994 for (i = 0; i < 100; i++) { 995 usb_delay_ms(&sc->sc_bus, 1); 996 hcr = EOREAD4(sc, EHCI_USBSTS) & 997 (EHCI_STS_ASS | EHCI_STS_PSS); 998 if (hcr == 0) 999 break; 1000 } 1001 if (hcr != 0) 1002 printf("%s: disable schedules timeout\n", 1003 sc->sc_bus.bdev.dv_xname); 1004 1005 /* 1006 * Then reset the host as if it was a shutdown. 1007 * 1008 * All USB devices are disconnected/reconnected during 1009 * a suspend/resume cycle so keep it simple. 1010 */ 1011 ehci_reset(sc); 1012 1013 sc->sc_bus.use_polling--; 1014 break; 1015 case DVACT_RESUME: 1016 sc->sc_bus.use_polling++; 1017 1018 ehci_reset(sc); 1019 1020 cparams = EREAD4(sc, EHCI_HCCPARAMS); 1021 /* MUST clear segment register if 64 bit capable. */ 1022 if (EHCI_HCC_64BIT(cparams)) 1023 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1024 1025 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1026 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1027 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1028 1029 hcr = 0; 1030 for (i = 1; i <= sc->sc_noport; i++) { 1031 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1032 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == EHCI_PS_SUSP) { 1033 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1034 hcr = 1; 1035 } 1036 } 1037 1038 if (hcr) { 1039 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1040 for (i = 1; i <= sc->sc_noport; i++) { 1041 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1042 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == 1043 EHCI_PS_SUSP) 1044 EOWRITE4(sc, EHCI_PORTSC(i), 1045 cmd & ~EHCI_PS_FPR); 1046 } 1047 } 1048 1049 /* Turn on controller */ 1050 EOWRITE4(sc, EHCI_USBCMD, 1051 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 1052 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 1053 EHCI_CMD_ASE | 1054 EHCI_CMD_PSE | 1055 EHCI_CMD_RS); 1056 1057 /* Take over port ownership */ 1058 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 1059 for (i = 0; i < 100; i++) { 1060 usb_delay_ms(&sc->sc_bus, 1); 1061 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1062 if (!hcr) 1063 break; 1064 } 1065 1066 if (hcr) { 1067 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 1068 /* XXX should we bail here? */ 1069 } 1070 1071 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1072 1073 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1074 1075 sc->sc_bus.use_polling--; 1076 rv = config_activate_children(self, act); 1077 break; 1078 case DVACT_POWERDOWN: 1079 rv = config_activate_children(self, act); 1080 ehci_reset(sc); 1081 break; 1082 default: 1083 rv = config_activate_children(self, act); 1084 break; 1085 } 1086 return (rv); 1087 } 1088 1089 usbd_status 1090 ehci_reset(struct ehci_softc *sc) 1091 { 1092 u_int32_t hcr, usbmode; 1093 int i; 1094 1095 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1096 for (i = 0; i < 100; i++) { 1097 usb_delay_ms(&sc->sc_bus, 1); 1098 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1099 if (hcr) 1100 break; 1101 } 1102 1103 if (!hcr) 1104 printf("%s: halt timeout\n", sc->sc_bus.bdev.dv_xname); 1105 1106 if (sc->sc_flags & EHCIF_USBMODE) 1107 usbmode = EOREAD4(sc, EHCI_USBMODE); 1108 1109 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1110 for (i = 0; i < 100; i++) { 1111 usb_delay_ms(&sc->sc_bus, 1); 1112 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 1113 if (!hcr) 1114 break; 1115 } 1116 1117 if (hcr) { 1118 printf("%s: reset timeout\n", sc->sc_bus.bdev.dv_xname); 1119 return (USBD_IOERROR); 1120 } 1121 1122 if (sc->sc_flags & EHCIF_USBMODE) 1123 EOWRITE4(sc, EHCI_USBMODE, usbmode); 1124 1125 return (USBD_NORMAL_COMPLETION); 1126 } 1127 1128 struct usbd_xfer * 1129 ehci_allocx(struct usbd_bus *bus) 1130 { 1131 struct ehci_xfer *ex; 1132 1133 ex = pool_get(ehcixfer, PR_NOWAIT | PR_ZERO); 1134 #ifdef DIAGNOSTIC 1135 if (ex != NULL) 1136 ex->isdone = 1; 1137 #endif 1138 return ((struct usbd_xfer *)ex); 1139 } 1140 1141 void 1142 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1143 { 1144 struct ehci_xfer *ex = (struct ehci_xfer*)xfer; 1145 1146 #ifdef DIAGNOSTIC 1147 if (!ex->isdone) { 1148 printf("%s: !isdone\n", __func__); 1149 return; 1150 } 1151 #endif 1152 pool_put(ehcixfer, ex); 1153 } 1154 1155 void 1156 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1157 { 1158 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1159 1160 #ifdef DIAGNOSTIC 1161 if ((epipe->sqh->qh.qh_qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) != 0) 1162 panic("ehci_device_clear_toggle: queue active"); 1163 #endif 1164 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1165 } 1166 1167 #ifdef EHCI_DEBUG 1168 void 1169 ehci_dump_regs(struct ehci_softc *sc) 1170 { 1171 int i; 1172 1173 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1174 EOREAD4(sc, EHCI_USBCMD), 1175 EOREAD4(sc, EHCI_USBSTS), 1176 EOREAD4(sc, EHCI_USBINTR)); 1177 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1178 EOREAD4(sc, EHCI_FRINDEX), 1179 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1180 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1181 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1182 for (i = 1; i <= sc->sc_noport; i++) 1183 printf("port %d status=0x%08x\n", i, 1184 EOREAD4(sc, EHCI_PORTSC(i))); 1185 } 1186 1187 /* 1188 * Unused function - this is meant to be called from a kernel 1189 * debugger. 1190 */ 1191 void 1192 ehci_dump(void) 1193 { 1194 ehci_dump_regs(theehci); 1195 } 1196 1197 void 1198 ehci_dump_link(ehci_link_t link, int type) 1199 { 1200 link = letoh32(link); 1201 printf("0x%08x", link); 1202 if (link & EHCI_LINK_TERMINATE) 1203 printf("<T>"); 1204 else { 1205 printf("<"); 1206 if (type) { 1207 switch (EHCI_LINK_TYPE(link)) { 1208 case EHCI_LINK_ITD: 1209 printf("ITD"); 1210 break; 1211 case EHCI_LINK_QH: 1212 printf("QH"); 1213 break; 1214 case EHCI_LINK_SITD: 1215 printf("SITD"); 1216 break; 1217 case EHCI_LINK_FSTN: 1218 printf("FSTN"); 1219 break; 1220 } 1221 } 1222 printf(">"); 1223 } 1224 } 1225 1226 void 1227 ehci_dump_sqtds(struct ehci_soft_qtd *sqtd) 1228 { 1229 int i; 1230 u_int32_t stop; 1231 1232 stop = 0; 1233 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1234 ehci_dump_sqtd(sqtd); 1235 usb_syncmem(&sqtd->dma, 1236 sqtd->offs + offsetof(struct ehci_qtd, qtd_next), 1237 sizeof(sqtd->qtd), 1238 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1239 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1240 usb_syncmem(&sqtd->dma, 1241 sqtd->offs + offsetof(struct ehci_qtd, qtd_next), 1242 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1243 } 1244 if (!stop) 1245 printf("dump aborted, too many TDs\n"); 1246 } 1247 1248 void 1249 ehci_dump_sqtd(struct ehci_soft_qtd *sqtd) 1250 { 1251 usb_syncmem(&sqtd->dma, sqtd->offs, 1252 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1253 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1254 ehci_dump_qtd(&sqtd->qtd); 1255 usb_syncmem(&sqtd->dma, sqtd->offs, 1256 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1257 } 1258 1259 void 1260 ehci_dump_qtd(struct ehci_qtd *qtd) 1261 { 1262 u_int32_t s; 1263 char sbuf[128]; 1264 1265 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1266 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1267 printf("\n"); 1268 s = letoh32(qtd->qtd_status); 1269 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), "\20\10ACTIVE\7HALTED" 1270 "\6BUFERR\5BABBLE\4XACTERR\3MISSED\2SPLIT\1PING", 1271 sbuf, sizeof(sbuf)); 1272 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1273 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1274 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1275 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1276 EHCI_QTD_GET_PID(s), sbuf); 1277 for (s = 0; s < 5; s++) 1278 printf(" buffer[%d]=0x%08x\n", s, letoh32(qtd->qtd_buffer[s])); 1279 } 1280 1281 void 1282 ehci_dump_sqh(struct ehci_soft_qh *sqh) 1283 { 1284 struct ehci_qh *qh = &sqh->qh; 1285 u_int32_t endp, endphub; 1286 1287 usb_syncmem(&sqh->dma, sqh->offs, 1288 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1289 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1290 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1291 endp = letoh32(qh->qh_endp); 1292 printf(" endp=0x%08x\n", endp); 1293 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1294 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1295 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1296 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1297 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1298 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1299 EHCI_QH_GET_NRL(endp)); 1300 endphub = letoh32(qh->qh_endphub); 1301 printf(" endphub=0x%08x\n", endphub); 1302 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1303 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1304 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1305 EHCI_QH_GET_MULT(endphub)); 1306 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1307 printf("Overlay qTD:\n"); 1308 ehci_dump_qtd(&qh->qh_qtd); 1309 usb_syncmem(&sqh->dma, sqh->offs, 1310 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1311 } 1312 1313 #if notyet 1314 void 1315 ehci_dump_itd(struct ehci_soft_itd *itd) 1316 { 1317 ehci_isoc_trans_t t; 1318 ehci_isoc_bufr_ptr_t b, b2, b3; 1319 int i; 1320 1321 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1322 1323 for (i = 0; i < 8; i++) { 1324 t = letoh32(itd->itd.itd_ctl[i]); 1325 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1326 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1327 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1328 EHCI_ITD_GET_OFFS(t)); 1329 } 1330 printf("ITDbufr: "); 1331 for (i = 0; i < 7; i++) 1332 printf("%X,", EHCI_ITD_GET_BPTR(letoh32(itd->itd.itd_bufr[i]))); 1333 1334 b = letoh32(itd->itd.itd_bufr[0]); 1335 b2 = letoh32(itd->itd.itd_bufr[1]); 1336 b3 = letoh32(itd->itd.itd_bufr[2]); 1337 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1338 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1339 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1340 } 1341 #endif 1342 1343 #ifdef DIAGNOSTIC 1344 void 1345 ehci_dump_exfer(struct ehci_xfer *ex) 1346 { 1347 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p " 1348 "isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, 1349 ex->itdend, ex->isdone); 1350 } 1351 #endif 1352 1353 #endif /* EHCI_DEBUG */ 1354 1355 usbd_status 1356 ehci_open(struct usbd_pipe *pipe) 1357 { 1358 struct usbd_device *dev = pipe->device; 1359 struct ehci_softc *sc = (struct ehci_softc *)dev->bus; 1360 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1361 u_int8_t addr = dev->address; 1362 u_int8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1363 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1364 struct ehci_soft_qh *sqh; 1365 usbd_status err; 1366 int s; 1367 int ival, speed, naks; 1368 int hshubaddr, hshubport; 1369 1370 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d\n", 1371 pipe, addr, ed->bEndpointAddress)); 1372 1373 if (sc->sc_bus.dying) 1374 return (USBD_IOERROR); 1375 1376 if (dev->myhsport) { 1377 hshubaddr = dev->myhsport->parent->address; 1378 hshubport = dev->myhsport->portno; 1379 } else { 1380 hshubaddr = 0; 1381 hshubport = 0; 1382 } 1383 1384 /* Root Hub */ 1385 if (pipe->device->depth == 0) { 1386 switch (ed->bEndpointAddress) { 1387 case USB_CONTROL_ENDPOINT: 1388 pipe->methods = &ehci_root_ctrl_methods; 1389 break; 1390 case UE_DIR_IN | EHCI_INTR_ENDPT: 1391 pipe->methods = &ehci_root_intr_methods; 1392 break; 1393 default: 1394 return (USBD_INVAL); 1395 } 1396 return (USBD_NORMAL_COMPLETION); 1397 } 1398 1399 /* XXX All this stuff is only valid for async. */ 1400 switch (dev->speed) { 1401 case USB_SPEED_LOW: 1402 speed = EHCI_QH_SPEED_LOW; 1403 break; 1404 case USB_SPEED_FULL: 1405 speed = EHCI_QH_SPEED_FULL; 1406 break; 1407 case USB_SPEED_HIGH: 1408 speed = EHCI_QH_SPEED_HIGH; 1409 break; 1410 default: 1411 panic("ehci_open: bad device speed %d", dev->speed); 1412 } 1413 1414 /* 1415 * NAK reload count: 1416 * must be zero with using periodic transfer. 1417 * Linux 4.20's driver (ehci-q.c) sets 4, we use same value. 1418 */ 1419 naks = ((xfertype == UE_CONTROL) || (xfertype == UE_BULK)) ? 4 : 0; 1420 1421 /* Allocate sqh for everything, save isoc xfers */ 1422 if (xfertype != UE_ISOCHRONOUS) { 1423 sqh = ehci_alloc_sqh(sc); 1424 if (sqh == NULL) 1425 return (USBD_NOMEM); 1426 /* qh_link filled when the QH is added */ 1427 sqh->qh.qh_endp = htole32( 1428 EHCI_QH_SET_ADDR(addr) | 1429 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1430 EHCI_QH_SET_EPS(speed) | 1431 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1432 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1433 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1434 EHCI_QH_CTL : 0) | 1435 EHCI_QH_SET_NRL(naks) 1436 ); 1437 /* 1438 * To reduce conflict with split isochronous transfer, 1439 * schedule (split) interrupt transfer at latter half of 1440 * 1ms frame: 1441 * 1442 * |<-------------- H-Frame -------------->| 1443 * .H0 :H1 H2 H3 H4 H5 H6 H7 .H0" :H1" 1444 * . : . : 1445 * [HS] . : SS CS CS' CS" . : 1446 * [FS/LS] . : |<== >>>> >>>| . : 1447 * . : . : 1448 * .B7' :B0 B1 B2 B3 B4 B5 B6 .B7 :B0" 1449 * |<-------------- B-Frame -------------->| 1450 * 1451 */ 1452 sqh->qh.qh_endphub = htole32( 1453 EHCI_QH_SET_MULT(1) | 1454 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x08 : 0) 1455 ); 1456 if (speed != EHCI_QH_SPEED_HIGH) { 1457 sqh->qh.qh_endphub |= htole32( 1458 EHCI_QH_SET_HUBA(hshubaddr) | 1459 EHCI_QH_SET_PORT(hshubport) | 1460 EHCI_QH_SET_CMASK(0xe0) 1461 ); 1462 } 1463 sqh->qh.qh_curqtd = htole32(EHCI_LINK_TERMINATE); 1464 /* Fill the overlay qTD */ 1465 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 1466 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1467 sqh->qh.qh_qtd.qtd_status = 1468 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1469 1470 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1471 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1472 epipe->sqh = sqh; 1473 } /*xfertype == UE_ISOC*/ 1474 1475 switch (xfertype) { 1476 case UE_CONTROL: 1477 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1478 0, USB_DMA_COHERENT, &epipe->u.ctl.reqdma); 1479 if (err) { 1480 ehci_free_sqh(sc, sqh); 1481 return (err); 1482 } 1483 pipe->methods = &ehci_device_ctrl_methods; 1484 s = splusb(); 1485 ehci_add_qh(sqh, sc->sc_async_head); 1486 splx(s); 1487 break; 1488 case UE_BULK: 1489 pipe->methods = &ehci_device_bulk_methods; 1490 s = splusb(); 1491 ehci_add_qh(sqh, sc->sc_async_head); 1492 splx(s); 1493 break; 1494 case UE_INTERRUPT: 1495 pipe->methods = &ehci_device_intr_methods; 1496 ival = pipe->interval; 1497 if (ival == USBD_DEFAULT_INTERVAL) 1498 ival = ed->bInterval; 1499 s = splusb(); 1500 err = ehci_device_setintr(sc, sqh, ival); 1501 splx(s); 1502 return (err); 1503 case UE_ISOCHRONOUS: 1504 switch (speed) { 1505 case EHCI_QH_SPEED_HIGH: 1506 case EHCI_QH_SPEED_FULL: 1507 pipe->methods = &ehci_device_isoc_methods; 1508 break; 1509 case EHCI_QH_SPEED_LOW: 1510 default: 1511 return (USBD_INVAL); 1512 } 1513 /* Spec page 271 says intervals > 16 are invalid */ 1514 if (ed->bInterval == 0 || ed->bInterval > 16) { 1515 printf("ehci: opening pipe with invalid bInterval\n"); 1516 return (USBD_INVAL); 1517 } 1518 if (UGETW(ed->wMaxPacketSize) == 0) { 1519 printf("ehci: zero length endpoint open request\n"); 1520 return (USBD_INVAL); 1521 } 1522 epipe->u.isoc.next_frame = 0; 1523 epipe->u.isoc.cur_xfers = 0; 1524 break; 1525 default: 1526 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1527 return (USBD_INVAL); 1528 } 1529 return (USBD_NORMAL_COMPLETION); 1530 } 1531 1532 /* 1533 * Add an ED to the schedule. Called at splusb(). 1534 * If in the async schedule, it will always have a next. 1535 * If in the intr schedule it may not. 1536 */ 1537 void 1538 ehci_add_qh(struct ehci_soft_qh *sqh, struct ehci_soft_qh *head) 1539 { 1540 splsoftassert(IPL_SOFTUSB); 1541 1542 usb_syncmem(&head->dma, head->offs + offsetof(struct ehci_qh, qh_link), 1543 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1544 sqh->next = head->next; 1545 sqh->prev = head; 1546 sqh->qh.qh_link = head->qh.qh_link; 1547 usb_syncmem(&sqh->dma, sqh->offs + offsetof(struct ehci_qh, qh_link), 1548 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1549 head->next = sqh; 1550 if (sqh->next) 1551 sqh->next->prev = sqh; 1552 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1553 usb_syncmem(&head->dma, head->offs + offsetof(struct ehci_qh, qh_link), 1554 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1555 } 1556 1557 /* 1558 * Remove an ED from the schedule. Called at splusb(). 1559 * Will always have a 'next' if it's in the async list as it's circular. 1560 */ 1561 void 1562 ehci_rem_qh(struct ehci_softc *sc, struct ehci_soft_qh *sqh) 1563 { 1564 splsoftassert(IPL_SOFTUSB); 1565 /* XXX */ 1566 usb_syncmem(&sqh->dma, sqh->offs + offsetof(struct ehci_qh, qh_link), 1567 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1568 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1569 sqh->prev->next = sqh->next; 1570 if (sqh->next) 1571 sqh->next->prev = sqh->prev; 1572 usb_syncmem(&sqh->prev->dma, 1573 sqh->prev->offs + offsetof(struct ehci_qh, qh_link), 1574 sizeof(sqh->prev->qh.qh_link), BUS_DMASYNC_PREWRITE); 1575 1576 ehci_sync_hc(sc); 1577 } 1578 1579 void 1580 ehci_set_qh_qtd(struct ehci_soft_qh *sqh, struct ehci_soft_qtd *sqtd) 1581 { 1582 int i; 1583 u_int32_t status; 1584 1585 /* Save toggle bit and ping status. */ 1586 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1587 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1588 status = sqh->qh.qh_qtd.qtd_status & 1589 htole32(EHCI_QTD_TOGGLE_MASK | 1590 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1591 /* Set HALTED to make hw leave it alone. */ 1592 sqh->qh.qh_qtd.qtd_status = 1593 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1594 usb_syncmem(&sqh->dma, 1595 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 1596 sizeof(sqh->qh.qh_qtd.qtd_status), 1597 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1598 sqh->qh.qh_curqtd = 0; 1599 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1600 sqh->qh.qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1601 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1602 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1603 sqh->sqtd = sqtd; 1604 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1605 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1606 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1607 sqh->qh.qh_qtd.qtd_status = status; 1608 usb_syncmem(&sqh->dma, 1609 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 1610 sizeof(sqh->qh.qh_qtd.qtd_status), 1611 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1612 } 1613 1614 /* 1615 * Ensure that the HC has released all references to the QH. We do this 1616 * by asking for a Async Advance Doorbell interrupt and then we wait for 1617 * the interrupt. 1618 * To make this easier we first obtain exclusive use of the doorbell. 1619 */ 1620 void 1621 ehci_sync_hc(struct ehci_softc *sc) 1622 { 1623 int s, error; 1624 int tries = 0; 1625 1626 if (sc->sc_bus.dying) { 1627 return; 1628 } 1629 1630 /* get doorbell */ 1631 rw_enter_write(&sc->sc_doorbell_lock); 1632 s = splhardusb(); 1633 do { 1634 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | 1635 EHCI_CMD_IAAD); 1636 error = tsleep_nsec(&sc->sc_async_head, PZERO, "ehcidi", 1637 MSEC_TO_NSEC(500)); 1638 } while (error && ++tries < 10); 1639 splx(s); 1640 /* release doorbell */ 1641 rw_exit_write(&sc->sc_doorbell_lock); 1642 #ifdef DIAGNOSTIC 1643 if (error) 1644 printf("ehci_sync_hc: tsleep() = %d\n", error); 1645 #endif 1646 } 1647 1648 void 1649 ehci_rem_itd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 1650 { 1651 struct ehci_soft_itd *itd, *prev = NULL; 1652 1653 splsoftassert(IPL_SOFTUSB); 1654 1655 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 1656 1657 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1658 prev = itd->u.frame_list.prev; 1659 /* Unlink itd from hardware chain, or frame array */ 1660 if (prev == NULL) { /* We're at the table head */ 1661 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1662 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1663 usb_syncmem(&sc->sc_fldma, 1664 sizeof(uint32_t) * itd->slot, sizeof(uint32_t), 1665 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1666 1667 if (itd->u.frame_list.next != NULL) 1668 itd->u.frame_list.next->u.frame_list.prev = 1669 NULL; 1670 } else { 1671 /* XXX this part is untested... */ 1672 prev->itd.itd_next = itd->itd.itd_next; 1673 usb_syncmem(&itd->dma, 1674 itd->offs + offsetof(struct ehci_itd, itd_next), 1675 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1676 1677 prev->u.frame_list.next = itd->u.frame_list.next; 1678 if (itd->u.frame_list.next != NULL) 1679 itd->u.frame_list.next->u.frame_list.prev = 1680 prev; 1681 } 1682 } 1683 } 1684 1685 void 1686 ehci_free_itd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 1687 { 1688 struct ehci_soft_itd *itd, *prev = NULL; 1689 1690 splsoftassert(IPL_SOFTUSB); 1691 1692 KASSERT(ex->itdstart != NULL && ex->itdend != NULL); 1693 1694 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1695 if (prev != NULL) 1696 ehci_free_itd(sc, prev); 1697 prev = itd; 1698 } 1699 if (prev) 1700 ehci_free_itd(sc, prev); 1701 ex->itdstart = NULL; 1702 ex->itdend = NULL; 1703 } 1704 1705 /* 1706 * Data structures and routines to emulate the root hub. 1707 */ 1708 usb_device_descriptor_t ehci_devd = { 1709 USB_DEVICE_DESCRIPTOR_SIZE, 1710 UDESC_DEVICE, /* type */ 1711 {0x00, 0x02}, /* USB version */ 1712 UDCLASS_HUB, /* class */ 1713 UDSUBCLASS_HUB, /* subclass */ 1714 UDPROTO_HSHUBSTT, /* protocol */ 1715 64, /* max packet */ 1716 {0},{0},{0x00,0x01}, /* device id */ 1717 1,2,0, /* string indicies */ 1718 1 /* # of configurations */ 1719 }; 1720 1721 usb_device_qualifier_t ehci_odevd = { 1722 USB_DEVICE_DESCRIPTOR_SIZE, 1723 UDESC_DEVICE_QUALIFIER, /* type */ 1724 {0x00, 0x02}, /* USB version */ 1725 UDCLASS_HUB, /* class */ 1726 UDSUBCLASS_HUB, /* subclass */ 1727 UDPROTO_FSHUB, /* protocol */ 1728 64, /* max packet */ 1729 1, /* # of configurations */ 1730 0 1731 }; 1732 1733 usb_config_descriptor_t ehci_confd = { 1734 USB_CONFIG_DESCRIPTOR_SIZE, 1735 UDESC_CONFIG, 1736 {USB_CONFIG_DESCRIPTOR_SIZE + 1737 USB_INTERFACE_DESCRIPTOR_SIZE + 1738 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1739 1, 1740 1, 1741 0, 1742 UC_BUS_POWERED | UC_SELF_POWERED, 1743 0 /* max power */ 1744 }; 1745 1746 usb_interface_descriptor_t ehci_ifcd = { 1747 USB_INTERFACE_DESCRIPTOR_SIZE, 1748 UDESC_INTERFACE, 1749 0, 1750 0, 1751 1, 1752 UICLASS_HUB, 1753 UISUBCLASS_HUB, 1754 UIPROTO_HSHUBSTT, 1755 0 1756 }; 1757 1758 usb_endpoint_descriptor_t ehci_endpd = { 1759 USB_ENDPOINT_DESCRIPTOR_SIZE, 1760 UDESC_ENDPOINT, 1761 UE_DIR_IN | EHCI_INTR_ENDPT, 1762 UE_INTERRUPT, 1763 {8, 0}, /* max packet */ 1764 12 1765 }; 1766 1767 usb_hub_descriptor_t ehci_hubd = { 1768 USB_HUB_DESCRIPTOR_SIZE, 1769 UDESC_HUB, 1770 0, 1771 {0,0}, 1772 0, 1773 0, 1774 {0}, 1775 }; 1776 1777 /* 1778 * Simulate a hardware hub by handling all the necessary requests. 1779 */ 1780 usbd_status 1781 ehci_root_ctrl_transfer(struct usbd_xfer *xfer) 1782 { 1783 usbd_status err; 1784 1785 /* Insert last in queue. */ 1786 err = usb_insert_transfer(xfer); 1787 if (err) 1788 return (err); 1789 1790 /* Pipe isn't running, start first */ 1791 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1792 } 1793 1794 usbd_status 1795 ehci_root_ctrl_start(struct usbd_xfer *xfer) 1796 { 1797 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1798 usb_device_request_t *req; 1799 void *buf = NULL; 1800 int port, i; 1801 int s, len, value, index, l, totlen = 0; 1802 usb_port_status_t ps; 1803 usb_hub_descriptor_t hubd; 1804 usbd_status err; 1805 u_int32_t v; 1806 1807 if (sc->sc_bus.dying) 1808 return (USBD_IOERROR); 1809 1810 #ifdef DIAGNOSTIC 1811 if (!(xfer->rqflags & URQ_REQUEST)) 1812 /* XXX panic */ 1813 return (USBD_INVAL); 1814 #endif 1815 req = &xfer->request; 1816 1817 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1818 req->bmRequestType, req->bRequest)); 1819 1820 len = UGETW(req->wLength); 1821 value = UGETW(req->wValue); 1822 index = UGETW(req->wIndex); 1823 1824 if (len != 0) 1825 buf = KERNADDR(&xfer->dmabuf, 0); 1826 1827 #define C(x,y) ((x) | ((y) << 8)) 1828 switch(C(req->bRequest, req->bmRequestType)) { 1829 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1830 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1831 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1832 /* 1833 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1834 * for the integrated root hub. 1835 */ 1836 break; 1837 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1838 if (len > 0) { 1839 *(u_int8_t *)buf = sc->sc_conf; 1840 totlen = 1; 1841 } 1842 break; 1843 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1844 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1845 switch(value >> 8) { 1846 case UDESC_DEVICE: 1847 if ((value & 0xff) != 0) { 1848 err = USBD_IOERROR; 1849 goto ret; 1850 } 1851 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1852 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1853 memcpy(buf, &ehci_devd, l); 1854 break; 1855 /* 1856 * We can't really operate at another speed, but the spec says 1857 * we need this descriptor. 1858 */ 1859 case UDESC_DEVICE_QUALIFIER: 1860 if ((value & 0xff) != 0) { 1861 err = USBD_IOERROR; 1862 goto ret; 1863 } 1864 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1865 memcpy(buf, &ehci_odevd, l); 1866 break; 1867 /* 1868 * We can't really operate at another speed, but the spec says 1869 * we need this descriptor. 1870 */ 1871 case UDESC_OTHER_SPEED_CONFIGURATION: 1872 case UDESC_CONFIG: 1873 if ((value & 0xff) != 0) { 1874 err = USBD_IOERROR; 1875 goto ret; 1876 } 1877 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1878 memcpy(buf, &ehci_confd, l); 1879 ((usb_config_descriptor_t *)buf)->bDescriptorType = 1880 value >> 8; 1881 buf = (char *)buf + l; 1882 len -= l; 1883 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1884 totlen += l; 1885 memcpy(buf, &ehci_ifcd, l); 1886 buf = (char *)buf + l; 1887 len -= l; 1888 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1889 totlen += l; 1890 memcpy(buf, &ehci_endpd, l); 1891 break; 1892 case UDESC_STRING: 1893 if (len == 0) 1894 break; 1895 *(u_int8_t *)buf = 0; 1896 totlen = 1; 1897 switch (value & 0xff) { 1898 case 0: /* Language table */ 1899 totlen = usbd_str(buf, len, "\001"); 1900 break; 1901 case 1: /* Vendor */ 1902 totlen = usbd_str(buf, len, sc->sc_vendor); 1903 break; 1904 case 2: /* Product */ 1905 totlen = usbd_str(buf, len, "EHCI root hub"); 1906 break; 1907 } 1908 break; 1909 default: 1910 err = USBD_IOERROR; 1911 goto ret; 1912 } 1913 break; 1914 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1915 if (len > 0) { 1916 *(u_int8_t *)buf = 0; 1917 totlen = 1; 1918 } 1919 break; 1920 case C(UR_GET_STATUS, UT_READ_DEVICE): 1921 if (len > 1) { 1922 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1923 totlen = 2; 1924 } 1925 break; 1926 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1927 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1928 if (len > 1) { 1929 USETW(((usb_status_t *)buf)->wStatus, 0); 1930 totlen = 2; 1931 } 1932 break; 1933 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1934 if (value >= USB_MAX_DEVICES) { 1935 err = USBD_IOERROR; 1936 goto ret; 1937 } 1938 break; 1939 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1940 if (value != 0 && value != 1) { 1941 err = USBD_IOERROR; 1942 goto ret; 1943 } 1944 sc->sc_conf = value; 1945 break; 1946 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1947 break; 1948 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1949 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1950 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1951 err = USBD_IOERROR; 1952 goto ret; 1953 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1954 break; 1955 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1956 break; 1957 /* Hub requests */ 1958 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1959 break; 1960 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1961 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 1962 "port=%d feature=%d\n", index, value)); 1963 if (index < 1 || index > sc->sc_noport) { 1964 err = USBD_IOERROR; 1965 goto ret; 1966 } 1967 port = EHCI_PORTSC(index); 1968 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 1969 switch(value) { 1970 case UHF_PORT_ENABLE: 1971 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 1972 break; 1973 case UHF_PORT_SUSPEND: 1974 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 1975 break; 1976 case UHF_PORT_POWER: 1977 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 1978 break; 1979 case UHF_PORT_TEST: 1980 DPRINTFN(2,("ehci_root_ctrl_start: " 1981 "clear port test %d\n", index)); 1982 break; 1983 case UHF_PORT_INDICATOR: 1984 DPRINTFN(2,("ehci_root_ctrl_start: " 1985 "clear port index %d\n", index)); 1986 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 1987 break; 1988 case UHF_C_PORT_CONNECTION: 1989 EOWRITE4(sc, port, v | EHCI_PS_CSC); 1990 break; 1991 case UHF_C_PORT_ENABLE: 1992 EOWRITE4(sc, port, v | EHCI_PS_PEC); 1993 break; 1994 case UHF_C_PORT_SUSPEND: 1995 /* how? */ 1996 break; 1997 case UHF_C_PORT_OVER_CURRENT: 1998 EOWRITE4(sc, port, v | EHCI_PS_OCC); 1999 break; 2000 case UHF_C_PORT_RESET: 2001 sc->sc_isreset = 0; 2002 break; 2003 default: 2004 err = USBD_IOERROR; 2005 goto ret; 2006 } 2007 break; 2008 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2009 if ((value & 0xff) != 0) { 2010 err = USBD_IOERROR; 2011 goto ret; 2012 } 2013 hubd = ehci_hubd; 2014 hubd.bNbrPorts = sc->sc_noport; 2015 v = EREAD4(sc, EHCI_HCSPARAMS); 2016 USETW(hubd.wHubCharacteristics, 2017 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 2018 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0)); 2019 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2020 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2021 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2022 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2023 l = min(len, hubd.bDescLength); 2024 totlen = l; 2025 memcpy(buf, &hubd, l); 2026 break; 2027 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2028 if (len != 4) { 2029 err = USBD_IOERROR; 2030 goto ret; 2031 } 2032 memset(buf, 0, len); /* ? XXX */ 2033 totlen = len; 2034 break; 2035 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2036 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2037 index)); 2038 if (index < 1 || index > sc->sc_noport) { 2039 err = USBD_IOERROR; 2040 goto ret; 2041 } 2042 if (len != 4) { 2043 err = USBD_IOERROR; 2044 goto ret; 2045 } 2046 v = EOREAD4(sc, EHCI_PORTSC(index)); 2047 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2048 i = UPS_HIGH_SPEED; 2049 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2050 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2051 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2052 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2053 if (v & EHCI_PS_PR) i |= UPS_RESET; 2054 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2055 USETW(ps.wPortStatus, i); 2056 i = 0; 2057 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2058 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2059 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2060 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 2061 USETW(ps.wPortChange, i); 2062 l = min(len, sizeof(ps)); 2063 memcpy(buf, &ps, l); 2064 totlen = l; 2065 break; 2066 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2067 err = USBD_IOERROR; 2068 goto ret; 2069 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2070 break; 2071 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2072 if (index < 1 || index > sc->sc_noport) { 2073 err = USBD_IOERROR; 2074 goto ret; 2075 } 2076 port = EHCI_PORTSC(index); 2077 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2078 switch(value) { 2079 case UHF_PORT_ENABLE: 2080 EOWRITE4(sc, port, v | EHCI_PS_PE); 2081 break; 2082 case UHF_PORT_SUSPEND: 2083 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2084 break; 2085 case UHF_PORT_DISOWN_TO_1_1: 2086 /* enter to Port Reset State */ 2087 v &= ~EHCI_PS_PE; 2088 EOWRITE4(sc, port, v | EHCI_PS_PR); 2089 ehci_disown(sc, index, 0); 2090 break; 2091 case UHF_PORT_RESET: 2092 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2093 index)); 2094 if (EHCI_PS_IS_LOWSPEED(v)) { 2095 /* Low speed device, give up ownership. */ 2096 ehci_disown(sc, index, 1); 2097 break; 2098 } 2099 /* Start reset sequence. */ 2100 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2101 EOWRITE4(sc, port, v | EHCI_PS_PR); 2102 /* Wait for reset to complete. */ 2103 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2104 if (sc->sc_bus.dying) { 2105 err = USBD_IOERROR; 2106 goto ret; 2107 } 2108 /* Terminate reset sequence. */ 2109 v = EOREAD4(sc, port); 2110 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2111 /* Wait for HC to complete reset. */ 2112 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2113 if (sc->sc_bus.dying) { 2114 err = USBD_IOERROR; 2115 goto ret; 2116 } 2117 v = EOREAD4(sc, port); 2118 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2119 if (v & EHCI_PS_PR) { 2120 printf("%s: port reset timeout\n", 2121 sc->sc_bus.bdev.dv_xname); 2122 err = USBD_IOERROR; 2123 goto ret; 2124 } 2125 if (!(v & EHCI_PS_PE)) { 2126 /* Not a high speed device, give up ownership.*/ 2127 ehci_disown(sc, index, 0); 2128 break; 2129 } 2130 sc->sc_isreset = 1; 2131 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2132 index, v)); 2133 break; 2134 case UHF_PORT_POWER: 2135 DPRINTFN(2,("ehci_root_ctrl_start: " 2136 "set port power %d\n", index)); 2137 EOWRITE4(sc, port, v | EHCI_PS_PP); 2138 break; 2139 case UHF_PORT_TEST: 2140 DPRINTFN(2,("ehci_root_ctrl_start: " 2141 "set port test %d\n", index)); 2142 break; 2143 case UHF_PORT_INDICATOR: 2144 DPRINTFN(2,("ehci_root_ctrl_start: " 2145 "set port ind %d\n", index)); 2146 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2147 break; 2148 default: 2149 err = USBD_IOERROR; 2150 goto ret; 2151 } 2152 break; 2153 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2154 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2155 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2156 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2157 break; 2158 default: 2159 err = USBD_IOERROR; 2160 goto ret; 2161 } 2162 xfer->actlen = totlen; 2163 err = USBD_NORMAL_COMPLETION; 2164 ret: 2165 xfer->status = err; 2166 s = splusb(); 2167 usb_transfer_complete(xfer); 2168 splx(s); 2169 return (err); 2170 } 2171 2172 void 2173 ehci_disown(struct ehci_softc *sc, int index, int lowspeed) 2174 { 2175 int port; 2176 u_int32_t v; 2177 2178 port = EHCI_PORTSC(index); 2179 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2180 EOWRITE4(sc, port, v | EHCI_PS_PO); 2181 } 2182 2183 /* Abort a root control request. */ 2184 void 2185 ehci_root_ctrl_abort(struct usbd_xfer *xfer) 2186 { 2187 /* Nothing to do, all transfers are synchronous. */ 2188 } 2189 2190 /* Close the root pipe. */ 2191 void 2192 ehci_root_ctrl_close(struct usbd_pipe *pipe) 2193 { 2194 /* Nothing to do. */ 2195 } 2196 2197 void 2198 ehci_root_intr_done(struct usbd_xfer *xfer) 2199 { 2200 } 2201 2202 usbd_status 2203 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2204 { 2205 usbd_status err; 2206 2207 /* Insert last in queue. */ 2208 err = usb_insert_transfer(xfer); 2209 if (err) 2210 return (err); 2211 2212 /* Pipe isn't running, start first */ 2213 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2214 } 2215 2216 usbd_status 2217 ehci_root_intr_start(struct usbd_xfer *xfer) 2218 { 2219 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2220 2221 if (sc->sc_bus.dying) 2222 return (USBD_IOERROR); 2223 2224 sc->sc_intrxfer = xfer; 2225 2226 return (USBD_IN_PROGRESS); 2227 } 2228 2229 void 2230 ehci_root_intr_abort(struct usbd_xfer *xfer) 2231 { 2232 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2233 int s; 2234 2235 sc->sc_intrxfer = NULL; 2236 2237 xfer->status = USBD_CANCELLED; 2238 s = splusb(); 2239 usb_transfer_complete(xfer); 2240 splx(s); 2241 } 2242 2243 void 2244 ehci_root_intr_close(struct usbd_pipe *pipe) 2245 { 2246 } 2247 2248 void 2249 ehci_root_ctrl_done(struct usbd_xfer *xfer) 2250 { 2251 } 2252 2253 struct ehci_soft_qh * 2254 ehci_alloc_sqh(struct ehci_softc *sc) 2255 { 2256 struct ehci_soft_qh *sqh = NULL; 2257 usbd_status err; 2258 int i, offs; 2259 struct usb_dma dma; 2260 int s; 2261 2262 s = splusb(); 2263 if (sc->sc_freeqhs == NULL) { 2264 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2265 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2266 EHCI_PAGE_SIZE, USB_DMA_COHERENT, &dma); 2267 if (err) 2268 goto out; 2269 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2270 offs = i * EHCI_SQH_SIZE; 2271 sqh = KERNADDR(&dma, offs); 2272 sqh->physaddr = DMAADDR(&dma, offs); 2273 sqh->dma = dma; 2274 sqh->offs = offs; 2275 sqh->next = sc->sc_freeqhs; 2276 sc->sc_freeqhs = sqh; 2277 } 2278 } 2279 sqh = sc->sc_freeqhs; 2280 sc->sc_freeqhs = sqh->next; 2281 memset(&sqh->qh, 0, sizeof(struct ehci_qh)); 2282 sqh->next = NULL; 2283 sqh->prev = NULL; 2284 2285 out: 2286 splx(s); 2287 return (sqh); 2288 } 2289 2290 void 2291 ehci_free_sqh(struct ehci_softc *sc, struct ehci_soft_qh *sqh) 2292 { 2293 int s; 2294 2295 s = splusb(); 2296 sqh->next = sc->sc_freeqhs; 2297 sc->sc_freeqhs = sqh; 2298 splx(s); 2299 } 2300 2301 struct ehci_soft_qtd * 2302 ehci_alloc_sqtd(struct ehci_softc *sc) 2303 { 2304 struct ehci_soft_qtd *sqtd = NULL; 2305 usbd_status err; 2306 int i, offs; 2307 struct usb_dma dma; 2308 int s; 2309 2310 s = splusb(); 2311 if (sc->sc_freeqtds == NULL) { 2312 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2313 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2314 EHCI_PAGE_SIZE, USB_DMA_COHERENT, &dma); 2315 if (err) 2316 goto out; 2317 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2318 offs = i * EHCI_SQTD_SIZE; 2319 sqtd = KERNADDR(&dma, offs); 2320 sqtd->physaddr = DMAADDR(&dma, offs); 2321 sqtd->dma = dma; 2322 sqtd->offs = offs; 2323 sqtd->nextqtd = sc->sc_freeqtds; 2324 sc->sc_freeqtds = sqtd; 2325 } 2326 } 2327 2328 sqtd = sc->sc_freeqtds; 2329 sc->sc_freeqtds = sqtd->nextqtd; 2330 memset(&sqtd->qtd, 0, sizeof(struct ehci_qtd)); 2331 sqtd->nextqtd = NULL; 2332 2333 out: 2334 splx(s); 2335 return (sqtd); 2336 } 2337 2338 void 2339 ehci_free_sqtd(struct ehci_softc *sc, struct ehci_soft_qtd *sqtd) 2340 { 2341 int s; 2342 2343 s = splusb(); 2344 sqtd->nextqtd = sc->sc_freeqtds; 2345 sc->sc_freeqtds = sqtd; 2346 splx(s); 2347 } 2348 2349 usbd_status 2350 ehci_alloc_sqtd_chain(struct ehci_softc *sc, u_int alen, struct usbd_xfer *xfer, 2351 struct ehci_soft_qtd **sp, struct ehci_soft_qtd **ep) 2352 { 2353 struct ehci_soft_qtd *next, *cur; 2354 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2355 u_int32_t qtdstatus; 2356 u_int len, curlen; 2357 int mps, i, iscontrol, forceshort; 2358 int rd = usbd_xfer_isread(xfer); 2359 struct usb_dma *dma = &xfer->dmabuf; 2360 2361 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2362 2363 len = alen; 2364 iscontrol = UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) == 2365 UE_CONTROL; 2366 2367 dataphys = DMAADDR(dma, 0); 2368 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2369 qtdstatus = EHCI_QTD_ACTIVE | 2370 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2371 EHCI_QTD_SET_CERR(3); /* IOC and BYTES set below */ 2372 mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize); 2373 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2374 len % mps == 0; 2375 /* 2376 * The control transfer data stage always starts with a toggle of 1. 2377 * For other transfers we let the hardware track the toggle state. 2378 */ 2379 if (iscontrol) 2380 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2381 2382 cur = ehci_alloc_sqtd(sc); 2383 *sp = cur; 2384 if (cur == NULL) 2385 goto nomem; 2386 2387 usb_syncmem(dma, 0, alen, 2388 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2389 for (;;) { 2390 dataphyspage = EHCI_PAGE(dataphys); 2391 /* The EHCI hardware can handle at most 5 pages. */ 2392 if (dataphyslastpage - dataphyspage < 2393 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2394 /* we can handle it in this QTD */ 2395 curlen = len; 2396 } else { 2397 /* must use multiple TDs, fill as much as possible. */ 2398 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2399 EHCI_PAGE_OFFSET(dataphys); 2400 #ifdef DIAGNOSTIC 2401 if (curlen > len) { 2402 printf("ehci_alloc_sqtd_chain: curlen=%u " 2403 "len=%u offs=0x%x\n", curlen, len, 2404 EHCI_PAGE_OFFSET(dataphys)); 2405 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2406 dataphyslastpage, dataphyspage, dataphys); 2407 curlen = len; 2408 } 2409 #endif 2410 /* the length must be a multiple of the max size */ 2411 curlen -= curlen % mps; 2412 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2413 "curlen=%u\n", curlen)); 2414 #ifdef DIAGNOSTIC 2415 if (curlen == 0) 2416 panic("ehci_alloc_std: curlen == 0"); 2417 #endif 2418 } 2419 2420 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2421 "dataphyslastpage=0x%08x len=%u curlen=%u\n", 2422 dataphys, dataphyslastpage, len, curlen)); 2423 len -= curlen; 2424 2425 /* 2426 * Allocate another transfer if there's more data left, 2427 * or if force last short transfer flag is set and we're 2428 * allocating a multiple of the max packet size. 2429 */ 2430 if (len != 0 || forceshort) { 2431 next = ehci_alloc_sqtd(sc); 2432 if (next == NULL) 2433 goto nomem; 2434 nextphys = htole32(next->physaddr); 2435 } else { 2436 next = NULL; 2437 nextphys = htole32(EHCI_LINK_TERMINATE); 2438 } 2439 2440 for (i = 0; i * EHCI_PAGE_SIZE < 2441 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2442 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2443 if (i != 0) /* use offset only in first buffer */ 2444 a = EHCI_PAGE(a); 2445 #ifdef DIAGNOSTIC 2446 if (i >= EHCI_QTD_NBUFFERS) { 2447 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2448 goto nomem; 2449 } 2450 #endif 2451 cur->qtd.qtd_buffer[i] = htole32(a); 2452 cur->qtd.qtd_buffer_hi[i] = 0; 2453 } 2454 cur->nextqtd = next; 2455 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2456 cur->qtd.qtd_status = htole32(qtdstatus | 2457 EHCI_QTD_SET_BYTES(curlen)); 2458 cur->len = curlen; 2459 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2460 dataphys, dataphys + curlen)); 2461 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%u\n", curlen)); 2462 if (iscontrol) { 2463 /* 2464 * adjust the toggle based on the number of packets 2465 * in this qtd 2466 */ 2467 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2468 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2469 } 2470 if (len == 0) { 2471 if (! forceshort) 2472 break; 2473 forceshort = 0; 2474 } 2475 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2476 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2477 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2478 dataphys += curlen; 2479 cur = next; 2480 } 2481 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2482 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2484 *ep = cur; 2485 2486 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2487 *sp, *ep)); 2488 2489 return (USBD_NORMAL_COMPLETION); 2490 2491 nomem: 2492 /* XXX free chain */ 2493 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2494 return (USBD_NOMEM); 2495 } 2496 2497 void 2498 ehci_free_sqtd_chain(struct ehci_softc *sc, struct ehci_xfer *ex) 2499 { 2500 struct ehci_pipe *epipe = (struct ehci_pipe *)ex->xfer.pipe; 2501 struct ehci_soft_qtd *sqtd, *next; 2502 2503 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p\n", ex->sqtdstart)); 2504 2505 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = next) { 2506 next = sqtd->nextqtd; 2507 ehci_free_sqtd(sc, sqtd); 2508 } 2509 ex->sqtdstart = ex->sqtdend = NULL; 2510 epipe->sqh->sqtd = NULL; 2511 } 2512 2513 struct ehci_soft_itd * 2514 ehci_alloc_itd(struct ehci_softc *sc) 2515 { 2516 struct ehci_soft_itd *itd, *freeitd; 2517 usbd_status err; 2518 int i, s, offs, frindex, previndex; 2519 struct usb_dma dma; 2520 2521 s = splusb(); 2522 2523 /* Find an itd that wasn't freed this frame or last frame. This can 2524 * discard itds that were freed before frindex wrapped around 2525 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2526 * interrupt and fiddling with list when that happens */ 2527 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2528 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2529 2530 freeitd = NULL; 2531 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2532 if (itd->slot != frindex && itd->slot != previndex) { 2533 freeitd = itd; 2534 break; 2535 } 2536 } 2537 2538 if (freeitd == NULL) { 2539 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2540 EHCI_PAGE_SIZE, USB_DMA_COHERENT, &dma); 2541 if (err) { 2542 splx(s); 2543 return (NULL); 2544 } 2545 2546 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2547 offs = i * EHCI_ITD_SIZE; 2548 itd = KERNADDR(&dma, offs); 2549 itd->physaddr = DMAADDR(&dma, offs); 2550 itd->dma = dma; 2551 itd->offs = offs; 2552 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2553 } 2554 freeitd = LIST_FIRST(&sc->sc_freeitds); 2555 } 2556 2557 itd = freeitd; 2558 LIST_REMOVE(itd, u.free_list); 2559 memset(&itd->itd, 0, sizeof(struct ehci_itd)); 2560 usb_syncmem(&itd->dma, itd->offs + offsetof(struct ehci_itd, itd_next), 2561 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2562 BUS_DMASYNC_PREREAD); 2563 2564 itd->u.frame_list.next = NULL; 2565 itd->u.frame_list.prev = NULL; 2566 itd->xfer_next = NULL; 2567 itd->slot = 0; 2568 splx(s); 2569 2570 return (itd); 2571 } 2572 2573 void 2574 ehci_free_itd(struct ehci_softc *sc, struct ehci_soft_itd *itd) 2575 { 2576 int s; 2577 2578 s = splusb(); 2579 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2580 splx(s); 2581 } 2582 2583 /* 2584 * Close a reqular pipe. 2585 * Assumes that there are no pending transactions. 2586 */ 2587 void 2588 ehci_close_pipe(struct usbd_pipe *pipe) 2589 { 2590 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2591 struct ehci_softc *sc = (struct ehci_softc *)pipe->device->bus; 2592 struct ehci_soft_qh *sqh = epipe->sqh; 2593 int s; 2594 2595 s = splusb(); 2596 ehci_rem_qh(sc, sqh); 2597 splx(s); 2598 pipe->endpoint->savedtoggle = 2599 EHCI_QTD_GET_TOGGLE(letoh32(sqh->qh.qh_qtd.qtd_status)); 2600 ehci_free_sqh(sc, epipe->sqh); 2601 } 2602 2603 /* 2604 * Abort a device request. 2605 * If this routine is called at splusb() it guarantees that the request 2606 * will be removed from the hardware scheduling and that the callback 2607 * for it will be called with USBD_CANCELLED status. 2608 * It's impossible to guarantee that the requested transfer will not 2609 * have happened since the hardware runs concurrently. 2610 * If the transaction has already happened we rely on the ordinary 2611 * interrupt processing to process it. 2612 */ 2613 void 2614 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2615 { 2616 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2617 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2618 struct ehci_xfer *ex = (struct ehci_xfer*)xfer; 2619 struct ehci_soft_qh *sqh = epipe->sqh; 2620 struct ehci_soft_qtd *sqtd; 2621 int s; 2622 2623 if (sc->sc_bus.dying || xfer->status == USBD_NOT_STARTED) { 2624 s = splusb(); 2625 if (xfer->status != USBD_NOT_STARTED) 2626 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2627 xfer->status = status; /* make software ignore it */ 2628 timeout_del(&xfer->timeout_handle); 2629 usb_rem_task(xfer->device, &xfer->abort_task); 2630 #ifdef DIAGNOSTIC 2631 ex->isdone = 1; 2632 #endif 2633 usb_transfer_complete(xfer); 2634 splx(s); 2635 return; 2636 } 2637 2638 if (xfer->device->bus->intr_context) 2639 panic("ehci_abort_xfer: not in process context"); 2640 2641 /* 2642 * If an abort is already in progress then just wait for it to 2643 * complete and return. 2644 */ 2645 if (ex->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2646 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2647 /* No need to wait if we're aborting from a timeout. */ 2648 if (status == USBD_TIMEOUT) 2649 return; 2650 /* Override the status which might be USBD_TIMEOUT. */ 2651 xfer->status = status; 2652 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2653 ex->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 2654 while (ex->ehci_xfer_flags & EHCI_XFER_ABORTING) 2655 tsleep_nsec(&ex->ehci_xfer_flags, PZERO, "ehciaw", INFSLP); 2656 return; 2657 } 2658 2659 /* 2660 * Step 1: Make interrupt routine and timeouts ignore xfer. 2661 */ 2662 s = splusb(); 2663 ex->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2664 xfer->status = status; /* make software ignore it */ 2665 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2666 timeout_del(&xfer->timeout_handle); 2667 usb_rem_task(xfer->device, &xfer->abort_task); 2668 splx(s); 2669 2670 /* 2671 * Step 2: Deactivate all of the qTDs that we will be removing, 2672 * otherwise the queue head may go active again. 2673 */ 2674 usb_syncmem(&sqh->dma, 2675 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 2676 sizeof(sqh->qh.qh_qtd.qtd_status), 2677 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2678 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2679 usb_syncmem(&sqh->dma, 2680 sqh->offs + offsetof(struct ehci_qh, qh_qtd.qtd_status), 2681 sizeof(sqh->qh.qh_qtd.qtd_status), 2682 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2683 2684 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) { 2685 usb_syncmem(&sqtd->dma, 2686 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 2687 sizeof(sqtd->qtd.qtd_status), 2688 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2689 sqtd->qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2690 usb_syncmem(&sqtd->dma, 2691 sqtd->offs + offsetof(struct ehci_qtd, qtd_status), 2692 sizeof(sqtd->qtd.qtd_status), 2693 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2694 } 2695 ehci_sync_hc(sc); 2696 2697 /* 2698 * Step 3: Make sure the soft interrupt routine has run. This 2699 * should remove any completed items off the queue. 2700 * The hardware has no reference to completed items (TDs). 2701 * It's safe to remove them at any time. 2702 */ 2703 s = splusb(); 2704 sc->sc_softwake = 1; 2705 usb_schedsoftintr(&sc->sc_bus); 2706 tsleep_nsec(&sc->sc_softwake, PZERO, "ehciab", INFSLP); 2707 2708 #ifdef DIAGNOSTIC 2709 ex->isdone = 1; 2710 #endif 2711 /* Do the wakeup first to avoid touching the xfer after the callback. */ 2712 ex->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 2713 if (ex->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 2714 ex->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 2715 wakeup(&ex->ehci_xfer_flags); 2716 } 2717 usb_transfer_complete(xfer); 2718 2719 splx(s); 2720 } 2721 2722 void 2723 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 2724 { 2725 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2726 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2727 ehci_isoc_trans_t trans_status; 2728 struct ehci_soft_itd *itd; 2729 int i; 2730 2731 splsoftassert(IPL_SOFTUSB); 2732 2733 if (sc->sc_bus.dying || xfer->status == USBD_NOT_STARTED) { 2734 if (xfer->status != USBD_NOT_STARTED) 2735 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2736 xfer->status = status; 2737 timeout_del(&xfer->timeout_handle); 2738 usb_rem_task(xfer->device, &xfer->abort_task); 2739 usb_transfer_complete(xfer); 2740 return; 2741 } 2742 2743 /* Transfer is already done. */ 2744 if (xfer->status != USBD_IN_PROGRESS) { 2745 DPRINTF(("%s: already done \n", __func__)); 2746 return; 2747 } 2748 2749 2750 #ifdef DIAGNOSTIC 2751 ex->isdone = 1; 2752 #endif 2753 xfer->status = status; 2754 TAILQ_REMOVE(&sc->sc_intrhead, ex, inext); 2755 timeout_del(&xfer->timeout_handle); 2756 usb_rem_task(xfer->device, &xfer->abort_task); 2757 2758 if (xfer->device->speed == USB_SPEED_HIGH) { 2759 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 2760 usb_syncmem(&itd->dma, 2761 itd->offs + offsetof(struct ehci_itd, itd_ctl), 2762 sizeof(itd->itd.itd_ctl), 2763 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2764 2765 for (i = 0; i < 8; i++) { 2766 trans_status = le32toh(itd->itd.itd_ctl[i]); 2767 trans_status &= ~EHCI_ITD_ACTIVE; 2768 itd->itd.itd_ctl[i] = htole32(trans_status); 2769 } 2770 2771 usb_syncmem(&itd->dma, 2772 itd->offs + offsetof(struct ehci_itd, itd_ctl), 2773 sizeof(itd->itd.itd_ctl), 2774 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2775 } 2776 } else { 2777 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 2778 usb_syncmem(&itd->dma, 2779 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 2780 sizeof(itd->sitd.sitd_trans), 2781 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2782 2783 trans_status = le32toh(itd->sitd.sitd_trans); 2784 trans_status &= ~EHCI_SITD_ACTIVE; 2785 itd->sitd.sitd_trans = htole32(trans_status); 2786 2787 usb_syncmem(&itd->dma, 2788 itd->offs + offsetof(struct ehci_sitd, sitd_trans), 2789 sizeof(itd->sitd.sitd_trans), 2790 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2791 } 2792 } 2793 2794 sc->sc_softwake = 1; 2795 usb_schedsoftintr(&sc->sc_bus); 2796 tsleep_nsec(&sc->sc_softwake, PZERO, "ehciab", INFSLP); 2797 2798 usb_transfer_complete(xfer); 2799 } 2800 2801 void 2802 ehci_timeout(void *addr) 2803 { 2804 struct usbd_xfer *xfer = addr; 2805 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2806 2807 if (sc->sc_bus.dying) { 2808 ehci_timeout_task(addr); 2809 return; 2810 } 2811 2812 usb_init_task(&xfer->abort_task, ehci_timeout_task, addr, 2813 USB_TASK_TYPE_ABORT); 2814 usb_add_task(xfer->device, &xfer->abort_task); 2815 } 2816 2817 void 2818 ehci_timeout_task(void *addr) 2819 { 2820 struct usbd_xfer *xfer = addr; 2821 int s; 2822 2823 s = splusb(); 2824 ehci_abort_xfer(xfer, USBD_TIMEOUT); 2825 splx(s); 2826 } 2827 2828 /* 2829 * Some EHCI chips from VIA / ATI seem to trigger interrupts before writing 2830 * back the qTD status, or miss signalling occasionally under heavy load. 2831 * If the host machine is too fast, we can miss transaction completion - when 2832 * we scan the active list the transaction still seems to be active. This 2833 * generally exhibits itself as a umass stall that never recovers. 2834 * 2835 * We work around this behaviour by setting up this callback after any softintr 2836 * that completes with transactions still pending, giving us another chance to 2837 * check for completion after the writeback has taken place. 2838 */ 2839 void 2840 ehci_intrlist_timeout(void *arg) 2841 { 2842 struct ehci_softc *sc = arg; 2843 int s; 2844 2845 if (sc->sc_bus.dying) 2846 return; 2847 2848 s = splusb(); 2849 DPRINTFN(1, ("ehci_intrlist_timeout\n")); 2850 usb_schedsoftintr(&sc->sc_bus); 2851 splx(s); 2852 } 2853 2854 usbd_status 2855 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 2856 { 2857 usbd_status err; 2858 2859 /* Insert last in queue. */ 2860 err = usb_insert_transfer(xfer); 2861 if (err) 2862 return (err); 2863 2864 /* Pipe isn't running, start first */ 2865 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2866 } 2867 2868 usbd_status 2869 ehci_device_ctrl_start(struct usbd_xfer *xfer) 2870 { 2871 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2872 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2873 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2874 usb_device_request_t *req = &xfer->request; 2875 struct ehci_soft_qtd *setup, *stat, *next; 2876 struct ehci_soft_qh *sqh; 2877 u_int len = UGETW(req->wLength); 2878 usbd_status err; 2879 int s; 2880 2881 KASSERT(xfer->rqflags & URQ_REQUEST); 2882 2883 if (sc->sc_bus.dying) 2884 return (USBD_IOERROR); 2885 2886 setup = ehci_alloc_sqtd(sc); 2887 if (setup == NULL) { 2888 err = USBD_NOMEM; 2889 goto bad1; 2890 } 2891 stat = ehci_alloc_sqtd(sc); 2892 if (stat == NULL) { 2893 err = USBD_NOMEM; 2894 goto bad2; 2895 } 2896 2897 sqh = epipe->sqh; 2898 2899 /* Set up data transaction */ 2900 if (len != 0) { 2901 struct ehci_soft_qtd *end; 2902 2903 err = ehci_alloc_sqtd_chain(sc, len, xfer, &next, &end); 2904 if (err) 2905 goto bad3; 2906 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 2907 end->nextqtd = stat; 2908 end->qtd.qtd_next = 2909 end->qtd.qtd_altnext = htole32(stat->physaddr); 2910 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 2911 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2912 } else { 2913 next = stat; 2914 } 2915 2916 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 2917 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2918 2919 /* Clear toggle */ 2920 setup->qtd.qtd_status = htole32( 2921 EHCI_QTD_ACTIVE | 2922 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 2923 EHCI_QTD_SET_CERR(3) | 2924 EHCI_QTD_SET_TOGGLE(0) | 2925 EHCI_QTD_SET_BYTES(sizeof(*req))); 2926 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 2927 setup->qtd.qtd_buffer_hi[0] = 0; 2928 setup->nextqtd = next; 2929 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 2930 setup->len = sizeof(*req); 2931 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 2932 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2933 2934 stat->qtd.qtd_status = htole32( 2935 EHCI_QTD_ACTIVE | 2936 EHCI_QTD_SET_PID(usbd_xfer_isread(xfer) ? 2937 EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 2938 EHCI_QTD_SET_CERR(3) | 2939 EHCI_QTD_SET_TOGGLE(1) | 2940 EHCI_QTD_IOC); 2941 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 2942 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 2943 stat->nextqtd = NULL; 2944 stat->qtd.qtd_next = stat->qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 2945 stat->len = 0; 2946 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 2947 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2948 2949 ex->sqtdstart = setup; 2950 ex->sqtdend = stat; 2951 #ifdef DIAGNOSTIC 2952 if (!ex->isdone) { 2953 printf("%s: not done, ex=%p\n", __func__, ex); 2954 } 2955 ex->isdone = 0; 2956 #endif 2957 2958 /* Insert qTD in QH list. */ 2959 s = splusb(); 2960 ehci_set_qh_qtd(sqh, setup); 2961 if (xfer->timeout && !sc->sc_bus.use_polling) { 2962 timeout_del(&xfer->timeout_handle); 2963 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 2964 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 2965 } 2966 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 2967 xfer->status = USBD_IN_PROGRESS; 2968 splx(s); 2969 2970 return (USBD_IN_PROGRESS); 2971 2972 bad3: 2973 ehci_free_sqtd(sc, stat); 2974 bad2: 2975 ehci_free_sqtd(sc, setup); 2976 bad1: 2977 xfer->status = err; 2978 usb_transfer_complete(xfer); 2979 return (err); 2980 } 2981 2982 void 2983 ehci_device_ctrl_done(struct usbd_xfer *xfer) 2984 { 2985 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 2986 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 2987 2988 KASSERT(xfer->rqflags & URQ_REQUEST); 2989 2990 if (xfer->status != USBD_NOMEM) { 2991 ehci_free_sqtd_chain(sc, ex); 2992 } 2993 } 2994 2995 void 2996 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 2997 { 2998 ehci_abort_xfer(xfer, USBD_CANCELLED); 2999 } 3000 3001 void 3002 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3003 { 3004 ehci_close_pipe(pipe); 3005 } 3006 3007 usbd_status 3008 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3009 { 3010 usbd_status err; 3011 3012 /* Insert last in queue. */ 3013 err = usb_insert_transfer(xfer); 3014 if (err) 3015 return (err); 3016 3017 /* Pipe isn't running, start first */ 3018 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3019 } 3020 3021 usbd_status 3022 ehci_device_bulk_start(struct usbd_xfer *xfer) 3023 { 3024 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3025 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3026 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3027 struct ehci_soft_qtd *data, *dataend; 3028 struct ehci_soft_qh *sqh; 3029 usbd_status err; 3030 int s; 3031 3032 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3033 3034 if (sc->sc_bus.dying) 3035 return (USBD_IOERROR); 3036 3037 sqh = epipe->sqh; 3038 3039 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3040 if (err) { 3041 xfer->status = err; 3042 usb_transfer_complete(xfer); 3043 return (err); 3044 } 3045 3046 /* Set up interrupt info. */ 3047 ex->sqtdstart = data; 3048 ex->sqtdend = dataend; 3049 #ifdef DIAGNOSTIC 3050 if (!ex->isdone) { 3051 printf("ehci_device_bulk_start: not done, ex=%p\n", ex); 3052 } 3053 ex->isdone = 0; 3054 #endif 3055 3056 s = splusb(); 3057 ehci_set_qh_qtd(sqh, data); 3058 if (xfer->timeout && !sc->sc_bus.use_polling) { 3059 timeout_del(&xfer->timeout_handle); 3060 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3061 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3062 } 3063 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3064 xfer->status = USBD_IN_PROGRESS; 3065 splx(s); 3066 3067 return (USBD_IN_PROGRESS); 3068 } 3069 3070 void 3071 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3072 { 3073 ehci_abort_xfer(xfer, USBD_CANCELLED); 3074 } 3075 3076 /* 3077 * Close a device bulk pipe. 3078 */ 3079 void 3080 ehci_device_bulk_close(struct usbd_pipe *pipe) 3081 { 3082 ehci_close_pipe(pipe); 3083 } 3084 3085 void 3086 ehci_device_bulk_done(struct usbd_xfer *xfer) 3087 { 3088 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3089 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3090 3091 if (xfer->status != USBD_NOMEM) { 3092 ehci_free_sqtd_chain(sc, ex); 3093 } 3094 } 3095 3096 usbd_status 3097 ehci_device_setintr(struct ehci_softc *sc, struct ehci_soft_qh *sqh, int ival) 3098 { 3099 struct ehci_soft_islot *isp; 3100 int islot, lev; 3101 3102 /* Find a poll rate that is large enough. */ 3103 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3104 if (EHCI_ILEV_IVAL(lev) <= ival) 3105 break; 3106 3107 /* Pick an interrupt slot at the right level. */ 3108 /* XXX could do better than picking at random */ 3109 islot = EHCI_IQHIDX(lev, arc4random()); 3110 3111 sqh->islot = islot; 3112 isp = &sc->sc_islots[islot]; 3113 ehci_add_qh(sqh, isp->sqh); 3114 3115 return (USBD_NORMAL_COMPLETION); 3116 } 3117 3118 usbd_status 3119 ehci_device_intr_transfer(struct usbd_xfer *xfer) 3120 { 3121 usbd_status err; 3122 3123 /* Insert last in queue. */ 3124 err = usb_insert_transfer(xfer); 3125 if (err) 3126 return (err); 3127 3128 /* 3129 * Pipe isn't running (otherwise err would be USBD_INPROG), 3130 * so start it first. 3131 */ 3132 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3133 } 3134 3135 usbd_status 3136 ehci_device_intr_start(struct usbd_xfer *xfer) 3137 { 3138 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3139 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3140 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3141 struct ehci_soft_qtd *data, *dataend; 3142 struct ehci_soft_qh *sqh; 3143 usbd_status err; 3144 int s; 3145 3146 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3147 3148 if (sc->sc_bus.dying) 3149 return (USBD_IOERROR); 3150 3151 sqh = epipe->sqh; 3152 3153 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3154 if (err) { 3155 xfer->status = err; 3156 usb_transfer_complete(xfer); 3157 return (err); 3158 } 3159 3160 /* Set up interrupt info. */ 3161 ex->sqtdstart = data; 3162 ex->sqtdend = dataend; 3163 #ifdef DIAGNOSTIC 3164 if (!ex->isdone) 3165 printf("ehci_device_intr_start: not done, ex=%p\n", ex); 3166 ex->isdone = 0; 3167 #endif 3168 3169 s = splusb(); 3170 ehci_set_qh_qtd(sqh, data); 3171 if (xfer->timeout && !sc->sc_bus.use_polling) { 3172 timeout_del(&xfer->timeout_handle); 3173 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3174 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3175 } 3176 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3177 xfer->status = USBD_IN_PROGRESS; 3178 splx(s); 3179 3180 return (USBD_IN_PROGRESS); 3181 } 3182 3183 void 3184 ehci_device_intr_abort(struct usbd_xfer *xfer) 3185 { 3186 KASSERT(!xfer->pipe->repeat || xfer->pipe->intrxfer == xfer); 3187 3188 /* 3189 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3190 * async doorbell. That's dependant on the async list, wheras 3191 * intr xfers are periodic, should not use this? 3192 */ 3193 ehci_abort_xfer(xfer, USBD_CANCELLED); 3194 } 3195 3196 void 3197 ehci_device_intr_close(struct usbd_pipe *pipe) 3198 { 3199 ehci_close_pipe(pipe); 3200 } 3201 3202 void 3203 ehci_device_intr_done(struct usbd_xfer *xfer) 3204 { 3205 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3206 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3207 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3208 struct ehci_soft_qtd *data, *dataend; 3209 struct ehci_soft_qh *sqh; 3210 usbd_status err; 3211 int s; 3212 3213 if (xfer->pipe->repeat) { 3214 ehci_free_sqtd_chain(sc, ex); 3215 3216 sqh = epipe->sqh; 3217 3218 err = ehci_alloc_sqtd_chain(sc, xfer->length, xfer, &data, &dataend); 3219 if (err) { 3220 xfer->status = err; 3221 return; 3222 } 3223 3224 /* Set up interrupt info. */ 3225 ex->sqtdstart = data; 3226 ex->sqtdend = dataend; 3227 #ifdef DIAGNOSTIC 3228 if (!ex->isdone) { 3229 printf("ehci_device_intr_done: not done, ex=%p\n", 3230 ex); 3231 } 3232 ex->isdone = 0; 3233 #endif 3234 3235 s = splusb(); 3236 ehci_set_qh_qtd(sqh, data); 3237 if (xfer->timeout && !sc->sc_bus.use_polling) { 3238 timeout_del(&xfer->timeout_handle); 3239 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3240 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3241 } 3242 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3243 xfer->status = USBD_IN_PROGRESS; 3244 splx(s); 3245 } else if (xfer->status != USBD_NOMEM) { 3246 ehci_free_sqtd_chain(sc, ex); 3247 } 3248 } 3249 3250 usbd_status 3251 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 3252 { 3253 usbd_status err; 3254 3255 err = usb_insert_transfer(xfer); 3256 if (err && err != USBD_IN_PROGRESS) 3257 return (err); 3258 3259 return (ehci_device_isoc_start(xfer)); 3260 } 3261 3262 usbd_status 3263 ehci_device_isoc_start(struct usbd_xfer *xfer) 3264 { 3265 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3266 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3267 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3268 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3269 uint8_t ival = ed->bInterval; 3270 struct ehci_soft_itd *itd; 3271 int s, frindex; 3272 uint32_t link; 3273 3274 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 3275 KASSERT(ival > 0 && ival <= 16); 3276 3277 /* 3278 * To allow continuous transfers, above we start all transfers 3279 * immediately. However, we're still going to get usbd_start_next call 3280 * this when another xfer completes. So, check if this is already 3281 * in progress or not 3282 */ 3283 if (ex->itdstart != NULL) 3284 return (USBD_IN_PROGRESS); 3285 3286 if (sc->sc_bus.dying) 3287 return (USBD_IOERROR); 3288 3289 /* Why would you do that anyway? */ 3290 if (sc->sc_bus.use_polling) 3291 return (USBD_INVAL); 3292 3293 /* 3294 * To avoid complication, don't allow a request right now that'll span 3295 * the entire frame table. To within 4 frames, to allow some leeway 3296 * on either side of where the hc currently is. 3297 */ 3298 if ((1 << (ival - 1)) * xfer->nframes >= (sc->sc_flsize - 4) * 8) 3299 return (USBD_INVAL); 3300 3301 /* 3302 * Step 1: Allocate and initialize itds. 3303 */ 3304 if (xfer->device->speed == USB_SPEED_HIGH) { 3305 if (ehci_alloc_itd_chain(sc, xfer)) 3306 return (USBD_INVAL); 3307 3308 link = EHCI_LINK_ITD; 3309 } else { 3310 if (ehci_alloc_sitd_chain(sc, xfer)) 3311 return (USBD_INVAL); 3312 3313 link = EHCI_LINK_SITD; 3314 } 3315 3316 #ifdef DIAGNOSTIC 3317 if (!ex->isdone) { 3318 printf("%s: not done, ex=%p\n", __func__, ex); 3319 } 3320 ex->isdone = 0; 3321 #endif 3322 3323 /* 3324 * Part 2: Transfer descriptors have now been set up, now they must 3325 * be scheduled into the period frame list. Erk. Not wanting to 3326 * complicate matters, transfer is denied if the transfer spans 3327 * more than the period frame list. 3328 */ 3329 s = splusb(); 3330 3331 /* Start inserting frames */ 3332 if (epipe->u.isoc.cur_xfers > 0) { 3333 frindex = epipe->u.isoc.next_frame; 3334 } else { 3335 frindex = EOREAD4(sc, EHCI_FRINDEX); 3336 frindex = frindex >> 3; /* Erase microframe index */ 3337 frindex += 2; 3338 } 3339 3340 if (frindex >= sc->sc_flsize) 3341 frindex &= (sc->sc_flsize - 1); 3342 3343 /* What's the frame interval? */ 3344 ival = (1 << (ival - 1)); 3345 if (ival / 8 == 0) 3346 ival = 1; 3347 else 3348 ival /= 8; 3349 3350 /* Abuse the fact that itd_next == sitd_next. */ 3351 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 3352 itd->itd.itd_next = sc->sc_flist[frindex]; 3353 if (itd->itd.itd_next == 0) 3354 itd->itd.itd_next = htole32(EHCI_LINK_TERMINATE); 3355 3356 sc->sc_flist[frindex] = htole32(link | itd->physaddr); 3357 itd->u.frame_list.next = sc->sc_softitds[frindex]; 3358 sc->sc_softitds[frindex] = itd; 3359 if (itd->u.frame_list.next != NULL) 3360 itd->u.frame_list.next->u.frame_list.prev = itd; 3361 itd->slot = frindex; 3362 itd->u.frame_list.prev = NULL; 3363 3364 frindex += ival; 3365 if (frindex >= sc->sc_flsize) 3366 frindex -= sc->sc_flsize; 3367 } 3368 3369 epipe->u.isoc.cur_xfers++; 3370 epipe->u.isoc.next_frame = frindex; 3371 3372 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, inext); 3373 xfer->status = USBD_IN_PROGRESS; 3374 xfer->done = 0; 3375 splx(s); 3376 3377 return (USBD_IN_PROGRESS); 3378 } 3379 3380 int 3381 ehci_alloc_itd_chain(struct ehci_softc *sc, struct usbd_xfer *xfer) 3382 { 3383 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3384 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3385 const uint32_t mps = UGETW(ed->wMaxPacketSize); 3386 struct ehci_soft_itd *itd = NULL, *pitd = NULL; 3387 int i, j, nframes, uframes, ufrperframe; 3388 int offs = 0, trans_count = 0; 3389 3390 /* 3391 * How many itds do we need? One per transfer if interval >= 8 3392 * microframes, fewer if we use multiple microframes per frame. 3393 */ 3394 switch (ed->bInterval) { 3395 case 1: 3396 ufrperframe = 8; 3397 break; 3398 case 2: 3399 ufrperframe = 4; 3400 break; 3401 case 3: 3402 ufrperframe = 2; 3403 break; 3404 default: 3405 ufrperframe = 1; 3406 break; 3407 } 3408 nframes = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3409 uframes = 8 / ufrperframe; 3410 if (nframes == 0) 3411 return (1); 3412 3413 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3414 usbd_xfer_isread(xfer) ? 3415 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3416 for (i = 0; i < nframes; i++) { 3417 uint32_t froffs = offs; 3418 3419 itd = ehci_alloc_itd(sc); 3420 if (itd == NULL) { 3421 ehci_free_itd_chain(sc, ex); 3422 return (1); 3423 } 3424 3425 if (pitd != NULL) 3426 pitd->xfer_next = itd; 3427 else 3428 ex->itdstart = itd; 3429 3430 /* 3431 * Step 1.5, initialize uframes 3432 */ 3433 for (j = 0; j < 8; j += uframes) { 3434 /* Calculate which page in the list this starts in */ 3435 int addr = DMAADDR(&xfer->dmabuf, froffs); 3436 addr = EHCI_PAGE_OFFSET(addr) + (offs - froffs); 3437 addr = EHCI_PAGE(addr) / EHCI_PAGE_SIZE; 3438 3439 /* This gets the initial offset into the first page, 3440 * looks how far further along the current uframe 3441 * offset is. Works out how many pages that is. 3442 */ 3443 itd->itd.itd_ctl[j] = htole32( 3444 EHCI_ITD_ACTIVE | 3445 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3446 EHCI_ITD_SET_PG(addr) | 3447 EHCI_ITD_SET_OFFS(DMAADDR(&xfer->dmabuf, offs)) 3448 ); 3449 3450 offs += xfer->frlengths[trans_count]; 3451 trans_count++; 3452 3453 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3454 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3455 break; 3456 } 3457 } 3458 3459 /* Step 1.75, set buffer pointers. To simplify matters, all 3460 * pointers are filled out for the next 7 hardware pages in 3461 * the dma block, so no need to worry what pages to cover 3462 * and what to not. 3463 */ 3464 3465 for (j = 0; j < 7; j++) { 3466 /* 3467 * Don't try to lookup a page that's past the end 3468 * of buffer 3469 */ 3470 int page_offs = EHCI_PAGE(froffs + 3471 (EHCI_PAGE_SIZE * j)); 3472 3473 if (page_offs >= xfer->dmabuf.block->size) 3474 break; 3475 3476 long long page = DMAADDR(&xfer->dmabuf, page_offs); 3477 page = EHCI_PAGE(page); 3478 itd->itd.itd_bufr[j] = htole32(page); 3479 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 3480 } 3481 3482 /* 3483 * Other special values 3484 */ 3485 itd->itd.itd_bufr[0] |= htole32( 3486 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 3487 EHCI_ITD_SET_DADDR(xfer->pipe->device->address) 3488 ); 3489 3490 itd->itd.itd_bufr[1] |= htole32( 3491 (usbd_xfer_isread(xfer) ? EHCI_ITD_SET_DIR(1) : 0) | 3492 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(mps)) 3493 ); 3494 /* FIXME: handle invalid trans */ 3495 itd->itd.itd_bufr[2] |= htole32( 3496 EHCI_ITD_SET_MULTI(UE_GET_TRANS(mps)+1) 3497 ); 3498 3499 pitd = itd; 3500 } 3501 3502 ex->itdend = itd; 3503 3504 return (0); 3505 } 3506 3507 int 3508 ehci_alloc_sitd_chain(struct ehci_softc *sc, struct usbd_xfer *xfer) 3509 { 3510 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3511 struct usbd_device *hshub = xfer->device->myhsport->parent; 3512 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 3513 struct ehci_soft_itd *itd = NULL, *pitd = NULL; 3514 uint8_t smask, cmask, tp, uf; 3515 int i, nframes, offs = 0; 3516 uint32_t endp; 3517 3518 nframes = xfer->nframes; 3519 if (nframes == 0) 3520 return (1); 3521 3522 endp = EHCI_SITD_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 3523 EHCI_SITD_SET_ADDR(xfer->device->address) | 3524 EHCI_SITD_SET_PORT(xfer->device->myhsport->portno) | 3525 EHCI_SITD_SET_HUBA(hshub->address); 3526 3527 if (usbd_xfer_isread(xfer)) 3528 endp |= EHCI_SITD_SET_DIR(1); 3529 3530 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3531 usbd_xfer_isread(xfer) ? 3532 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3533 for (i = 0; i < nframes; i++) { 3534 uint32_t addr = DMAADDR(&xfer->dmabuf, offs); 3535 uint32_t page = EHCI_PAGE(addr + xfer->frlengths[i] - 1); 3536 3537 itd = ehci_alloc_itd(sc); 3538 if (itd == NULL) { 3539 ehci_free_itd_chain(sc, ex); 3540 return (1); 3541 } 3542 if (pitd) 3543 pitd->xfer_next = itd; 3544 else 3545 ex->itdstart = itd; 3546 3547 itd->sitd.sitd_endp = htole32(endp); 3548 itd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 3549 itd->sitd.sitd_trans = htole32( 3550 EHCI_SITD_ACTIVE | 3551 EHCI_SITD_SET_LEN(xfer->frlengths[i]) | 3552 ((i == nframes - 1) ? EHCI_SITD_IOC : 0) 3553 ); 3554 3555 uf = max(1, ((xfer->frlengths[i] + 187) / 188)); 3556 3557 /* 3558 * Since we do not yet budget and schedule micro-frames 3559 * we assume there is no other transfer using the same 3560 * TT. 3561 */ 3562 if (usbd_xfer_isread(xfer)) { 3563 smask = 0x01; 3564 cmask = ((1 << (uf + 2)) - 1) << 2; 3565 } else { 3566 /* Is the payload is greater than 188 bytes? */ 3567 if (uf == 1) 3568 tp = EHCI_SITD_TP_ALL; 3569 else 3570 tp = EHCI_SITD_TP_BEGIN; 3571 3572 page |= EHCI_SITD_SET_TCOUNT(uf) | EHCI_SITD_SET_TP(tp); 3573 smask = (1 << uf) - 1; 3574 cmask = 0x00; 3575 } 3576 3577 itd->sitd.sitd_sched = htole32( 3578 EHCI_SITD_SET_SMASK(smask) | EHCI_SITD_SET_CMASK(cmask) 3579 ); 3580 itd->sitd.sitd_bufr[0] = htole32(addr); 3581 itd->sitd.sitd_bufr[1] = htole32(page); 3582 3583 offs += xfer->frlengths[i]; 3584 pitd = itd; 3585 } 3586 3587 ex->itdend = itd; 3588 3589 return (0); 3590 } 3591 3592 void 3593 ehci_device_isoc_abort(struct usbd_xfer *xfer) 3594 { 3595 int s; 3596 3597 s = splusb(); 3598 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 3599 splx(s); 3600 } 3601 3602 void 3603 ehci_device_isoc_close(struct usbd_pipe *pipe) 3604 { 3605 } 3606 3607 void 3608 ehci_device_isoc_done(struct usbd_xfer *xfer) 3609 { 3610 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 3611 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3612 struct ehci_xfer *ex = (struct ehci_xfer *)xfer; 3613 int s; 3614 3615 s = splusb(); 3616 epipe->u.isoc.cur_xfers--; 3617 if (xfer->status != USBD_NOMEM) { 3618 ehci_rem_itd_chain(sc, ex); 3619 ehci_free_itd_chain(sc, ex); 3620 } 3621 splx(s); 3622 } 3623