1 /* $OpenBSD: ehci.c,v 1.104 2009/11/04 19:14:10 kettenis Exp $ */ 2 /* $NetBSD: ehci.c,v 1.66 2004/06/30 03:11:56 mycroft Exp $ */ 3 4 /* 5 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and 10 * Jeremy Morse (jeremy.morse@gmail.com). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/usb_20.zip 41 */ 42 43 /* 44 * TODO: 45 * 1) The hub driver needs to handle and schedule the transaction translator, 46 * to assign place in frame where different devices get to go. See chapter 47 * on hubs in USB 2.0 for details. 48 * 49 * 2) Command failures are not recovered correctly. 50 */ 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/rwlock.h> 56 #include <sys/malloc.h> 57 #include <sys/device.h> 58 #include <sys/selinfo.h> 59 #include <sys/proc.h> 60 #include <sys/queue.h> 61 #include <sys/timeout.h> 62 63 #include <machine/bus.h> 64 #include <machine/endian.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 #include <dev/usb/usbdivar.h> 69 #include <dev/usb/usb_mem.h> 70 #include <dev/usb/usb_quirks.h> 71 72 #include <dev/usb/ehcireg.h> 73 #include <dev/usb/ehcivar.h> 74 75 #include <dev/rndvar.h> 76 77 struct cfdriver ehci_cd = { 78 NULL, "ehci", DV_DULL 79 }; 80 81 #ifdef EHCI_DEBUG 82 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 83 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 84 int ehcidebug = 0; 85 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n,x) 89 #endif 90 91 #define mstohz(ms) ((ms) * hz / 1000) 92 93 struct ehci_pipe { 94 struct usbd_pipe pipe; 95 96 ehci_soft_qh_t *sqh; 97 union { 98 ehci_soft_qtd_t *qtd; 99 /* ehci_soft_itd_t *itd; */ 100 } tail; 101 union { 102 /* Control pipe */ 103 struct { 104 usb_dma_t reqdma; 105 u_int length; 106 /*ehci_soft_qtd_t *setup, *data, *stat;*/ 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 u_int length; 111 } intr; 112 /* Bulk pipe */ 113 struct { 114 u_int length; 115 } bulk; 116 /* Iso pipe */ 117 struct { 118 u_int next_frame; 119 u_int cur_xfers; 120 } isoc; 121 } u; 122 }; 123 124 u_int8_t ehci_reverse_bits(u_int8_t, int); 125 126 void ehci_power(int, void *); 127 128 usbd_status ehci_open(usbd_pipe_handle); 129 void ehci_poll(struct usbd_bus *); 130 void ehci_softintr(void *); 131 int ehci_intr1(ehci_softc_t *); 132 void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 133 void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 134 void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 135 void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 136 void ehci_idone(struct ehci_xfer *); 137 void ehci_timeout(void *); 138 void ehci_timeout_task(void *); 139 void ehci_intrlist_timeout(void *); 140 141 usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 142 void ehci_freem(struct usbd_bus *, usb_dma_t *); 143 144 usbd_xfer_handle ehci_allocx(struct usbd_bus *); 145 void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 146 147 usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 148 usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 149 void ehci_root_ctrl_abort(usbd_xfer_handle); 150 void ehci_root_ctrl_close(usbd_pipe_handle); 151 void ehci_root_ctrl_done(usbd_xfer_handle); 152 153 usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 154 usbd_status ehci_root_intr_start(usbd_xfer_handle); 155 void ehci_root_intr_abort(usbd_xfer_handle); 156 void ehci_root_intr_close(usbd_pipe_handle); 157 void ehci_root_intr_done(usbd_xfer_handle); 158 159 usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 160 usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 161 void ehci_device_ctrl_abort(usbd_xfer_handle); 162 void ehci_device_ctrl_close(usbd_pipe_handle); 163 void ehci_device_ctrl_done(usbd_xfer_handle); 164 165 usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 166 usbd_status ehci_device_bulk_start(usbd_xfer_handle); 167 void ehci_device_bulk_abort(usbd_xfer_handle); 168 void ehci_device_bulk_close(usbd_pipe_handle); 169 void ehci_device_bulk_done(usbd_xfer_handle); 170 171 usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 172 usbd_status ehci_device_intr_start(usbd_xfer_handle); 173 void ehci_device_intr_abort(usbd_xfer_handle); 174 void ehci_device_intr_close(usbd_pipe_handle); 175 void ehci_device_intr_done(usbd_xfer_handle); 176 177 usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 178 usbd_status ehci_device_isoc_start(usbd_xfer_handle); 179 void ehci_device_isoc_abort(usbd_xfer_handle); 180 void ehci_device_isoc_close(usbd_pipe_handle); 181 void ehci_device_isoc_done(usbd_xfer_handle); 182 183 void ehci_device_clear_toggle(usbd_pipe_handle pipe); 184 void ehci_noop(usbd_pipe_handle pipe); 185 186 int ehci_str(usb_string_descriptor_t *, int, const char *); 187 void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 188 void ehci_disown(ehci_softc_t *, int, int); 189 190 ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 191 void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 192 193 ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 194 void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 195 usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 196 ehci_softc_t *, u_int, int, usbd_xfer_handle, 197 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 198 void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 199 ehci_soft_qtd_t *); 200 201 ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 202 void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 203 void ehci_rem_free_itd_chain(ehci_softc_t *sc, 204 struct ehci_xfer *exfer); 205 void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 206 usbd_status status); 207 208 usbd_status ehci_device_request(usbd_xfer_handle xfer); 209 210 usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 211 int ival); 212 213 void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 214 void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 215 ehci_soft_qh_t *); 216 void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 217 void ehci_sync_hc(ehci_softc_t *); 218 219 void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 220 void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 221 222 #ifdef EHCI_DEBUG 223 void ehci_dump_regs(ehci_softc_t *); 224 void ehci_dump(void); 225 ehci_softc_t *theehci; 226 void ehci_dump_link(ehci_link_t, int); 227 void ehci_dump_sqtds(ehci_soft_qtd_t *); 228 void ehci_dump_sqtd(ehci_soft_qtd_t *); 229 void ehci_dump_qtd(ehci_qtd_t *); 230 void ehci_dump_sqh(ehci_soft_qh_t *); 231 #if notyet 232 void ehci_dump_sitd(struct ehci_soft_itd *itd); 233 void ehci_dump_itd(struct ehci_soft_itd *); 234 #endif 235 #ifdef DIAGNOSTIC 236 void ehci_dump_exfer(struct ehci_xfer *); 237 #endif 238 #endif 239 240 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 241 242 #define EHCI_INTR_ENDPT 1 243 244 #define ehci_add_intr_list(sc, ex) \ 245 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 246 #define ehci_del_intr_list(sc, ex) \ 247 do { \ 248 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 249 (ex)->inext.tqe_prev = NULL; \ 250 } while (0) 251 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 252 253 struct usbd_bus_methods ehci_bus_methods = { 254 ehci_open, 255 ehci_softintr, 256 ehci_poll, 257 ehci_allocm, 258 ehci_freem, 259 ehci_allocx, 260 ehci_freex, 261 }; 262 263 struct usbd_pipe_methods ehci_root_ctrl_methods = { 264 ehci_root_ctrl_transfer, 265 ehci_root_ctrl_start, 266 ehci_root_ctrl_abort, 267 ehci_root_ctrl_close, 268 ehci_noop, 269 ehci_root_ctrl_done, 270 }; 271 272 struct usbd_pipe_methods ehci_root_intr_methods = { 273 ehci_root_intr_transfer, 274 ehci_root_intr_start, 275 ehci_root_intr_abort, 276 ehci_root_intr_close, 277 ehci_noop, 278 ehci_root_intr_done, 279 }; 280 281 struct usbd_pipe_methods ehci_device_ctrl_methods = { 282 ehci_device_ctrl_transfer, 283 ehci_device_ctrl_start, 284 ehci_device_ctrl_abort, 285 ehci_device_ctrl_close, 286 ehci_noop, 287 ehci_device_ctrl_done, 288 }; 289 290 struct usbd_pipe_methods ehci_device_intr_methods = { 291 ehci_device_intr_transfer, 292 ehci_device_intr_start, 293 ehci_device_intr_abort, 294 ehci_device_intr_close, 295 ehci_device_clear_toggle, 296 ehci_device_intr_done, 297 }; 298 299 struct usbd_pipe_methods ehci_device_bulk_methods = { 300 ehci_device_bulk_transfer, 301 ehci_device_bulk_start, 302 ehci_device_bulk_abort, 303 ehci_device_bulk_close, 304 ehci_device_clear_toggle, 305 ehci_device_bulk_done, 306 }; 307 308 struct usbd_pipe_methods ehci_device_isoc_methods = { 309 ehci_device_isoc_transfer, 310 ehci_device_isoc_start, 311 ehci_device_isoc_abort, 312 ehci_device_isoc_close, 313 ehci_noop, 314 ehci_device_isoc_done, 315 }; 316 317 /* 318 * Reverse a number with nbits bits. Used to evenly distribute lower-level 319 * interrupt heads in the periodic schedule. 320 * Suitable for use with EHCI_IPOLLRATES <= 9. 321 */ 322 u_int8_t 323 ehci_reverse_bits(u_int8_t c, int nbits) 324 { 325 c = ((c >> 1) & 0x55) | ((c << 1) & 0xaa); 326 c = ((c >> 2) & 0x33) | ((c << 2) & 0xcc); 327 c = ((c >> 4) & 0x0f) | ((c << 4) & 0xf0); 328 329 return c >> (8 - nbits); 330 } 331 332 usbd_status 333 ehci_init(ehci_softc_t *sc) 334 { 335 u_int32_t sparams, cparams, hcr; 336 u_int i, j; 337 usbd_status err; 338 ehci_soft_qh_t *sqh; 339 340 #ifdef EHCI_DEBUG 341 u_int32_t vers; 342 theehci = sc; 343 344 DPRINTF(("ehci_init: start\n")); 345 346 vers = EREAD2(sc, EHCI_HCIVERSION); 347 DPRINTF(("%s: EHCI version %x.%x\n", sc->sc_bus.bdev.dv_xname, 348 vers >> 8, vers & 0xff)); 349 #endif 350 351 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 352 353 sparams = EREAD4(sc, EHCI_HCSPARAMS); 354 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 355 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 356 cparams = EREAD4(sc, EHCI_HCCPARAMS); 357 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 358 359 /* MUST clear segment register if 64 bit capable. */ 360 if (EHCI_HCC_64BIT(cparams)) 361 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 362 363 sc->sc_bus.usbrev = USBREV_2_0; 364 365 /* Reset the controller */ 366 DPRINTF(("%s: resetting\n", sc->sc_bus.bdev.dv_xname)); 367 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 368 usb_delay_ms(&sc->sc_bus, 1); 369 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 370 for (i = 0; i < 100; i++) { 371 usb_delay_ms(&sc->sc_bus, 1); 372 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 373 if (!hcr) 374 break; 375 } 376 if (hcr) { 377 printf("%s: reset timeout\n", 378 sc->sc_bus.bdev.dv_xname); 379 return (USBD_IOERROR); 380 } 381 382 /* XXX need proper intr scheduling */ 383 sc->sc_rand = 96; 384 385 /* frame list size at default, read back what we got and use that */ 386 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 387 case 0: 388 sc->sc_flsize = 1024; 389 break; 390 case 1: 391 sc->sc_flsize = 512; 392 break; 393 case 2: 394 sc->sc_flsize = 256; 395 break; 396 case 3: 397 return (USBD_IOERROR); 398 } 399 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 400 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 401 if (err) 402 return (err); 403 DPRINTF(("%s: flsize=%d\n", sc->sc_bus.bdev.dv_xname,sc->sc_flsize)); 404 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 405 406 for (i = 0; i < sc->sc_flsize; i++) 407 sc->sc_flist[i] = EHCI_NULL; 408 409 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 410 411 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 412 M_USB, M_NOWAIT | M_ZERO); 413 if (sc->sc_softitds == NULL) 414 return (ENOMEM); 415 LIST_INIT(&sc->sc_freeitds); 416 TAILQ_INIT(&sc->sc_intrhead); 417 418 /* Set up the bus struct. */ 419 sc->sc_bus.methods = &ehci_bus_methods; 420 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 421 422 sc->sc_powerhook = powerhook_establish(ehci_power, sc); 423 424 sc->sc_eintrs = EHCI_NORMAL_INTRS; 425 426 /* 427 * Allocate the interrupt dummy QHs. These are arranged to give poll 428 * intervals that are powers of 2 times 1ms. 429 */ 430 for (i = 0; i < EHCI_INTRQHS; i++) { 431 sqh = ehci_alloc_sqh(sc); 432 if (sqh == NULL) { 433 err = USBD_NOMEM; 434 goto bad1; 435 } 436 sc->sc_islots[i].sqh = sqh; 437 } 438 for (i = 0; i < EHCI_INTRQHS; i++) { 439 sqh = sc->sc_islots[i].sqh; 440 if (i == 0) { 441 /* The last (1ms) QH terminates. */ 442 sqh->qh.qh_link = EHCI_NULL; 443 sqh->next = NULL; 444 } else { 445 /* Otherwise the next QH has half the poll interval */ 446 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 447 sqh->qh.qh_link = htole32(sqh->next->physaddr | 448 EHCI_LINK_QH); 449 } 450 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 451 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 452 sqh->qh.qh_curqtd = EHCI_NULL; 453 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 454 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 455 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 456 sqh->sqtd = NULL; 457 } 458 /* Point the frame list at the last level (128ms). */ 459 for (i = 0; i < (1 << (EHCI_IPOLLRATES - 1)); i++) 460 for (j = i; j < sc->sc_flsize; j += 1 << (EHCI_IPOLLRATES - 1)) 461 sc->sc_flist[j] = htole32(EHCI_LINK_QH | sc->sc_islots[ 462 EHCI_IQHIDX(EHCI_IPOLLRATES - 1, ehci_reverse_bits( 463 i, EHCI_IPOLLRATES - 1))].sqh->physaddr); 464 465 /* Allocate dummy QH that starts the async list. */ 466 sqh = ehci_alloc_sqh(sc); 467 if (sqh == NULL) { 468 err = USBD_NOMEM; 469 goto bad1; 470 } 471 /* Fill the QH */ 472 sqh->qh.qh_endp = 473 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 474 sqh->qh.qh_link = 475 htole32(sqh->physaddr | EHCI_LINK_QH); 476 sqh->qh.qh_curqtd = EHCI_NULL; 477 sqh->prev = sqh; /*It's a circular list.. */ 478 sqh->next = sqh; 479 /* Fill the overlay qTD */ 480 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 481 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 482 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 483 sqh->sqtd = NULL; 484 #ifdef EHCI_DEBUG 485 if (ehcidebug) 486 ehci_dump_sqh(sqh); 487 #endif 488 489 /* Point to async list */ 490 sc->sc_async_head = sqh; 491 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 492 493 timeout_set(&sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 494 495 rw_init(&sc->sc_doorbell_lock, "ehcidb"); 496 497 /* Turn on controller */ 498 EOWRITE4(sc, EHCI_USBCMD, 499 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 500 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 501 EHCI_CMD_ASE | 502 EHCI_CMD_PSE | 503 EHCI_CMD_RS); 504 505 /* Take over port ownership */ 506 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 507 508 for (i = 0; i < 100; i++) { 509 usb_delay_ms(&sc->sc_bus, 1); 510 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 511 if (!hcr) 512 break; 513 } 514 if (hcr) { 515 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 516 return (USBD_IOERROR); 517 } 518 519 /* Enable interrupts */ 520 DPRINTFN(1,("ehci_init: enabling\n")); 521 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 522 523 return (USBD_NORMAL_COMPLETION); 524 525 #if 0 526 bad2: 527 ehci_free_sqh(sc, sc->sc_async_head); 528 #endif 529 bad1: 530 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 531 return (err); 532 } 533 534 int 535 ehci_intr(void *v) 536 { 537 ehci_softc_t *sc = v; 538 539 if (sc == NULL || sc->sc_dying) 540 return (0); 541 542 /* If we get an interrupt while polling, then just ignore it. */ 543 if (sc->sc_bus.use_polling) { 544 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 545 546 if (intrs) 547 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 548 return (0); 549 } 550 551 return (ehci_intr1(sc)); 552 } 553 554 int 555 ehci_intr1(ehci_softc_t *sc) 556 { 557 u_int32_t intrs, eintrs; 558 559 DPRINTFN(20,("ehci_intr1: enter\n")); 560 561 /* In case the interrupt occurs before initialization has completed. */ 562 if (sc == NULL) { 563 #ifdef DIAGNOSTIC 564 printf("ehci_intr1: sc == NULL\n"); 565 #endif 566 return (0); 567 } 568 569 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 570 if (intrs == 0xffffffff) { 571 sc->sc_dying = 1; 572 return (0); 573 } 574 if (!intrs) 575 return (0); 576 577 eintrs = intrs & sc->sc_eintrs; 578 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 579 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), (u_int)eintrs)); 580 if (!eintrs) 581 return (0); 582 583 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 584 sc->sc_bus.intr_context++; 585 sc->sc_bus.no_intrs++; 586 if (eintrs & EHCI_STS_IAA) { 587 DPRINTF(("ehci_intr1: door bell\n")); 588 wakeup(&sc->sc_async_head); 589 eintrs &= ~EHCI_STS_IAA; 590 } 591 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 592 DPRINTFN(5,("ehci_intr1: %s %s\n", 593 eintrs & EHCI_STS_INT ? "INT" : "", 594 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 595 usb_schedsoftintr(&sc->sc_bus); 596 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 597 } 598 if (eintrs & EHCI_STS_HSE) { 599 printf("%s: unrecoverable error, controller halted\n", 600 sc->sc_bus.bdev.dv_xname); 601 /* XXX what else */ 602 } 603 if (eintrs & EHCI_STS_PCD) { 604 ehci_pcd(sc, sc->sc_intrxfer); 605 eintrs &= ~EHCI_STS_PCD; 606 } 607 608 sc->sc_bus.intr_context--; 609 610 if (eintrs != 0) { 611 /* Block unprocessed interrupts. */ 612 sc->sc_eintrs &= ~eintrs; 613 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 614 printf("%s: blocking intrs 0x%x\n", 615 sc->sc_bus.bdev.dv_xname, eintrs); 616 } 617 618 return (1); 619 } 620 621 void 622 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 623 { 624 u_char *p; 625 int i, m; 626 627 if (xfer == NULL) { 628 /* Just ignore the change. */ 629 return; 630 } 631 632 p = KERNADDR(&xfer->dmabuf, 0); 633 m = min(sc->sc_noport, xfer->length * 8 - 1); 634 memset(p, 0, xfer->length); 635 for (i = 1; i <= m; i++) { 636 /* Pick out CHANGE bits from the status reg. */ 637 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 638 p[i/8] |= 1 << (i%8); 639 } 640 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 641 xfer->actlen = xfer->length; 642 xfer->status = USBD_NORMAL_COMPLETION; 643 644 usb_transfer_complete(xfer); 645 } 646 647 void 648 ehci_softintr(void *v) 649 { 650 ehci_softc_t *sc = v; 651 struct ehci_xfer *ex, *nextex; 652 653 DPRINTFN(10,("%s: ehci_softintr (%d)\n", sc->sc_bus.bdev.dv_xname, 654 sc->sc_bus.intr_context)); 655 656 sc->sc_bus.intr_context++; 657 658 /* 659 * The only explanation I can think of for why EHCI is as brain dead 660 * as UHCI interrupt-wise is that Intel was involved in both. 661 * An interrupt just tells us that something is done, we have no 662 * clue what, so we need to scan through all active transfers. :-( 663 */ 664 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 665 nextex = TAILQ_NEXT(ex, inext); 666 ehci_check_intr(sc, ex); 667 } 668 669 /* Schedule a callout to catch any dropped transactions. */ 670 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 671 !TAILQ_EMPTY(&sc->sc_intrhead)) { 672 timeout_add_sec(&sc->sc_tmo_intrlist, 1); 673 } 674 675 if (sc->sc_softwake) { 676 sc->sc_softwake = 0; 677 wakeup(&sc->sc_softwake); 678 } 679 680 sc->sc_bus.intr_context--; 681 } 682 683 /* Check for an interrupt. */ 684 void 685 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 686 { 687 int attr; 688 689 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 690 691 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 692 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 693 ehci_check_itd_intr(sc, ex); 694 else 695 ehci_check_qh_intr(sc, ex); 696 697 return; 698 } 699 700 void 701 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 702 { 703 ehci_soft_qtd_t *sqtd, *lsqtd; 704 __uint32_t status; 705 706 if (ex->sqtdstart == NULL) { 707 printf("ehci_check_qh_intr: not valid sqtd\n"); 708 return; 709 } 710 711 lsqtd = ex->sqtdend; 712 #ifdef DIAGNOSTIC 713 if (lsqtd == NULL) { 714 printf("ehci_check_qh_intr: lsqtd==0\n"); 715 return; 716 } 717 #endif 718 /* 719 * If the last TD is still active we need to check whether there 720 * is a an error somewhere in the middle, or whether there was a 721 * short packet (SPD and not ACTIVE). 722 */ 723 if (letoh32(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 724 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 725 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 726 status = letoh32(sqtd->qtd.qtd_status); 727 /* If there's an active QTD the xfer isn't done. */ 728 if (status & EHCI_QTD_ACTIVE) 729 break; 730 /* Any kind of error makes the xfer done. */ 731 if (status & EHCI_QTD_HALTED) 732 goto done; 733 /* We want short packets, and it is short: it's done */ 734 if (EHCI_QTD_GET_BYTES(status) != 0) 735 goto done; 736 } 737 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 738 ex, ex->sqtdstart)); 739 return; 740 } 741 done: 742 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 743 timeout_del(&ex->xfer.timeout_handle); 744 usb_rem_task(ex->xfer.pipe->device, &ex->abort_task); 745 ehci_idone(ex); 746 } 747 748 void 749 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 750 ehci_soft_itd_t *itd; 751 int i; 752 753 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 754 return; 755 756 if (ex->itdstart == NULL) { 757 printf("ehci_check_itd_intr: not valid itd\n"); 758 return; 759 } 760 761 itd = ex->itdend; 762 #ifdef DIAGNOSTIC 763 if (itd == NULL) { 764 printf("ehci_check_itd_intr: itdend == 0\n"); 765 return; 766 } 767 #endif 768 769 /* 770 * Step 1, check no active transfers in last itd, meaning we're finished 771 * check no active transfers in last itd, meaning we're finished 772 */ 773 for (i = 0; i < 8; i++) { 774 if (letoh32(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 775 break; 776 } 777 778 if (i == 8) { 779 goto done; /* All 8 descriptors inactive, it's done */ 780 } 781 782 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 783 ex->itdstart)); 784 return; 785 done: 786 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 787 timeout_del(&ex->xfer.timeout_handle); 788 ehci_idone(ex); 789 } 790 791 void 792 ehci_idone(struct ehci_xfer *ex) 793 { 794 usbd_xfer_handle xfer = &ex->xfer; 795 #ifdef EHCI_DEBUG 796 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 797 #endif 798 ehci_soft_qtd_t *sqtd, *lsqtd; 799 u_int32_t status = 0, nstatus = 0; 800 int actlen, cerr; 801 802 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 803 #ifdef DIAGNOSTIC 804 { 805 int s = splhigh(); 806 if (ex->isdone) { 807 splx(s); 808 #ifdef EHCI_DEBUG 809 printf("ehci_idone: ex is done!\n "); 810 ehci_dump_exfer(ex); 811 #else 812 printf("ehci_idone: ex=%p is done!\n", ex); 813 #endif 814 return; 815 } 816 ex->isdone = 1; 817 splx(s); 818 } 819 #endif 820 if (xfer->status == USBD_CANCELLED || 821 xfer->status == USBD_TIMEOUT) { 822 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 823 return; 824 } 825 826 #ifdef EHCI_DEBUG 827 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 828 if (ehcidebug > 10) 829 ehci_dump_sqtds(ex->sqtdstart); 830 #endif 831 832 /* The transfer is done, compute actual length and status. */ 833 834 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 835 == UE_ISOCHRONOUS) { 836 /* Isoc transfer */ 837 struct ehci_soft_itd *itd; 838 int i, nframes, len, uframes; 839 840 nframes = 0; 841 actlen = 0; 842 843 switch (xfer->pipe->endpoint->edesc->bInterval) { 844 case 0: 845 panic("ehci: isoc xfer suddenly has 0 bInterval, " 846 "invalid"); 847 case 1: 848 uframes = 1; 849 break; 850 case 2: 851 uframes = 2; 852 break; 853 case 3: 854 uframes = 4; 855 break; 856 default: 857 uframes = 8; 858 break; 859 } 860 861 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 862 for (i = 0; i < 8; i += uframes) { 863 /* XXX - driver didn't fill in the frame full 864 * of uframes. This leads to scheduling 865 * inefficiencies, but working around 866 * this doubles complexity of tracking 867 * an xfer. 868 */ 869 if (nframes >= xfer->nframes) 870 break; 871 872 status = letoh32(itd->itd.itd_ctl[i]); 873 len = EHCI_ITD_GET_LEN(status); 874 if (EHCI_ITD_GET_STATUS(status) != 0) 875 len = 0; /*No valid data on error*/ 876 877 xfer->frlengths[nframes++] = len; 878 actlen += len; 879 } 880 881 if (nframes >= xfer->nframes) 882 break; 883 } 884 885 xfer->actlen = actlen; 886 xfer->status = USBD_NORMAL_COMPLETION; 887 888 goto end; 889 } 890 891 /* Continue processing xfers using queue heads */ 892 893 lsqtd = ex->sqtdend; 894 actlen = 0; 895 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; 896 sqtd = sqtd->nextqtd) { 897 nstatus = letoh32(sqtd->qtd.qtd_status); 898 if (nstatus & EHCI_QTD_ACTIVE) 899 break; 900 901 status = nstatus; 902 /* halt is ok if descriptor is last, and complete */ 903 if (sqtd->qtd.qtd_next == EHCI_NULL && 904 EHCI_QTD_GET_BYTES(status) == 0) 905 status &= ~EHCI_QTD_HALTED; 906 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 907 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 908 } 909 910 cerr = EHCI_QTD_GET_CERR(status); 911 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 912 "status=0x%x\n", xfer->length, actlen, cerr, status)); 913 xfer->actlen = actlen; 914 if ((status & EHCI_QTD_HALTED) != 0) { 915 #ifdef EHCI_DEBUG 916 char sbuf[128]; 917 918 bitmask_snprintf((u_int32_t)status, 919 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 920 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 921 922 DPRINTFN(2, 923 ("ehci_idone: error, addr=%d, endpt=0x%02x, " 924 "status 0x%s\n", 925 xfer->pipe->device->address, 926 xfer->pipe->endpoint->edesc->bEndpointAddress, 927 sbuf)); 928 if (ehcidebug > 2) { 929 ehci_dump_sqh(epipe->sqh); 930 ehci_dump_sqtds(ex->sqtdstart); 931 } 932 #endif 933 if ((status & EHCI_QTD_BABBLE) == 0 && cerr > 0) 934 xfer->status = USBD_STALLED; 935 else 936 xfer->status = USBD_IOERROR; /* more info XXX */ 937 } else 938 xfer->status = USBD_NORMAL_COMPLETION; 939 end: 940 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 941 * during this call, before methods->done is called: dma sync required 942 * beforehand? */ 943 usb_transfer_complete(xfer); 944 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 945 } 946 947 /* 948 * Wait here until controller claims to have an interrupt. 949 * Then call ehci_intr and return. Use timeout to avoid waiting 950 * too long. 951 */ 952 void 953 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 954 { 955 int timo; 956 u_int32_t intrs; 957 958 xfer->status = USBD_IN_PROGRESS; 959 for (timo = xfer->timeout; timo >= 0; timo--) { 960 usb_delay_ms(&sc->sc_bus, 1); 961 if (sc->sc_dying) 962 break; 963 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 964 sc->sc_eintrs; 965 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 966 #ifdef EHCI_DEBUG 967 if (ehcidebug > 15) 968 ehci_dump_regs(sc); 969 #endif 970 if (intrs) { 971 ehci_intr1(sc); 972 if (xfer->status != USBD_IN_PROGRESS) 973 return; 974 } 975 } 976 977 /* Timeout */ 978 DPRINTF(("ehci_waitintr: timeout\n")); 979 xfer->status = USBD_TIMEOUT; 980 usb_transfer_complete(xfer); 981 /* XXX should free TD */ 982 } 983 984 void 985 ehci_poll(struct usbd_bus *bus) 986 { 987 ehci_softc_t *sc = (ehci_softc_t *)bus; 988 #ifdef EHCI_DEBUG 989 static int last; 990 int new; 991 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 992 if (new != last) { 993 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 994 last = new; 995 } 996 #endif 997 998 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 999 ehci_intr1(sc); 1000 } 1001 1002 int 1003 ehci_detach(struct ehci_softc *sc, int flags) 1004 { 1005 int rv = 0; 1006 1007 if (sc->sc_child != NULL) 1008 rv = config_detach(sc->sc_child, flags); 1009 1010 if (rv != 0) 1011 return (rv); 1012 1013 timeout_del(&sc->sc_tmo_intrlist); 1014 1015 if (sc->sc_powerhook != NULL) 1016 powerhook_disestablish(sc->sc_powerhook); 1017 if (sc->sc_shutdownhook != NULL) 1018 shutdownhook_disestablish(sc->sc_shutdownhook); 1019 1020 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1021 1022 /* XXX free other data structures XXX */ 1023 1024 return (rv); 1025 } 1026 1027 1028 int 1029 ehci_activate(struct device *self, int act) 1030 { 1031 struct ehci_softc *sc = (struct ehci_softc *)self; 1032 int rv = 0; 1033 1034 switch (act) { 1035 case DVACT_ACTIVATE: 1036 break; 1037 1038 case DVACT_DEACTIVATE: 1039 if (sc->sc_child != NULL) 1040 rv = config_deactivate(sc->sc_child); 1041 sc->sc_dying = 1; 1042 break; 1043 } 1044 return (rv); 1045 } 1046 1047 /* 1048 * Handle suspend/resume. 1049 * 1050 * We need to switch to polling mode here, because this routine is 1051 * called from an interrupt context. This is all right since we 1052 * are almost suspended anyway. 1053 */ 1054 void 1055 ehci_power(int why, void *v) 1056 { 1057 ehci_softc_t *sc = v; 1058 u_int32_t cmd, hcr; 1059 int s, i; 1060 1061 #ifdef EHCI_DEBUG 1062 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why)); 1063 if (ehcidebug > 0) 1064 ehci_dump_regs(sc); 1065 #endif 1066 1067 s = splhardusb(); 1068 switch (why) { 1069 case PWR_SUSPEND: 1070 case PWR_STANDBY: 1071 sc->sc_bus.use_polling++; 1072 1073 for (i = 1; i <= sc->sc_noport; i++) { 1074 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1075 if ((cmd & (EHCI_PS_PO|EHCI_PS_PE)) == EHCI_PS_PE) 1076 EOWRITE4(sc, EHCI_PORTSC(i), 1077 cmd | EHCI_PS_SUSP); 1078 } 1079 1080 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1081 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1082 EOWRITE4(sc, EHCI_USBCMD, cmd); 1083 1084 for (i = 0; i < 100; i++) { 1085 hcr = EOREAD4(sc, EHCI_USBSTS) & 1086 (EHCI_STS_ASS | EHCI_STS_PSS); 1087 if (hcr == 0) 1088 break; 1089 1090 usb_delay_ms(&sc->sc_bus, 1); 1091 } 1092 if (hcr != 0) 1093 printf("%s: reset timeout\n", 1094 sc->sc_bus.bdev.dv_xname); 1095 1096 cmd &= ~EHCI_CMD_RS; 1097 EOWRITE4(sc, EHCI_USBCMD, cmd); 1098 1099 for (i = 0; i < 100; i++) { 1100 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1101 if (hcr == EHCI_STS_HCH) 1102 break; 1103 1104 usb_delay_ms(&sc->sc_bus, 1); 1105 } 1106 if (hcr != EHCI_STS_HCH) 1107 printf("%s: config timeout\n", 1108 sc->sc_bus.bdev.dv_xname); 1109 1110 sc->sc_bus.use_polling--; 1111 break; 1112 1113 case PWR_RESUME: 1114 sc->sc_bus.use_polling++; 1115 1116 /* restore things in case the bios sucks */ 1117 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1118 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1119 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1120 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1121 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1122 1123 hcr = 0; 1124 for (i = 1; i <= sc->sc_noport; i++) { 1125 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1126 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == EHCI_PS_SUSP) { 1127 EOWRITE4(sc, EHCI_PORTSC(i), 1128 cmd | EHCI_PS_FPR); 1129 hcr = 1; 1130 } 1131 } 1132 1133 if (hcr) { 1134 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1135 for (i = 1; i <= sc->sc_noport; i++) { 1136 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1137 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == 1138 EHCI_PS_SUSP) 1139 EOWRITE4(sc, EHCI_PORTSC(i), 1140 cmd & ~EHCI_PS_FPR); 1141 } 1142 } 1143 1144 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1145 1146 /* Take over port ownership */ 1147 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 1148 1149 for (i = 0; i < 100; i++) { 1150 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1151 if (hcr != EHCI_STS_HCH) 1152 break; 1153 1154 usb_delay_ms(&sc->sc_bus, 1); 1155 } 1156 if (hcr == EHCI_STS_HCH) 1157 printf("%s: config timeout\n", 1158 sc->sc_bus.bdev.dv_xname); 1159 1160 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1161 1162 sc->sc_bus.use_polling--; 1163 break; 1164 } 1165 splx(s); 1166 1167 #ifdef EHCI_DEBUG 1168 DPRINTF(("ehci_power: sc=%p\n", sc)); 1169 if (ehcidebug > 0) 1170 ehci_dump_regs(sc); 1171 #endif 1172 } 1173 1174 /* 1175 * Shut down the controller when the system is going down. 1176 */ 1177 void 1178 ehci_shutdown(void *v) 1179 { 1180 ehci_softc_t *sc = v; 1181 1182 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1183 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1184 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1185 } 1186 1187 usbd_status 1188 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1189 { 1190 struct ehci_softc *sc = (struct ehci_softc *)bus; 1191 usbd_status err; 1192 1193 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1194 #ifdef EHCI_DEBUG 1195 if (err) 1196 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1197 #endif 1198 return (err); 1199 } 1200 1201 void 1202 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1203 { 1204 struct ehci_softc *sc = (struct ehci_softc *)bus; 1205 1206 usb_freemem(&sc->sc_bus, dma); 1207 } 1208 1209 usbd_xfer_handle 1210 ehci_allocx(struct usbd_bus *bus) 1211 { 1212 struct ehci_softc *sc = (struct ehci_softc *)bus; 1213 usbd_xfer_handle xfer; 1214 1215 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1216 if (xfer != NULL) { 1217 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1218 #ifdef DIAGNOSTIC 1219 if (xfer->busy_free != XFER_FREE) 1220 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", 1221 xfer, xfer->busy_free); 1222 #endif 1223 } else 1224 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1225 1226 if (xfer != NULL) { 1227 memset(xfer, 0, sizeof(struct ehci_xfer)); 1228 usb_init_task(&EXFER(xfer)->abort_task, ehci_timeout_task, 1229 xfer); 1230 EXFER(xfer)->ehci_xfer_flags = 0; 1231 #ifdef DIAGNOSTIC 1232 EXFER(xfer)->isdone = 1; 1233 xfer->busy_free = XFER_BUSY; 1234 #endif 1235 } 1236 return (xfer); 1237 } 1238 1239 void 1240 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1241 { 1242 struct ehci_softc *sc = (struct ehci_softc *)bus; 1243 1244 #ifdef DIAGNOSTIC 1245 if (xfer->busy_free != XFER_BUSY) { 1246 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1247 xfer->busy_free); 1248 return; 1249 } 1250 xfer->busy_free = XFER_FREE; 1251 if (!EXFER(xfer)->isdone) { 1252 printf("ehci_freex: !isdone\n"); 1253 return; 1254 } 1255 #endif 1256 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1257 } 1258 1259 void 1260 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1261 { 1262 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1263 1264 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1265 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1266 #if defined(EHCI_DEBUG) && defined(USB_DEBUG) 1267 if (ehcidebug) 1268 usbd_dump_pipe(pipe); 1269 #endif 1270 #ifdef DIAGNOSTIC 1271 if ((epipe->sqh->qh.qh_qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) != 0) 1272 panic("ehci_device_clear_toggle: queue active"); 1273 #endif 1274 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1275 } 1276 1277 void 1278 ehci_noop(usbd_pipe_handle pipe) 1279 { 1280 } 1281 1282 #ifdef EHCI_DEBUG 1283 void 1284 ehci_dump_regs(ehci_softc_t *sc) 1285 { 1286 int i; 1287 1288 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1289 EOREAD4(sc, EHCI_USBCMD), 1290 EOREAD4(sc, EHCI_USBSTS), 1291 EOREAD4(sc, EHCI_USBINTR)); 1292 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1293 EOREAD4(sc, EHCI_FRINDEX), 1294 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1295 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1296 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1297 for (i = 1; i <= sc->sc_noport; i++) 1298 printf("port %d status=0x%08x\n", i, 1299 EOREAD4(sc, EHCI_PORTSC(i))); 1300 } 1301 1302 /* 1303 * Unused function - this is meant to be called from a kernel 1304 * debugger. 1305 */ 1306 void 1307 ehci_dump() 1308 { 1309 ehci_dump_regs(theehci); 1310 } 1311 1312 void 1313 ehci_dump_link(ehci_link_t link, int type) 1314 { 1315 link = letoh32(link); 1316 printf("0x%08x", link); 1317 if (link & EHCI_LINK_TERMINATE) 1318 printf("<T>"); 1319 else { 1320 printf("<"); 1321 if (type) { 1322 switch (EHCI_LINK_TYPE(link)) { 1323 case EHCI_LINK_ITD: 1324 printf("ITD"); 1325 break; 1326 case EHCI_LINK_QH: 1327 printf("QH"); 1328 break; 1329 case EHCI_LINK_SITD: 1330 printf("SITD"); 1331 break; 1332 case EHCI_LINK_FSTN: 1333 printf("FSTN"); 1334 break; 1335 } 1336 } 1337 printf(">"); 1338 } 1339 } 1340 1341 void 1342 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1343 { 1344 int i; 1345 u_int32_t stop; 1346 1347 stop = 0; 1348 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1349 ehci_dump_sqtd(sqtd); 1350 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1351 } 1352 if (!stop) 1353 printf("dump aborted, too many TDs\n"); 1354 } 1355 1356 void 1357 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1358 { 1359 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1360 ehci_dump_qtd(&sqtd->qtd); 1361 } 1362 1363 void 1364 ehci_dump_qtd(ehci_qtd_t *qtd) 1365 { 1366 u_int32_t s; 1367 char sbuf[128]; 1368 1369 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1370 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1371 printf("\n"); 1372 s = letoh32(qtd->qtd_status); 1373 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), "\20\10ACTIVE\7HALTED" 1374 "\6BUFERR\5BABBLE\4XACTERR\3MISSED\2SPLIT\1PING", 1375 sbuf, sizeof(sbuf)); 1376 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1377 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1378 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1379 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1380 EHCI_QTD_GET_PID(s), sbuf); 1381 for (s = 0; s < 5; s++) 1382 printf(" buffer[%d]=0x%08x\n", s, letoh32(qtd->qtd_buffer[s])); 1383 } 1384 1385 void 1386 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1387 { 1388 ehci_qh_t *qh = &sqh->qh; 1389 u_int32_t endp, endphub; 1390 1391 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1392 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1393 endp = letoh32(qh->qh_endp); 1394 printf(" endp=0x%08x\n", endp); 1395 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1396 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1397 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1398 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1399 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1400 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1401 EHCI_QH_GET_NRL(endp)); 1402 endphub = letoh32(qh->qh_endphub); 1403 printf(" endphub=0x%08x\n", endphub); 1404 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1405 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1406 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1407 EHCI_QH_GET_MULT(endphub)); 1408 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1409 printf("Overlay qTD:\n"); 1410 ehci_dump_qtd(&qh->qh_qtd); 1411 } 1412 1413 #if notyet 1414 void 1415 ehci_dump_itd(struct ehci_soft_itd *itd) 1416 { 1417 ehci_isoc_trans_t t; 1418 ehci_isoc_bufr_ptr_t b, b2, b3; 1419 int i; 1420 1421 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1422 1423 for (i = 0; i < 8;i++) { 1424 t = letoh32(itd->itd.itd_ctl[i]); 1425 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1426 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1427 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1428 EHCI_ITD_GET_OFFS(t)); 1429 } 1430 printf("ITDbufr: "); 1431 for (i = 0; i < 7; i++) 1432 printf("%X,", EHCI_ITD_GET_BPTR(letoh32(itd->itd.itd_bufr[i]))); 1433 1434 b = letoh32(itd->itd.itd_bufr[0]); 1435 b2 = letoh32(itd->itd.itd_bufr[1]); 1436 b3 = letoh32(itd->itd.itd_bufr[2]); 1437 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1438 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1439 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1440 } 1441 1442 void 1443 ehci_dump_sitd(struct ehci_soft_itd *itd) 1444 { 1445 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1446 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1447 itd->xfer_next, itd->physaddr, itd->slot); 1448 } 1449 #endif 1450 1451 #ifdef DIAGNOSTIC 1452 void 1453 ehci_dump_exfer(struct ehci_xfer *ex) 1454 { 1455 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p " 1456 "isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, 1457 ex->itdend, ex->isdone); 1458 } 1459 #endif 1460 1461 #endif /* EHCI_DEBUG */ 1462 1463 usbd_status 1464 ehci_open(usbd_pipe_handle pipe) 1465 { 1466 usbd_device_handle dev = pipe->device; 1467 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1468 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1469 u_int8_t addr = dev->address; 1470 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1471 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1472 ehci_soft_qh_t *sqh; 1473 usbd_status err; 1474 int s; 1475 int ival, speed, naks; 1476 int hshubaddr, hshubport; 1477 1478 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1479 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1480 1481 if (sc->sc_dying) 1482 return (USBD_IOERROR); 1483 1484 if (dev->myhsport) { 1485 hshubaddr = dev->myhsport->parent->address; 1486 hshubport = dev->myhsport->portno; 1487 } else { 1488 hshubaddr = 0; 1489 hshubport = 0; 1490 } 1491 1492 if (addr == sc->sc_addr) { 1493 switch (ed->bEndpointAddress) { 1494 case USB_CONTROL_ENDPOINT: 1495 pipe->methods = &ehci_root_ctrl_methods; 1496 break; 1497 case UE_DIR_IN | EHCI_INTR_ENDPT: 1498 pipe->methods = &ehci_root_intr_methods; 1499 break; 1500 default: 1501 return (USBD_INVAL); 1502 } 1503 return (USBD_NORMAL_COMPLETION); 1504 } 1505 1506 /* XXX All this stuff is only valid for async. */ 1507 switch (dev->speed) { 1508 case USB_SPEED_LOW: 1509 speed = EHCI_QH_SPEED_LOW; 1510 break; 1511 case USB_SPEED_FULL: 1512 speed = EHCI_QH_SPEED_FULL; 1513 break; 1514 case USB_SPEED_HIGH: 1515 speed = EHCI_QH_SPEED_HIGH; 1516 break; 1517 default: 1518 panic("ehci_open: bad device speed %d", dev->speed); 1519 } 1520 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1521 printf("%s: Error opening low/full speed isoc endpoint.\n" 1522 "A low/full speed device is attached to a USB2 hub, and " 1523 "transaction translations are not yet supported.\n" 1524 "Reattach the device to the root hub instead.\n", 1525 sc->sc_bus.bdev.dv_xname); 1526 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1527 hshubaddr, hshubport)); 1528 return (USBD_INVAL); 1529 } 1530 1531 naks = 8; /* XXX */ 1532 1533 /* Allocate sqh for everything, save isoc xfers */ 1534 if (xfertype != UE_ISOCHRONOUS) { 1535 sqh = ehci_alloc_sqh(sc); 1536 if (sqh == NULL) 1537 return (USBD_NOMEM); 1538 /* qh_link filled when the QH is added */ 1539 sqh->qh.qh_endp = htole32( 1540 EHCI_QH_SET_ADDR(addr) | 1541 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1542 EHCI_QH_SET_EPS(speed) | 1543 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1544 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1545 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1546 EHCI_QH_CTL : 0) | 1547 EHCI_QH_SET_NRL(naks) 1548 ); 1549 sqh->qh.qh_endphub = htole32( 1550 EHCI_QH_SET_MULT(1) | 1551 EHCI_QH_SET_HUBA(hshubaddr) | 1552 EHCI_QH_SET_PORT(hshubport) | 1553 EHCI_QH_SET_CMASK(0x1c) | /* XXX */ 1554 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0) 1555 ); 1556 sqh->qh.qh_curqtd = EHCI_NULL; 1557 /* Fill the overlay qTD */ 1558 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1559 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1560 sqh->qh.qh_qtd.qtd_status = 1561 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1562 epipe->sqh = sqh; 1563 } else { 1564 sqh = NULL; 1565 } /*xfertype == UE_ISOC*/ 1566 1567 switch (xfertype) { 1568 case UE_CONTROL: 1569 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1570 0, &epipe->u.ctl.reqdma); 1571 #ifdef EHCI_DEBUG 1572 if (err) 1573 printf("ehci_open: usb_allocmem()=%d\n", err); 1574 #endif 1575 if (err) 1576 goto bad; 1577 pipe->methods = &ehci_device_ctrl_methods; 1578 s = splusb(); 1579 ehci_add_qh(sqh, sc->sc_async_head); 1580 splx(s); 1581 break; 1582 case UE_BULK: 1583 pipe->methods = &ehci_device_bulk_methods; 1584 s = splusb(); 1585 ehci_add_qh(sqh, sc->sc_async_head); 1586 splx(s); 1587 break; 1588 case UE_INTERRUPT: 1589 pipe->methods = &ehci_device_intr_methods; 1590 ival = pipe->interval; 1591 if (ival == USBD_DEFAULT_INTERVAL) 1592 ival = ed->bInterval; 1593 s = splusb(); 1594 err = ehci_device_setintr(sc, sqh, ival); 1595 splx(s); 1596 return (err); 1597 case UE_ISOCHRONOUS: 1598 pipe->methods = &ehci_device_isoc_methods; 1599 if (ed->bInterval == 0 || ed->bInterval > 16) { 1600 printf("ehci: opening pipe with invalid bInterval\n"); 1601 err = USBD_INVAL; 1602 goto bad; 1603 } 1604 if (UGETW(ed->wMaxPacketSize) == 0) { 1605 printf("ehci: zero length endpoint open request\n"); 1606 err = USBD_INVAL; 1607 goto bad; 1608 } 1609 epipe->u.isoc.next_frame = 0; 1610 epipe->u.isoc.cur_xfers = 0; 1611 break; 1612 default: 1613 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1614 return (USBD_INVAL); 1615 } 1616 return (USBD_NORMAL_COMPLETION); 1617 1618 bad: 1619 if (sqh != NULL) 1620 ehci_free_sqh(sc, sqh); 1621 return (err); 1622 } 1623 1624 /* 1625 * Add an ED to the schedule. Called at splusb(). 1626 * If in the async schedule, it will always have a next. 1627 * If in the intr schedule it may not. 1628 */ 1629 void 1630 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1631 { 1632 SPLUSBCHECK; 1633 1634 sqh->next = head->next; 1635 sqh->prev = head; 1636 sqh->qh.qh_link = head->qh.qh_link; 1637 head->next = sqh; 1638 if (sqh->next) 1639 sqh->next->prev = sqh; 1640 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1641 1642 #ifdef EHCI_DEBUG 1643 if (ehcidebug > 5) { 1644 printf("ehci_add_qh:\n"); 1645 ehci_dump_sqh(sqh); 1646 } 1647 #endif 1648 } 1649 1650 /* 1651 * Remove an ED from the schedule. Called at splusb(). 1652 * Will always have a 'next' if it's in the async list as it's circular. 1653 */ 1654 void 1655 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1656 { 1657 SPLUSBCHECK; 1658 /* XXX */ 1659 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1660 sqh->prev->next = sqh->next; 1661 if (sqh->next) 1662 sqh->next->prev = sqh->prev; 1663 ehci_sync_hc(sc); 1664 } 1665 1666 void 1667 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1668 { 1669 int i; 1670 u_int32_t status; 1671 1672 /* Save toggle bit and ping status. */ 1673 status = sqh->qh.qh_qtd.qtd_status & 1674 htole32(EHCI_QTD_TOGGLE_MASK | 1675 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1676 /* Set HALTED to make hw leave it alone. */ 1677 sqh->qh.qh_qtd.qtd_status = 1678 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1679 sqh->qh.qh_curqtd = 0; 1680 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1681 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1682 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1683 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1684 sqh->sqtd = sqtd; 1685 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1686 sqh->qh.qh_qtd.qtd_status = status; 1687 } 1688 1689 /* 1690 * Ensure that the HC has released all references to the QH. We do this 1691 * by asking for a Async Advance Doorbell interrupt and then we wait for 1692 * the interrupt. 1693 * To make this easier we first obtain exclusive use of the doorbell. 1694 */ 1695 void 1696 ehci_sync_hc(ehci_softc_t *sc) 1697 { 1698 int s, error; 1699 int tries = 0; 1700 1701 if (sc->sc_dying) { 1702 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1703 return; 1704 } 1705 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1706 /* get doorbell */ 1707 rw_enter_write(&sc->sc_doorbell_lock); 1708 s = splhardusb(); 1709 do { 1710 /* ask for doorbell */ 1711 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | 1712 EHCI_CMD_IAAD); 1713 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1714 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1715 /* bell wait */ 1716 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz / 2); 1717 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1718 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1719 } while (error && ++tries < 10); 1720 splx(s); 1721 /* release doorbell */ 1722 rw_exit_write(&sc->sc_doorbell_lock); 1723 #ifdef DIAGNOSTIC 1724 if (error) 1725 printf("ehci_sync_hc: tsleep() = %d\n", error); 1726 #endif 1727 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1728 } 1729 1730 /*Call at splusb*/ 1731 void 1732 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1733 { 1734 struct ehci_soft_itd *itd, *prev; 1735 1736 prev = NULL; 1737 1738 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1739 panic("ehci isoc xfer being freed, but with no itd chain"); 1740 1741 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1742 prev = itd->u.frame_list.prev; 1743 /* Unlink itd from hardware chain, or frame array */ 1744 if (prev == NULL) { /* We're at the table head */ 1745 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1746 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1747 1748 if (itd->u.frame_list.next != NULL) 1749 itd->u.frame_list.next->u.frame_list.prev = 1750 NULL; 1751 } else { 1752 /* XXX this part is untested... */ 1753 prev->itd.itd_next = itd->itd.itd_next; 1754 prev->u.frame_list.next = itd->u.frame_list.next; 1755 if (itd->u.frame_list.next != NULL) 1756 itd->u.frame_list.next->u.frame_list.prev = 1757 prev; 1758 } 1759 } 1760 1761 prev = NULL; 1762 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1763 if (prev != NULL) 1764 ehci_free_itd(sc, prev); 1765 prev = itd; 1766 } 1767 if (prev) 1768 ehci_free_itd(sc, prev); 1769 exfer->itdstart = NULL; 1770 exfer->itdend = NULL; 1771 } 1772 1773 /***********/ 1774 1775 /* 1776 * Data structures and routines to emulate the root hub. 1777 */ 1778 usb_device_descriptor_t ehci_devd = { 1779 USB_DEVICE_DESCRIPTOR_SIZE, 1780 UDESC_DEVICE, /* type */ 1781 {0x00, 0x02}, /* USB version */ 1782 UDCLASS_HUB, /* class */ 1783 UDSUBCLASS_HUB, /* subclass */ 1784 UDPROTO_HSHUBSTT, /* protocol */ 1785 64, /* max packet */ 1786 {0},{0},{0x00,0x01}, /* device id */ 1787 1,2,0, /* string indicies */ 1788 1 /* # of configurations */ 1789 }; 1790 1791 usb_device_qualifier_t ehci_odevd = { 1792 USB_DEVICE_DESCRIPTOR_SIZE, 1793 UDESC_DEVICE_QUALIFIER, /* type */ 1794 {0x00, 0x02}, /* USB version */ 1795 UDCLASS_HUB, /* class */ 1796 UDSUBCLASS_HUB, /* subclass */ 1797 UDPROTO_FSHUB, /* protocol */ 1798 64, /* max packet */ 1799 1, /* # of configurations */ 1800 0 1801 }; 1802 1803 usb_config_descriptor_t ehci_confd = { 1804 USB_CONFIG_DESCRIPTOR_SIZE, 1805 UDESC_CONFIG, 1806 {USB_CONFIG_DESCRIPTOR_SIZE + 1807 USB_INTERFACE_DESCRIPTOR_SIZE + 1808 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1809 1, 1810 1, 1811 0, 1812 UC_SELF_POWERED, 1813 0 /* max power */ 1814 }; 1815 1816 usb_interface_descriptor_t ehci_ifcd = { 1817 USB_INTERFACE_DESCRIPTOR_SIZE, 1818 UDESC_INTERFACE, 1819 0, 1820 0, 1821 1, 1822 UICLASS_HUB, 1823 UISUBCLASS_HUB, 1824 UIPROTO_HSHUBSTT, 1825 0 1826 }; 1827 1828 usb_endpoint_descriptor_t ehci_endpd = { 1829 USB_ENDPOINT_DESCRIPTOR_SIZE, 1830 UDESC_ENDPOINT, 1831 UE_DIR_IN | EHCI_INTR_ENDPT, 1832 UE_INTERRUPT, 1833 {8, 0}, /* max packet */ 1834 255 1835 }; 1836 1837 usb_hub_descriptor_t ehci_hubd = { 1838 USB_HUB_DESCRIPTOR_SIZE, 1839 UDESC_HUB, 1840 0, 1841 {0,0}, 1842 0, 1843 0, 1844 {0}, 1845 }; 1846 1847 int 1848 ehci_str(usb_string_descriptor_t *p, int l, const char *s) 1849 { 1850 int i; 1851 1852 if (l == 0) 1853 return (0); 1854 p->bLength = 2 * strlen(s) + 2; 1855 if (l == 1) 1856 return (1); 1857 p->bDescriptorType = UDESC_STRING; 1858 l -= 2; 1859 for (i = 0; s[i] && l > 1; i++, l -= 2) 1860 USETW2(p->bString[i], 0, s[i]); 1861 return (2*i+2); 1862 } 1863 1864 /* 1865 * Simulate a hardware hub by handling all the necessary requests. 1866 */ 1867 usbd_status 1868 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1869 { 1870 usbd_status err; 1871 1872 /* Insert last in queue. */ 1873 err = usb_insert_transfer(xfer); 1874 if (err) 1875 return (err); 1876 1877 /* Pipe isn't running, start first */ 1878 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1879 } 1880 1881 usbd_status 1882 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1883 { 1884 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 1885 usb_device_request_t *req; 1886 void *buf = NULL; 1887 int port, i; 1888 int s, len, value, index, l, totlen = 0; 1889 usb_port_status_t ps; 1890 usb_hub_descriptor_t hubd; 1891 usbd_status err; 1892 u_int32_t v; 1893 1894 if (sc->sc_dying) 1895 return (USBD_IOERROR); 1896 1897 #ifdef DIAGNOSTIC 1898 if (!(xfer->rqflags & URQ_REQUEST)) 1899 /* XXX panic */ 1900 return (USBD_INVAL); 1901 #endif 1902 req = &xfer->request; 1903 1904 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1905 req->bmRequestType, req->bRequest)); 1906 1907 len = UGETW(req->wLength); 1908 value = UGETW(req->wValue); 1909 index = UGETW(req->wIndex); 1910 1911 if (len != 0) 1912 buf = KERNADDR(&xfer->dmabuf, 0); 1913 1914 #define C(x,y) ((x) | ((y) << 8)) 1915 switch(C(req->bRequest, req->bmRequestType)) { 1916 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1917 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1918 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1919 /* 1920 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1921 * for the integrated root hub. 1922 */ 1923 break; 1924 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1925 if (len > 0) { 1926 *(u_int8_t *)buf = sc->sc_conf; 1927 totlen = 1; 1928 } 1929 break; 1930 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1931 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1932 switch(value >> 8) { 1933 case UDESC_DEVICE: 1934 if ((value & 0xff) != 0) { 1935 err = USBD_IOERROR; 1936 goto ret; 1937 } 1938 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1939 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1940 memcpy(buf, &ehci_devd, l); 1941 break; 1942 /* 1943 * We can't really operate at another speed, but the spec says 1944 * we need this descriptor. 1945 */ 1946 case UDESC_DEVICE_QUALIFIER: 1947 if ((value & 0xff) != 0) { 1948 err = USBD_IOERROR; 1949 goto ret; 1950 } 1951 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1952 memcpy(buf, &ehci_odevd, l); 1953 break; 1954 /* 1955 * We can't really operate at another speed, but the spec says 1956 * we need this descriptor. 1957 */ 1958 case UDESC_OTHER_SPEED_CONFIGURATION: 1959 case UDESC_CONFIG: 1960 if ((value & 0xff) != 0) { 1961 err = USBD_IOERROR; 1962 goto ret; 1963 } 1964 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1965 memcpy(buf, &ehci_confd, l); 1966 ((usb_config_descriptor_t *)buf)->bDescriptorType = 1967 value >> 8; 1968 buf = (char *)buf + l; 1969 len -= l; 1970 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1971 totlen += l; 1972 memcpy(buf, &ehci_ifcd, l); 1973 buf = (char *)buf + l; 1974 len -= l; 1975 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1976 totlen += l; 1977 memcpy(buf, &ehci_endpd, l); 1978 break; 1979 case UDESC_STRING: 1980 if (len == 0) 1981 break; 1982 *(u_int8_t *)buf = 0; 1983 totlen = 1; 1984 switch (value & 0xff) { 1985 case 0: /* Language table */ 1986 totlen = ehci_str(buf, len, "\001"); 1987 break; 1988 case 1: /* Vendor */ 1989 totlen = ehci_str(buf, len, sc->sc_vendor); 1990 break; 1991 case 2: /* Product */ 1992 totlen = ehci_str(buf, len, "EHCI root hub"); 1993 break; 1994 } 1995 break; 1996 default: 1997 err = USBD_IOERROR; 1998 goto ret; 1999 } 2000 break; 2001 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2002 if (len > 0) { 2003 *(u_int8_t *)buf = 0; 2004 totlen = 1; 2005 } 2006 break; 2007 case C(UR_GET_STATUS, UT_READ_DEVICE): 2008 if (len > 1) { 2009 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2010 totlen = 2; 2011 } 2012 break; 2013 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2014 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2015 if (len > 1) { 2016 USETW(((usb_status_t *)buf)->wStatus, 0); 2017 totlen = 2; 2018 } 2019 break; 2020 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2021 if (value >= USB_MAX_DEVICES) { 2022 err = USBD_IOERROR; 2023 goto ret; 2024 } 2025 sc->sc_addr = value; 2026 break; 2027 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2028 if (value != 0 && value != 1) { 2029 err = USBD_IOERROR; 2030 goto ret; 2031 } 2032 sc->sc_conf = value; 2033 break; 2034 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2035 break; 2036 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2037 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2038 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2039 err = USBD_IOERROR; 2040 goto ret; 2041 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2042 break; 2043 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2044 break; 2045 /* Hub requests */ 2046 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2047 break; 2048 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2049 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2050 "port=%d feature=%d\n", index, value)); 2051 if (index < 1 || index > sc->sc_noport) { 2052 err = USBD_IOERROR; 2053 goto ret; 2054 } 2055 port = EHCI_PORTSC(index); 2056 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2057 switch(value) { 2058 case UHF_PORT_ENABLE: 2059 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2060 break; 2061 case UHF_PORT_SUSPEND: 2062 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 2063 break; 2064 case UHF_PORT_POWER: 2065 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2066 break; 2067 case UHF_PORT_TEST: 2068 DPRINTFN(2,("ehci_root_ctrl_start: " 2069 "clear port test %d\n", index)); 2070 break; 2071 case UHF_PORT_INDICATOR: 2072 DPRINTFN(2,("ehci_root_ctrl_start: " 2073 "clear port index %d\n", index)); 2074 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2075 break; 2076 case UHF_C_PORT_CONNECTION: 2077 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2078 break; 2079 case UHF_C_PORT_ENABLE: 2080 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2081 break; 2082 case UHF_C_PORT_SUSPEND: 2083 /* how? */ 2084 break; 2085 case UHF_C_PORT_OVER_CURRENT: 2086 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2087 break; 2088 case UHF_C_PORT_RESET: 2089 sc->sc_isreset = 0; 2090 break; 2091 default: 2092 err = USBD_IOERROR; 2093 goto ret; 2094 } 2095 break; 2096 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2097 if ((value & 0xff) != 0) { 2098 err = USBD_IOERROR; 2099 goto ret; 2100 } 2101 hubd = ehci_hubd; 2102 hubd.bNbrPorts = sc->sc_noport; 2103 v = EOREAD4(sc, EHCI_HCSPARAMS); 2104 USETW(hubd.wHubCharacteristics, 2105 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2106 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2107 ? UHD_PORT_IND : 0); 2108 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2109 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2110 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2111 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2112 l = min(len, hubd.bDescLength); 2113 totlen = l; 2114 memcpy(buf, &hubd, l); 2115 break; 2116 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2117 if (len != 4) { 2118 err = USBD_IOERROR; 2119 goto ret; 2120 } 2121 memset(buf, 0, len); /* ? XXX */ 2122 totlen = len; 2123 break; 2124 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2125 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2126 index)); 2127 if (index < 1 || index > sc->sc_noport) { 2128 err = USBD_IOERROR; 2129 goto ret; 2130 } 2131 if (len != 4) { 2132 err = USBD_IOERROR; 2133 goto ret; 2134 } 2135 v = EOREAD4(sc, EHCI_PORTSC(index)); 2136 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2137 i = UPS_HIGH_SPEED; 2138 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2139 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2140 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2141 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2142 if (v & EHCI_PS_PR) i |= UPS_RESET; 2143 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2144 USETW(ps.wPortStatus, i); 2145 i = 0; 2146 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2147 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2148 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2149 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 2150 USETW(ps.wPortChange, i); 2151 l = min(len, sizeof(ps)); 2152 memcpy(buf, &ps, l); 2153 totlen = l; 2154 break; 2155 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2156 err = USBD_IOERROR; 2157 goto ret; 2158 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2159 break; 2160 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2161 if (index < 1 || index > sc->sc_noport) { 2162 err = USBD_IOERROR; 2163 goto ret; 2164 } 2165 port = EHCI_PORTSC(index); 2166 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2167 switch(value) { 2168 case UHF_PORT_ENABLE: 2169 EOWRITE4(sc, port, v | EHCI_PS_PE); 2170 break; 2171 case UHF_PORT_SUSPEND: 2172 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2173 break; 2174 case UHF_PORT_DISOWN_TO_1_1: 2175 /* enter to Port Reset State */ 2176 v &= ~EHCI_PS_PE; 2177 EOWRITE4(sc, port, v | EHCI_PS_PR); 2178 ehci_disown(sc, index, 0); 2179 break; 2180 case UHF_PORT_RESET: 2181 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2182 index)); 2183 if (EHCI_PS_IS_LOWSPEED(v)) { 2184 /* Low speed device, give up ownership. */ 2185 ehci_disown(sc, index, 1); 2186 break; 2187 } 2188 /* Start reset sequence. */ 2189 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2190 EOWRITE4(sc, port, v | EHCI_PS_PR); 2191 /* Wait for reset to complete. */ 2192 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2193 if (sc->sc_dying) { 2194 err = USBD_IOERROR; 2195 goto ret; 2196 } 2197 /* Terminate reset sequence. */ 2198 v = EOREAD4(sc, port); 2199 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2200 /* Wait for HC to complete reset. */ 2201 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2202 if (sc->sc_dying) { 2203 err = USBD_IOERROR; 2204 goto ret; 2205 } 2206 v = EOREAD4(sc, port); 2207 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2208 if (v & EHCI_PS_PR) { 2209 printf("%s: port reset timeout\n", 2210 sc->sc_bus.bdev.dv_xname); 2211 return (USBD_TIMEOUT); 2212 } 2213 if (!(v & EHCI_PS_PE)) { 2214 /* Not a high speed device, give up ownership.*/ 2215 ehci_disown(sc, index, 0); 2216 break; 2217 } 2218 sc->sc_isreset = 1; 2219 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2220 index, v)); 2221 break; 2222 case UHF_PORT_POWER: 2223 DPRINTFN(2,("ehci_root_ctrl_start: " 2224 "set port power %d\n", index)); 2225 EOWRITE4(sc, port, v | EHCI_PS_PP); 2226 break; 2227 case UHF_PORT_TEST: 2228 DPRINTFN(2,("ehci_root_ctrl_start: " 2229 "set port test %d\n", index)); 2230 break; 2231 case UHF_PORT_INDICATOR: 2232 DPRINTFN(2,("ehci_root_ctrl_start: " 2233 "set port ind %d\n", index)); 2234 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2235 break; 2236 default: 2237 err = USBD_IOERROR; 2238 goto ret; 2239 } 2240 break; 2241 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2242 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2243 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2244 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2245 break; 2246 default: 2247 err = USBD_IOERROR; 2248 goto ret; 2249 } 2250 xfer->actlen = totlen; 2251 err = USBD_NORMAL_COMPLETION; 2252 ret: 2253 xfer->status = err; 2254 s = splusb(); 2255 usb_transfer_complete(xfer); 2256 splx(s); 2257 return (USBD_IN_PROGRESS); 2258 } 2259 2260 void 2261 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2262 { 2263 int port; 2264 u_int32_t v; 2265 2266 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2267 2268 port = EHCI_PORTSC(index); 2269 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2270 EOWRITE4(sc, port, v | EHCI_PS_PO); 2271 } 2272 2273 /* Abort a root control request. */ 2274 void 2275 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2276 { 2277 /* Nothing to do, all transfers are synchronous. */ 2278 } 2279 2280 /* Close the root pipe. */ 2281 void 2282 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2283 { 2284 DPRINTF(("ehci_root_ctrl_close\n")); 2285 /* Nothing to do. */ 2286 } 2287 2288 void 2289 ehci_root_intr_done(usbd_xfer_handle xfer) 2290 { 2291 } 2292 2293 usbd_status 2294 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2295 { 2296 usbd_status err; 2297 2298 /* Insert last in queue. */ 2299 err = usb_insert_transfer(xfer); 2300 if (err) 2301 return (err); 2302 2303 /* Pipe isn't running, start first */ 2304 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2305 } 2306 2307 usbd_status 2308 ehci_root_intr_start(usbd_xfer_handle xfer) 2309 { 2310 usbd_pipe_handle pipe = xfer->pipe; 2311 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2312 2313 if (sc->sc_dying) 2314 return (USBD_IOERROR); 2315 2316 sc->sc_intrxfer = xfer; 2317 2318 return (USBD_IN_PROGRESS); 2319 } 2320 2321 /* Abort a root interrupt request. */ 2322 void 2323 ehci_root_intr_abort(usbd_xfer_handle xfer) 2324 { 2325 int s; 2326 2327 if (xfer->pipe->intrxfer == xfer) { 2328 DPRINTF(("ehci_root_intr_abort: remove\n")); 2329 xfer->pipe->intrxfer = NULL; 2330 } 2331 xfer->status = USBD_CANCELLED; 2332 s = splusb(); 2333 usb_transfer_complete(xfer); 2334 splx(s); 2335 } 2336 2337 /* Close the root pipe. */ 2338 void 2339 ehci_root_intr_close(usbd_pipe_handle pipe) 2340 { 2341 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2342 2343 DPRINTF(("ehci_root_intr_close\n")); 2344 2345 sc->sc_intrxfer = NULL; 2346 } 2347 2348 void 2349 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2350 { 2351 } 2352 2353 /************************/ 2354 2355 ehci_soft_qh_t * 2356 ehci_alloc_sqh(ehci_softc_t *sc) 2357 { 2358 ehci_soft_qh_t *sqh; 2359 usbd_status err; 2360 int i, offs; 2361 usb_dma_t dma; 2362 2363 if (sc->sc_freeqhs == NULL) { 2364 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2365 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2366 EHCI_PAGE_SIZE, &dma); 2367 #ifdef EHCI_DEBUG 2368 if (err) 2369 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2370 #endif 2371 if (err) 2372 return (NULL); 2373 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2374 offs = i * EHCI_SQH_SIZE; 2375 sqh = KERNADDR(&dma, offs); 2376 sqh->physaddr = DMAADDR(&dma, offs); 2377 sqh->next = sc->sc_freeqhs; 2378 sc->sc_freeqhs = sqh; 2379 } 2380 } 2381 sqh = sc->sc_freeqhs; 2382 sc->sc_freeqhs = sqh->next; 2383 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2384 sqh->next = NULL; 2385 sqh->prev = NULL; 2386 return (sqh); 2387 } 2388 2389 void 2390 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2391 { 2392 sqh->next = sc->sc_freeqhs; 2393 sc->sc_freeqhs = sqh; 2394 } 2395 2396 ehci_soft_qtd_t * 2397 ehci_alloc_sqtd(ehci_softc_t *sc) 2398 { 2399 ehci_soft_qtd_t *sqtd; 2400 usbd_status err; 2401 int i, offs; 2402 usb_dma_t dma; 2403 int s; 2404 2405 if (sc->sc_freeqtds == NULL) { 2406 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2407 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2408 EHCI_PAGE_SIZE, &dma); 2409 #ifdef EHCI_DEBUG 2410 if (err) 2411 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2412 #endif 2413 if (err) 2414 return (NULL); 2415 s = splusb(); 2416 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2417 offs = i * EHCI_SQTD_SIZE; 2418 sqtd = KERNADDR(&dma, offs); 2419 sqtd->physaddr = DMAADDR(&dma, offs); 2420 sqtd->nextqtd = sc->sc_freeqtds; 2421 sc->sc_freeqtds = sqtd; 2422 } 2423 splx(s); 2424 } 2425 2426 s = splusb(); 2427 sqtd = sc->sc_freeqtds; 2428 sc->sc_freeqtds = sqtd->nextqtd; 2429 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2430 sqtd->nextqtd = NULL; 2431 sqtd->xfer = NULL; 2432 splx(s); 2433 2434 return (sqtd); 2435 } 2436 2437 void 2438 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2439 { 2440 int s; 2441 2442 s = splusb(); 2443 sqtd->nextqtd = sc->sc_freeqtds; 2444 sc->sc_freeqtds = sqtd; 2445 splx(s); 2446 } 2447 2448 usbd_status 2449 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, u_int alen, 2450 int rd, usbd_xfer_handle xfer, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2451 { 2452 ehci_soft_qtd_t *next, *cur; 2453 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2454 u_int32_t qtdstatus; 2455 u_int len, curlen; 2456 int mps, i, iscontrol, forceshort; 2457 usb_dma_t *dma = &xfer->dmabuf; 2458 2459 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2460 2461 len = alen; 2462 iscontrol = (epipe->pipe.endpoint->edesc->bmAttributes & UE_XFERTYPE) == 2463 UE_CONTROL; 2464 2465 dataphys = DMAADDR(dma, 0); 2466 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2467 qtdstatus = EHCI_QTD_ACTIVE | 2468 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2469 EHCI_QTD_SET_CERR(3); /* IOC and BYTES set below */ 2470 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2471 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2472 len % mps == 0; 2473 /* 2474 * The control transfer data stage always starts with a toggle of 1. 2475 * For other transfers we let the hardware track the toggle state. 2476 */ 2477 if (iscontrol) 2478 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2479 2480 cur = ehci_alloc_sqtd(sc); 2481 *sp = cur; 2482 if (cur == NULL) 2483 goto nomem; 2484 for (;;) { 2485 dataphyspage = EHCI_PAGE(dataphys); 2486 /* The EHCI hardware can handle at most 5 pages. */ 2487 if (dataphyslastpage - dataphyspage < 2488 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2489 /* we can handle it in this QTD */ 2490 curlen = len; 2491 } else { 2492 /* must use multiple TDs, fill as much as possible. */ 2493 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2494 EHCI_PAGE_OFFSET(dataphys); 2495 #ifdef DIAGNOSTIC 2496 if (curlen > len) { 2497 printf("ehci_alloc_sqtd_chain: curlen=%u " 2498 "len=%u offs=0x%x\n", curlen, len, 2499 EHCI_PAGE_OFFSET(dataphys)); 2500 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2501 dataphyslastpage, dataphyspage, dataphys); 2502 curlen = len; 2503 } 2504 #endif 2505 /* the length must be a multiple of the max size */ 2506 curlen -= curlen % mps; 2507 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2508 "curlen=%u\n", curlen)); 2509 #ifdef DIAGNOSTIC 2510 if (curlen == 0) 2511 panic("ehci_alloc_std: curlen == 0"); 2512 #endif 2513 } 2514 2515 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2516 "dataphyslastpage=0x%08x len=%u curlen=%u\n", 2517 dataphys, dataphyslastpage, len, curlen)); 2518 len -= curlen; 2519 2520 /* 2521 * Allocate another transfer if there's more data left, 2522 * or if force last short transfer flag is set and we're 2523 * allocating a multiple of the max packet size. 2524 */ 2525 if (len != 0 || forceshort) { 2526 next = ehci_alloc_sqtd(sc); 2527 if (next == NULL) 2528 goto nomem; 2529 nextphys = htole32(next->physaddr); 2530 } else { 2531 next = NULL; 2532 nextphys = EHCI_NULL; 2533 } 2534 2535 for (i = 0; i * EHCI_PAGE_SIZE < 2536 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2537 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2538 if (i != 0) /* use offset only in first buffer */ 2539 a = EHCI_PAGE(a); 2540 #ifdef DIAGNOSTIC 2541 if (i >= EHCI_QTD_NBUFFERS) { 2542 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2543 goto nomem; 2544 } 2545 #endif 2546 cur->qtd.qtd_buffer[i] = htole32(a); 2547 cur->qtd.qtd_buffer_hi[i] = 0; 2548 } 2549 cur->nextqtd = next; 2550 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2551 cur->qtd.qtd_status = htole32(qtdstatus | 2552 EHCI_QTD_SET_BYTES(curlen)); 2553 cur->xfer = xfer; 2554 cur->len = curlen; 2555 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2556 dataphys, dataphys + curlen)); 2557 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%u\n", curlen)); 2558 if (iscontrol) { 2559 /* 2560 * adjust the toggle based on the number of packets 2561 * in this qtd 2562 */ 2563 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2564 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2565 } 2566 if (len == 0) { 2567 if (! forceshort) 2568 break; 2569 forceshort = 0; 2570 } 2571 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2572 dataphys += curlen; 2573 cur = next; 2574 } 2575 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2576 *ep = cur; 2577 2578 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2579 *sp, *ep)); 2580 2581 return (USBD_NORMAL_COMPLETION); 2582 2583 nomem: 2584 /* XXX free chain */ 2585 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2586 return (USBD_NOMEM); 2587 } 2588 2589 void 2590 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2591 ehci_soft_qtd_t *sqtdend) 2592 { 2593 ehci_soft_qtd_t *p; 2594 int i; 2595 2596 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2597 sqtd, sqtdend)); 2598 2599 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2600 p = sqtd->nextqtd; 2601 ehci_free_sqtd(sc, sqtd); 2602 } 2603 } 2604 2605 ehci_soft_itd_t * 2606 ehci_alloc_itd(ehci_softc_t *sc) 2607 { 2608 struct ehci_soft_itd *itd, *freeitd; 2609 usbd_status err; 2610 int i, s, offs, frindex, previndex; 2611 usb_dma_t dma; 2612 2613 s = splusb(); 2614 2615 /* Find an itd that wasn't freed this frame or last frame. This can 2616 * discard itds that were freed before frindex wrapped around 2617 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2618 * interrupt and fiddling with list when that happens */ 2619 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2620 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2621 2622 freeitd = NULL; 2623 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2624 if (itd == NULL) 2625 break; 2626 if (itd->slot != frindex && itd->slot != previndex) { 2627 freeitd = itd; 2628 break; 2629 } 2630 } 2631 2632 if (freeitd == NULL) { 2633 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2634 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2635 EHCI_PAGE_SIZE, &dma); 2636 2637 if (err) { 2638 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2639 return (NULL); 2640 } 2641 2642 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2643 offs = i * EHCI_ITD_SIZE; 2644 itd = KERNADDR(&dma, offs); 2645 itd->physaddr = DMAADDR(&dma, offs); 2646 itd->dma = dma; 2647 itd->offs = offs; 2648 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2649 } 2650 freeitd = LIST_FIRST(&sc->sc_freeitds); 2651 } 2652 2653 itd = freeitd; 2654 LIST_REMOVE(itd, u.free_list); 2655 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2656 itd->u.frame_list.next = NULL; 2657 itd->u.frame_list.prev = NULL; 2658 itd->xfer_next = NULL; 2659 itd->slot = 0; 2660 splx(s); 2661 2662 return (itd); 2663 } 2664 2665 void 2666 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2667 { 2668 int s; 2669 2670 s = splusb(); 2671 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2672 splx(s); 2673 } 2674 2675 /****************/ 2676 2677 /* 2678 * Close a reqular pipe. 2679 * Assumes that there are no pending transactions. 2680 */ 2681 void 2682 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2683 { 2684 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2685 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2686 ehci_soft_qh_t *sqh = epipe->sqh; 2687 int s; 2688 2689 s = splusb(); 2690 ehci_rem_qh(sc, sqh, head); 2691 splx(s); 2692 pipe->endpoint->savedtoggle = 2693 EHCI_QTD_GET_TOGGLE(letoh32(sqh->qh.qh_qtd.qtd_status)); 2694 ehci_free_sqh(sc, epipe->sqh); 2695 } 2696 2697 /* 2698 * Abort a device request. 2699 * If this routine is called at splusb() it guarantees that the request 2700 * will be removed from the hardware scheduling and that the callback 2701 * for it will be called with USBD_CANCELLED status. 2702 * It's impossible to guarantee that the requested transfer will not 2703 * have happened since the hardware runs concurrently. 2704 * If the transaction has already happened we rely on the ordinary 2705 * interrupt processing to process it. 2706 */ 2707 void 2708 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2709 { 2710 #define exfer EXFER(xfer) 2711 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2712 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2713 ehci_soft_qh_t *sqh = epipe->sqh; 2714 ehci_soft_qtd_t *sqtd, *snext, **psqtd; 2715 ehci_physaddr_t cur, us, next; 2716 int s; 2717 int hit; 2718 ehci_soft_qh_t *psqh; 2719 2720 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2721 2722 if (sc->sc_dying) { 2723 /* If we're dying, just do the software part. */ 2724 s = splusb(); 2725 xfer->status = status; /* make software ignore it */ 2726 timeout_del(&xfer->timeout_handle); 2727 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 2728 usb_transfer_complete(xfer); 2729 splx(s); 2730 return; 2731 } 2732 2733 if (xfer->device->bus->intr_context) 2734 panic("ehci_abort_xfer: not in process context"); 2735 2736 /* 2737 * If an abort is already in progress then just wait for it to 2738 * complete and return. 2739 */ 2740 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2741 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2742 /* No need to wait if we're aborting from a timeout. */ 2743 if (status == USBD_TIMEOUT) 2744 return; 2745 /* Override the status which might be USBD_TIMEOUT. */ 2746 xfer->status = status; 2747 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2748 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 2749 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 2750 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciaw", 0); 2751 return; 2752 } 2753 2754 /* 2755 * Step 1: Make interrupt routine and timeouts ignore xfer. 2756 */ 2757 s = splusb(); 2758 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2759 xfer->status = status; /* make software ignore it */ 2760 timeout_del(&xfer->timeout_handle); 2761 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 2762 splx(s); 2763 2764 /* 2765 * Step 2: Wait until we know hardware has finished any possible 2766 * use of the xfer. We do this by removing the entire 2767 * queue from the async schedule and waiting for the doorbell. 2768 * Nothing else should be touching the queue now. 2769 */ 2770 psqh = sqh->prev; 2771 ehci_rem_qh(sc, sqh, psqh); 2772 2773 /* 2774 * Step 3: Deactivate all of the qTDs that we will be removing, 2775 * otherwise the queue head may go active again. The EHCI spec 2776 * suggests we should perform the deactivation before removing the 2777 * queue head from the schedule, however the VT6202 (at least) only 2778 * behaves correctly when we deactivate them afterwards. 2779 */ 2780 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2781 sqtd->qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2782 if (sqtd == exfer->sqtdend) 2783 break; 2784 } 2785 ehci_sync_hc(sc); 2786 2787 /* 2788 * Step 4: make sure the soft interrupt routine 2789 * has run. This should remove any completed items off the queue. 2790 * The hardware has no reference to completed items (TDs). 2791 * It's safe to remove them at any time. 2792 * use of the xfer. Also make sure the soft interrupt routine 2793 * has run. 2794 */ 2795 s = splusb(); 2796 sc->sc_softwake = 1; 2797 usb_schedsoftintr(&sc->sc_bus); 2798 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2799 2800 /* 2801 * Step 5: Remove any vestiges of the xfer from the hardware. 2802 * The complication here is that the hardware may have executed 2803 * into or even beyond the xfer we're trying to abort. 2804 * So as we're scanning the TDs of this xfer we check if 2805 * the hardware points to any of them. 2806 * 2807 * first we need to see if there are any transfers 2808 * on this queue before the xfer we are aborting.. we need 2809 * to update any pointers that point to us to point past 2810 * the aborting xfer. (If there is something past us). 2811 * Hardware and software. 2812 */ 2813 cur = EHCI_LINK_ADDR(letoh32(sqh->qh.qh_curqtd)); 2814 hit = 0; 2815 2816 /* If they initially point here. */ 2817 us = exfer->sqtdstart->physaddr; 2818 2819 /* We will change them to point here */ 2820 snext = exfer->sqtdend->nextqtd; 2821 next = snext ? snext->physaddr : EHCI_NULL; 2822 2823 /* 2824 * Now loop through any qTDs before us and keep track of the pointer 2825 * that points to us for the end. 2826 */ 2827 psqtd = &sqh->sqtd; 2828 sqtd = sqh->sqtd; 2829 while (sqtd && sqtd != exfer->sqtdstart) { 2830 hit |= (cur == sqtd->physaddr); 2831 if (EHCI_LINK_ADDR(letoh32(sqtd->qtd.qtd_next)) == us) 2832 sqtd->qtd.qtd_next = next; 2833 if (EHCI_LINK_ADDR(letoh32(sqtd->qtd.qtd_altnext)) == us) 2834 sqtd->qtd.qtd_altnext = next; 2835 psqtd = &sqtd->nextqtd; 2836 sqtd = sqtd->nextqtd; 2837 } 2838 /* make the software pointer bypass us too */ 2839 *psqtd = exfer->sqtdend->nextqtd; 2840 2841 /* 2842 * If we already saw the active one then we are pretty much done. 2843 * We've done all the relinking we need to do. 2844 */ 2845 if (!hit) { 2846 2847 /* 2848 * Now reinitialise the QH to point to the next qTD 2849 * (if there is one). We only need to do this if 2850 * it was previously pointing to us. 2851 * XXX Not quite sure what to do about the data toggle. 2852 */ 2853 sqtd = exfer->sqtdstart; 2854 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2855 if (cur == sqtd->physaddr) { 2856 hit++; 2857 } 2858 if (sqtd == exfer->sqtdend) 2859 break; 2860 } 2861 /* 2862 * Only need to alter the QH if it was pointing at a qTD 2863 * that we are removing. 2864 */ 2865 if (hit) { 2866 if (snext) { 2867 ehci_set_qh_qtd(sqh, snext); 2868 } else { 2869 2870 sqh->qh.qh_curqtd = 0; /* unlink qTDs */ 2871 sqh->qh.qh_qtd.qtd_status = 0; 2872 sqh->qh.qh_qtd.qtd_next = 2873 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2874 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2875 } 2876 } 2877 } 2878 ehci_add_qh(sqh, psqh); 2879 2880 /* 2881 * Step 6: Execute callback. 2882 */ 2883 #ifdef DIAGNOSTIC 2884 exfer->isdone = 1; 2885 #endif 2886 /* Do the wakeup first to avoid touching the xfer after the callback. */ 2887 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 2888 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 2889 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 2890 wakeup(&exfer->ehci_xfer_flags); 2891 } 2892 usb_transfer_complete(xfer); 2893 2894 splx(s); 2895 #undef exfer 2896 } 2897 2898 void 2899 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 2900 { 2901 ehci_isoc_trans_t trans_status; 2902 struct ehci_pipe *epipe; 2903 struct ehci_xfer *exfer; 2904 ehci_softc_t *sc; 2905 struct ehci_soft_itd *itd; 2906 int s, i, wake; 2907 2908 epipe = (struct ehci_pipe *) xfer->pipe; 2909 exfer = EXFER(xfer); 2910 sc = (ehci_softc_t *)epipe->pipe.device->bus; 2911 2912 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 2913 2914 if (sc->sc_dying) { 2915 s = splusb(); 2916 xfer->status = status; 2917 timeout_del(&xfer->timeout_handle); 2918 usb_transfer_complete(xfer); 2919 splx(s); 2920 return; 2921 } 2922 2923 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2924 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 2925 2926 #ifdef DIAGNOSTIC 2927 if (status == USBD_TIMEOUT) 2928 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2929 #endif 2930 2931 xfer->status = status; 2932 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2933 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2934 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 2935 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciiaw", 0); 2936 return; 2937 } 2938 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2939 2940 xfer->status = status; 2941 timeout_del(&xfer->timeout_handle); 2942 2943 s = splusb(); 2944 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2945 for (i = 0; i < 8; i++) { 2946 trans_status = letoh32(itd->itd.itd_ctl[i]); 2947 trans_status &= ~EHCI_ITD_ACTIVE; 2948 itd->itd.itd_ctl[i] = htole32(trans_status); 2949 } 2950 } 2951 splx(s); 2952 2953 s = splusb(); 2954 sc->sc_softwake = 1; 2955 usb_schedsoftintr(&sc->sc_bus); 2956 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2957 splx(s); 2958 2959 #ifdef DIAGNOSTIC 2960 exfer->isdone = 1; 2961 #endif 2962 wake = exfer->ehci_xfer_flags & EHCI_XFER_ABORTING; 2963 exfer->ehci_xfer_flags &= ~(EHCI_XFER_ABORTING | EHCI_XFER_ABORTWAIT); 2964 usb_transfer_complete(xfer); 2965 if (wake) 2966 wakeup(&exfer->ehci_xfer_flags); 2967 2968 return; 2969 } 2970 2971 void 2972 ehci_timeout(void *addr) 2973 { 2974 struct ehci_xfer *exfer = addr; 2975 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 2976 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2977 2978 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 2979 #if defined(EHCI_DEBUG) && defined(USB_DEBUG) 2980 if (ehcidebug > 1) 2981 usbd_dump_pipe(exfer->xfer.pipe); 2982 #endif 2983 2984 if (sc->sc_dying) { 2985 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 2986 return; 2987 } 2988 2989 /* Execute the abort in a process context. */ 2990 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task); 2991 } 2992 2993 void 2994 ehci_timeout_task(void *addr) 2995 { 2996 usbd_xfer_handle xfer = addr; 2997 int s; 2998 2999 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3000 3001 s = splusb(); 3002 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3003 splx(s); 3004 } 3005 3006 /* 3007 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3008 * qTD status, or miss signalling occasionally under heavy load. If the host 3009 * machine is too fast, we we can miss transaction completion - when we scan 3010 * the active list the transaction still seems to be active. This generally 3011 * exhibits itself as a umass stall that never recovers. 3012 * 3013 * We work around this behaviour by setting up this callback after any softintr 3014 * that completes with transactions still pending, giving us another chance to 3015 * check for completion after the writeback has taken place. 3016 */ 3017 void 3018 ehci_intrlist_timeout(void *arg) 3019 { 3020 ehci_softc_t *sc = arg; 3021 int s = splusb(); 3022 3023 DPRINTFN(1, ("ehci_intrlist_timeout\n")); 3024 usb_schedsoftintr(&sc->sc_bus); 3025 3026 splx(s); 3027 } 3028 3029 /************************/ 3030 3031 usbd_status 3032 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3033 { 3034 usbd_status err; 3035 3036 /* Insert last in queue. */ 3037 err = usb_insert_transfer(xfer); 3038 if (err) 3039 return (err); 3040 3041 /* Pipe isn't running, start first */ 3042 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3043 } 3044 3045 usbd_status 3046 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3047 { 3048 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3049 usbd_status err; 3050 3051 if (sc->sc_dying) 3052 return (USBD_IOERROR); 3053 3054 #ifdef DIAGNOSTIC 3055 if (!(xfer->rqflags & URQ_REQUEST)) { 3056 /* XXX panic */ 3057 printf("ehci_device_ctrl_transfer: not a request\n"); 3058 return (USBD_INVAL); 3059 } 3060 #endif 3061 3062 err = ehci_device_request(xfer); 3063 if (err) 3064 return (err); 3065 3066 if (sc->sc_bus.use_polling) 3067 ehci_waitintr(sc, xfer); 3068 return (USBD_IN_PROGRESS); 3069 } 3070 3071 void 3072 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3073 { 3074 struct ehci_xfer *ex = EXFER(xfer); 3075 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3076 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 3077 3078 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3079 3080 #ifdef DIAGNOSTIC 3081 if (!(xfer->rqflags & URQ_REQUEST)) { 3082 panic("ehci_ctrl_done: not a request"); 3083 } 3084 #endif 3085 3086 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3087 ehci_del_intr_list(sc, ex); /* remove from active list */ 3088 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3089 } 3090 3091 DPRINTFN(5, ("ehci_ctrl_done: length=%u\n", xfer->actlen)); 3092 } 3093 3094 /* Abort a device control request. */ 3095 void 3096 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3097 { 3098 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3099 ehci_abort_xfer(xfer, USBD_CANCELLED); 3100 } 3101 3102 /* Close a device control pipe. */ 3103 void 3104 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3105 { 3106 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3107 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3108 3109 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3110 ehci_close_pipe(pipe, sc->sc_async_head); 3111 } 3112 3113 usbd_status 3114 ehci_device_request(usbd_xfer_handle xfer) 3115 { 3116 #define exfer EXFER(xfer) 3117 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3118 usb_device_request_t *req = &xfer->request; 3119 usbd_device_handle dev = epipe->pipe.device; 3120 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3121 int addr = dev->address; 3122 ehci_soft_qtd_t *setup, *stat, *next; 3123 ehci_soft_qh_t *sqh; 3124 int isread; 3125 u_int len; 3126 usbd_status err; 3127 int s; 3128 3129 isread = req->bmRequestType & UT_READ; 3130 len = UGETW(req->wLength); 3131 3132 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3133 "wValue=0x%04x, wIndex=0x%04x len=%u, addr=%d, endpt=%d\n", 3134 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3135 UGETW(req->wIndex), len, addr, 3136 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3137 3138 setup = ehci_alloc_sqtd(sc); 3139 if (setup == NULL) { 3140 err = USBD_NOMEM; 3141 goto bad1; 3142 } 3143 stat = ehci_alloc_sqtd(sc); 3144 if (stat == NULL) { 3145 err = USBD_NOMEM; 3146 goto bad2; 3147 } 3148 3149 sqh = epipe->sqh; 3150 epipe->u.ctl.length = len; 3151 3152 /* Update device address and length since they may have changed 3153 during the setup of the control pipe in usbd_new_device(). */ 3154 /* XXX This only needs to be done once, but it's too early in open. */ 3155 /* XXXX Should not touch ED here! */ 3156 sqh->qh.qh_endp = 3157 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3158 htole32( 3159 EHCI_QH_SET_ADDR(addr) | 3160 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3161 ); 3162 3163 /* Set up data transaction */ 3164 if (len != 0) { 3165 ehci_soft_qtd_t *end; 3166 3167 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3168 &next, &end); 3169 if (err) 3170 goto bad3; 3171 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3172 end->nextqtd = stat; 3173 end->qtd.qtd_next = 3174 end->qtd.qtd_altnext = htole32(stat->physaddr); 3175 } else { 3176 next = stat; 3177 } 3178 3179 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 3180 3181 /* Clear toggle */ 3182 setup->qtd.qtd_status = htole32( 3183 EHCI_QTD_ACTIVE | 3184 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3185 EHCI_QTD_SET_CERR(3) | 3186 EHCI_QTD_SET_TOGGLE(0) | 3187 EHCI_QTD_SET_BYTES(sizeof(*req))); 3188 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3189 setup->qtd.qtd_buffer_hi[0] = 0; 3190 setup->nextqtd = next; 3191 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3192 setup->xfer = xfer; 3193 setup->len = sizeof(*req); 3194 3195 stat->qtd.qtd_status = htole32( 3196 EHCI_QTD_ACTIVE | 3197 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3198 EHCI_QTD_SET_CERR(3) | 3199 EHCI_QTD_SET_TOGGLE(1) | 3200 EHCI_QTD_IOC); 3201 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3202 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3203 stat->nextqtd = NULL; 3204 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3205 stat->xfer = xfer; 3206 stat->len = 0; 3207 3208 #ifdef EHCI_DEBUG 3209 if (ehcidebug > 5) { 3210 DPRINTF(("ehci_device_request:\n")); 3211 ehci_dump_sqh(sqh); 3212 ehci_dump_sqtds(setup); 3213 } 3214 #endif 3215 3216 exfer->sqtdstart = setup; 3217 exfer->sqtdend = stat; 3218 #ifdef DIAGNOSTIC 3219 if (!exfer->isdone) { 3220 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3221 } 3222 exfer->isdone = 0; 3223 #endif 3224 3225 /* Insert qTD in QH list. */ 3226 s = splusb(); 3227 ehci_set_qh_qtd(sqh, setup); 3228 if (xfer->timeout && !sc->sc_bus.use_polling) { 3229 timeout_del(&xfer->timeout_handle); 3230 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3231 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3232 } 3233 ehci_add_intr_list(sc, exfer); 3234 xfer->status = USBD_IN_PROGRESS; 3235 splx(s); 3236 3237 #ifdef EHCI_DEBUG 3238 if (ehcidebug > 10) { 3239 DPRINTF(("ehci_device_request: status=%x\n", 3240 EOREAD4(sc, EHCI_USBSTS))); 3241 delay(10000); 3242 ehci_dump_regs(sc); 3243 ehci_dump_sqh(sc->sc_async_head); 3244 ehci_dump_sqh(sqh); 3245 ehci_dump_sqtds(setup); 3246 } 3247 #endif 3248 3249 return (USBD_NORMAL_COMPLETION); 3250 3251 bad3: 3252 ehci_free_sqtd(sc, stat); 3253 bad2: 3254 ehci_free_sqtd(sc, setup); 3255 bad1: 3256 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3257 xfer->status = err; 3258 usb_transfer_complete(xfer); 3259 return (err); 3260 #undef exfer 3261 } 3262 3263 /************************/ 3264 3265 usbd_status 3266 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3267 { 3268 usbd_status err; 3269 3270 /* Insert last in queue. */ 3271 err = usb_insert_transfer(xfer); 3272 if (err) 3273 return (err); 3274 3275 /* Pipe isn't running, start first */ 3276 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3277 } 3278 3279 usbd_status 3280 ehci_device_bulk_start(usbd_xfer_handle xfer) 3281 { 3282 #define exfer EXFER(xfer) 3283 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3284 usbd_device_handle dev = epipe->pipe.device; 3285 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3286 ehci_soft_qtd_t *data, *dataend; 3287 ehci_soft_qh_t *sqh; 3288 usbd_status err; 3289 u_int len; 3290 int isread, endpt; 3291 int s; 3292 3293 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%u flags=%d\n", 3294 xfer, xfer->length, xfer->flags)); 3295 3296 if (sc->sc_dying) 3297 return (USBD_IOERROR); 3298 3299 #ifdef DIAGNOSTIC 3300 if (xfer->rqflags & URQ_REQUEST) 3301 panic("ehci_device_bulk_start: a request"); 3302 #endif 3303 3304 len = xfer->length; 3305 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3306 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3307 sqh = epipe->sqh; 3308 3309 epipe->u.bulk.length = len; 3310 3311 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3312 &dataend); 3313 if (err) { 3314 DPRINTFN(-1,("ehci_device_bulk_start: no memory\n")); 3315 xfer->status = err; 3316 usb_transfer_complete(xfer); 3317 return (err); 3318 } 3319 3320 #ifdef EHCI_DEBUG 3321 if (ehcidebug > 5) { 3322 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3323 ehci_dump_sqh(sqh); 3324 ehci_dump_sqtds(data); 3325 } 3326 #endif 3327 3328 /* Set up interrupt info. */ 3329 exfer->sqtdstart = data; 3330 exfer->sqtdend = dataend; 3331 #ifdef DIAGNOSTIC 3332 if (!exfer->isdone) { 3333 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3334 } 3335 exfer->isdone = 0; 3336 #endif 3337 3338 s = splusb(); 3339 ehci_set_qh_qtd(sqh, data); 3340 if (xfer->timeout && !sc->sc_bus.use_polling) { 3341 timeout_del(&xfer->timeout_handle); 3342 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3343 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3344 } 3345 ehci_add_intr_list(sc, exfer); 3346 xfer->status = USBD_IN_PROGRESS; 3347 splx(s); 3348 3349 #ifdef EHCI_DEBUG 3350 if (ehcidebug > 10) { 3351 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3352 delay(10000); 3353 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3354 ehci_dump_regs(sc); 3355 #if 0 3356 printf("async_head:\n"); 3357 ehci_dump_sqh(sc->sc_async_head); 3358 #endif 3359 printf("sqh:\n"); 3360 ehci_dump_sqh(sqh); 3361 ehci_dump_sqtds(data); 3362 } 3363 #endif 3364 3365 if (sc->sc_bus.use_polling) 3366 ehci_waitintr(sc, xfer); 3367 3368 return (USBD_IN_PROGRESS); 3369 #undef exfer 3370 } 3371 3372 void 3373 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3374 { 3375 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3376 ehci_abort_xfer(xfer, USBD_CANCELLED); 3377 } 3378 3379 /* 3380 * Close a device bulk pipe. 3381 */ 3382 void 3383 ehci_device_bulk_close(usbd_pipe_handle pipe) 3384 { 3385 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3386 3387 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3388 ehci_close_pipe(pipe, sc->sc_async_head); 3389 } 3390 3391 void 3392 ehci_device_bulk_done(usbd_xfer_handle xfer) 3393 { 3394 struct ehci_xfer *ex = EXFER(xfer); 3395 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3396 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 3397 3398 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3399 xfer, xfer->actlen)); 3400 3401 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3402 ehci_del_intr_list(sc, ex); /* remove from active list */ 3403 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3404 } 3405 3406 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3407 } 3408 3409 /************************/ 3410 3411 usbd_status 3412 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3413 { 3414 struct ehci_soft_islot *isp; 3415 int islot, lev; 3416 3417 /* Find a poll rate that is large enough. */ 3418 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3419 if (EHCI_ILEV_IVAL(lev) <= ival) 3420 break; 3421 3422 /* Pick an interrupt slot at the right level. */ 3423 /* XXX could do better than picking at random */ 3424 if (cold) { 3425 /* XXX prevent panics at boot by not using arc4random */ 3426 sc->sc_rand = (sc->sc_rand + 192) % sc->sc_flsize; 3427 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3428 } else 3429 islot = EHCI_IQHIDX(lev, arc4random()); 3430 3431 sqh->islot = islot; 3432 isp = &sc->sc_islots[islot]; 3433 ehci_add_qh(sqh, isp->sqh); 3434 3435 return (USBD_NORMAL_COMPLETION); 3436 } 3437 3438 usbd_status 3439 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3440 { 3441 usbd_status err; 3442 3443 /* Insert last in queue. */ 3444 err = usb_insert_transfer(xfer); 3445 if (err) 3446 return (err); 3447 3448 /* 3449 * Pipe isn't running (otherwise err would be USBD_INPROG), 3450 * so start it first. 3451 */ 3452 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3453 } 3454 3455 usbd_status 3456 ehci_device_intr_start(usbd_xfer_handle xfer) 3457 { 3458 #define exfer EXFER(xfer) 3459 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3460 usbd_device_handle dev = xfer->pipe->device; 3461 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3462 ehci_soft_qtd_t *data, *dataend; 3463 ehci_soft_qh_t *sqh; 3464 usbd_status err; 3465 u_int len; 3466 int isread, endpt; 3467 int s; 3468 3469 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%u flags=%d\n", 3470 xfer, xfer->length, xfer->flags)); 3471 3472 if (sc->sc_dying) 3473 return (USBD_IOERROR); 3474 3475 #ifdef DIAGNOSTIC 3476 if (xfer->rqflags & URQ_REQUEST) 3477 panic("ehci_device_intr_start: a request"); 3478 #endif 3479 3480 len = xfer->length; 3481 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3482 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3483 sqh = epipe->sqh; 3484 3485 epipe->u.intr.length = len; 3486 3487 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3488 &dataend); 3489 if (err) { 3490 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3491 xfer->status = err; 3492 usb_transfer_complete(xfer); 3493 return (err); 3494 } 3495 3496 #ifdef EHCI_DEBUG 3497 if (ehcidebug > 5) { 3498 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3499 ehci_dump_sqh(sqh); 3500 ehci_dump_sqtds(data); 3501 } 3502 #endif 3503 3504 /* Set up interrupt info. */ 3505 exfer->sqtdstart = data; 3506 exfer->sqtdend = dataend; 3507 #ifdef DIAGNOSTIC 3508 if (!exfer->isdone) 3509 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3510 exfer->isdone = 0; 3511 #endif 3512 3513 s = splusb(); 3514 ehci_set_qh_qtd(sqh, data); 3515 if (xfer->timeout && !sc->sc_bus.use_polling) { 3516 timeout_del(&xfer->timeout_handle); 3517 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3518 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3519 } 3520 ehci_add_intr_list(sc, exfer); 3521 xfer->status = USBD_IN_PROGRESS; 3522 splx(s); 3523 3524 #ifdef EHCI_DEBUG 3525 if (ehcidebug > 10) { 3526 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3527 delay(10000); 3528 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3529 ehci_dump_regs(sc); 3530 printf("sqh:\n"); 3531 ehci_dump_sqh(sqh); 3532 ehci_dump_sqtds(data); 3533 } 3534 #endif 3535 3536 if (sc->sc_bus.use_polling) 3537 ehci_waitintr(sc, xfer); 3538 3539 return (USBD_IN_PROGRESS); 3540 #undef exfer 3541 } 3542 3543 void 3544 ehci_device_intr_abort(usbd_xfer_handle xfer) 3545 { 3546 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3547 if (xfer->pipe->intrxfer == xfer) { 3548 DPRINTFN(1, ("ehci_device_intr_abort: remove\n")); 3549 xfer->pipe->intrxfer = NULL; 3550 } 3551 /* 3552 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3553 * async doorbell. That's dependant on the async list, wheras 3554 * intr xfers are periodic, should not use this? 3555 */ 3556 ehci_abort_xfer(xfer, USBD_CANCELLED); 3557 } 3558 3559 void 3560 ehci_device_intr_close(usbd_pipe_handle pipe) 3561 { 3562 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3563 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3564 struct ehci_soft_islot *isp; 3565 3566 isp = &sc->sc_islots[epipe->sqh->islot]; 3567 ehci_close_pipe(pipe, isp->sqh); 3568 } 3569 3570 void 3571 ehci_device_intr_done(usbd_xfer_handle xfer) 3572 { 3573 #define exfer EXFER(xfer) 3574 struct ehci_xfer *ex = EXFER(xfer); 3575 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3576 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3577 ehci_soft_qtd_t *data, *dataend; 3578 ehci_soft_qh_t *sqh; 3579 usbd_status err; 3580 u_int len; 3581 int isread, endpt, s; 3582 3583 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3584 xfer, xfer->actlen)); 3585 3586 if (xfer->pipe->repeat) { 3587 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3588 3589 len = epipe->u.intr.length; 3590 xfer->length = len; 3591 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3592 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3593 sqh = epipe->sqh; 3594 3595 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3596 &data, &dataend); 3597 if (err) { 3598 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3599 xfer->status = err; 3600 return; 3601 } 3602 3603 /* Set up interrupt info. */ 3604 exfer->sqtdstart = data; 3605 exfer->sqtdend = dataend; 3606 #ifdef DIAGNOSTIC 3607 if (!exfer->isdone) { 3608 printf("ehci_device_intr_done: not done, ex=%p\n", 3609 exfer); 3610 } 3611 exfer->isdone = 0; 3612 #endif 3613 3614 s = splusb(); 3615 ehci_set_qh_qtd(sqh, data); 3616 if (xfer->timeout && !sc->sc_bus.use_polling) { 3617 timeout_del(&xfer->timeout_handle); 3618 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3619 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3620 } 3621 splx(s); 3622 3623 xfer->status = USBD_IN_PROGRESS; 3624 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3625 ehci_del_intr_list(sc, ex); /* remove from active list */ 3626 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3627 } 3628 #undef exfer 3629 } 3630 3631 /************************/ 3632 3633 usbd_status 3634 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3635 { 3636 usbd_status err; 3637 3638 err = usb_insert_transfer(xfer); 3639 if (err && err != USBD_IN_PROGRESS) 3640 return (err); 3641 3642 return (ehci_device_isoc_start(xfer)); 3643 } 3644 3645 usbd_status 3646 ehci_device_isoc_start(usbd_xfer_handle xfer) 3647 { 3648 struct ehci_pipe *epipe; 3649 ehci_softc_t *sc; 3650 struct ehci_xfer *exfer; 3651 ehci_soft_itd_t *itd, *prev, *start, *stop; 3652 usb_dma_t *dma_buf; 3653 int i, j, k, frames, uframes, ufrperframe; 3654 int s, trans_count, offs, total_length; 3655 int frindex; 3656 3657 start = NULL; 3658 prev = NULL; 3659 itd = NULL; 3660 trans_count = 0; 3661 total_length = 0; 3662 exfer = (struct ehci_xfer *) xfer; 3663 sc = (ehci_softc_t *)xfer->pipe->device->bus; 3664 epipe = (struct ehci_pipe *)xfer->pipe; 3665 3666 /* 3667 * To allow continuous transfers, above we start all transfers 3668 * immediately. However, we're still going to get usbd_start_next call 3669 * this when another xfer completes. So, check if this is already 3670 * in progress or not 3671 */ 3672 3673 if (exfer->itdstart != NULL) 3674 return (USBD_IN_PROGRESS); 3675 3676 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %u flags %d\n", 3677 xfer, xfer->length, xfer->flags)); 3678 3679 if (sc->sc_dying) 3680 return (USBD_IOERROR); 3681 3682 /* 3683 * To avoid complication, don't allow a request right now that'll span 3684 * the entire frame table. To within 4 frames, to allow some leeway 3685 * on either side of where the hc currently is. 3686 */ 3687 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3688 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3689 printf("ehci: isoc descriptor requested that spans the entire " 3690 "frametable, too many frames\n"); 3691 return (USBD_INVAL); 3692 } 3693 3694 #ifdef DIAGNOSTIC 3695 if (xfer->rqflags & URQ_REQUEST) 3696 panic("ehci_device_isoc_start: request"); 3697 3698 if (!exfer->isdone) 3699 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3700 exfer->isdone = 0; 3701 #endif 3702 3703 /* 3704 * Step 1: Allocate and initialize itds, how many do we need? 3705 * One per transfer if interval >= 8 microframes, fewer if we use 3706 * multiple microframes per frame. 3707 */ 3708 3709 i = epipe->pipe.endpoint->edesc->bInterval; 3710 if (i > 16 || i == 0) { 3711 /* Spec page 271 says intervals > 16 are invalid */ 3712 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3713 return (USBD_INVAL); 3714 } 3715 3716 switch (i) { 3717 case 1: 3718 ufrperframe = 8; 3719 break; 3720 case 2: 3721 ufrperframe = 4; 3722 break; 3723 case 3: 3724 ufrperframe = 2; 3725 break; 3726 default: 3727 ufrperframe = 1; 3728 break; 3729 } 3730 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3731 uframes = 8 / ufrperframe; 3732 3733 if (frames == 0) { 3734 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3735 return (USBD_INVAL); 3736 } 3737 3738 dma_buf = &xfer->dmabuf; 3739 offs = 0; 3740 3741 for (i = 0; i < frames; i++) { 3742 int froffs = offs; 3743 itd = ehci_alloc_itd(sc); 3744 3745 if (prev != NULL) { 3746 prev->itd.itd_next = 3747 htole32(itd->physaddr | EHCI_LINK_ITD); 3748 prev->xfer_next = itd; 3749 } else { 3750 start = itd; 3751 } 3752 3753 /* 3754 * Step 1.5, initialize uframes 3755 */ 3756 for (j = 0; j < 8; j += uframes) { 3757 /* Calculate which page in the list this starts in */ 3758 int addr = DMAADDR(dma_buf, froffs); 3759 addr = EHCI_PAGE_OFFSET(addr); 3760 addr += (offs - froffs); 3761 addr = EHCI_PAGE(addr); 3762 addr /= EHCI_PAGE_SIZE; 3763 3764 /* This gets the initial offset into the first page, 3765 * looks how far further along the current uframe 3766 * offset is. Works out how many pages that is. 3767 */ 3768 3769 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3770 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3771 EHCI_ITD_SET_PG(addr) | 3772 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf, 3773 offs)))); 3774 3775 total_length += xfer->frlengths[trans_count]; 3776 offs += xfer->frlengths[trans_count]; 3777 trans_count++; 3778 3779 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3780 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3781 break; 3782 } 3783 } 3784 3785 /* Step 1.75, set buffer pointers. To simplify matters, all 3786 * pointers are filled out for the next 7 hardware pages in 3787 * the dma block, so no need to worry what pages to cover 3788 * and what to not. 3789 */ 3790 3791 for (j=0; j < 7; j++) { 3792 /* 3793 * Don't try to lookup a page that's past the end 3794 * of buffer 3795 */ 3796 int page_offs = EHCI_PAGE(froffs + 3797 (EHCI_PAGE_SIZE * j)); 3798 3799 if (page_offs >= dma_buf->block->size) 3800 break; 3801 3802 long long page = DMAADDR(dma_buf, page_offs); 3803 page = EHCI_PAGE(page); 3804 itd->itd.itd_bufr[j] = 3805 htole32(EHCI_ITD_SET_BPTR(page)); 3806 itd->itd.itd_bufr_hi[j] = 3807 htole32(page >> 32); 3808 } 3809 3810 /* 3811 * Other special values 3812 */ 3813 3814 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3815 itd->itd.itd_bufr[0] |= 3816 htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3817 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3818 3819 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3820 ? 1 : 0; 3821 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3822 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3823 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3824 3825 /* FIXME: handle invalid trans */ 3826 itd->itd.itd_bufr[2] |= 3827 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3828 prev = itd; 3829 } /* End of frame */ 3830 3831 stop = itd; 3832 stop->xfer_next = NULL; 3833 exfer->isoc_len = total_length; 3834 3835 /* 3836 * Part 2: Transfer descriptors have now been set up, now they must 3837 * be scheduled into the period frame list. Erk. Not wanting to 3838 * complicate matters, transfer is denied if the transfer spans 3839 * more than the period frame list. 3840 */ 3841 3842 s = splusb(); 3843 3844 /* Start inserting frames */ 3845 if (epipe->u.isoc.cur_xfers > 0) { 3846 frindex = epipe->u.isoc.next_frame; 3847 } else { 3848 frindex = EOREAD4(sc, EHCI_FRINDEX); 3849 frindex = frindex >> 3; /* Erase microframe index */ 3850 frindex += 2; 3851 } 3852 3853 if (frindex >= sc->sc_flsize) 3854 frindex &= (sc->sc_flsize - 1); 3855 3856 /* Whats the frame interval? */ 3857 i = (1 << epipe->pipe.endpoint->edesc->bInterval); 3858 if (i / 8 == 0) 3859 i = 1; 3860 else 3861 i /= 8; 3862 3863 itd = start; 3864 for (j = 0; j < frames; j++) { 3865 if (itd == NULL) 3866 panic("ehci: unexpectedly ran out of isoc itds, " 3867 "isoc_start"); 3868 3869 itd->itd.itd_next = sc->sc_flist[frindex]; 3870 if (itd->itd.itd_next == 0) 3871 /* FIXME: frindex table gets initialized to NULL 3872 * or EHCI_NULL? */ 3873 itd->itd.itd_next = htole32(EHCI_NULL); 3874 3875 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 3876 itd->u.frame_list.next = sc->sc_softitds[frindex]; 3877 sc->sc_softitds[frindex] = itd; 3878 if (itd->u.frame_list.next != NULL) 3879 itd->u.frame_list.next->u.frame_list.prev = itd; 3880 itd->slot = frindex; 3881 itd->u.frame_list.prev = NULL; 3882 3883 frindex += i; 3884 if (frindex >= sc->sc_flsize) 3885 frindex -= sc->sc_flsize; 3886 3887 itd = itd->xfer_next; 3888 } 3889 3890 epipe->u.isoc.cur_xfers++; 3891 epipe->u.isoc.next_frame = frindex; 3892 3893 exfer->itdstart = start; 3894 exfer->itdend = stop; 3895 exfer->sqtdstart = NULL; 3896 exfer->sqtdstart = NULL; 3897 3898 ehci_add_intr_list(sc, exfer); 3899 xfer->status = USBD_IN_PROGRESS; 3900 xfer->done = 0; 3901 splx(s); 3902 3903 if (sc->sc_bus.use_polling) { 3904 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 3905 ehci_waitintr(sc, xfer); 3906 } 3907 3908 return (USBD_IN_PROGRESS); 3909 } 3910 3911 void 3912 ehci_device_isoc_abort(usbd_xfer_handle xfer) 3913 { 3914 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 3915 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 3916 } 3917 3918 void 3919 ehci_device_isoc_close(usbd_pipe_handle pipe) 3920 { 3921 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 3922 } 3923 3924 void 3925 ehci_device_isoc_done(usbd_xfer_handle xfer) 3926 { 3927 struct ehci_xfer *exfer; 3928 ehci_softc_t *sc; 3929 struct ehci_pipe *epipe; 3930 int s; 3931 3932 exfer = EXFER(xfer); 3933 sc = (ehci_softc_t *)xfer->pipe->device->bus; 3934 epipe = (struct ehci_pipe *) xfer->pipe; 3935 3936 s = splusb(); 3937 epipe->u.isoc.cur_xfers--; 3938 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 3939 ehci_del_intr_list(sc, exfer); 3940 ehci_rem_free_itd_chain(sc, exfer); 3941 } 3942 splx(s); 3943 } 3944