1 /* $OpenBSD: ehci.c,v 1.124 2012/07/07 12:54:04 mpi Exp $ */ 2 /* $NetBSD: ehci.c,v 1.66 2004/06/30 03:11:56 mycroft Exp $ */ 3 4 /* 5 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and 10 * Jeremy Morse (jeremy.morse@gmail.com). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/usb_20.zip 41 */ 42 43 /* 44 * TODO: 45 * 1) The hub driver needs to handle and schedule the transaction translator, 46 * to assign place in frame where different devices get to go. See chapter 47 * on hubs in USB 2.0 for details. 48 * 49 * 2) Command failures are not recovered correctly. 50 */ 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/rwlock.h> 56 #include <sys/malloc.h> 57 #include <sys/device.h> 58 #include <sys/selinfo.h> 59 #include <sys/proc.h> 60 #include <sys/queue.h> 61 #include <sys/timeout.h> 62 63 #include <machine/bus.h> 64 #include <machine/endian.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 #include <dev/usb/usbdivar.h> 69 #include <dev/usb/usb_mem.h> 70 #include <dev/usb/usb_quirks.h> 71 72 #include <dev/usb/ehcireg.h> 73 #include <dev/usb/ehcivar.h> 74 75 #include <dev/rndvar.h> 76 77 struct cfdriver ehci_cd = { 78 NULL, "ehci", DV_DULL 79 }; 80 81 #ifdef EHCI_DEBUG 82 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 83 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 84 int ehcidebug = 0; 85 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n,x) 89 #endif 90 91 #define mstohz(ms) ((ms) * hz / 1000) 92 93 struct ehci_pipe { 94 struct usbd_pipe pipe; 95 96 ehci_soft_qh_t *sqh; 97 union { 98 ehci_soft_qtd_t *qtd; 99 /* ehci_soft_itd_t *itd; */ 100 } tail; 101 union { 102 /* Control pipe */ 103 struct { 104 usb_dma_t reqdma; 105 u_int length; 106 /*ehci_soft_qtd_t *setup, *data, *stat;*/ 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 u_int length; 111 } intr; 112 /* Bulk pipe */ 113 struct { 114 u_int length; 115 } bulk; 116 /* Iso pipe */ 117 struct { 118 u_int next_frame; 119 u_int cur_xfers; 120 } isoc; 121 } u; 122 }; 123 124 u_int8_t ehci_reverse_bits(u_int8_t, int); 125 126 usbd_status ehci_open(usbd_pipe_handle); 127 void ehci_poll(struct usbd_bus *); 128 void ehci_softintr(void *); 129 int ehci_intr1(ehci_softc_t *); 130 void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 131 void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 132 void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 133 void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 134 void ehci_idone(struct ehci_xfer *); 135 void ehci_timeout(void *); 136 void ehci_timeout_task(void *); 137 void ehci_intrlist_timeout(void *); 138 139 usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 140 void ehci_freem(struct usbd_bus *, usb_dma_t *); 141 142 usbd_xfer_handle ehci_allocx(struct usbd_bus *); 143 void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 144 145 usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 146 usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 147 void ehci_root_ctrl_abort(usbd_xfer_handle); 148 void ehci_root_ctrl_close(usbd_pipe_handle); 149 void ehci_root_ctrl_done(usbd_xfer_handle); 150 151 usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 152 usbd_status ehci_root_intr_start(usbd_xfer_handle); 153 void ehci_root_intr_abort(usbd_xfer_handle); 154 void ehci_root_intr_close(usbd_pipe_handle); 155 void ehci_root_intr_done(usbd_xfer_handle); 156 157 usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 158 usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 159 void ehci_device_ctrl_abort(usbd_xfer_handle); 160 void ehci_device_ctrl_close(usbd_pipe_handle); 161 void ehci_device_ctrl_done(usbd_xfer_handle); 162 163 usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 164 usbd_status ehci_device_bulk_start(usbd_xfer_handle); 165 void ehci_device_bulk_abort(usbd_xfer_handle); 166 void ehci_device_bulk_close(usbd_pipe_handle); 167 void ehci_device_bulk_done(usbd_xfer_handle); 168 169 usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 170 usbd_status ehci_device_intr_start(usbd_xfer_handle); 171 void ehci_device_intr_abort(usbd_xfer_handle); 172 void ehci_device_intr_close(usbd_pipe_handle); 173 void ehci_device_intr_done(usbd_xfer_handle); 174 175 usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 176 usbd_status ehci_device_isoc_start(usbd_xfer_handle); 177 void ehci_device_isoc_abort(usbd_xfer_handle); 178 void ehci_device_isoc_close(usbd_pipe_handle); 179 void ehci_device_isoc_done(usbd_xfer_handle); 180 181 void ehci_device_clear_toggle(usbd_pipe_handle pipe); 182 void ehci_noop(usbd_pipe_handle pipe); 183 184 int ehci_str(usb_string_descriptor_t *, int, const char *); 185 void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 186 void ehci_disown(ehci_softc_t *, int, int); 187 188 ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 189 void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 190 191 ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 192 void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 193 usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 194 ehci_softc_t *, u_int, int, usbd_xfer_handle, 195 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 196 void ehci_free_sqtd_chain(ehci_softc_t *, struct ehci_xfer *exfer); 197 198 ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 199 void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 200 void ehci_rem_free_itd_chain(ehci_softc_t *sc, 201 struct ehci_xfer *exfer); 202 void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 203 usbd_status status); 204 205 usbd_status ehci_device_request(usbd_xfer_handle xfer); 206 207 usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 208 int ival); 209 210 void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 211 void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *); 212 void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 213 void ehci_sync_hc(ehci_softc_t *); 214 215 void ehci_close_pipe(usbd_pipe_handle); 216 void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 217 218 #ifdef EHCI_DEBUG 219 void ehci_dump_regs(ehci_softc_t *); 220 void ehci_dump(void); 221 ehci_softc_t *theehci; 222 void ehci_dump_link(ehci_link_t, int); 223 void ehci_dump_sqtds(ehci_soft_qtd_t *); 224 void ehci_dump_sqtd(ehci_soft_qtd_t *); 225 void ehci_dump_qtd(ehci_qtd_t *); 226 void ehci_dump_sqh(ehci_soft_qh_t *); 227 #if notyet 228 void ehci_dump_sitd(struct ehci_soft_itd *itd); 229 void ehci_dump_itd(struct ehci_soft_itd *); 230 #endif 231 #ifdef DIAGNOSTIC 232 void ehci_dump_exfer(struct ehci_xfer *); 233 #endif 234 #endif 235 236 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 237 238 #define EHCI_INTR_ENDPT 1 239 240 #define ehci_add_intr_list(sc, ex) \ 241 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 242 #define ehci_del_intr_list(sc, ex) \ 243 do { \ 244 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 245 (ex)->inext.tqe_prev = NULL; \ 246 } while (0) 247 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 248 249 struct usbd_bus_methods ehci_bus_methods = { 250 ehci_open, 251 ehci_softintr, 252 ehci_poll, 253 ehci_allocm, 254 ehci_freem, 255 ehci_allocx, 256 ehci_freex, 257 }; 258 259 struct usbd_pipe_methods ehci_root_ctrl_methods = { 260 ehci_root_ctrl_transfer, 261 ehci_root_ctrl_start, 262 ehci_root_ctrl_abort, 263 ehci_root_ctrl_close, 264 ehci_noop, 265 ehci_root_ctrl_done, 266 }; 267 268 struct usbd_pipe_methods ehci_root_intr_methods = { 269 ehci_root_intr_transfer, 270 ehci_root_intr_start, 271 ehci_root_intr_abort, 272 ehci_root_intr_close, 273 ehci_noop, 274 ehci_root_intr_done, 275 }; 276 277 struct usbd_pipe_methods ehci_device_ctrl_methods = { 278 ehci_device_ctrl_transfer, 279 ehci_device_ctrl_start, 280 ehci_device_ctrl_abort, 281 ehci_device_ctrl_close, 282 ehci_noop, 283 ehci_device_ctrl_done, 284 }; 285 286 struct usbd_pipe_methods ehci_device_intr_methods = { 287 ehci_device_intr_transfer, 288 ehci_device_intr_start, 289 ehci_device_intr_abort, 290 ehci_device_intr_close, 291 ehci_device_clear_toggle, 292 ehci_device_intr_done, 293 }; 294 295 struct usbd_pipe_methods ehci_device_bulk_methods = { 296 ehci_device_bulk_transfer, 297 ehci_device_bulk_start, 298 ehci_device_bulk_abort, 299 ehci_device_bulk_close, 300 ehci_device_clear_toggle, 301 ehci_device_bulk_done, 302 }; 303 304 struct usbd_pipe_methods ehci_device_isoc_methods = { 305 ehci_device_isoc_transfer, 306 ehci_device_isoc_start, 307 ehci_device_isoc_abort, 308 ehci_device_isoc_close, 309 ehci_noop, 310 ehci_device_isoc_done, 311 }; 312 313 /* 314 * Reverse a number with nbits bits. Used to evenly distribute lower-level 315 * interrupt heads in the periodic schedule. 316 * Suitable for use with EHCI_IPOLLRATES <= 9. 317 */ 318 u_int8_t 319 ehci_reverse_bits(u_int8_t c, int nbits) 320 { 321 c = ((c >> 1) & 0x55) | ((c << 1) & 0xaa); 322 c = ((c >> 2) & 0x33) | ((c << 2) & 0xcc); 323 c = ((c >> 4) & 0x0f) | ((c << 4) & 0xf0); 324 325 return c >> (8 - nbits); 326 } 327 328 usbd_status 329 ehci_init(ehci_softc_t *sc) 330 { 331 u_int32_t sparams, cparams, hcr; 332 u_int i, j; 333 usbd_status err; 334 ehci_soft_qh_t *sqh; 335 336 #ifdef EHCI_DEBUG 337 u_int32_t vers; 338 theehci = sc; 339 340 DPRINTF(("ehci_init: start\n")); 341 342 vers = EREAD2(sc, EHCI_HCIVERSION); 343 DPRINTF(("%s: EHCI version %x.%x\n", sc->sc_bus.bdev.dv_xname, 344 vers >> 8, vers & 0xff)); 345 #endif 346 347 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 348 349 sparams = EREAD4(sc, EHCI_HCSPARAMS); 350 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 351 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 352 cparams = EREAD4(sc, EHCI_HCCPARAMS); 353 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 354 355 /* MUST clear segment register if 64 bit capable. */ 356 if (EHCI_HCC_64BIT(cparams)) 357 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 358 359 sc->sc_bus.usbrev = USBREV_2_0; 360 361 /* Reset the controller */ 362 DPRINTF(("%s: resetting\n", sc->sc_bus.bdev.dv_xname)); 363 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 364 usb_delay_ms(&sc->sc_bus, 1); 365 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 366 for (i = 0; i < 100; i++) { 367 usb_delay_ms(&sc->sc_bus, 1); 368 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 369 if (!hcr) 370 break; 371 } 372 if (hcr) { 373 printf("%s: reset timeout\n", 374 sc->sc_bus.bdev.dv_xname); 375 return (USBD_IOERROR); 376 } 377 378 /* XXX need proper intr scheduling */ 379 sc->sc_rand = 96; 380 381 /* frame list size at default, read back what we got and use that */ 382 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 383 case 0: 384 sc->sc_flsize = 1024; 385 break; 386 case 1: 387 sc->sc_flsize = 512; 388 break; 389 case 2: 390 sc->sc_flsize = 256; 391 break; 392 case 3: 393 return (USBD_IOERROR); 394 } 395 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 396 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 397 if (err) 398 return (err); 399 DPRINTF(("%s: flsize=%d\n", sc->sc_bus.bdev.dv_xname,sc->sc_flsize)); 400 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 401 402 for (i = 0; i < sc->sc_flsize; i++) 403 sc->sc_flist[i] = EHCI_NULL; 404 405 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 406 407 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 408 M_USB, M_NOWAIT | M_ZERO); 409 if (sc->sc_softitds == NULL) 410 return (ENOMEM); 411 LIST_INIT(&sc->sc_freeitds); 412 TAILQ_INIT(&sc->sc_intrhead); 413 414 /* Set up the bus struct. */ 415 sc->sc_bus.methods = &ehci_bus_methods; 416 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 417 418 sc->sc_eintrs = EHCI_NORMAL_INTRS; 419 420 /* 421 * Allocate the interrupt dummy QHs. These are arranged to give poll 422 * intervals that are powers of 2 times 1ms. 423 */ 424 for (i = 0; i < EHCI_INTRQHS; i++) { 425 sqh = ehci_alloc_sqh(sc); 426 if (sqh == NULL) { 427 err = USBD_NOMEM; 428 goto bad1; 429 } 430 sc->sc_islots[i].sqh = sqh; 431 } 432 for (i = 0; i < EHCI_INTRQHS; i++) { 433 sqh = sc->sc_islots[i].sqh; 434 if (i == 0) { 435 /* The last (1ms) QH terminates. */ 436 sqh->qh.qh_link = EHCI_NULL; 437 sqh->next = NULL; 438 } else { 439 /* Otherwise the next QH has half the poll interval */ 440 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 441 sqh->qh.qh_link = htole32(sqh->next->physaddr | 442 EHCI_LINK_QH); 443 } 444 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 445 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 446 sqh->qh.qh_curqtd = EHCI_NULL; 447 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 448 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 449 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 450 sqh->sqtd = NULL; 451 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 452 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 453 } 454 /* Point the frame list at the last level (128ms). */ 455 for (i = 0; i < (1 << (EHCI_IPOLLRATES - 1)); i++) 456 for (j = i; j < sc->sc_flsize; j += 1 << (EHCI_IPOLLRATES - 1)) 457 sc->sc_flist[j] = htole32(EHCI_LINK_QH | sc->sc_islots[ 458 EHCI_IQHIDX(EHCI_IPOLLRATES - 1, ehci_reverse_bits( 459 i, EHCI_IPOLLRATES - 1))].sqh->physaddr); 460 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 461 BUS_DMASYNC_PREWRITE); 462 463 /* Allocate dummy QH that starts the async list. */ 464 sqh = ehci_alloc_sqh(sc); 465 if (sqh == NULL) { 466 err = USBD_NOMEM; 467 goto bad1; 468 } 469 /* Fill the QH */ 470 sqh->qh.qh_endp = 471 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 472 sqh->qh.qh_link = 473 htole32(sqh->physaddr | EHCI_LINK_QH); 474 sqh->qh.qh_curqtd = EHCI_NULL; 475 sqh->prev = sqh; /*It's a circular list.. */ 476 sqh->next = sqh; 477 /* Fill the overlay qTD */ 478 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 479 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 480 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 481 sqh->sqtd = NULL; 482 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 484 #ifdef EHCI_DEBUG 485 if (ehcidebug) 486 ehci_dump_sqh(sqh); 487 #endif 488 489 /* Point to async list */ 490 sc->sc_async_head = sqh; 491 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 492 493 timeout_set(&sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 494 495 rw_init(&sc->sc_doorbell_lock, "ehcidb"); 496 497 /* Turn on controller */ 498 EOWRITE4(sc, EHCI_USBCMD, 499 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 500 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 501 EHCI_CMD_ASE | 502 EHCI_CMD_PSE | 503 EHCI_CMD_RS); 504 505 /* Take over port ownership */ 506 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 507 508 for (i = 0; i < 100; i++) { 509 usb_delay_ms(&sc->sc_bus, 1); 510 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 511 if (!hcr) 512 break; 513 } 514 if (hcr) { 515 printf("%s: run timeout\n", sc->sc_bus.bdev.dv_xname); 516 return (USBD_IOERROR); 517 } 518 519 /* Enable interrupts */ 520 DPRINTFN(1,("ehci_init: enabling\n")); 521 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 522 523 return (USBD_NORMAL_COMPLETION); 524 525 #if 0 526 bad2: 527 ehci_free_sqh(sc, sc->sc_async_head); 528 #endif 529 bad1: 530 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 531 return (err); 532 } 533 534 int 535 ehci_intr(void *v) 536 { 537 ehci_softc_t *sc = v; 538 539 if (sc == NULL || sc->sc_bus.dying) 540 return (0); 541 542 /* If we get an interrupt while polling, then just ignore it. */ 543 if (sc->sc_bus.use_polling) { 544 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 545 546 if (intrs) 547 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 548 return (0); 549 } 550 551 return (ehci_intr1(sc)); 552 } 553 554 int 555 ehci_intr1(ehci_softc_t *sc) 556 { 557 u_int32_t intrs, eintrs; 558 559 DPRINTFN(20,("ehci_intr1: enter\n")); 560 561 /* In case the interrupt occurs before initialization has completed. */ 562 if (sc == NULL) { 563 #ifdef DIAGNOSTIC 564 printf("ehci_intr1: sc == NULL\n"); 565 #endif 566 return (0); 567 } 568 569 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 570 if (intrs == 0xffffffff) { 571 sc->sc_bus.dying = 1; 572 return (0); 573 } 574 if (!intrs) 575 return (0); 576 577 eintrs = intrs & sc->sc_eintrs; 578 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 579 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), (u_int)eintrs)); 580 if (!eintrs) 581 return (0); 582 583 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 584 sc->sc_bus.intr_context++; 585 sc->sc_bus.no_intrs++; 586 if (eintrs & EHCI_STS_HSE) { 587 printf("%s: unrecoverable error, controller halted\n", 588 sc->sc_bus.bdev.dv_xname); 589 sc->sc_bus.dying = 1; 590 sc->sc_bus.intr_context--; 591 return (1); 592 } 593 if (eintrs & EHCI_STS_IAA) { 594 DPRINTF(("ehci_intr1: door bell\n")); 595 wakeup(&sc->sc_async_head); 596 eintrs &= ~EHCI_STS_IAA; 597 } 598 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 599 DPRINTFN(5,("ehci_intr1: %s %s\n", 600 eintrs & EHCI_STS_INT ? "INT" : "", 601 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 602 usb_schedsoftintr(&sc->sc_bus); 603 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 604 } 605 if (eintrs & EHCI_STS_PCD) { 606 ehci_pcd(sc, sc->sc_intrxfer); 607 eintrs &= ~EHCI_STS_PCD; 608 } 609 610 sc->sc_bus.intr_context--; 611 612 if (eintrs != 0) { 613 /* Block unprocessed interrupts. */ 614 sc->sc_eintrs &= ~eintrs; 615 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 616 printf("%s: blocking intrs 0x%x\n", 617 sc->sc_bus.bdev.dv_xname, eintrs); 618 } 619 620 return (1); 621 } 622 623 void 624 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 625 { 626 u_char *p; 627 int i, m; 628 629 if (xfer == NULL) { 630 /* Just ignore the change. */ 631 return; 632 } 633 634 p = KERNADDR(&xfer->dmabuf, 0); 635 m = min(sc->sc_noport, xfer->length * 8 - 1); 636 memset(p, 0, xfer->length); 637 for (i = 1; i <= m; i++) { 638 /* Pick out CHANGE bits from the status reg. */ 639 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 640 p[i/8] |= 1 << (i%8); 641 } 642 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 643 xfer->actlen = xfer->length; 644 xfer->status = USBD_NORMAL_COMPLETION; 645 646 usb_transfer_complete(xfer); 647 } 648 649 void 650 ehci_softintr(void *v) 651 { 652 ehci_softc_t *sc = v; 653 struct ehci_xfer *ex, *nextex; 654 655 DPRINTFN(10,("%s: ehci_softintr (%d)\n", sc->sc_bus.bdev.dv_xname, 656 sc->sc_bus.intr_context)); 657 658 if (sc->sc_bus.dying) 659 return; 660 661 sc->sc_bus.intr_context++; 662 663 /* 664 * The only explanation I can think of for why EHCI is as brain dead 665 * as UHCI interrupt-wise is that Intel was involved in both. 666 * An interrupt just tells us that something is done, we have no 667 * clue what, so we need to scan through all active transfers. :-( 668 */ 669 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 670 nextex = TAILQ_NEXT(ex, inext); 671 ehci_check_intr(sc, ex); 672 } 673 674 /* Schedule a callout to catch any dropped transactions. */ 675 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 676 !TAILQ_EMPTY(&sc->sc_intrhead)) { 677 timeout_add_sec(&sc->sc_tmo_intrlist, 1); 678 } 679 680 if (sc->sc_softwake) { 681 sc->sc_softwake = 0; 682 wakeup(&sc->sc_softwake); 683 } 684 685 sc->sc_bus.intr_context--; 686 } 687 688 /* Check for an interrupt. */ 689 void 690 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 691 { 692 int attr; 693 694 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 695 696 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 697 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 698 ehci_check_itd_intr(sc, ex); 699 else 700 ehci_check_qh_intr(sc, ex); 701 702 return; 703 } 704 705 void 706 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 707 { 708 ehci_soft_qtd_t *sqtd, *lsqtd; 709 __uint32_t status; 710 711 if (ex->sqtdstart == NULL) { 712 printf("ehci_check_qh_intr: not valid sqtd\n"); 713 return; 714 } 715 716 lsqtd = ex->sqtdend; 717 #ifdef DIAGNOSTIC 718 if (lsqtd == NULL) { 719 printf("ehci_check_qh_intr: lsqtd==0\n"); 720 return; 721 } 722 #endif 723 /* 724 * If the last TD is still active we need to check whether there 725 * is a an error somewhere in the middle, or whether there was a 726 * short packet (SPD and not ACTIVE). 727 */ 728 usb_syncmem(&lsqtd->dma, 729 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 730 sizeof(lsqtd->qtd.qtd_status), 731 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 732 if (letoh32(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 733 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 734 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 735 usb_syncmem(&sqtd->dma, 736 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 737 sizeof(sqtd->qtd.qtd_status), 738 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 739 status = letoh32(sqtd->qtd.qtd_status); 740 usb_syncmem(&sqtd->dma, 741 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 742 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 743 /* If there's an active QTD the xfer isn't done. */ 744 if (status & EHCI_QTD_ACTIVE) 745 break; 746 /* Any kind of error makes the xfer done. */ 747 if (status & EHCI_QTD_HALTED) 748 goto done; 749 /* We want short packets, and it is short: it's done */ 750 if (EHCI_QTD_GET_BYTES(status) != 0) 751 goto done; 752 } 753 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 754 ex, ex->sqtdstart)); 755 usb_syncmem(&lsqtd->dma, 756 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 757 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 758 return; 759 } 760 done: 761 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 762 timeout_del(&ex->xfer.timeout_handle); 763 usb_rem_task(ex->xfer.pipe->device, &ex->abort_task); 764 ehci_idone(ex); 765 } 766 767 void 768 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 769 ehci_soft_itd_t *itd; 770 int i; 771 772 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 773 return; 774 775 if (ex->itdstart == NULL) { 776 printf("ehci_check_itd_intr: not valid itd\n"); 777 return; 778 } 779 780 itd = ex->itdend; 781 #ifdef DIAGNOSTIC 782 if (itd == NULL) { 783 printf("ehci_check_itd_intr: itdend == 0\n"); 784 return; 785 } 786 #endif 787 788 /* 789 * check no active transfers in last itd, meaning we're finished 790 */ 791 792 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 793 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 794 BUS_DMASYNC_POSTREAD); 795 796 for (i = 0; i < 8; i++) { 797 if (letoh32(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 798 break; 799 } 800 801 if (i == 8) { 802 goto done; /* All 8 descriptors inactive, it's done */ 803 } 804 805 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 806 ex->itdstart)); 807 return; 808 done: 809 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 810 timeout_del(&ex->xfer.timeout_handle); 811 ehci_idone(ex); 812 } 813 814 void 815 ehci_idone(struct ehci_xfer *ex) 816 { 817 usbd_xfer_handle xfer = &ex->xfer; 818 #ifdef EHCI_DEBUG 819 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 820 #endif 821 ehci_soft_qtd_t *sqtd; 822 u_int32_t status = 0, nstatus = 0; 823 int actlen, cerr; 824 825 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 826 #ifdef DIAGNOSTIC 827 { 828 int s = splhigh(); 829 if (ex->isdone) { 830 splx(s); 831 #ifdef EHCI_DEBUG 832 printf("ehci_idone: ex is done!\n "); 833 ehci_dump_exfer(ex); 834 #else 835 printf("ehci_idone: ex=%p is done!\n", ex); 836 #endif 837 return; 838 } 839 ex->isdone = 1; 840 splx(s); 841 } 842 #endif 843 if (xfer->status == USBD_CANCELLED || 844 xfer->status == USBD_TIMEOUT) { 845 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 846 return; 847 } 848 849 #ifdef EHCI_DEBUG 850 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 851 if (ehcidebug > 10) 852 ehci_dump_sqtds(ex->sqtdstart); 853 #endif 854 855 /* The transfer is done, compute actual length and status. */ 856 857 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 858 == UE_ISOCHRONOUS) { 859 /* Isoc transfer */ 860 struct ehci_soft_itd *itd; 861 int i, nframes, len, uframes; 862 863 nframes = 0; 864 actlen = 0; 865 866 switch (xfer->pipe->endpoint->edesc->bInterval) { 867 case 0: 868 panic("ehci: isoc xfer suddenly has 0 bInterval, " 869 "invalid"); 870 case 1: 871 uframes = 1; 872 break; 873 case 2: 874 uframes = 2; 875 break; 876 case 3: 877 uframes = 4; 878 break; 879 default: 880 uframes = 8; 881 break; 882 } 883 884 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 885 usb_syncmem(&itd->dma, 886 itd->offs + offsetof(ehci_itd_t, itd_ctl), 887 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 888 BUS_DMASYNC_POSTREAD); 889 890 for (i = 0; i < 8; i += uframes) { 891 /* XXX - driver didn't fill in the frame full 892 * of uframes. This leads to scheduling 893 * inefficiencies, but working around 894 * this doubles complexity of tracking 895 * an xfer. 896 */ 897 if (nframes >= xfer->nframes) 898 break; 899 900 status = letoh32(itd->itd.itd_ctl[i]); 901 len = EHCI_ITD_GET_LEN(status); 902 if (EHCI_ITD_GET_STATUS(status) != 0) 903 len = 0; /*No valid data on error*/ 904 905 xfer->frlengths[nframes++] = len; 906 actlen += len; 907 } 908 909 if (nframes >= xfer->nframes) 910 break; 911 } 912 913 xfer->actlen = actlen; 914 xfer->status = USBD_NORMAL_COMPLETION; 915 916 goto end; 917 } 918 919 /* Continue processing xfers using queue heads */ 920 921 actlen = 0; 922 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) { 923 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 924 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 925 nstatus = letoh32(sqtd->qtd.qtd_status); 926 if (nstatus & EHCI_QTD_ACTIVE) 927 break; 928 929 status = nstatus; 930 /* halt is ok if descriptor is last, and complete */ 931 if (sqtd->qtd.qtd_next == EHCI_NULL && 932 EHCI_QTD_GET_BYTES(status) == 0) 933 status &= ~EHCI_QTD_HALTED; 934 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 935 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 936 } 937 938 cerr = EHCI_QTD_GET_CERR(status); 939 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 940 "status=0x%x\n", xfer->length, actlen, cerr, status)); 941 xfer->actlen = actlen; 942 if ((status & EHCI_QTD_HALTED) != 0) { 943 #ifdef EHCI_DEBUG 944 char sbuf[128]; 945 946 bitmask_snprintf((u_int32_t)status, 947 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 948 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 949 950 DPRINTFN(2, 951 ("ehci_idone: error, addr=%d, endpt=0x%02x, " 952 "status 0x%s\n", 953 xfer->pipe->device->address, 954 xfer->pipe->endpoint->edesc->bEndpointAddress, 955 sbuf)); 956 if (ehcidebug > 2) { 957 ehci_dump_sqh(epipe->sqh); 958 ehci_dump_sqtds(ex->sqtdstart); 959 } 960 #endif 961 if ((status & EHCI_QTD_BABBLE) == 0 && cerr > 0) 962 xfer->status = USBD_STALLED; 963 else 964 xfer->status = USBD_IOERROR; /* more info XXX */ 965 } else 966 xfer->status = USBD_NORMAL_COMPLETION; 967 end: 968 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 969 * during this call, before methods->done is called: dma sync required 970 * beforehand? */ 971 usb_transfer_complete(xfer); 972 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 973 } 974 975 /* 976 * Wait here until controller claims to have an interrupt. 977 * Then call ehci_intr and return. Use timeout to avoid waiting 978 * too long. 979 */ 980 void 981 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 982 { 983 int timo; 984 u_int32_t intrs; 985 986 xfer->status = USBD_IN_PROGRESS; 987 for (timo = xfer->timeout; timo >= 0; timo--) { 988 usb_delay_ms(&sc->sc_bus, 1); 989 if (sc->sc_bus.dying) 990 break; 991 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 992 sc->sc_eintrs; 993 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 994 #ifdef EHCI_DEBUG 995 if (ehcidebug > 15) 996 ehci_dump_regs(sc); 997 #endif 998 if (intrs) { 999 ehci_intr1(sc); 1000 if (xfer->status != USBD_IN_PROGRESS) 1001 return; 1002 } 1003 } 1004 1005 /* Timeout */ 1006 DPRINTF(("ehci_waitintr: timeout\n")); 1007 xfer->status = USBD_TIMEOUT; 1008 usb_transfer_complete(xfer); 1009 /* XXX should free TD */ 1010 } 1011 1012 void 1013 ehci_poll(struct usbd_bus *bus) 1014 { 1015 ehci_softc_t *sc = (ehci_softc_t *)bus; 1016 #ifdef EHCI_DEBUG 1017 static int last; 1018 int new; 1019 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1020 if (new != last) { 1021 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1022 last = new; 1023 } 1024 #endif 1025 1026 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1027 ehci_intr1(sc); 1028 } 1029 1030 int 1031 ehci_detach(struct ehci_softc *sc, int flags) 1032 { 1033 int rv = 0; 1034 1035 if (sc->sc_child != NULL) 1036 rv = config_detach(sc->sc_child, flags); 1037 1038 if (rv != 0) 1039 return (rv); 1040 1041 timeout_del(&sc->sc_tmo_intrlist); 1042 1043 if (sc->sc_shutdownhook != NULL) 1044 shutdownhook_disestablish(sc->sc_shutdownhook); 1045 1046 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1047 1048 /* XXX free other data structures XXX */ 1049 1050 return (rv); 1051 } 1052 1053 1054 int 1055 ehci_activate(struct device *self, int act) 1056 { 1057 struct ehci_softc *sc = (struct ehci_softc *)self; 1058 u_int32_t cmd, hcr; 1059 int i, rv = 0; 1060 1061 switch (act) { 1062 case DVACT_QUIESCE: 1063 rv = config_activate_children(self, act); 1064 break; 1065 case DVACT_SUSPEND: 1066 sc->sc_bus.use_polling++; 1067 1068 for (i = 1; i <= sc->sc_noport; i++) { 1069 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1070 if ((cmd & (EHCI_PS_PO|EHCI_PS_PE)) == EHCI_PS_PE) 1071 EOWRITE4(sc, EHCI_PORTSC(i), 1072 cmd | EHCI_PS_SUSP); 1073 } 1074 1075 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1076 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1077 EOWRITE4(sc, EHCI_USBCMD, cmd); 1078 1079 for (i = 0; i < 100; i++) { 1080 hcr = EOREAD4(sc, EHCI_USBSTS) & 1081 (EHCI_STS_ASS | EHCI_STS_PSS); 1082 if (hcr == 0) 1083 break; 1084 1085 usb_delay_ms(&sc->sc_bus, 1); 1086 } 1087 if (hcr != 0) 1088 printf("%s: reset timeout\n", 1089 sc->sc_bus.bdev.dv_xname); 1090 1091 cmd &= ~EHCI_CMD_RS; 1092 EOWRITE4(sc, EHCI_USBCMD, cmd); 1093 1094 for (i = 0; i < 100; i++) { 1095 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1096 if (hcr == EHCI_STS_HCH) 1097 break; 1098 1099 usb_delay_ms(&sc->sc_bus, 1); 1100 } 1101 if (hcr != EHCI_STS_HCH) 1102 printf("%s: config timeout\n", 1103 sc->sc_bus.bdev.dv_xname); 1104 1105 sc->sc_bus.use_polling--; 1106 break; 1107 case DVACT_RESUME: 1108 sc->sc_bus.use_polling++; 1109 1110 /* restore things in case the bios sucks */ 1111 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1112 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1113 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1114 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1115 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1116 1117 hcr = 0; 1118 for (i = 1; i <= sc->sc_noport; i++) { 1119 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1120 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == EHCI_PS_SUSP) { 1121 EOWRITE4(sc, EHCI_PORTSC(i), 1122 cmd | EHCI_PS_FPR); 1123 hcr = 1; 1124 } 1125 } 1126 1127 if (hcr) { 1128 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1129 for (i = 1; i <= sc->sc_noport; i++) { 1130 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1131 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == 1132 EHCI_PS_SUSP) 1133 EOWRITE4(sc, EHCI_PORTSC(i), 1134 cmd & ~EHCI_PS_FPR); 1135 } 1136 } 1137 1138 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1139 1140 /* Take over port ownership */ 1141 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 1142 1143 for (i = 0; i < 100; i++) { 1144 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1145 if (hcr != EHCI_STS_HCH) 1146 break; 1147 1148 usb_delay_ms(&sc->sc_bus, 1); 1149 } 1150 if (hcr == EHCI_STS_HCH) 1151 printf("%s: config timeout\n", 1152 sc->sc_bus.bdev.dv_xname); 1153 1154 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1155 1156 sc->sc_bus.use_polling--; 1157 rv = config_activate_children(self, act); 1158 break; 1159 case DVACT_DEACTIVATE: 1160 if (sc->sc_child != NULL) 1161 rv = config_deactivate(sc->sc_child); 1162 sc->sc_bus.dying = 1; 1163 break; 1164 } 1165 return (rv); 1166 } 1167 1168 /* 1169 * Shut down the controller when the system is going down. 1170 */ 1171 void 1172 ehci_shutdown(void *v) 1173 { 1174 ehci_softc_t *sc = v; 1175 1176 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1177 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1178 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1179 } 1180 1181 usbd_status 1182 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1183 { 1184 struct ehci_softc *sc = (struct ehci_softc *)bus; 1185 usbd_status err; 1186 1187 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1188 #ifdef EHCI_DEBUG 1189 if (err) 1190 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1191 #endif 1192 return (err); 1193 } 1194 1195 void 1196 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1197 { 1198 struct ehci_softc *sc = (struct ehci_softc *)bus; 1199 1200 usb_freemem(&sc->sc_bus, dma); 1201 } 1202 1203 usbd_xfer_handle 1204 ehci_allocx(struct usbd_bus *bus) 1205 { 1206 struct ehci_softc *sc = (struct ehci_softc *)bus; 1207 usbd_xfer_handle xfer; 1208 1209 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1210 if (xfer != NULL) { 1211 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1212 #ifdef DIAGNOSTIC 1213 if (xfer->busy_free != XFER_FREE) 1214 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", 1215 xfer, xfer->busy_free); 1216 #endif 1217 } else 1218 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1219 1220 if (xfer != NULL) { 1221 memset(xfer, 0, sizeof(struct ehci_xfer)); 1222 usb_init_task(&EXFER(xfer)->abort_task, ehci_timeout_task, 1223 xfer, USB_TASK_TYPE_ABORT); 1224 EXFER(xfer)->ehci_xfer_flags = 0; 1225 #ifdef DIAGNOSTIC 1226 EXFER(xfer)->isdone = 1; 1227 xfer->busy_free = XFER_BUSY; 1228 #endif 1229 } 1230 return (xfer); 1231 } 1232 1233 void 1234 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1235 { 1236 struct ehci_softc *sc = (struct ehci_softc *)bus; 1237 1238 #ifdef DIAGNOSTIC 1239 if (xfer->busy_free != XFER_BUSY) { 1240 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1241 xfer->busy_free); 1242 return; 1243 } 1244 xfer->busy_free = XFER_FREE; 1245 if (!EXFER(xfer)->isdone) { 1246 printf("ehci_freex: !isdone\n"); 1247 return; 1248 } 1249 #endif 1250 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1251 } 1252 1253 void 1254 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1255 { 1256 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1257 1258 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1259 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1260 #if defined(EHCI_DEBUG) && defined(USB_DEBUG) 1261 if (ehcidebug) 1262 usbd_dump_pipe(pipe); 1263 #endif 1264 #ifdef DIAGNOSTIC 1265 if ((epipe->sqh->qh.qh_qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) != 0) 1266 panic("ehci_device_clear_toggle: queue active"); 1267 #endif 1268 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1269 } 1270 1271 void 1272 ehci_noop(usbd_pipe_handle pipe) 1273 { 1274 } 1275 1276 #ifdef EHCI_DEBUG 1277 void 1278 ehci_dump_regs(ehci_softc_t *sc) 1279 { 1280 int i; 1281 1282 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1283 EOREAD4(sc, EHCI_USBCMD), 1284 EOREAD4(sc, EHCI_USBSTS), 1285 EOREAD4(sc, EHCI_USBINTR)); 1286 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1287 EOREAD4(sc, EHCI_FRINDEX), 1288 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1289 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1290 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1291 for (i = 1; i <= sc->sc_noport; i++) 1292 printf("port %d status=0x%08x\n", i, 1293 EOREAD4(sc, EHCI_PORTSC(i))); 1294 } 1295 1296 /* 1297 * Unused function - this is meant to be called from a kernel 1298 * debugger. 1299 */ 1300 void 1301 ehci_dump(void) 1302 { 1303 ehci_dump_regs(theehci); 1304 } 1305 1306 void 1307 ehci_dump_link(ehci_link_t link, int type) 1308 { 1309 link = letoh32(link); 1310 printf("0x%08x", link); 1311 if (link & EHCI_LINK_TERMINATE) 1312 printf("<T>"); 1313 else { 1314 printf("<"); 1315 if (type) { 1316 switch (EHCI_LINK_TYPE(link)) { 1317 case EHCI_LINK_ITD: 1318 printf("ITD"); 1319 break; 1320 case EHCI_LINK_QH: 1321 printf("QH"); 1322 break; 1323 case EHCI_LINK_SITD: 1324 printf("SITD"); 1325 break; 1326 case EHCI_LINK_FSTN: 1327 printf("FSTN"); 1328 break; 1329 } 1330 } 1331 printf(">"); 1332 } 1333 } 1334 1335 void 1336 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1337 { 1338 int i; 1339 u_int32_t stop; 1340 1341 stop = 0; 1342 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1343 ehci_dump_sqtd(sqtd); 1344 usb_syncmem(&sqtd->dma, 1345 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1346 sizeof(sqtd->qtd), 1347 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1348 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1349 usb_syncmem(&sqtd->dma, 1350 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1351 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1352 } 1353 if (!stop) 1354 printf("dump aborted, too many TDs\n"); 1355 } 1356 1357 void 1358 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1359 { 1360 usb_syncmem(&sqtd->dma, sqtd->offs, 1361 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1362 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1363 ehci_dump_qtd(&sqtd->qtd); 1364 usb_syncmem(&sqtd->dma, sqtd->offs, 1365 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1366 } 1367 1368 void 1369 ehci_dump_qtd(ehci_qtd_t *qtd) 1370 { 1371 u_int32_t s; 1372 char sbuf[128]; 1373 1374 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1375 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1376 printf("\n"); 1377 s = letoh32(qtd->qtd_status); 1378 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), "\20\10ACTIVE\7HALTED" 1379 "\6BUFERR\5BABBLE\4XACTERR\3MISSED\2SPLIT\1PING", 1380 sbuf, sizeof(sbuf)); 1381 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1382 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1383 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1384 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1385 EHCI_QTD_GET_PID(s), sbuf); 1386 for (s = 0; s < 5; s++) 1387 printf(" buffer[%d]=0x%08x\n", s, letoh32(qtd->qtd_buffer[s])); 1388 } 1389 1390 void 1391 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1392 { 1393 ehci_qh_t *qh = &sqh->qh; 1394 u_int32_t endp, endphub; 1395 1396 usb_syncmem(&sqh->dma, sqh->offs, 1397 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1398 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1399 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1400 endp = letoh32(qh->qh_endp); 1401 printf(" endp=0x%08x\n", endp); 1402 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1403 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1404 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1405 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1406 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1407 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1408 EHCI_QH_GET_NRL(endp)); 1409 endphub = letoh32(qh->qh_endphub); 1410 printf(" endphub=0x%08x\n", endphub); 1411 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1412 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1413 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1414 EHCI_QH_GET_MULT(endphub)); 1415 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1416 printf("Overlay qTD:\n"); 1417 ehci_dump_qtd(&qh->qh_qtd); 1418 usb_syncmem(&sqh->dma, sqh->offs, 1419 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1420 } 1421 1422 #if notyet 1423 void 1424 ehci_dump_itd(struct ehci_soft_itd *itd) 1425 { 1426 ehci_isoc_trans_t t; 1427 ehci_isoc_bufr_ptr_t b, b2, b3; 1428 int i; 1429 1430 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1431 1432 for (i = 0; i < 8;i++) { 1433 t = letoh32(itd->itd.itd_ctl[i]); 1434 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1435 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1436 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1437 EHCI_ITD_GET_OFFS(t)); 1438 } 1439 printf("ITDbufr: "); 1440 for (i = 0; i < 7; i++) 1441 printf("%X,", EHCI_ITD_GET_BPTR(letoh32(itd->itd.itd_bufr[i]))); 1442 1443 b = letoh32(itd->itd.itd_bufr[0]); 1444 b2 = letoh32(itd->itd.itd_bufr[1]); 1445 b3 = letoh32(itd->itd.itd_bufr[2]); 1446 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1447 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1448 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1449 } 1450 1451 void 1452 ehci_dump_sitd(struct ehci_soft_itd *itd) 1453 { 1454 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1455 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1456 itd->xfer_next, itd->physaddr, itd->slot); 1457 } 1458 #endif 1459 1460 #ifdef DIAGNOSTIC 1461 void 1462 ehci_dump_exfer(struct ehci_xfer *ex) 1463 { 1464 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p " 1465 "isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, 1466 ex->itdend, ex->isdone); 1467 } 1468 #endif 1469 1470 #endif /* EHCI_DEBUG */ 1471 1472 usbd_status 1473 ehci_open(usbd_pipe_handle pipe) 1474 { 1475 usbd_device_handle dev = pipe->device; 1476 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1477 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1478 u_int8_t addr = dev->address; 1479 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1480 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1481 ehci_soft_qh_t *sqh; 1482 usbd_status err; 1483 int s; 1484 int ival, speed, naks; 1485 int hshubaddr, hshubport; 1486 1487 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1488 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1489 1490 if (sc->sc_bus.dying) 1491 return (USBD_IOERROR); 1492 1493 if (dev->myhsport) { 1494 hshubaddr = dev->myhsport->parent->address; 1495 hshubport = dev->myhsport->portno; 1496 } else { 1497 hshubaddr = 0; 1498 hshubport = 0; 1499 } 1500 1501 if (addr == sc->sc_addr) { 1502 switch (ed->bEndpointAddress) { 1503 case USB_CONTROL_ENDPOINT: 1504 pipe->methods = &ehci_root_ctrl_methods; 1505 break; 1506 case UE_DIR_IN | EHCI_INTR_ENDPT: 1507 pipe->methods = &ehci_root_intr_methods; 1508 break; 1509 default: 1510 return (USBD_INVAL); 1511 } 1512 return (USBD_NORMAL_COMPLETION); 1513 } 1514 1515 /* XXX All this stuff is only valid for async. */ 1516 switch (dev->speed) { 1517 case USB_SPEED_LOW: 1518 speed = EHCI_QH_SPEED_LOW; 1519 break; 1520 case USB_SPEED_FULL: 1521 speed = EHCI_QH_SPEED_FULL; 1522 break; 1523 case USB_SPEED_HIGH: 1524 speed = EHCI_QH_SPEED_HIGH; 1525 break; 1526 default: 1527 panic("ehci_open: bad device speed %d", dev->speed); 1528 } 1529 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1530 printf("%s: Error opening low/full speed isoc endpoint.\n" 1531 "A low/full speed device is attached to a USB2 hub, and " 1532 "transaction translations are not yet supported.\n" 1533 "Reattach the device to the root hub instead.\n", 1534 sc->sc_bus.bdev.dv_xname); 1535 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1536 hshubaddr, hshubport)); 1537 return (USBD_INVAL); 1538 } 1539 1540 naks = 8; /* XXX */ 1541 1542 /* Allocate sqh for everything, save isoc xfers */ 1543 if (xfertype != UE_ISOCHRONOUS) { 1544 sqh = ehci_alloc_sqh(sc); 1545 if (sqh == NULL) 1546 return (USBD_NOMEM); 1547 /* qh_link filled when the QH is added */ 1548 sqh->qh.qh_endp = htole32( 1549 EHCI_QH_SET_ADDR(addr) | 1550 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1551 EHCI_QH_SET_EPS(speed) | 1552 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1553 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1554 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1555 EHCI_QH_CTL : 0) | 1556 EHCI_QH_SET_NRL(naks) 1557 ); 1558 sqh->qh.qh_endphub = htole32( 1559 EHCI_QH_SET_MULT(1) | 1560 EHCI_QH_SET_HUBA(hshubaddr) | 1561 EHCI_QH_SET_PORT(hshubport) | 1562 EHCI_QH_SET_CMASK(0x1c) | /* XXX */ 1563 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0) 1564 ); 1565 sqh->qh.qh_curqtd = EHCI_NULL; 1566 /* Fill the overlay qTD */ 1567 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1568 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1569 sqh->qh.qh_qtd.qtd_status = 1570 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1571 1572 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1573 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1574 epipe->sqh = sqh; 1575 } else { 1576 sqh = NULL; 1577 } /*xfertype == UE_ISOC*/ 1578 1579 switch (xfertype) { 1580 case UE_CONTROL: 1581 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1582 0, &epipe->u.ctl.reqdma); 1583 #ifdef EHCI_DEBUG 1584 if (err) 1585 printf("ehci_open: usb_allocmem()=%d\n", err); 1586 #endif 1587 if (err) 1588 goto bad; 1589 pipe->methods = &ehci_device_ctrl_methods; 1590 s = splusb(); 1591 ehci_add_qh(sqh, sc->sc_async_head); 1592 splx(s); 1593 break; 1594 case UE_BULK: 1595 pipe->methods = &ehci_device_bulk_methods; 1596 s = splusb(); 1597 ehci_add_qh(sqh, sc->sc_async_head); 1598 splx(s); 1599 break; 1600 case UE_INTERRUPT: 1601 pipe->methods = &ehci_device_intr_methods; 1602 ival = pipe->interval; 1603 if (ival == USBD_DEFAULT_INTERVAL) 1604 ival = ed->bInterval; 1605 s = splusb(); 1606 err = ehci_device_setintr(sc, sqh, ival); 1607 splx(s); 1608 return (err); 1609 case UE_ISOCHRONOUS: 1610 pipe->methods = &ehci_device_isoc_methods; 1611 if (ed->bInterval == 0 || ed->bInterval > 16) { 1612 printf("ehci: opening pipe with invalid bInterval\n"); 1613 err = USBD_INVAL; 1614 goto bad; 1615 } 1616 if (UGETW(ed->wMaxPacketSize) == 0) { 1617 printf("ehci: zero length endpoint open request\n"); 1618 err = USBD_INVAL; 1619 goto bad; 1620 } 1621 epipe->u.isoc.next_frame = 0; 1622 epipe->u.isoc.cur_xfers = 0; 1623 break; 1624 default: 1625 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1626 return (USBD_INVAL); 1627 } 1628 return (USBD_NORMAL_COMPLETION); 1629 1630 bad: 1631 if (sqh != NULL) 1632 ehci_free_sqh(sc, sqh); 1633 return (err); 1634 } 1635 1636 /* 1637 * Add an ED to the schedule. Called at splusb(). 1638 * If in the async schedule, it will always have a next. 1639 * If in the intr schedule it may not. 1640 */ 1641 void 1642 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1643 { 1644 SPLUSBCHECK; 1645 1646 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1647 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1648 sqh->next = head->next; 1649 sqh->prev = head; 1650 sqh->qh.qh_link = head->qh.qh_link; 1651 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1652 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1653 head->next = sqh; 1654 if (sqh->next) 1655 sqh->next->prev = sqh; 1656 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1657 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1658 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1659 1660 #ifdef EHCI_DEBUG 1661 if (ehcidebug > 5) { 1662 printf("ehci_add_qh:\n"); 1663 ehci_dump_sqh(sqh); 1664 } 1665 #endif 1666 } 1667 1668 /* 1669 * Remove an ED from the schedule. Called at splusb(). 1670 * Will always have a 'next' if it's in the async list as it's circular. 1671 */ 1672 void 1673 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 1674 { 1675 SPLUSBCHECK; 1676 /* XXX */ 1677 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1678 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1679 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1680 sqh->prev->next = sqh->next; 1681 if (sqh->next) 1682 sqh->next->prev = sqh->prev; 1683 usb_syncmem(&sqh->prev->dma, 1684 sqh->prev->offs + offsetof(ehci_qh_t, qh_link), 1685 sizeof(sqh->prev->qh.qh_link), BUS_DMASYNC_PREWRITE); 1686 1687 ehci_sync_hc(sc); 1688 } 1689 1690 void 1691 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1692 { 1693 int i; 1694 u_int32_t status; 1695 1696 /* Save toggle bit and ping status. */ 1697 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1698 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1699 status = sqh->qh.qh_qtd.qtd_status & 1700 htole32(EHCI_QTD_TOGGLE_MASK | 1701 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1702 /* Set HALTED to make hw leave it alone. */ 1703 sqh->qh.qh_qtd.qtd_status = 1704 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1705 usb_syncmem(&sqh->dma, 1706 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1707 sizeof(sqh->qh.qh_qtd.qtd_status), 1708 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1709 sqh->qh.qh_curqtd = 0; 1710 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1711 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1712 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1713 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1714 sqh->sqtd = sqtd; 1715 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1716 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1717 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1718 sqh->qh.qh_qtd.qtd_status = status; 1719 usb_syncmem(&sqh->dma, 1720 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1721 sizeof(sqh->qh.qh_qtd.qtd_status), 1722 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1723 } 1724 1725 /* 1726 * Ensure that the HC has released all references to the QH. We do this 1727 * by asking for a Async Advance Doorbell interrupt and then we wait for 1728 * the interrupt. 1729 * To make this easier we first obtain exclusive use of the doorbell. 1730 */ 1731 void 1732 ehci_sync_hc(ehci_softc_t *sc) 1733 { 1734 int s, error; 1735 int tries = 0; 1736 1737 if (sc->sc_bus.dying) { 1738 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1739 return; 1740 } 1741 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1742 /* get doorbell */ 1743 rw_enter_write(&sc->sc_doorbell_lock); 1744 s = splhardusb(); 1745 do { 1746 /* ask for doorbell */ 1747 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | 1748 EHCI_CMD_IAAD); 1749 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1750 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1751 /* bell wait */ 1752 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz / 2); 1753 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1754 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1755 } while (error && ++tries < 10); 1756 splx(s); 1757 /* release doorbell */ 1758 rw_exit_write(&sc->sc_doorbell_lock); 1759 #ifdef DIAGNOSTIC 1760 if (error) 1761 printf("ehci_sync_hc: tsleep() = %d\n", error); 1762 #endif 1763 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1764 } 1765 1766 /*Call at splusb*/ 1767 void 1768 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1769 { 1770 struct ehci_soft_itd *itd, *prev; 1771 1772 prev = NULL; 1773 1774 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1775 panic("ehci isoc xfer being freed, but with no itd chain"); 1776 1777 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1778 prev = itd->u.frame_list.prev; 1779 /* Unlink itd from hardware chain, or frame array */ 1780 if (prev == NULL) { /* We're at the table head */ 1781 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1782 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1783 usb_syncmem(&sc->sc_fldma, 1784 sizeof(ehci_link_t) * itd->slot, 1785 sizeof(ehci_link_t), 1786 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1787 1788 if (itd->u.frame_list.next != NULL) 1789 itd->u.frame_list.next->u.frame_list.prev = 1790 NULL; 1791 } else { 1792 /* XXX this part is untested... */ 1793 prev->itd.itd_next = itd->itd.itd_next; 1794 usb_syncmem(&itd->dma, 1795 itd->offs + offsetof(ehci_itd_t, itd_next), 1796 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1797 1798 prev->u.frame_list.next = itd->u.frame_list.next; 1799 if (itd->u.frame_list.next != NULL) 1800 itd->u.frame_list.next->u.frame_list.prev = 1801 prev; 1802 } 1803 } 1804 1805 prev = NULL; 1806 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1807 if (prev != NULL) 1808 ehci_free_itd(sc, prev); 1809 prev = itd; 1810 } 1811 if (prev) 1812 ehci_free_itd(sc, prev); 1813 exfer->itdstart = NULL; 1814 exfer->itdend = NULL; 1815 } 1816 1817 /***********/ 1818 1819 /* 1820 * Data structures and routines to emulate the root hub. 1821 */ 1822 usb_device_descriptor_t ehci_devd = { 1823 USB_DEVICE_DESCRIPTOR_SIZE, 1824 UDESC_DEVICE, /* type */ 1825 {0x00, 0x02}, /* USB version */ 1826 UDCLASS_HUB, /* class */ 1827 UDSUBCLASS_HUB, /* subclass */ 1828 UDPROTO_HSHUBSTT, /* protocol */ 1829 64, /* max packet */ 1830 {0},{0},{0x00,0x01}, /* device id */ 1831 1,2,0, /* string indicies */ 1832 1 /* # of configurations */ 1833 }; 1834 1835 usb_device_qualifier_t ehci_odevd = { 1836 USB_DEVICE_DESCRIPTOR_SIZE, 1837 UDESC_DEVICE_QUALIFIER, /* type */ 1838 {0x00, 0x02}, /* USB version */ 1839 UDCLASS_HUB, /* class */ 1840 UDSUBCLASS_HUB, /* subclass */ 1841 UDPROTO_FSHUB, /* protocol */ 1842 64, /* max packet */ 1843 1, /* # of configurations */ 1844 0 1845 }; 1846 1847 usb_config_descriptor_t ehci_confd = { 1848 USB_CONFIG_DESCRIPTOR_SIZE, 1849 UDESC_CONFIG, 1850 {USB_CONFIG_DESCRIPTOR_SIZE + 1851 USB_INTERFACE_DESCRIPTOR_SIZE + 1852 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1853 1, 1854 1, 1855 0, 1856 UC_SELF_POWERED, 1857 0 /* max power */ 1858 }; 1859 1860 usb_interface_descriptor_t ehci_ifcd = { 1861 USB_INTERFACE_DESCRIPTOR_SIZE, 1862 UDESC_INTERFACE, 1863 0, 1864 0, 1865 1, 1866 UICLASS_HUB, 1867 UISUBCLASS_HUB, 1868 UIPROTO_HSHUBSTT, 1869 0 1870 }; 1871 1872 usb_endpoint_descriptor_t ehci_endpd = { 1873 USB_ENDPOINT_DESCRIPTOR_SIZE, 1874 UDESC_ENDPOINT, 1875 UE_DIR_IN | EHCI_INTR_ENDPT, 1876 UE_INTERRUPT, 1877 {8, 0}, /* max packet */ 1878 255 1879 }; 1880 1881 usb_hub_descriptor_t ehci_hubd = { 1882 USB_HUB_DESCRIPTOR_SIZE, 1883 UDESC_HUB, 1884 0, 1885 {0,0}, 1886 0, 1887 0, 1888 {0}, 1889 }; 1890 1891 int 1892 ehci_str(usb_string_descriptor_t *p, int l, const char *s) 1893 { 1894 int i; 1895 1896 if (l == 0) 1897 return (0); 1898 p->bLength = 2 * strlen(s) + 2; 1899 if (l == 1) 1900 return (1); 1901 p->bDescriptorType = UDESC_STRING; 1902 l -= 2; 1903 for (i = 0; s[i] && l > 1; i++, l -= 2) 1904 USETW2(p->bString[i], 0, s[i]); 1905 return (2*i+2); 1906 } 1907 1908 /* 1909 * Simulate a hardware hub by handling all the necessary requests. 1910 */ 1911 usbd_status 1912 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1913 { 1914 usbd_status err; 1915 1916 /* Insert last in queue. */ 1917 err = usb_insert_transfer(xfer); 1918 if (err) 1919 return (err); 1920 1921 /* Pipe isn't running, start first */ 1922 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1923 } 1924 1925 usbd_status 1926 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1927 { 1928 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 1929 usb_device_request_t *req; 1930 void *buf = NULL; 1931 int port, i; 1932 int s, len, value, index, l, totlen = 0; 1933 usb_port_status_t ps; 1934 usb_hub_descriptor_t hubd; 1935 usbd_status err; 1936 u_int32_t v; 1937 1938 if (sc->sc_bus.dying) 1939 return (USBD_IOERROR); 1940 1941 #ifdef DIAGNOSTIC 1942 if (!(xfer->rqflags & URQ_REQUEST)) 1943 /* XXX panic */ 1944 return (USBD_INVAL); 1945 #endif 1946 req = &xfer->request; 1947 1948 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1949 req->bmRequestType, req->bRequest)); 1950 1951 len = UGETW(req->wLength); 1952 value = UGETW(req->wValue); 1953 index = UGETW(req->wIndex); 1954 1955 if (len != 0) 1956 buf = KERNADDR(&xfer->dmabuf, 0); 1957 1958 #define C(x,y) ((x) | ((y) << 8)) 1959 switch(C(req->bRequest, req->bmRequestType)) { 1960 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1961 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1962 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1963 /* 1964 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1965 * for the integrated root hub. 1966 */ 1967 break; 1968 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1969 if (len > 0) { 1970 *(u_int8_t *)buf = sc->sc_conf; 1971 totlen = 1; 1972 } 1973 break; 1974 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1975 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1976 switch(value >> 8) { 1977 case UDESC_DEVICE: 1978 if ((value & 0xff) != 0) { 1979 err = USBD_IOERROR; 1980 goto ret; 1981 } 1982 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1983 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1984 memcpy(buf, &ehci_devd, l); 1985 break; 1986 /* 1987 * We can't really operate at another speed, but the spec says 1988 * we need this descriptor. 1989 */ 1990 case UDESC_DEVICE_QUALIFIER: 1991 if ((value & 0xff) != 0) { 1992 err = USBD_IOERROR; 1993 goto ret; 1994 } 1995 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1996 memcpy(buf, &ehci_odevd, l); 1997 break; 1998 /* 1999 * We can't really operate at another speed, but the spec says 2000 * we need this descriptor. 2001 */ 2002 case UDESC_OTHER_SPEED_CONFIGURATION: 2003 case UDESC_CONFIG: 2004 if ((value & 0xff) != 0) { 2005 err = USBD_IOERROR; 2006 goto ret; 2007 } 2008 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2009 memcpy(buf, &ehci_confd, l); 2010 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2011 value >> 8; 2012 buf = (char *)buf + l; 2013 len -= l; 2014 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2015 totlen += l; 2016 memcpy(buf, &ehci_ifcd, l); 2017 buf = (char *)buf + l; 2018 len -= l; 2019 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2020 totlen += l; 2021 memcpy(buf, &ehci_endpd, l); 2022 break; 2023 case UDESC_STRING: 2024 if (len == 0) 2025 break; 2026 *(u_int8_t *)buf = 0; 2027 totlen = 1; 2028 switch (value & 0xff) { 2029 case 0: /* Language table */ 2030 totlen = ehci_str(buf, len, "\001"); 2031 break; 2032 case 1: /* Vendor */ 2033 totlen = ehci_str(buf, len, sc->sc_vendor); 2034 break; 2035 case 2: /* Product */ 2036 totlen = ehci_str(buf, len, "EHCI root hub"); 2037 break; 2038 } 2039 break; 2040 default: 2041 err = USBD_IOERROR; 2042 goto ret; 2043 } 2044 break; 2045 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2046 if (len > 0) { 2047 *(u_int8_t *)buf = 0; 2048 totlen = 1; 2049 } 2050 break; 2051 case C(UR_GET_STATUS, UT_READ_DEVICE): 2052 if (len > 1) { 2053 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2054 totlen = 2; 2055 } 2056 break; 2057 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2058 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2059 if (len > 1) { 2060 USETW(((usb_status_t *)buf)->wStatus, 0); 2061 totlen = 2; 2062 } 2063 break; 2064 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2065 if (value >= USB_MAX_DEVICES) { 2066 err = USBD_IOERROR; 2067 goto ret; 2068 } 2069 sc->sc_addr = value; 2070 break; 2071 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2072 if (value != 0 && value != 1) { 2073 err = USBD_IOERROR; 2074 goto ret; 2075 } 2076 sc->sc_conf = value; 2077 break; 2078 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2079 break; 2080 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2081 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2082 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2083 err = USBD_IOERROR; 2084 goto ret; 2085 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2086 break; 2087 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2088 break; 2089 /* Hub requests */ 2090 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2091 break; 2092 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2093 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2094 "port=%d feature=%d\n", index, value)); 2095 if (index < 1 || index > sc->sc_noport) { 2096 err = USBD_IOERROR; 2097 goto ret; 2098 } 2099 port = EHCI_PORTSC(index); 2100 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2101 switch(value) { 2102 case UHF_PORT_ENABLE: 2103 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2104 break; 2105 case UHF_PORT_SUSPEND: 2106 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 2107 break; 2108 case UHF_PORT_POWER: 2109 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2110 break; 2111 case UHF_PORT_TEST: 2112 DPRINTFN(2,("ehci_root_ctrl_start: " 2113 "clear port test %d\n", index)); 2114 break; 2115 case UHF_PORT_INDICATOR: 2116 DPRINTFN(2,("ehci_root_ctrl_start: " 2117 "clear port index %d\n", index)); 2118 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2119 break; 2120 case UHF_C_PORT_CONNECTION: 2121 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2122 break; 2123 case UHF_C_PORT_ENABLE: 2124 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2125 break; 2126 case UHF_C_PORT_SUSPEND: 2127 /* how? */ 2128 break; 2129 case UHF_C_PORT_OVER_CURRENT: 2130 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2131 break; 2132 case UHF_C_PORT_RESET: 2133 sc->sc_isreset = 0; 2134 break; 2135 default: 2136 err = USBD_IOERROR; 2137 goto ret; 2138 } 2139 break; 2140 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2141 if ((value & 0xff) != 0) { 2142 err = USBD_IOERROR; 2143 goto ret; 2144 } 2145 hubd = ehci_hubd; 2146 hubd.bNbrPorts = sc->sc_noport; 2147 v = EREAD4(sc, EHCI_HCSPARAMS); 2148 USETW(hubd.wHubCharacteristics, 2149 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 2150 (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0)); 2151 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2152 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2153 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2154 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2155 l = min(len, hubd.bDescLength); 2156 totlen = l; 2157 memcpy(buf, &hubd, l); 2158 break; 2159 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2160 if (len != 4) { 2161 err = USBD_IOERROR; 2162 goto ret; 2163 } 2164 memset(buf, 0, len); /* ? XXX */ 2165 totlen = len; 2166 break; 2167 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2168 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2169 index)); 2170 if (index < 1 || index > sc->sc_noport) { 2171 err = USBD_IOERROR; 2172 goto ret; 2173 } 2174 if (len != 4) { 2175 err = USBD_IOERROR; 2176 goto ret; 2177 } 2178 v = EOREAD4(sc, EHCI_PORTSC(index)); 2179 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2180 i = UPS_HIGH_SPEED; 2181 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2182 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2183 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2184 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2185 if (v & EHCI_PS_PR) i |= UPS_RESET; 2186 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2187 USETW(ps.wPortStatus, i); 2188 i = 0; 2189 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2190 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2191 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2192 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 2193 USETW(ps.wPortChange, i); 2194 l = min(len, sizeof(ps)); 2195 memcpy(buf, &ps, l); 2196 totlen = l; 2197 break; 2198 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2199 err = USBD_IOERROR; 2200 goto ret; 2201 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2202 break; 2203 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2204 if (index < 1 || index > sc->sc_noport) { 2205 err = USBD_IOERROR; 2206 goto ret; 2207 } 2208 port = EHCI_PORTSC(index); 2209 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2210 switch(value) { 2211 case UHF_PORT_ENABLE: 2212 EOWRITE4(sc, port, v | EHCI_PS_PE); 2213 break; 2214 case UHF_PORT_SUSPEND: 2215 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2216 break; 2217 case UHF_PORT_DISOWN_TO_1_1: 2218 /* enter to Port Reset State */ 2219 v &= ~EHCI_PS_PE; 2220 EOWRITE4(sc, port, v | EHCI_PS_PR); 2221 ehci_disown(sc, index, 0); 2222 break; 2223 case UHF_PORT_RESET: 2224 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2225 index)); 2226 if (EHCI_PS_IS_LOWSPEED(v)) { 2227 /* Low speed device, give up ownership. */ 2228 ehci_disown(sc, index, 1); 2229 break; 2230 } 2231 /* Start reset sequence. */ 2232 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2233 EOWRITE4(sc, port, v | EHCI_PS_PR); 2234 /* Wait for reset to complete. */ 2235 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2236 if (sc->sc_bus.dying) { 2237 err = USBD_IOERROR; 2238 goto ret; 2239 } 2240 /* Terminate reset sequence. */ 2241 v = EOREAD4(sc, port); 2242 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2243 /* Wait for HC to complete reset. */ 2244 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2245 if (sc->sc_bus.dying) { 2246 err = USBD_IOERROR; 2247 goto ret; 2248 } 2249 v = EOREAD4(sc, port); 2250 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2251 if (v & EHCI_PS_PR) { 2252 printf("%s: port reset timeout\n", 2253 sc->sc_bus.bdev.dv_xname); 2254 err = USBD_IOERROR; 2255 goto ret; 2256 } 2257 if (!(v & EHCI_PS_PE)) { 2258 /* Not a high speed device, give up ownership.*/ 2259 ehci_disown(sc, index, 0); 2260 break; 2261 } 2262 sc->sc_isreset = 1; 2263 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2264 index, v)); 2265 break; 2266 case UHF_PORT_POWER: 2267 DPRINTFN(2,("ehci_root_ctrl_start: " 2268 "set port power %d\n", index)); 2269 EOWRITE4(sc, port, v | EHCI_PS_PP); 2270 break; 2271 case UHF_PORT_TEST: 2272 DPRINTFN(2,("ehci_root_ctrl_start: " 2273 "set port test %d\n", index)); 2274 break; 2275 case UHF_PORT_INDICATOR: 2276 DPRINTFN(2,("ehci_root_ctrl_start: " 2277 "set port ind %d\n", index)); 2278 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2279 break; 2280 default: 2281 err = USBD_IOERROR; 2282 goto ret; 2283 } 2284 break; 2285 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2286 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2287 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2288 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2289 break; 2290 default: 2291 err = USBD_IOERROR; 2292 goto ret; 2293 } 2294 xfer->actlen = totlen; 2295 err = USBD_NORMAL_COMPLETION; 2296 ret: 2297 xfer->status = err; 2298 s = splusb(); 2299 usb_transfer_complete(xfer); 2300 splx(s); 2301 return (USBD_IN_PROGRESS); 2302 } 2303 2304 void 2305 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2306 { 2307 int port; 2308 u_int32_t v; 2309 2310 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2311 2312 port = EHCI_PORTSC(index); 2313 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2314 EOWRITE4(sc, port, v | EHCI_PS_PO); 2315 } 2316 2317 /* Abort a root control request. */ 2318 void 2319 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2320 { 2321 /* Nothing to do, all transfers are synchronous. */ 2322 } 2323 2324 /* Close the root pipe. */ 2325 void 2326 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2327 { 2328 DPRINTF(("ehci_root_ctrl_close\n")); 2329 /* Nothing to do. */ 2330 } 2331 2332 void 2333 ehci_root_intr_done(usbd_xfer_handle xfer) 2334 { 2335 } 2336 2337 usbd_status 2338 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2339 { 2340 usbd_status err; 2341 2342 /* Insert last in queue. */ 2343 err = usb_insert_transfer(xfer); 2344 if (err) 2345 return (err); 2346 2347 /* Pipe isn't running, start first */ 2348 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2349 } 2350 2351 usbd_status 2352 ehci_root_intr_start(usbd_xfer_handle xfer) 2353 { 2354 usbd_pipe_handle pipe = xfer->pipe; 2355 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2356 2357 if (sc->sc_bus.dying) 2358 return (USBD_IOERROR); 2359 2360 sc->sc_intrxfer = xfer; 2361 2362 return (USBD_IN_PROGRESS); 2363 } 2364 2365 /* Abort a root interrupt request. */ 2366 void 2367 ehci_root_intr_abort(usbd_xfer_handle xfer) 2368 { 2369 int s; 2370 2371 if (xfer->pipe->intrxfer == xfer) { 2372 DPRINTF(("ehci_root_intr_abort: remove\n")); 2373 xfer->pipe->intrxfer = NULL; 2374 } 2375 xfer->status = USBD_CANCELLED; 2376 s = splusb(); 2377 usb_transfer_complete(xfer); 2378 splx(s); 2379 } 2380 2381 /* Close the root pipe. */ 2382 void 2383 ehci_root_intr_close(usbd_pipe_handle pipe) 2384 { 2385 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2386 2387 DPRINTF(("ehci_root_intr_close\n")); 2388 2389 sc->sc_intrxfer = NULL; 2390 } 2391 2392 void 2393 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2394 { 2395 } 2396 2397 /************************/ 2398 2399 ehci_soft_qh_t * 2400 ehci_alloc_sqh(ehci_softc_t *sc) 2401 { 2402 ehci_soft_qh_t *sqh; 2403 usbd_status err; 2404 int i, offs; 2405 usb_dma_t dma; 2406 2407 if (sc->sc_freeqhs == NULL) { 2408 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2409 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2410 EHCI_PAGE_SIZE, &dma); 2411 #ifdef EHCI_DEBUG 2412 if (err) 2413 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2414 #endif 2415 if (err) 2416 return (NULL); 2417 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2418 offs = i * EHCI_SQH_SIZE; 2419 sqh = KERNADDR(&dma, offs); 2420 sqh->physaddr = DMAADDR(&dma, offs); 2421 sqh->dma = dma; 2422 sqh->offs = offs; 2423 sqh->next = sc->sc_freeqhs; 2424 sc->sc_freeqhs = sqh; 2425 } 2426 } 2427 sqh = sc->sc_freeqhs; 2428 sc->sc_freeqhs = sqh->next; 2429 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2430 sqh->next = NULL; 2431 sqh->prev = NULL; 2432 return (sqh); 2433 } 2434 2435 void 2436 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2437 { 2438 sqh->next = sc->sc_freeqhs; 2439 sc->sc_freeqhs = sqh; 2440 } 2441 2442 ehci_soft_qtd_t * 2443 ehci_alloc_sqtd(ehci_softc_t *sc) 2444 { 2445 ehci_soft_qtd_t *sqtd; 2446 usbd_status err; 2447 int i, offs; 2448 usb_dma_t dma; 2449 int s; 2450 2451 if (sc->sc_freeqtds == NULL) { 2452 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2453 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2454 EHCI_PAGE_SIZE, &dma); 2455 #ifdef EHCI_DEBUG 2456 if (err) 2457 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2458 #endif 2459 if (err) 2460 return (NULL); 2461 s = splusb(); 2462 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2463 offs = i * EHCI_SQTD_SIZE; 2464 sqtd = KERNADDR(&dma, offs); 2465 sqtd->physaddr = DMAADDR(&dma, offs); 2466 sqtd->dma = dma; 2467 sqtd->offs = offs; 2468 sqtd->nextqtd = sc->sc_freeqtds; 2469 sc->sc_freeqtds = sqtd; 2470 } 2471 splx(s); 2472 } 2473 2474 s = splusb(); 2475 sqtd = sc->sc_freeqtds; 2476 sc->sc_freeqtds = sqtd->nextqtd; 2477 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2478 sqtd->nextqtd = NULL; 2479 splx(s); 2480 2481 return (sqtd); 2482 } 2483 2484 void 2485 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2486 { 2487 int s; 2488 2489 s = splusb(); 2490 sqtd->nextqtd = sc->sc_freeqtds; 2491 sc->sc_freeqtds = sqtd; 2492 splx(s); 2493 } 2494 2495 usbd_status 2496 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, u_int alen, 2497 int rd, usbd_xfer_handle xfer, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2498 { 2499 ehci_soft_qtd_t *next, *cur; 2500 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2501 u_int32_t qtdstatus; 2502 u_int len, curlen; 2503 int mps, i, iscontrol, forceshort; 2504 usb_dma_t *dma = &xfer->dmabuf; 2505 2506 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2507 2508 len = alen; 2509 iscontrol = (epipe->pipe.endpoint->edesc->bmAttributes & UE_XFERTYPE) == 2510 UE_CONTROL; 2511 2512 dataphys = DMAADDR(dma, 0); 2513 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2514 qtdstatus = EHCI_QTD_ACTIVE | 2515 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2516 EHCI_QTD_SET_CERR(3); /* IOC and BYTES set below */ 2517 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2518 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2519 len % mps == 0; 2520 /* 2521 * The control transfer data stage always starts with a toggle of 1. 2522 * For other transfers we let the hardware track the toggle state. 2523 */ 2524 if (iscontrol) 2525 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2526 2527 cur = ehci_alloc_sqtd(sc); 2528 *sp = cur; 2529 if (cur == NULL) 2530 goto nomem; 2531 2532 usb_syncmem(dma, 0, alen, 2533 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2534 for (;;) { 2535 dataphyspage = EHCI_PAGE(dataphys); 2536 /* The EHCI hardware can handle at most 5 pages. */ 2537 if (dataphyslastpage - dataphyspage < 2538 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2539 /* we can handle it in this QTD */ 2540 curlen = len; 2541 } else { 2542 /* must use multiple TDs, fill as much as possible. */ 2543 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2544 EHCI_PAGE_OFFSET(dataphys); 2545 #ifdef DIAGNOSTIC 2546 if (curlen > len) { 2547 printf("ehci_alloc_sqtd_chain: curlen=%u " 2548 "len=%u offs=0x%x\n", curlen, len, 2549 EHCI_PAGE_OFFSET(dataphys)); 2550 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2551 dataphyslastpage, dataphyspage, dataphys); 2552 curlen = len; 2553 } 2554 #endif 2555 /* the length must be a multiple of the max size */ 2556 curlen -= curlen % mps; 2557 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2558 "curlen=%u\n", curlen)); 2559 #ifdef DIAGNOSTIC 2560 if (curlen == 0) 2561 panic("ehci_alloc_std: curlen == 0"); 2562 #endif 2563 } 2564 2565 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2566 "dataphyslastpage=0x%08x len=%u curlen=%u\n", 2567 dataphys, dataphyslastpage, len, curlen)); 2568 len -= curlen; 2569 2570 /* 2571 * Allocate another transfer if there's more data left, 2572 * or if force last short transfer flag is set and we're 2573 * allocating a multiple of the max packet size. 2574 */ 2575 if (len != 0 || forceshort) { 2576 next = ehci_alloc_sqtd(sc); 2577 if (next == NULL) 2578 goto nomem; 2579 nextphys = htole32(next->physaddr); 2580 } else { 2581 next = NULL; 2582 nextphys = EHCI_NULL; 2583 } 2584 2585 for (i = 0; i * EHCI_PAGE_SIZE < 2586 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2587 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2588 if (i != 0) /* use offset only in first buffer */ 2589 a = EHCI_PAGE(a); 2590 #ifdef DIAGNOSTIC 2591 if (i >= EHCI_QTD_NBUFFERS) { 2592 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2593 goto nomem; 2594 } 2595 #endif 2596 cur->qtd.qtd_buffer[i] = htole32(a); 2597 cur->qtd.qtd_buffer_hi[i] = 0; 2598 } 2599 cur->nextqtd = next; 2600 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2601 cur->qtd.qtd_status = htole32(qtdstatus | 2602 EHCI_QTD_SET_BYTES(curlen)); 2603 cur->len = curlen; 2604 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2605 dataphys, dataphys + curlen)); 2606 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%u\n", curlen)); 2607 if (iscontrol) { 2608 /* 2609 * adjust the toggle based on the number of packets 2610 * in this qtd 2611 */ 2612 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2613 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2614 } 2615 if (len == 0) { 2616 if (! forceshort) 2617 break; 2618 forceshort = 0; 2619 } 2620 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2621 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2622 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2623 dataphys += curlen; 2624 cur = next; 2625 } 2626 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2627 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2628 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2629 *ep = cur; 2630 2631 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2632 *sp, *ep)); 2633 2634 return (USBD_NORMAL_COMPLETION); 2635 2636 nomem: 2637 /* XXX free chain */ 2638 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2639 return (USBD_NOMEM); 2640 } 2641 2642 void 2643 ehci_free_sqtd_chain(ehci_softc_t *sc, struct ehci_xfer *ex) 2644 { 2645 struct ehci_pipe *epipe = (struct ehci_pipe *)ex->xfer.pipe; 2646 ehci_soft_qtd_t *sqtd, *next; 2647 2648 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p\n", ex->sqtdstart)); 2649 2650 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = next) { 2651 next = sqtd->nextqtd; 2652 ehci_free_sqtd(sc, sqtd); 2653 } 2654 ex->sqtdstart = ex->sqtdend = NULL; 2655 epipe->sqh->sqtd = NULL; 2656 } 2657 2658 ehci_soft_itd_t * 2659 ehci_alloc_itd(ehci_softc_t *sc) 2660 { 2661 struct ehci_soft_itd *itd, *freeitd; 2662 usbd_status err; 2663 int i, s, offs, frindex, previndex; 2664 usb_dma_t dma; 2665 2666 s = splusb(); 2667 2668 /* Find an itd that wasn't freed this frame or last frame. This can 2669 * discard itds that were freed before frindex wrapped around 2670 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2671 * interrupt and fiddling with list when that happens */ 2672 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2673 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2674 2675 freeitd = NULL; 2676 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2677 if (itd == NULL) 2678 break; 2679 if (itd->slot != frindex && itd->slot != previndex) { 2680 freeitd = itd; 2681 break; 2682 } 2683 } 2684 2685 if (freeitd == NULL) { 2686 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2687 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2688 EHCI_PAGE_SIZE, &dma); 2689 2690 if (err) { 2691 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2692 return (NULL); 2693 } 2694 2695 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2696 offs = i * EHCI_ITD_SIZE; 2697 itd = KERNADDR(&dma, offs); 2698 itd->physaddr = DMAADDR(&dma, offs); 2699 itd->dma = dma; 2700 itd->offs = offs; 2701 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2702 } 2703 freeitd = LIST_FIRST(&sc->sc_freeitds); 2704 } 2705 2706 itd = freeitd; 2707 LIST_REMOVE(itd, u.free_list); 2708 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2709 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2710 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2711 BUS_DMASYNC_PREREAD); 2712 2713 itd->u.frame_list.next = NULL; 2714 itd->u.frame_list.prev = NULL; 2715 itd->xfer_next = NULL; 2716 itd->slot = 0; 2717 splx(s); 2718 2719 return (itd); 2720 } 2721 2722 void 2723 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2724 { 2725 int s; 2726 2727 s = splusb(); 2728 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2729 splx(s); 2730 } 2731 2732 /****************/ 2733 2734 /* 2735 * Close a reqular pipe. 2736 * Assumes that there are no pending transactions. 2737 */ 2738 void 2739 ehci_close_pipe(usbd_pipe_handle pipe) 2740 { 2741 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2742 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2743 ehci_soft_qh_t *sqh = epipe->sqh; 2744 int s; 2745 2746 s = splusb(); 2747 ehci_rem_qh(sc, sqh); 2748 splx(s); 2749 pipe->endpoint->savedtoggle = 2750 EHCI_QTD_GET_TOGGLE(letoh32(sqh->qh.qh_qtd.qtd_status)); 2751 ehci_free_sqh(sc, epipe->sqh); 2752 } 2753 2754 /* 2755 * Abort a device request. 2756 * If this routine is called at splusb() it guarantees that the request 2757 * will be removed from the hardware scheduling and that the callback 2758 * for it will be called with USBD_CANCELLED status. 2759 * It's impossible to guarantee that the requested transfer will not 2760 * have happened since the hardware runs concurrently. 2761 * If the transaction has already happened we rely on the ordinary 2762 * interrupt processing to process it. 2763 */ 2764 void 2765 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2766 { 2767 #define exfer EXFER(xfer) 2768 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2769 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2770 ehci_soft_qh_t *sqh = epipe->sqh; 2771 ehci_soft_qtd_t *sqtd; 2772 int s; 2773 2774 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2775 2776 if (sc->sc_bus.dying) { 2777 /* If we're dying, just do the software part. */ 2778 s = splusb(); 2779 xfer->status = status; /* make software ignore it */ 2780 timeout_del(&xfer->timeout_handle); 2781 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 2782 usb_transfer_complete(xfer); 2783 splx(s); 2784 return; 2785 } 2786 2787 if (xfer->device->bus->intr_context) 2788 panic("ehci_abort_xfer: not in process context"); 2789 2790 /* 2791 * If an abort is already in progress then just wait for it to 2792 * complete and return. 2793 */ 2794 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2795 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2796 /* No need to wait if we're aborting from a timeout. */ 2797 if (status == USBD_TIMEOUT) 2798 return; 2799 /* Override the status which might be USBD_TIMEOUT. */ 2800 xfer->status = status; 2801 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2802 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 2803 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 2804 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciaw", 0); 2805 return; 2806 } 2807 2808 /* 2809 * Step 1: Make interrupt routine and timeouts ignore xfer. 2810 */ 2811 s = splusb(); 2812 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2813 xfer->status = status; /* make software ignore it */ 2814 timeout_del(&xfer->timeout_handle); 2815 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 2816 splx(s); 2817 2818 /* 2819 * Step 2: Deactivate all of the qTDs that we will be removing, 2820 * otherwise the queue head may go active again. 2821 */ 2822 usb_syncmem(&sqh->dma, 2823 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2824 sizeof(sqh->qh.qh_qtd.qtd_status), 2825 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2826 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2827 usb_syncmem(&sqh->dma, 2828 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2829 sizeof(sqh->qh.qh_qtd.qtd_status), 2830 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2831 2832 for (sqtd = exfer->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) { 2833 usb_syncmem(&sqtd->dma, 2834 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2835 sizeof(sqtd->qtd.qtd_status), 2836 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2837 sqtd->qtd.qtd_status = htole32(EHCI_QTD_HALTED); 2838 usb_syncmem(&sqtd->dma, 2839 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2840 sizeof(sqtd->qtd.qtd_status), 2841 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2842 } 2843 ehci_sync_hc(sc); 2844 2845 /* 2846 * Step 3: Make sure the soft interrupt routine has run. This 2847 * should remove any completed items off the queue. 2848 * The hardware has no reference to completed items (TDs). 2849 * It's safe to remove them at any time. 2850 */ 2851 s = splusb(); 2852 sc->sc_softwake = 1; 2853 usb_schedsoftintr(&sc->sc_bus); 2854 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2855 2856 #ifdef DIAGNOSTIC 2857 exfer->isdone = 1; 2858 #endif 2859 /* Do the wakeup first to avoid touching the xfer after the callback. */ 2860 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 2861 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 2862 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 2863 wakeup(&exfer->ehci_xfer_flags); 2864 } 2865 usb_transfer_complete(xfer); 2866 2867 splx(s); 2868 #undef exfer 2869 } 2870 2871 void 2872 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 2873 { 2874 ehci_isoc_trans_t trans_status; 2875 struct ehci_pipe *epipe; 2876 struct ehci_xfer *exfer; 2877 ehci_softc_t *sc; 2878 struct ehci_soft_itd *itd; 2879 int s, i, wake; 2880 2881 epipe = (struct ehci_pipe *) xfer->pipe; 2882 exfer = EXFER(xfer); 2883 sc = (ehci_softc_t *)epipe->pipe.device->bus; 2884 2885 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 2886 2887 if (sc->sc_bus.dying) { 2888 s = splusb(); 2889 xfer->status = status; 2890 timeout_del(&xfer->timeout_handle); 2891 usb_transfer_complete(xfer); 2892 splx(s); 2893 return; 2894 } 2895 2896 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2897 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 2898 2899 #ifdef DIAGNOSTIC 2900 if (status == USBD_TIMEOUT) 2901 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2902 #endif 2903 2904 xfer->status = status; 2905 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2906 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2907 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 2908 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciiaw", 0); 2909 return; 2910 } 2911 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2912 2913 xfer->status = status; 2914 timeout_del(&xfer->timeout_handle); 2915 2916 s = splusb(); 2917 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2918 for (i = 0; i < 8; i++) { 2919 trans_status = letoh32(itd->itd.itd_ctl[i]); 2920 trans_status &= ~EHCI_ITD_ACTIVE; 2921 itd->itd.itd_ctl[i] = htole32(trans_status); 2922 } 2923 } 2924 splx(s); 2925 2926 s = splusb(); 2927 sc->sc_softwake = 1; 2928 usb_schedsoftintr(&sc->sc_bus); 2929 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2930 splx(s); 2931 2932 #ifdef DIAGNOSTIC 2933 exfer->isdone = 1; 2934 #endif 2935 wake = exfer->ehci_xfer_flags & EHCI_XFER_ABORTING; 2936 exfer->ehci_xfer_flags &= ~(EHCI_XFER_ABORTING | EHCI_XFER_ABORTWAIT); 2937 usb_transfer_complete(xfer); 2938 if (wake) 2939 wakeup(&exfer->ehci_xfer_flags); 2940 2941 return; 2942 } 2943 2944 void 2945 ehci_timeout(void *addr) 2946 { 2947 struct ehci_xfer *exfer = addr; 2948 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 2949 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2950 2951 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 2952 #if defined(EHCI_DEBUG) && defined(USB_DEBUG) 2953 if (ehcidebug > 1) 2954 usbd_dump_pipe(exfer->xfer.pipe); 2955 #endif 2956 2957 if (sc->sc_bus.dying) { 2958 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 2959 return; 2960 } 2961 2962 /* Execute the abort in a process context. */ 2963 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task); 2964 } 2965 2966 void 2967 ehci_timeout_task(void *addr) 2968 { 2969 usbd_xfer_handle xfer = addr; 2970 int s; 2971 2972 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 2973 2974 s = splusb(); 2975 ehci_abort_xfer(xfer, USBD_TIMEOUT); 2976 splx(s); 2977 } 2978 2979 /* 2980 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 2981 * qTD status, or miss signalling occasionally under heavy load. If the host 2982 * machine is too fast, we we can miss transaction completion - when we scan 2983 * the active list the transaction still seems to be active. This generally 2984 * exhibits itself as a umass stall that never recovers. 2985 * 2986 * We work around this behaviour by setting up this callback after any softintr 2987 * that completes with transactions still pending, giving us another chance to 2988 * check for completion after the writeback has taken place. 2989 */ 2990 void 2991 ehci_intrlist_timeout(void *arg) 2992 { 2993 ehci_softc_t *sc = arg; 2994 int s; 2995 2996 if (sc->sc_bus.dying) 2997 return; 2998 2999 s = splusb(); 3000 DPRINTFN(1, ("ehci_intrlist_timeout\n")); 3001 usb_schedsoftintr(&sc->sc_bus); 3002 splx(s); 3003 } 3004 3005 /************************/ 3006 3007 usbd_status 3008 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3009 { 3010 usbd_status err; 3011 3012 /* Insert last in queue. */ 3013 err = usb_insert_transfer(xfer); 3014 if (err) 3015 return (err); 3016 3017 /* Pipe isn't running, start first */ 3018 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3019 } 3020 3021 usbd_status 3022 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3023 { 3024 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3025 usbd_status err; 3026 3027 if (sc->sc_bus.dying) 3028 return (USBD_IOERROR); 3029 3030 #ifdef DIAGNOSTIC 3031 if (!(xfer->rqflags & URQ_REQUEST)) { 3032 /* XXX panic */ 3033 printf("ehci_device_ctrl_transfer: not a request\n"); 3034 return (USBD_INVAL); 3035 } 3036 #endif 3037 3038 err = ehci_device_request(xfer); 3039 if (err) 3040 return (err); 3041 3042 if (sc->sc_bus.use_polling) 3043 ehci_waitintr(sc, xfer); 3044 return (USBD_IN_PROGRESS); 3045 } 3046 3047 void 3048 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3049 { 3050 struct ehci_xfer *ex = EXFER(xfer); 3051 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3052 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 3053 3054 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3055 3056 #ifdef DIAGNOSTIC 3057 if (!(xfer->rqflags & URQ_REQUEST)) { 3058 panic("ehci_ctrl_done: not a request"); 3059 } 3060 #endif 3061 3062 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3063 ehci_del_intr_list(sc, ex); /* remove from active list */ 3064 ehci_free_sqtd_chain(sc, ex); 3065 } 3066 3067 DPRINTFN(5, ("ehci_ctrl_done: length=%u\n", xfer->actlen)); 3068 } 3069 3070 /* Abort a device control request. */ 3071 void 3072 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3073 { 3074 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3075 ehci_abort_xfer(xfer, USBD_CANCELLED); 3076 } 3077 3078 /* Close a device control pipe. */ 3079 void 3080 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3081 { 3082 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3083 ehci_close_pipe(pipe); 3084 } 3085 3086 usbd_status 3087 ehci_device_request(usbd_xfer_handle xfer) 3088 { 3089 #define exfer EXFER(xfer) 3090 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3091 usb_device_request_t *req = &xfer->request; 3092 usbd_device_handle dev = epipe->pipe.device; 3093 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3094 int addr = dev->address; 3095 ehci_soft_qtd_t *setup, *stat, *next; 3096 ehci_soft_qh_t *sqh; 3097 int isread; 3098 u_int len; 3099 usbd_status err; 3100 int s; 3101 3102 isread = req->bmRequestType & UT_READ; 3103 len = UGETW(req->wLength); 3104 3105 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3106 "wValue=0x%04x, wIndex=0x%04x len=%u, addr=%d, endpt=%d\n", 3107 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3108 UGETW(req->wIndex), len, addr, 3109 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3110 3111 setup = ehci_alloc_sqtd(sc); 3112 if (setup == NULL) { 3113 err = USBD_NOMEM; 3114 goto bad1; 3115 } 3116 stat = ehci_alloc_sqtd(sc); 3117 if (stat == NULL) { 3118 err = USBD_NOMEM; 3119 goto bad2; 3120 } 3121 3122 sqh = epipe->sqh; 3123 epipe->u.ctl.length = len; 3124 3125 /* Update device address and length since they may have changed 3126 during the setup of the control pipe in usbd_new_device(). */ 3127 /* XXX This only needs to be done once, but it's too early in open. */ 3128 /* XXXX Should not touch ED here! */ 3129 sqh->qh.qh_endp = 3130 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3131 htole32( 3132 EHCI_QH_SET_ADDR(addr) | 3133 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3134 ); 3135 3136 /* Set up data transaction */ 3137 if (len != 0) { 3138 ehci_soft_qtd_t *end; 3139 3140 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3141 &next, &end); 3142 if (err) 3143 goto bad3; 3144 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3145 end->nextqtd = stat; 3146 end->qtd.qtd_next = 3147 end->qtd.qtd_altnext = htole32(stat->physaddr); 3148 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3149 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3150 } else { 3151 next = stat; 3152 } 3153 3154 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 3155 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3156 3157 /* Clear toggle */ 3158 setup->qtd.qtd_status = htole32( 3159 EHCI_QTD_ACTIVE | 3160 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3161 EHCI_QTD_SET_CERR(3) | 3162 EHCI_QTD_SET_TOGGLE(0) | 3163 EHCI_QTD_SET_BYTES(sizeof(*req))); 3164 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3165 setup->qtd.qtd_buffer_hi[0] = 0; 3166 setup->nextqtd = next; 3167 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3168 setup->len = sizeof(*req); 3169 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3170 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3171 3172 stat->qtd.qtd_status = htole32( 3173 EHCI_QTD_ACTIVE | 3174 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3175 EHCI_QTD_SET_CERR(3) | 3176 EHCI_QTD_SET_TOGGLE(1) | 3177 EHCI_QTD_IOC); 3178 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3179 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3180 stat->nextqtd = NULL; 3181 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3182 stat->len = 0; 3183 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3184 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3185 3186 #ifdef EHCI_DEBUG 3187 if (ehcidebug > 5) { 3188 DPRINTF(("ehci_device_request:\n")); 3189 ehci_dump_sqh(sqh); 3190 ehci_dump_sqtds(setup); 3191 } 3192 #endif 3193 3194 exfer->sqtdstart = setup; 3195 exfer->sqtdend = stat; 3196 #ifdef DIAGNOSTIC 3197 if (!exfer->isdone) { 3198 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3199 } 3200 exfer->isdone = 0; 3201 #endif 3202 3203 /* Insert qTD in QH list. */ 3204 s = splusb(); 3205 ehci_set_qh_qtd(sqh, setup); 3206 if (xfer->timeout && !sc->sc_bus.use_polling) { 3207 timeout_del(&xfer->timeout_handle); 3208 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3209 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3210 } 3211 ehci_add_intr_list(sc, exfer); 3212 xfer->status = USBD_IN_PROGRESS; 3213 splx(s); 3214 3215 #ifdef EHCI_DEBUG 3216 if (ehcidebug > 10) { 3217 DPRINTF(("ehci_device_request: status=%x\n", 3218 EOREAD4(sc, EHCI_USBSTS))); 3219 delay(10000); 3220 ehci_dump_regs(sc); 3221 ehci_dump_sqh(sc->sc_async_head); 3222 ehci_dump_sqh(sqh); 3223 ehci_dump_sqtds(setup); 3224 } 3225 #endif 3226 3227 return (USBD_NORMAL_COMPLETION); 3228 3229 bad3: 3230 ehci_free_sqtd(sc, stat); 3231 bad2: 3232 ehci_free_sqtd(sc, setup); 3233 bad1: 3234 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3235 xfer->status = err; 3236 usb_transfer_complete(xfer); 3237 return (err); 3238 #undef exfer 3239 } 3240 3241 /************************/ 3242 3243 usbd_status 3244 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3245 { 3246 usbd_status err; 3247 3248 /* Insert last in queue. */ 3249 err = usb_insert_transfer(xfer); 3250 if (err) 3251 return (err); 3252 3253 /* Pipe isn't running, start first */ 3254 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3255 } 3256 3257 usbd_status 3258 ehci_device_bulk_start(usbd_xfer_handle xfer) 3259 { 3260 #define exfer EXFER(xfer) 3261 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3262 usbd_device_handle dev = epipe->pipe.device; 3263 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3264 ehci_soft_qtd_t *data, *dataend; 3265 ehci_soft_qh_t *sqh; 3266 usbd_status err; 3267 u_int len; 3268 int isread, endpt; 3269 int s; 3270 3271 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%u flags=%d\n", 3272 xfer, xfer->length, xfer->flags)); 3273 3274 if (sc->sc_bus.dying) 3275 return (USBD_IOERROR); 3276 3277 #ifdef DIAGNOSTIC 3278 if (xfer->rqflags & URQ_REQUEST) 3279 panic("ehci_device_bulk_start: a request"); 3280 #endif 3281 3282 len = xfer->length; 3283 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3284 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3285 sqh = epipe->sqh; 3286 3287 epipe->u.bulk.length = len; 3288 3289 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3290 &dataend); 3291 if (err) { 3292 DPRINTFN(-1,("ehci_device_bulk_start: no memory\n")); 3293 xfer->status = err; 3294 usb_transfer_complete(xfer); 3295 return (err); 3296 } 3297 3298 #ifdef EHCI_DEBUG 3299 if (ehcidebug > 5) { 3300 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3301 ehci_dump_sqh(sqh); 3302 ehci_dump_sqtds(data); 3303 } 3304 #endif 3305 3306 /* Set up interrupt info. */ 3307 exfer->sqtdstart = data; 3308 exfer->sqtdend = dataend; 3309 #ifdef DIAGNOSTIC 3310 if (!exfer->isdone) { 3311 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3312 } 3313 exfer->isdone = 0; 3314 #endif 3315 3316 s = splusb(); 3317 ehci_set_qh_qtd(sqh, data); 3318 if (xfer->timeout && !sc->sc_bus.use_polling) { 3319 timeout_del(&xfer->timeout_handle); 3320 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3321 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3322 } 3323 ehci_add_intr_list(sc, exfer); 3324 xfer->status = USBD_IN_PROGRESS; 3325 splx(s); 3326 3327 #ifdef EHCI_DEBUG 3328 if (ehcidebug > 10) { 3329 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3330 delay(10000); 3331 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3332 ehci_dump_regs(sc); 3333 #if 0 3334 printf("async_head:\n"); 3335 ehci_dump_sqh(sc->sc_async_head); 3336 #endif 3337 printf("sqh:\n"); 3338 ehci_dump_sqh(sqh); 3339 ehci_dump_sqtds(data); 3340 } 3341 #endif 3342 3343 if (sc->sc_bus.use_polling) 3344 ehci_waitintr(sc, xfer); 3345 3346 return (USBD_IN_PROGRESS); 3347 #undef exfer 3348 } 3349 3350 void 3351 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3352 { 3353 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3354 ehci_abort_xfer(xfer, USBD_CANCELLED); 3355 } 3356 3357 /* 3358 * Close a device bulk pipe. 3359 */ 3360 void 3361 ehci_device_bulk_close(usbd_pipe_handle pipe) 3362 { 3363 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3364 ehci_close_pipe(pipe); 3365 } 3366 3367 void 3368 ehci_device_bulk_done(usbd_xfer_handle xfer) 3369 { 3370 struct ehci_xfer *ex = EXFER(xfer); 3371 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3372 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3373 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3374 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3375 3376 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3377 xfer, xfer->actlen)); 3378 3379 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3380 ehci_del_intr_list(sc, ex); /* remove from active list */ 3381 ehci_free_sqtd_chain(sc, ex); 3382 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3383 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3384 } 3385 3386 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3387 } 3388 3389 /************************/ 3390 3391 usbd_status 3392 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3393 { 3394 struct ehci_soft_islot *isp; 3395 int islot, lev; 3396 3397 /* Find a poll rate that is large enough. */ 3398 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3399 if (EHCI_ILEV_IVAL(lev) <= ival) 3400 break; 3401 3402 /* Pick an interrupt slot at the right level. */ 3403 /* XXX could do better than picking at random */ 3404 if (cold) { 3405 /* XXX prevent panics at boot by not using arc4random */ 3406 sc->sc_rand = (sc->sc_rand + 192) % sc->sc_flsize; 3407 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3408 } else 3409 islot = EHCI_IQHIDX(lev, arc4random()); 3410 3411 sqh->islot = islot; 3412 isp = &sc->sc_islots[islot]; 3413 ehci_add_qh(sqh, isp->sqh); 3414 3415 return (USBD_NORMAL_COMPLETION); 3416 } 3417 3418 usbd_status 3419 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3420 { 3421 usbd_status err; 3422 3423 /* Insert last in queue. */ 3424 err = usb_insert_transfer(xfer); 3425 if (err) 3426 return (err); 3427 3428 /* 3429 * Pipe isn't running (otherwise err would be USBD_INPROG), 3430 * so start it first. 3431 */ 3432 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3433 } 3434 3435 usbd_status 3436 ehci_device_intr_start(usbd_xfer_handle xfer) 3437 { 3438 #define exfer EXFER(xfer) 3439 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3440 usbd_device_handle dev = xfer->pipe->device; 3441 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3442 ehci_soft_qtd_t *data, *dataend; 3443 ehci_soft_qh_t *sqh; 3444 usbd_status err; 3445 u_int len; 3446 int isread, endpt; 3447 int s; 3448 3449 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%u flags=%d\n", 3450 xfer, xfer->length, xfer->flags)); 3451 3452 if (sc->sc_bus.dying) 3453 return (USBD_IOERROR); 3454 3455 #ifdef DIAGNOSTIC 3456 if (xfer->rqflags & URQ_REQUEST) 3457 panic("ehci_device_intr_start: a request"); 3458 #endif 3459 3460 len = xfer->length; 3461 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3462 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3463 sqh = epipe->sqh; 3464 3465 epipe->u.intr.length = len; 3466 3467 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3468 &dataend); 3469 if (err) { 3470 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3471 xfer->status = err; 3472 usb_transfer_complete(xfer); 3473 return (err); 3474 } 3475 3476 #ifdef EHCI_DEBUG 3477 if (ehcidebug > 5) { 3478 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3479 ehci_dump_sqh(sqh); 3480 ehci_dump_sqtds(data); 3481 } 3482 #endif 3483 3484 /* Set up interrupt info. */ 3485 exfer->sqtdstart = data; 3486 exfer->sqtdend = dataend; 3487 #ifdef DIAGNOSTIC 3488 if (!exfer->isdone) 3489 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3490 exfer->isdone = 0; 3491 #endif 3492 3493 s = splusb(); 3494 ehci_set_qh_qtd(sqh, data); 3495 if (xfer->timeout && !sc->sc_bus.use_polling) { 3496 timeout_del(&xfer->timeout_handle); 3497 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3498 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3499 } 3500 ehci_add_intr_list(sc, exfer); 3501 xfer->status = USBD_IN_PROGRESS; 3502 splx(s); 3503 3504 #ifdef EHCI_DEBUG 3505 if (ehcidebug > 10) { 3506 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3507 delay(10000); 3508 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3509 ehci_dump_regs(sc); 3510 printf("sqh:\n"); 3511 ehci_dump_sqh(sqh); 3512 ehci_dump_sqtds(data); 3513 } 3514 #endif 3515 3516 if (sc->sc_bus.use_polling) 3517 ehci_waitintr(sc, xfer); 3518 3519 return (USBD_IN_PROGRESS); 3520 #undef exfer 3521 } 3522 3523 void 3524 ehci_device_intr_abort(usbd_xfer_handle xfer) 3525 { 3526 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3527 if (xfer->pipe->intrxfer == xfer) { 3528 DPRINTFN(1, ("ehci_device_intr_abort: remove\n")); 3529 xfer->pipe->intrxfer = NULL; 3530 } 3531 /* 3532 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3533 * async doorbell. That's dependant on the async list, wheras 3534 * intr xfers are periodic, should not use this? 3535 */ 3536 ehci_abort_xfer(xfer, USBD_CANCELLED); 3537 } 3538 3539 void 3540 ehci_device_intr_close(usbd_pipe_handle pipe) 3541 { 3542 DPRINTF(("ehci_device_intr_close: pipe=%p\n", pipe)); 3543 ehci_close_pipe(pipe); 3544 } 3545 3546 void 3547 ehci_device_intr_done(usbd_xfer_handle xfer) 3548 { 3549 #define exfer EXFER(xfer) 3550 struct ehci_xfer *ex = EXFER(xfer); 3551 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3552 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3553 ehci_soft_qtd_t *data, *dataend; 3554 ehci_soft_qh_t *sqh; 3555 usbd_status err; 3556 u_int len; 3557 int isread, endpt, s; 3558 3559 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3560 xfer, xfer->actlen)); 3561 3562 if (xfer->pipe->repeat) { 3563 ehci_free_sqtd_chain(sc, ex); 3564 3565 len = epipe->u.intr.length; 3566 xfer->length = len; 3567 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3568 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3569 usb_syncmem(&xfer->dmabuf, 0, len, 3570 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3571 sqh = epipe->sqh; 3572 3573 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3574 &data, &dataend); 3575 if (err) { 3576 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3577 xfer->status = err; 3578 return; 3579 } 3580 3581 /* Set up interrupt info. */ 3582 exfer->sqtdstart = data; 3583 exfer->sqtdend = dataend; 3584 #ifdef DIAGNOSTIC 3585 if (!exfer->isdone) { 3586 printf("ehci_device_intr_done: not done, ex=%p\n", 3587 exfer); 3588 } 3589 exfer->isdone = 0; 3590 #endif 3591 3592 s = splusb(); 3593 ehci_set_qh_qtd(sqh, data); 3594 if (xfer->timeout && !sc->sc_bus.use_polling) { 3595 timeout_del(&xfer->timeout_handle); 3596 timeout_set(&xfer->timeout_handle, ehci_timeout, xfer); 3597 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3598 } 3599 splx(s); 3600 3601 xfer->status = USBD_IN_PROGRESS; 3602 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3603 ehci_del_intr_list(sc, ex); /* remove from active list */ 3604 ehci_free_sqtd_chain(sc, ex); 3605 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3606 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3607 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3608 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3609 } 3610 #undef exfer 3611 } 3612 3613 /************************/ 3614 3615 usbd_status 3616 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3617 { 3618 usbd_status err; 3619 3620 err = usb_insert_transfer(xfer); 3621 if (err && err != USBD_IN_PROGRESS) 3622 return (err); 3623 3624 return (ehci_device_isoc_start(xfer)); 3625 } 3626 3627 usbd_status 3628 ehci_device_isoc_start(usbd_xfer_handle xfer) 3629 { 3630 struct ehci_pipe *epipe; 3631 ehci_softc_t *sc; 3632 struct ehci_xfer *exfer; 3633 ehci_soft_itd_t *itd, *prev, *start, *stop; 3634 usb_dma_t *dma_buf; 3635 int i, j, k, frames, uframes, ufrperframe; 3636 int s, trans_count, offs, total_length; 3637 int frindex; 3638 3639 start = NULL; 3640 prev = NULL; 3641 itd = NULL; 3642 trans_count = 0; 3643 total_length = 0; 3644 exfer = (struct ehci_xfer *) xfer; 3645 sc = (ehci_softc_t *)xfer->pipe->device->bus; 3646 epipe = (struct ehci_pipe *)xfer->pipe; 3647 3648 /* 3649 * To allow continuous transfers, above we start all transfers 3650 * immediately. However, we're still going to get usbd_start_next call 3651 * this when another xfer completes. So, check if this is already 3652 * in progress or not 3653 */ 3654 3655 if (exfer->itdstart != NULL) 3656 return (USBD_IN_PROGRESS); 3657 3658 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %u flags %d\n", 3659 xfer, xfer->length, xfer->flags)); 3660 3661 if (sc->sc_bus.dying) 3662 return (USBD_IOERROR); 3663 3664 /* 3665 * To avoid complication, don't allow a request right now that'll span 3666 * the entire frame table. To within 4 frames, to allow some leeway 3667 * on either side of where the hc currently is. 3668 */ 3669 if ((1 << (epipe->pipe.endpoint->edesc->bInterval - 1)) * 3670 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3671 printf("ehci: isoc descriptor requested that spans the entire " 3672 "frametable, too many frames\n"); 3673 return (USBD_INVAL); 3674 } 3675 3676 #ifdef DIAGNOSTIC 3677 if (xfer->rqflags & URQ_REQUEST) 3678 panic("ehci_device_isoc_start: request"); 3679 3680 if (!exfer->isdone) 3681 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3682 exfer->isdone = 0; 3683 #endif 3684 3685 /* 3686 * Step 1: Allocate and initialize itds, how many do we need? 3687 * One per transfer if interval >= 8 microframes, fewer if we use 3688 * multiple microframes per frame. 3689 */ 3690 3691 i = epipe->pipe.endpoint->edesc->bInterval; 3692 if (i > 16 || i == 0) { 3693 /* Spec page 271 says intervals > 16 are invalid */ 3694 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3695 return (USBD_INVAL); 3696 } 3697 3698 switch (i) { 3699 case 1: 3700 ufrperframe = 8; 3701 break; 3702 case 2: 3703 ufrperframe = 4; 3704 break; 3705 case 3: 3706 ufrperframe = 2; 3707 break; 3708 default: 3709 ufrperframe = 1; 3710 break; 3711 } 3712 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3713 uframes = 8 / ufrperframe; 3714 3715 if (frames == 0) { 3716 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3717 return (USBD_INVAL); 3718 } 3719 3720 dma_buf = &xfer->dmabuf; 3721 offs = 0; 3722 3723 for (i = 0; i < frames; i++) { 3724 int froffs = offs; 3725 itd = ehci_alloc_itd(sc); 3726 3727 if (prev != NULL) { 3728 prev->itd.itd_next = 3729 htole32(itd->physaddr | EHCI_LINK_ITD); 3730 prev->xfer_next = itd; 3731 } else { 3732 start = itd; 3733 } 3734 3735 /* 3736 * Step 1.5, initialize uframes 3737 */ 3738 for (j = 0; j < 8; j += uframes) { 3739 /* Calculate which page in the list this starts in */ 3740 int addr = DMAADDR(dma_buf, froffs); 3741 addr = EHCI_PAGE_OFFSET(addr); 3742 addr += (offs - froffs); 3743 addr = EHCI_PAGE(addr); 3744 addr /= EHCI_PAGE_SIZE; 3745 3746 /* This gets the initial offset into the first page, 3747 * looks how far further along the current uframe 3748 * offset is. Works out how many pages that is. 3749 */ 3750 3751 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3752 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3753 EHCI_ITD_SET_PG(addr) | 3754 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf, 3755 offs)))); 3756 3757 total_length += xfer->frlengths[trans_count]; 3758 offs += xfer->frlengths[trans_count]; 3759 trans_count++; 3760 3761 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3762 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3763 break; 3764 } 3765 } 3766 3767 /* Step 1.75, set buffer pointers. To simplify matters, all 3768 * pointers are filled out for the next 7 hardware pages in 3769 * the dma block, so no need to worry what pages to cover 3770 * and what to not. 3771 */ 3772 3773 for (j=0; j < 7; j++) { 3774 /* 3775 * Don't try to lookup a page that's past the end 3776 * of buffer 3777 */ 3778 int page_offs = EHCI_PAGE(froffs + 3779 (EHCI_PAGE_SIZE * j)); 3780 3781 if (page_offs >= dma_buf->block->size) 3782 break; 3783 3784 long long page = DMAADDR(dma_buf, page_offs); 3785 page = EHCI_PAGE(page); 3786 itd->itd.itd_bufr[j] = 3787 htole32(EHCI_ITD_SET_BPTR(page)); 3788 itd->itd.itd_bufr_hi[j] = 3789 htole32(page >> 32); 3790 } 3791 3792 /* 3793 * Other special values 3794 */ 3795 3796 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3797 itd->itd.itd_bufr[0] |= 3798 htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3799 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3800 3801 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3802 ? 1 : 0; 3803 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3804 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3805 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3806 3807 /* FIXME: handle invalid trans */ 3808 itd->itd.itd_bufr[2] |= 3809 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3810 prev = itd; 3811 } /* End of frame */ 3812 3813 stop = itd; 3814 stop->xfer_next = NULL; 3815 exfer->isoc_len = total_length; 3816 3817 /* 3818 * Part 2: Transfer descriptors have now been set up, now they must 3819 * be scheduled into the period frame list. Erk. Not wanting to 3820 * complicate matters, transfer is denied if the transfer spans 3821 * more than the period frame list. 3822 */ 3823 3824 s = splusb(); 3825 3826 /* Start inserting frames */ 3827 if (epipe->u.isoc.cur_xfers > 0) { 3828 frindex = epipe->u.isoc.next_frame; 3829 } else { 3830 frindex = EOREAD4(sc, EHCI_FRINDEX); 3831 frindex = frindex >> 3; /* Erase microframe index */ 3832 frindex += 2; 3833 } 3834 3835 if (frindex >= sc->sc_flsize) 3836 frindex &= (sc->sc_flsize - 1); 3837 3838 /* Whats the frame interval? */ 3839 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 3840 if (i / 8 == 0) 3841 i = 1; 3842 else 3843 i /= 8; 3844 3845 itd = start; 3846 for (j = 0; j < frames; j++) { 3847 if (itd == NULL) 3848 panic("ehci: unexpectedly ran out of isoc itds, " 3849 "isoc_start"); 3850 3851 itd->itd.itd_next = sc->sc_flist[frindex]; 3852 if (itd->itd.itd_next == 0) 3853 /* FIXME: frindex table gets initialized to NULL 3854 * or EHCI_NULL? */ 3855 itd->itd.itd_next = htole32(EHCI_NULL); 3856 3857 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 3858 itd->u.frame_list.next = sc->sc_softitds[frindex]; 3859 sc->sc_softitds[frindex] = itd; 3860 if (itd->u.frame_list.next != NULL) 3861 itd->u.frame_list.next->u.frame_list.prev = itd; 3862 itd->slot = frindex; 3863 itd->u.frame_list.prev = NULL; 3864 3865 frindex += i; 3866 if (frindex >= sc->sc_flsize) 3867 frindex -= sc->sc_flsize; 3868 3869 itd = itd->xfer_next; 3870 } 3871 3872 epipe->u.isoc.cur_xfers++; 3873 epipe->u.isoc.next_frame = frindex; 3874 3875 exfer->itdstart = start; 3876 exfer->itdend = stop; 3877 exfer->sqtdstart = NULL; 3878 exfer->sqtdend = NULL; 3879 3880 ehci_add_intr_list(sc, exfer); 3881 xfer->status = USBD_IN_PROGRESS; 3882 xfer->done = 0; 3883 splx(s); 3884 3885 if (sc->sc_bus.use_polling) { 3886 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 3887 ehci_waitintr(sc, xfer); 3888 } 3889 3890 return (USBD_IN_PROGRESS); 3891 } 3892 3893 void 3894 ehci_device_isoc_abort(usbd_xfer_handle xfer) 3895 { 3896 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 3897 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 3898 } 3899 3900 void 3901 ehci_device_isoc_close(usbd_pipe_handle pipe) 3902 { 3903 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 3904 } 3905 3906 void 3907 ehci_device_isoc_done(usbd_xfer_handle xfer) 3908 { 3909 struct ehci_xfer *exfer; 3910 ehci_softc_t *sc; 3911 struct ehci_pipe *epipe; 3912 int s; 3913 3914 exfer = EXFER(xfer); 3915 sc = (ehci_softc_t *)xfer->pipe->device->bus; 3916 epipe = (struct ehci_pipe *) xfer->pipe; 3917 3918 s = splusb(); 3919 epipe->u.isoc.cur_xfers--; 3920 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 3921 ehci_del_intr_list(sc, exfer); 3922 ehci_rem_free_itd_chain(sc, exfer); 3923 } 3924 splx(s); 3925 } 3926