1 /* $OpenBSD: dwc2_hcdqueue.c,v 1.8 2017/06/29 17:36:16 deraadt Exp $ */ 2 /* $NetBSD: dwc2_hcdqueue.c,v 1.11 2014/09/03 10:00:08 skrll Exp $ */ 3 4 /* 5 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * This file contains the functions to manage Queue Heads and Queue 42 * Transfer Descriptors for Host mode 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/types.h> 48 #include <sys/malloc.h> 49 #include <sys/pool.h> 50 51 #include <machine/bus.h> 52 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usbdi.h> 55 #include <dev/usb/usbdivar.h> 56 #include <dev/usb/usb_mem.h> 57 58 #include <dev/usb/dwc2/dwc2.h> 59 #include <dev/usb/dwc2/dwc2var.h> 60 61 #include <dev/usb/dwc2/dwc2_core.h> 62 #include <dev/usb/dwc2/dwc2_hcd.h> 63 64 STATIC u32 dwc2_calc_bus_time(struct dwc2_hsotg *, int, int, int, int); 65 66 /** 67 * dwc2_qh_init() - Initializes a QH structure 68 * 69 * @hsotg: The HCD state structure for the DWC OTG controller 70 * @qh: The QH to init 71 * @urb: Holds the information about the device/endpoint needed to initialize 72 * the QH 73 */ 74 #define SCHEDULE_SLOP 10 75 STATIC void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 76 struct dwc2_hcd_urb *urb) 77 { 78 int dev_speed, hub_addr, hub_port; 79 80 dev_vdbg(hsotg->dev, "%s()\n", __func__); 81 82 /* Initialize QH */ 83 qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 84 qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0; 85 86 qh->data_toggle = DWC2_HC_PID_DATA0; 87 qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info); 88 TAILQ_INIT(&qh->qtd_list); 89 qh->linked = 0; 90 91 /* FS/LS Endpoint on HS Hub, NOT virtual root hub */ 92 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 93 94 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 95 qh->nak_frame = 0xffff; 96 97 if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) && 98 hub_addr != 0 && hub_addr != 1) { 99 dev_vdbg(hsotg->dev, 100 "QH init: EP %d: TT found at hub addr %d, for port %d\n", 101 dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr, 102 hub_port); 103 qh->do_split = 1; 104 } 105 106 if (qh->ep_type == USB_ENDPOINT_XFER_INT || 107 qh->ep_type == USB_ENDPOINT_XFER_ISOC) { 108 /* Compute scheduling parameters once and save them */ 109 u32 hprt, prtspd; 110 111 /* Todo: Account for split transfers in the bus time */ 112 int bytecount = 113 dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp); 114 115 qh->usecs = dwc2_calc_bus_time(hsotg, qh->do_split ? 116 USB_SPEED_HIGH : dev_speed, qh->ep_is_in, 117 qh->ep_type == USB_ENDPOINT_XFER_ISOC, 118 bytecount); 119 /* Start in a slightly future (micro)frame */ 120 qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number, 121 SCHEDULE_SLOP); 122 qh->interval = urb->interval; 123 #if 0 124 /* Increase interrupt polling rate for debugging */ 125 if (qh->ep_type == USB_ENDPOINT_XFER_INT) 126 qh->interval = 8; 127 #endif 128 hprt = DWC2_READ_4(hsotg, HPRT0); 129 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 130 if (prtspd == HPRT0_SPD_HIGH_SPEED && 131 (dev_speed == USB_SPEED_LOW || 132 dev_speed == USB_SPEED_FULL)) { 133 qh->interval *= 8; 134 qh->sched_frame |= 0x7; 135 qh->start_split_frame = qh->sched_frame; 136 } 137 dev_dbg(hsotg->dev, "interval=%d\n", qh->interval); 138 } 139 140 dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n"); 141 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh); 142 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n", 143 dwc2_hcd_get_dev_addr(&urb->pipe_info)); 144 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n", 145 dwc2_hcd_get_ep_num(&urb->pipe_info), 146 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); 147 148 qh->dev_speed = dev_speed; 149 150 #ifdef DWC2_DEBUG 151 const char *speed, *type; 152 switch (dev_speed) { 153 case USB_SPEED_LOW: 154 speed = "low"; 155 break; 156 case USB_SPEED_FULL: 157 speed = "full"; 158 break; 159 case USB_SPEED_HIGH: 160 speed = "high"; 161 break; 162 default: 163 speed = "?"; 164 break; 165 } 166 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed); 167 168 switch (qh->ep_type) { 169 case USB_ENDPOINT_XFER_ISOC: 170 type = "isochronous"; 171 break; 172 case USB_ENDPOINT_XFER_INT: 173 type = "interrupt"; 174 break; 175 case USB_ENDPOINT_XFER_CONTROL: 176 type = "control"; 177 break; 178 case USB_ENDPOINT_XFER_BULK: 179 type = "bulk"; 180 break; 181 default: 182 type = "?"; 183 break; 184 } 185 186 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type); 187 #endif 188 189 if (qh->ep_type == USB_ENDPOINT_XFER_INT) { 190 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n", 191 qh->usecs); 192 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n", 193 qh->interval); 194 } 195 } 196 197 /** 198 * dwc2_hcd_qh_create() - Allocates and initializes a QH 199 * 200 * @hsotg: The HCD state structure for the DWC OTG controller 201 * @urb: Holds the information about the device/endpoint needed 202 * to initialize the QH 203 * @mem_flags: Flag to do atomic allocation if needed 204 * 205 * Return: Pointer to the newly allocated QH, or NULL on error 206 */ 207 STATIC struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 208 struct dwc2_hcd_urb *urb, 209 gfp_t mem_flags) 210 { 211 struct dwc2_softc *sc = hsotg->hsotg_sc; 212 struct dwc2_qh *qh; 213 214 if (!urb->priv) 215 return NULL; 216 217 /* Allocate memory */ 218 qh = pool_get(&sc->sc_qhpool, PR_NOWAIT); 219 if (!qh) 220 return NULL; 221 222 memset(qh, 0, sizeof(*qh)); 223 dwc2_qh_init(hsotg, qh, urb); 224 225 if (hsotg->core_params->dma_desc_enable > 0 && 226 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) { 227 dwc2_hcd_qh_free(hsotg, qh); 228 return NULL; 229 } 230 231 return qh; 232 } 233 234 /** 235 * dwc2_hcd_qh_free() - Frees the QH 236 * 237 * @hsotg: HCD instance 238 * @qh: The QH to free 239 * 240 * QH should already be removed from the list. QTD list should already be empty 241 * if called from URB Dequeue. 242 * 243 * Must NOT be called with interrupt disabled or spinlock held 244 */ 245 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 246 { 247 struct dwc2_softc *sc = hsotg->hsotg_sc; 248 249 if (hsotg->core_params->dma_desc_enable > 0) { 250 dwc2_hcd_qh_free_ddma(hsotg, qh); 251 } else if (qh->dw_align_buf) { 252 /* XXXNH */ 253 usb_freemem(&hsotg->hsotg_sc->sc_bus, &qh->dw_align_buf_usbdma); 254 } 255 256 pool_put(&sc->sc_qhpool, qh); 257 } 258 259 /** 260 * dwc2_periodic_channel_available() - Checks that a channel is available for a 261 * periodic transfer 262 * 263 * @hsotg: The HCD state structure for the DWC OTG controller 264 * 265 * Return: 0 if successful, negative error code otherwise 266 */ 267 STATIC int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg) 268 { 269 /* 270 * Currently assuming that there is a dedicated host channel for 271 * each periodic transaction plus at least one host channel for 272 * non-periodic transactions 273 */ 274 int status; 275 int num_channels; 276 277 num_channels = hsotg->core_params->host_channels; 278 if (hsotg->periodic_channels + hsotg->non_periodic_channels < 279 num_channels 280 && hsotg->periodic_channels < num_channels - 1) { 281 status = 0; 282 } else { 283 dev_dbg(hsotg->dev, 284 "%s: Total channels: %d, Periodic: %d, " 285 "Non-periodic: %d\n", __func__, num_channels, 286 hsotg->periodic_channels, hsotg->non_periodic_channels); 287 status = -ENOSPC; 288 } 289 290 return status; 291 } 292 293 /** 294 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth 295 * for the specified QH in the periodic schedule 296 * 297 * @hsotg: The HCD state structure for the DWC OTG controller 298 * @qh: QH containing periodic bandwidth required 299 * 300 * Return: 0 if successful, negative error code otherwise 301 * 302 * For simplicity, this calculation assumes that all the transfers in the 303 * periodic schedule may occur in the same (micro)frame 304 */ 305 STATIC int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg, 306 struct dwc2_qh *qh) 307 { 308 int status; 309 s16 max_claimed_usecs; 310 311 status = 0; 312 313 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) { 314 /* 315 * High speed mode 316 * Max periodic usecs is 80% x 125 usec = 100 usec 317 */ 318 max_claimed_usecs = 100 - qh->usecs; 319 } else { 320 /* 321 * Full speed mode 322 * Max periodic usecs is 90% x 1000 usec = 900 usec 323 */ 324 max_claimed_usecs = 900 - qh->usecs; 325 } 326 327 if (hsotg->periodic_usecs > max_claimed_usecs) { 328 dev_err(hsotg->dev, 329 "%s: already claimed usecs %d, required usecs %d\n", 330 __func__, hsotg->periodic_usecs, qh->usecs); 331 status = -ENOSPC; 332 } 333 334 return status; 335 } 336 337 /** 338 * Microframe scheduler 339 * track the total use in hsotg->frame_usecs 340 * keep each qh use in qh->frame_usecs 341 * when surrendering the qh then donate the time back 342 */ 343 STATIC const unsigned short max_uframe_usecs[] = { 344 100, 100, 100, 100, 100, 100, 30, 0 345 }; 346 347 void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg) 348 { 349 int i; 350 351 for (i = 0; i < 8; i++) 352 hsotg->frame_usecs[i] = max_uframe_usecs[i]; 353 } 354 355 STATIC int dwc2_find_single_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 356 { 357 unsigned short utime = qh->usecs; 358 int i; 359 360 for (i = 0; i < 8; i++) { 361 /* At the start hsotg->frame_usecs[i] = max_uframe_usecs[i] */ 362 if (utime <= hsotg->frame_usecs[i]) { 363 hsotg->frame_usecs[i] -= utime; 364 qh->frame_usecs[i] += utime; 365 return i; 366 } 367 } 368 return -ENOSPC; 369 } 370 371 /* 372 * use this for FS apps that can span multiple uframes 373 */ 374 STATIC int dwc2_find_multi_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 375 { 376 unsigned short utime = qh->usecs; 377 unsigned short xtime; 378 int t_left; 379 int i; 380 int j; 381 int k; 382 383 for (i = 0; i < 8; i++) { 384 if (hsotg->frame_usecs[i] <= 0) 385 continue; 386 387 /* 388 * we need n consecutive slots so use j as a start slot 389 * j plus j+1 must be enough time (for now) 390 */ 391 xtime = hsotg->frame_usecs[i]; 392 for (j = i + 1; j < 8; j++) { 393 /* 394 * if we add this frame remaining time to xtime we may 395 * be OK, if not we need to test j for a complete frame 396 */ 397 if (xtime + hsotg->frame_usecs[j] < utime) { 398 if (hsotg->frame_usecs[j] < 399 max_uframe_usecs[j]) 400 continue; 401 } 402 if (xtime >= utime) { 403 t_left = utime; 404 for (k = i; k < 8; k++) { 405 t_left -= hsotg->frame_usecs[k]; 406 if (t_left <= 0) { 407 qh->frame_usecs[k] += 408 hsotg->frame_usecs[k] 409 + t_left; 410 hsotg->frame_usecs[k] = -t_left; 411 return i; 412 } else { 413 qh->frame_usecs[k] += 414 hsotg->frame_usecs[k]; 415 hsotg->frame_usecs[k] = 0; 416 } 417 } 418 } 419 /* add the frame time to x time */ 420 xtime += hsotg->frame_usecs[j]; 421 /* we must have a fully available next frame or break */ 422 if (xtime < utime && 423 hsotg->frame_usecs[j] == max_uframe_usecs[j]) 424 continue; 425 } 426 } 427 return -ENOSPC; 428 } 429 430 STATIC int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 431 { 432 int ret; 433 434 if (qh->dev_speed == USB_SPEED_HIGH) { 435 /* if this is a hs transaction we need a full frame */ 436 ret = dwc2_find_single_uframe(hsotg, qh); 437 } else { 438 /* 439 * if this is a fs transaction we may need a sequence 440 * of frames 441 */ 442 ret = dwc2_find_multi_uframe(hsotg, qh); 443 } 444 return ret; 445 } 446 447 /** 448 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a 449 * host channel is large enough to handle the maximum data transfer in a single 450 * (micro)frame for a periodic transfer 451 * 452 * @hsotg: The HCD state structure for the DWC OTG controller 453 * @qh: QH for a periodic endpoint 454 * 455 * Return: 0 if successful, negative error code otherwise 456 */ 457 STATIC int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg, 458 struct dwc2_qh *qh) 459 { 460 u32 max_xfer_size; 461 u32 max_channel_xfer_size; 462 int status = 0; 463 464 max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp); 465 max_channel_xfer_size = hsotg->core_params->max_transfer_size; 466 467 if (max_xfer_size > max_channel_xfer_size) { 468 dev_err(hsotg->dev, 469 "%s: Periodic xfer length %d > max xfer length for channel %d\n", 470 __func__, max_xfer_size, max_channel_xfer_size); 471 status = -ENOSPC; 472 } 473 474 return status; 475 } 476 477 /** 478 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in 479 * the periodic schedule 480 * 481 * @hsotg: The HCD state structure for the DWC OTG controller 482 * @qh: QH for the periodic transfer. The QH should already contain the 483 * scheduling information. 484 * 485 * Return: 0 if successful, negative error code otherwise 486 */ 487 STATIC int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 488 { 489 int status; 490 491 if (hsotg->core_params->uframe_sched > 0) { 492 int frame = -1; 493 494 status = dwc2_find_uframe(hsotg, qh); 495 if (status == 0) 496 frame = 7; 497 else if (status > 0) 498 frame = status - 1; 499 500 /* Set the new frame up */ 501 if (frame >= 0) { 502 qh->sched_frame &= ~0x7; 503 qh->sched_frame |= (frame & 7); 504 } 505 506 if (status > 0) 507 status = 0; 508 } else { 509 status = dwc2_periodic_channel_available(hsotg); 510 if (status) { 511 dev_info(hsotg->dev, 512 "%s: No host channel available for periodic transfer\n", 513 __func__); 514 return status; 515 } 516 517 status = dwc2_check_periodic_bandwidth(hsotg, qh); 518 } 519 520 if (status) { 521 dev_dbg(hsotg->dev, 522 "%s: Insufficient periodic bandwidth for periodic transfer\n", 523 __func__); 524 return status; 525 } 526 527 status = dwc2_check_max_xfer_size(hsotg, qh); 528 if (status) { 529 dev_dbg(hsotg->dev, 530 "%s: Channel max transfer size too small for periodic transfer\n", 531 __func__); 532 return status; 533 } 534 535 if (hsotg->core_params->dma_desc_enable > 0) 536 /* Don't rely on SOF and start in ready schedule */ 537 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_ready, qh, qh_list_entry); 538 else 539 /* Always start in inactive schedule */ 540 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_inactive, qh, qh_list_entry); 541 qh->linked = 1; 542 543 if (hsotg->core_params->uframe_sched <= 0) 544 /* Reserve periodic channel */ 545 hsotg->periodic_channels++; 546 547 /* Update claimed usecs per (micro)frame */ 548 hsotg->periodic_usecs += qh->usecs; 549 550 return status; 551 } 552 553 /** 554 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer 555 * from the periodic schedule 556 * 557 * @hsotg: The HCD state structure for the DWC OTG controller 558 * @qh: QH for the periodic transfer 559 */ 560 STATIC void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg, 561 struct dwc2_qh *qh) 562 { 563 int i; 564 565 qh->linked = 0; 566 567 /* Update claimed usecs per (micro)frame */ 568 hsotg->periodic_usecs -= qh->usecs; 569 570 if (hsotg->core_params->uframe_sched > 0) { 571 for (i = 0; i < 8; i++) { 572 hsotg->frame_usecs[i] += qh->frame_usecs[i]; 573 qh->frame_usecs[i] = 0; 574 } 575 } else { 576 /* Release periodic channel reservation */ 577 hsotg->periodic_channels--; 578 } 579 } 580 581 /** 582 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic 583 * schedule if it is not already in the schedule. If the QH is already in 584 * the schedule, no action is taken. 585 * 586 * @hsotg: The HCD state structure for the DWC OTG controller 587 * @qh: The QH to add 588 * 589 * Return: 0 if successful, negative error code otherwise 590 */ 591 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 592 { 593 int status; 594 u32 intr_mask; 595 596 if (dbg_qh(qh)) 597 dev_vdbg(hsotg->dev, "%s()\n", __func__); 598 599 if (qh->linked != 0) { 600 /* QH already in a schedule */ 601 return 0; 602 } 603 604 /* Add the new QH to the appropriate schedule */ 605 if (dwc2_qh_is_non_per(qh)) { 606 /* Always start in inactive schedule */ 607 TAILQ_INSERT_TAIL(&hsotg->non_periodic_sched_inactive, qh, qh_list_entry); 608 qh->linked = 1; 609 return 0; 610 } 611 status = dwc2_schedule_periodic(hsotg, qh); 612 if (status) 613 return status; 614 if (!hsotg->periodic_qh_count) { 615 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 616 intr_mask |= GINTSTS_SOF; 617 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); 618 } 619 hsotg->periodic_qh_count++; 620 621 return 0; 622 } 623 624 /** 625 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic 626 * schedule. Memory is not freed. 627 * 628 * @hsotg: The HCD state structure 629 * @qh: QH to remove from schedule 630 */ 631 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 632 { 633 u32 intr_mask; 634 635 dev_vdbg(hsotg->dev, "%s()\n", __func__); 636 637 if (qh->linked == 0) { 638 /* QH is not in a schedule */ 639 return; 640 } 641 642 if (dwc2_qh_is_non_per(qh)) { 643 if (hsotg->non_periodic_qh_ptr == qh) { 644 hsotg->non_periodic_qh_ptr = 645 TAILQ_NEXT(qh, qh_list_entry); 646 } 647 648 if (qh->channel) { 649 TAILQ_REMOVE(&hsotg->non_periodic_sched_active, qh, qh_list_entry); 650 } else { 651 TAILQ_REMOVE(&hsotg->non_periodic_sched_inactive, qh, qh_list_entry); 652 } 653 qh->linked = 0; 654 655 if (hsotg->non_periodic_qh_ptr == NULL) 656 hsotg->non_periodic_qh_ptr = TAILQ_FIRST(&hsotg->non_periodic_sched_active); 657 return; 658 } 659 dwc2_deschedule_periodic(hsotg, qh); 660 hsotg->periodic_qh_count--; 661 if (!hsotg->periodic_qh_count) { 662 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 663 intr_mask &= ~GINTSTS_SOF; 664 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); 665 } 666 } 667 668 /* 669 * Schedule the next continuing periodic split transfer 670 */ 671 STATIC void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg, 672 struct dwc2_qh *qh, u16 frame_number, 673 int sched_next_periodic_split) 674 { 675 u16 incr; 676 677 if (sched_next_periodic_split) { 678 qh->sched_frame = frame_number; 679 incr = dwc2_frame_num_inc(qh->start_split_frame, 1); 680 if (dwc2_frame_num_le(frame_number, incr)) { 681 /* 682 * Allow one frame to elapse after start split 683 * microframe before scheduling complete split, but 684 * DON'T if we are doing the next start split in the 685 * same frame for an ISOC out 686 */ 687 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC || 688 qh->ep_is_in != 0) { 689 qh->sched_frame = 690 dwc2_frame_num_inc(qh->sched_frame, 1); 691 } 692 } 693 } else { 694 qh->sched_frame = dwc2_frame_num_inc(qh->start_split_frame, 695 qh->interval); 696 if (dwc2_frame_num_le(qh->sched_frame, frame_number)) 697 qh->sched_frame = frame_number; 698 qh->sched_frame |= 0x7; 699 qh->start_split_frame = qh->sched_frame; 700 } 701 } 702 703 /* 704 * Deactivates a QH. For non-periodic QHs, removes the QH from the active 705 * non-periodic schedule. The QH is added to the inactive non-periodic 706 * schedule if any QTDs are still attached to the QH. 707 * 708 * For periodic QHs, the QH is removed from the periodic queued schedule. If 709 * there are any QTDs still attached to the QH, the QH is added to either the 710 * periodic inactive schedule or the periodic ready schedule and its next 711 * scheduled frame is calculated. The QH is placed in the ready schedule if 712 * the scheduled frame has been reached already. Otherwise it's placed in the 713 * inactive schedule. If there are no QTDs attached to the QH, the QH is 714 * completely removed from the periodic schedule. 715 */ 716 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 717 int sched_next_periodic_split) 718 { 719 u16 frame_number; 720 721 if (dbg_qh(qh)) 722 dev_vdbg(hsotg->dev, "%s()\n", __func__); 723 724 if (dwc2_qh_is_non_per(qh)) { 725 dwc2_hcd_qh_unlink(hsotg, qh); 726 if (!TAILQ_EMPTY(&qh->qtd_list)) 727 /* Add back to inactive non-periodic schedule */ 728 dwc2_hcd_qh_add(hsotg, qh); 729 return; 730 } 731 732 frame_number = dwc2_hcd_get_frame_number(hsotg); 733 734 if (qh->do_split) { 735 dwc2_sched_periodic_split(hsotg, qh, frame_number, 736 sched_next_periodic_split); 737 } else { 738 qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame, 739 qh->interval); 740 if (dwc2_frame_num_le(qh->sched_frame, frame_number)) 741 qh->sched_frame = frame_number; 742 } 743 744 if (TAILQ_EMPTY(&qh->qtd_list)) { 745 dwc2_hcd_qh_unlink(hsotg, qh); 746 return; 747 } 748 /* 749 * Remove from periodic_sched_queued and move to 750 * appropriate queue 751 */ 752 TAILQ_REMOVE(&hsotg->periodic_sched_queued, qh, qh_list_entry); 753 if ((hsotg->core_params->uframe_sched > 0 && 754 dwc2_frame_num_le(qh->sched_frame, frame_number)) || 755 (hsotg->core_params->uframe_sched <= 0 && 756 qh->sched_frame == frame_number)) { 757 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_ready, qh, qh_list_entry); 758 } else { 759 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_inactive, qh, qh_list_entry); 760 } 761 } 762 763 /** 764 * dwc2_hcd_qtd_init() - Initializes a QTD structure 765 * 766 * @qtd: The QTD to initialize 767 * @urb: The associated URB 768 */ 769 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 770 { 771 qtd->urb = urb; 772 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) == 773 USB_ENDPOINT_XFER_CONTROL) { 774 /* 775 * The only time the QTD data toggle is used is on the data 776 * phase of control transfers. This phase always starts with 777 * DATA1. 778 */ 779 qtd->data_toggle = DWC2_HC_PID_DATA1; 780 qtd->control_phase = DWC2_CONTROL_SETUP; 781 } 782 783 /* Start split */ 784 qtd->complete_split = 0; 785 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; 786 qtd->isoc_split_offset = 0; 787 qtd->in_process = 0; 788 789 /* Store the qtd ptr in the urb to reference the QTD */ 790 urb->qtd = qtd; 791 } 792 793 /** 794 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH 795 * 796 * @hsotg: The DWC HCD structure 797 * @qtd: The QTD to add 798 * @qh: Out parameter to return queue head 799 * @mem_flags: Flag to do atomic alloc if needed 800 * 801 * Return: 0 if successful, negative error code otherwise 802 * 803 * Finds the correct QH to place the QTD into. If it does not find a QH, it 804 * will create a new QH. If the QH to which the QTD is added is not currently 805 * scheduled, it is placed into the proper schedule based on its EP type. 806 * 807 * HCD lock must be held and interrupts must be disabled on entry 808 */ 809 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 810 struct dwc2_qh **qh, gfp_t mem_flags) 811 { 812 struct dwc2_hcd_urb *urb = qtd->urb; 813 int allocated = 0; 814 int retval; 815 816 /* 817 * Get the QH which holds the QTD-list to insert to. Create QH if it 818 * doesn't exist. 819 */ 820 if (*qh == NULL) { 821 *qh = dwc2_hcd_qh_create(hsotg, urb, mem_flags); 822 if (*qh == NULL) 823 return -ENOMEM; 824 allocated = 1; 825 } 826 827 retval = dwc2_hcd_qh_add(hsotg, *qh); 828 if (retval) 829 goto fail; 830 831 qtd->qh = *qh; 832 TAILQ_INSERT_TAIL(&(*qh)->qtd_list, qtd, qtd_list_entry); 833 834 return 0; 835 836 fail: 837 if (allocated) { 838 struct dwc2_qtd *qtd2, *qtd2_tmp; 839 struct dwc2_qh *qh_tmp = *qh; 840 841 *qh = NULL; 842 dwc2_hcd_qh_unlink(hsotg, qh_tmp); 843 844 /* Free each QTD in the QH's QTD list */ 845 TAILQ_FOREACH_SAFE(qtd2, &qh_tmp->qtd_list, qtd_list_entry, qtd2_tmp) 846 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh_tmp); 847 848 dwc2_hcd_qh_free(hsotg, qh_tmp); 849 } 850 851 return retval; 852 } 853 854 void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 855 struct dwc2_qtd *qtd, 856 struct dwc2_qh *qh) 857 { 858 struct dwc2_softc *sc = hsotg->hsotg_sc; 859 860 TAILQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); 861 pool_put(&sc->sc_qtdpool, qtd); 862 } 863 864 #define BITSTUFFTIME(bytecount) ((8 * 7 * (bytecount)) / 6) 865 #define HS_HOST_DELAY 5 /* nanoseconds */ 866 #define FS_LS_HOST_DELAY 1000 /* nanoseconds */ 867 #define HUB_LS_SETUP 333 /* nanoseconds */ 868 869 STATIC u32 dwc2_calc_bus_time(struct dwc2_hsotg *hsotg, int speed, int is_in, 870 int is_isoc, int bytecount) 871 { 872 unsigned long retval; 873 874 switch (speed) { 875 case USB_SPEED_HIGH: 876 if (is_isoc) 877 retval = 878 ((38 * 8 * 2083) + 879 (2083 * (3 + BITSTUFFTIME(bytecount)))) / 1000 + 880 HS_HOST_DELAY; 881 else 882 retval = 883 ((55 * 8 * 2083) + 884 (2083 * (3 + BITSTUFFTIME(bytecount)))) / 1000 + 885 HS_HOST_DELAY; 886 break; 887 case USB_SPEED_FULL: 888 if (is_isoc) { 889 retval = 890 (8354 * (31 + 10 * BITSTUFFTIME(bytecount))) / 1000; 891 if (is_in) 892 retval = 7268 + FS_LS_HOST_DELAY + retval; 893 else 894 retval = 6265 + FS_LS_HOST_DELAY + retval; 895 } else { 896 retval = 897 (8354 * (31 + 10 * BITSTUFFTIME(bytecount))) / 1000; 898 retval = 9107 + FS_LS_HOST_DELAY + retval; 899 } 900 break; 901 case USB_SPEED_LOW: 902 if (is_in) { 903 retval = 904 (67667 * (31 + 10 * BITSTUFFTIME(bytecount))) / 905 1000; 906 retval = 907 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + 908 retval; 909 } else { 910 retval = 911 (66700 * (31 + 10 * BITSTUFFTIME(bytecount))) / 912 1000; 913 retval = 914 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + 915 retval; 916 } 917 break; 918 default: 919 dev_warn(hsotg->dev, "Unknown device speed\n"); 920 retval = -1; 921 } 922 923 return NS_TO_US(retval); 924 } 925