1 /* $OpenBSD: dwc2_hcd.h,v 1.13 2015/06/28 11:48:18 jmatthew Exp $ */ 2 /* $NetBSD: dwc2_hcd.h,v 1.9 2014/09/03 10:00:08 skrll Exp $ */ 3 4 /* 5 * hcd.h - DesignWare HS OTG Controller host-mode declarations 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 #ifndef __DWC2_HCD_H__ 40 #define __DWC2_HCD_H__ 41 42 /* 43 * This file contains the structures, constants, and interfaces for the 44 * Host Contoller Driver (HCD) 45 * 46 * The Host Controller Driver (HCD) is responsible for translating requests 47 * from the USB Driver into the appropriate actions on the DWC_otg controller. 48 * It isolates the USBD from the specifics of the controller by providing an 49 * API to the USBD. 50 */ 51 52 struct dwc2_qh; 53 54 /** 55 * struct dwc2_host_chan - Software host channel descriptor 56 * 57 * @hc_num: Host channel number, used for register address lookup 58 * @dev_addr: Address of the device 59 * @ep_num: Endpoint of the device 60 * @ep_is_in: Endpoint direction 61 * @speed: Device speed. One of the following values: 62 * - USB_SPEED_LOW 63 * - USB_SPEED_FULL 64 * - USB_SPEED_HIGH 65 * @ep_type: Endpoint type. One of the following values: 66 * - USB_ENDPOINT_XFER_CONTROL: 0 67 * - USB_ENDPOINT_XFER_ISOC: 1 68 * - USB_ENDPOINT_XFER_BULK: 2 69 * - USB_ENDPOINT_XFER_INTR: 3 70 * @max_packet: Max packet size in bytes 71 * @data_pid_start: PID for initial transaction. 72 * 0: DATA0 73 * 1: DATA2 74 * 2: DATA1 75 * 3: MDATA (non-Control EP), 76 * SETUP (Control EP) 77 * @multi_count: Number of additional periodic transactions per 78 * (micro)frame 79 * @xfer_buf: Pointer to current transfer buffer position 80 * @xfer_dma: DMA address of xfer_buf 81 * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not 82 * DWORD aligned 83 * @xfer_len: Total number of bytes to transfer 84 * @xfer_count: Number of bytes transferred so far 85 * @start_pkt_count: Packet count at start of transfer 86 * @xfer_started: True if the transfer has been started 87 * @ping: True if a PING request should be issued on this channel 88 * @error_state: True if the error count for this transaction is non-zero 89 * @halt_on_queue: True if this channel should be halted the next time a 90 * request is queued for the channel. This is necessary in 91 * slave mode if no request queue space is available when 92 * an attempt is made to halt the channel. 93 * @halt_pending: True if the host channel has been halted, but the core 94 * is not finished flushing queued requests 95 * @do_split: Enable split for the channel 96 * @complete_split: Enable complete split 97 * @hub_addr: Address of high speed hub for the split 98 * @hub_port: Port of the low/full speed device for the split 99 * @xact_pos: Split transaction position. One of the following values: 100 * - DWC2_HCSPLT_XACTPOS_MID 101 * - DWC2_HCSPLT_XACTPOS_BEGIN 102 * - DWC2_HCSPLT_XACTPOS_END 103 * - DWC2_HCSPLT_XACTPOS_ALL 104 * @requests: Number of requests issued for this channel since it was 105 * assigned to the current transfer (not counting PINGs) 106 * @schinfo: Scheduling micro-frame bitmap 107 * @ntd: Number of transfer descriptors for the transfer 108 * @halt_status: Reason for halting the host channel 109 * @hcint Contents of the HCINT register when the interrupt came 110 * @qh: QH for the transfer being processed by this channel 111 * @hc_list_entry: For linking to list of host channels 112 * @desc_list_addr: Current QH's descriptor list DMA address 113 * 114 * This structure represents the state of a single host channel when acting in 115 * host mode. It contains the data items needed to transfer packets to an 116 * endpoint via a host channel. 117 */ 118 struct dwc2_host_chan { 119 u8 hc_num; 120 121 unsigned dev_addr:7; 122 unsigned ep_num:4; 123 unsigned ep_is_in:1; 124 unsigned speed:4; 125 unsigned ep_type:2; 126 unsigned max_packet:11; 127 unsigned data_pid_start:2; 128 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0 129 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2 130 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1 131 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA 132 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP 133 134 unsigned multi_count:2; 135 136 struct usb_dma *xfer_usbdma; 137 u8 *xfer_buf; 138 dma_addr_t xfer_dma; 139 dma_addr_t align_buf; 140 u32 xfer_len; 141 u32 xfer_count; 142 u16 start_pkt_count; 143 u8 xfer_started; 144 u8 do_ping; 145 u8 error_state; 146 u8 halt_on_queue; 147 u8 halt_pending; 148 u8 do_split; 149 u8 complete_split; 150 u8 hub_addr; 151 u8 hub_port; 152 u8 xact_pos; 153 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID 154 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END 155 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN 156 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL 157 158 u8 requests; 159 u8 schinfo; 160 u16 ntd; 161 enum dwc2_halt_status halt_status; 162 u32 hcint; 163 struct dwc2_qh *qh; 164 LIST_ENTRY(dwc2_host_chan) hc_list_entry; 165 dma_addr_t desc_list_addr; 166 int in_freelist; 167 }; 168 169 struct dwc2_hcd_pipe_info { 170 u8 dev_addr; 171 u8 ep_num; 172 u8 pipe_type; 173 u8 pipe_dir; 174 u16 mps; 175 }; 176 177 struct dwc2_hcd_iso_packet_desc { 178 u32 offset; 179 u32 length; 180 u32 actual_length; 181 u32 status; 182 }; 183 184 struct dwc2_qtd; 185 186 struct dwc2_hcd_urb { 187 void *priv; /* the xfer handle */ 188 struct dwc2_qtd *qtd; 189 struct usb_dma *usbdma; 190 u8 *buf; 191 dma_addr_t dma; 192 struct usb_dma *setup_usbdma; 193 void *setup_packet; 194 dma_addr_t setup_dma; 195 u32 length; 196 u32 actual_length; 197 u32 status; 198 u32 error_count; 199 u32 packet_count; 200 u32 flags; 201 u16 interval; 202 struct dwc2_hcd_pipe_info pipe_info; 203 struct dwc2_hcd_iso_packet_desc iso_descs[0]; 204 }; 205 206 /* Phases for control transfers */ 207 enum dwc2_control_phase { 208 DWC2_CONTROL_SETUP, 209 DWC2_CONTROL_DATA, 210 DWC2_CONTROL_STATUS, 211 }; 212 213 /* Transaction types */ 214 enum dwc2_transaction_type { 215 DWC2_TRANSACTION_NONE, 216 DWC2_TRANSACTION_PERIODIC, 217 DWC2_TRANSACTION_NON_PERIODIC, 218 DWC2_TRANSACTION_ALL, 219 }; 220 221 /** 222 * struct dwc2_qh - Software queue head structure 223 * 224 * @ep_type: Endpoint type. One of the following values: 225 * - USB_ENDPOINT_XFER_CONTROL 226 * - USB_ENDPOINT_XFER_BULK 227 * - USB_ENDPOINT_XFER_INT 228 * - USB_ENDPOINT_XFER_ISOC 229 * @ep_is_in: Endpoint direction 230 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor 231 * @dev_speed: Device speed. One of the following values: 232 * - USB_SPEED_LOW 233 * - USB_SPEED_FULL 234 * - USB_SPEED_HIGH 235 * @data_toggle: Determines the PID of the next data packet for 236 * non-controltransfers. Ignored for control transfers. 237 * One of the following values: 238 * - DWC2_HC_PID_DATA0 239 * - DWC2_HC_PID_DATA1 240 * @ping_state: Ping state 241 * @do_split: Full/low speed endpoint on high-speed hub requires split 242 * @td_first: Index of first activated isochronous transfer descriptor 243 * @td_last: Index of last activated isochronous transfer descriptor 244 * @usecs: Bandwidth in microseconds per (micro)frame 245 * @interval: Interval between transfers in (micro)frames 246 * @sched_frame: (Micro)frame to initialize a periodic transfer. 247 * The transfer executes in the following (micro)frame. 248 * @nak_frame: Internal variable used by the NAK holdoff code 249 * @frame_usecs: Internal variable used by the microframe scheduler 250 * @start_split_frame: (Micro)frame at which last start split was initialized 251 * @ntd: Actual number of transfer descriptors in a list 252 * @dw_align_buf: Used instead of original buffer if its physical address 253 * is not dword-aligned 254 * @dw_align_buf_dma: DMA address for align_buf 255 * @qtd_list: List of QTDs for this QH 256 * @channel: Host channel currently processing transfers for this QH 257 * @qh_list_entry: Entry for QH in either the periodic or non-periodic 258 * schedule 259 * @desc_list: List of transfer descriptors 260 * @desc_list_dma: Physical address of desc_list 261 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer 262 * descriptor and indicates original XferSize value for the 263 * descriptor 264 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending 265 * 266 * A Queue Head (QH) holds the static characteristics of an endpoint and 267 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may 268 * be entered in either the non-periodic or periodic schedule. 269 */ 270 struct dwc2_qh { 271 u8 ep_type; 272 u8 ep_is_in; 273 u16 maxp; 274 u8 dev_speed; 275 u8 data_toggle; 276 u8 ping_state; 277 u8 do_split; 278 u8 td_first; 279 u8 td_last; 280 u16 usecs; 281 u16 interval; 282 u16 sched_frame; 283 u16 nak_frame; 284 u16 frame_usecs[8]; 285 u16 start_split_frame; 286 u16 ntd; 287 struct usb_dma dw_align_buf_usbdma; 288 u8 *dw_align_buf; 289 dma_addr_t dw_align_buf_dma; 290 TAILQ_HEAD(, dwc2_qtd) qtd_list; 291 struct dwc2_host_chan *channel; 292 TAILQ_ENTRY(dwc2_qh) qh_list_entry; 293 struct usb_dma desc_list_usbdma; 294 struct dwc2_hcd_dma_desc *desc_list; 295 dma_addr_t desc_list_dma; 296 u32 *n_bytes; 297 unsigned tt_buffer_dirty:1; 298 unsigned linked:1; 299 }; 300 301 /** 302 * struct dwc2_qtd - Software queue transfer descriptor (QTD) 303 * 304 * @control_phase: Current phase for control transfers (Setup, Data, or 305 * Status) 306 * @in_process: Indicates if this QTD is currently processed by HW 307 * @data_toggle: Determines the PID of the next data packet for the 308 * data phase of control transfers. Ignored for other 309 * transfer types. One of the following values: 310 * - DWC2_HC_PID_DATA0 311 * - DWC2_HC_PID_DATA1 312 * @complete_split: Keeps track of the current split type for FS/LS 313 * endpoints on a HS Hub 314 * @isoc_split_pos: Position of the ISOC split in full/low speed 315 * @isoc_frame_index: Index of the next frame descriptor for an isochronous 316 * transfer. A frame descriptor describes the buffer 317 * position and length of the data to be transferred in the 318 * next scheduled (micro)frame of an isochronous transfer. 319 * It also holds status for that transaction. The frame 320 * index starts at 0. 321 * @isoc_split_offset: Position of the ISOC split in the buffer for the 322 * current frame 323 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT 324 * @error_count: Holds the number of bus errors that have occurred for 325 * a transaction within this transfer 326 * @n_desc: Number of DMA descriptors for this QTD 327 * @isoc_frame_index_last: Last activated frame (packet) index, used in 328 * descriptor DMA mode only 329 * @urb: URB for this transfer 330 * @qh: Queue head for this QTD 331 * @qtd_list_entry: For linking to the QH's list of QTDs 332 * 333 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, 334 * interrupt, or isochronous transfer. A single QTD is created for each URB 335 * (of one of these types) submitted to the HCD. The transfer associated with 336 * a QTD may require one or multiple transactions. 337 * 338 * A QTD is linked to a Queue Head, which is entered in either the 339 * non-periodic or periodic schedule for execution. When a QTD is chosen for 340 * execution, some or all of its transactions may be executed. After 341 * execution, the state of the QTD is updated. The QTD may be retired if all 342 * its transactions are complete or if an error occurred. Otherwise, it 343 * remains in the schedule so more transactions can be executed later. 344 */ 345 struct dwc2_qtd { 346 enum dwc2_control_phase control_phase; 347 u8 in_process; 348 u8 data_toggle; 349 u8 complete_split; 350 u8 isoc_split_pos; 351 u16 isoc_frame_index; 352 u16 isoc_split_offset; 353 u32 ssplit_out_xfer_count; 354 u8 error_count; 355 u8 n_desc; 356 u16 isoc_frame_index_last; 357 struct dwc2_hcd_urb *urb; 358 struct dwc2_qh *qh; 359 TAILQ_ENTRY(dwc2_qtd) qtd_list_entry; 360 }; 361 362 #ifdef DEBUG 363 struct hc_xfer_info { 364 struct dwc2_hsotg *hsotg; 365 struct dwc2_host_chan *chan; 366 }; 367 #endif 368 369 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ 370 STATIC_INLINE struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) 371 { 372 return (struct usb_hcd *)hsotg->priv; 373 } 374 375 /* 376 * Inline used to disable one channel interrupt. Channel interrupts are 377 * disabled when the channel is halted or released by the interrupt handler. 378 * There is no need to handle further interrupts of that type until the 379 * channel is re-assigned. In fact, subsequent handling may cause crashes 380 * because the channel structures are cleaned up when the channel is released. 381 */ 382 STATIC_INLINE void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 383 { 384 u32 mask = DWC2_READ_4(hsotg, HCINTMSK(chnum)); 385 386 mask &= ~intr; 387 DWC2_WRITE_4(hsotg, HCINTMSK(chnum), mask); 388 } 389 390 /* 391 * Returns the mode of operation, host or device 392 */ 393 STATIC_INLINE int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 394 { 395 return (DWC2_READ_4(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 396 } 397 398 STATIC_INLINE int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 399 { 400 return (DWC2_READ_4(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 401 } 402 403 /* 404 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they 405 * are read as 1, they won't clear when written back. 406 */ 407 STATIC_INLINE u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 408 { 409 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 410 411 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 412 return hprt0; 413 } 414 415 STATIC_INLINE u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) 416 { 417 return pipe->ep_num; 418 } 419 420 STATIC_INLINE u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) 421 { 422 return pipe->pipe_type; 423 } 424 425 STATIC_INLINE u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe) 426 { 427 return pipe->mps; 428 } 429 430 STATIC_INLINE u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) 431 { 432 return pipe->dev_addr; 433 } 434 435 STATIC_INLINE u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe) 436 { 437 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; 438 } 439 440 STATIC_INLINE u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe) 441 { 442 return pipe->pipe_type == USB_ENDPOINT_XFER_INT; 443 } 444 445 STATIC_INLINE u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) 446 { 447 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; 448 } 449 450 STATIC_INLINE u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) 451 { 452 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; 453 } 454 455 STATIC_INLINE u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) 456 { 457 return pipe->pipe_dir == USB_DIR_IN; 458 } 459 460 STATIC_INLINE u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) 461 { 462 return !dwc2_hcd_is_pipe_in(pipe); 463 } 464 465 extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg, 466 const struct dwc2_core_params *params); 467 extern int dwc2_hcd_dma_config(struct dwc2_hsotg *hsotg, 468 struct dwc2_core_dma_config *config); 469 extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); 470 extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 471 const struct dwc2_core_params *params); 472 extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); 473 extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 474 475 /* Transaction Execution Functions */ 476 extern enum dwc2_transaction_type dwc2_hcd_select_transactions( 477 struct dwc2_hsotg *hsotg); 478 extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 479 enum dwc2_transaction_type tr_type); 480 481 /* Schedule Queue Functions */ 482 /* Implemented in hcd_queue.c */ 483 extern void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg); 484 extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 485 extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 486 extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 487 extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 488 int sched_csplit); 489 490 extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 491 extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 492 struct dwc2_qh **qh, int mem_flags); 493 494 /* Removes and frees a QTD */ 495 extern void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 496 struct dwc2_qtd *qtd, 497 struct dwc2_qh *qh); 498 499 /* Descriptor DMA support functions */ 500 extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, 501 struct dwc2_qh *qh); 502 extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 503 struct dwc2_host_chan *chan, int chnum, 504 enum dwc2_halt_status halt_status); 505 506 extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 507 gfp_t mem_flags); 508 extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 509 510 /* Check if QH is non-periodic */ 511 #define dwc2_qh_is_non_per(_qh_ptr_) \ 512 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ 513 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) 514 515 #ifdef DWC2_DEBUG 516 STATIC_INLINE bool dbg_hc(struct dwc2_host_chan *hc) { return true; } 517 STATIC_INLINE bool dbg_qh(struct dwc2_qh *qh) { return true; } 518 STATIC_INLINE bool dbg_perio(void) { return true; } 519 #else /* !DWC2_DEBUG */ 520 STATIC_INLINE bool dbg_hc(struct dwc2_host_chan *hc) 521 { 522 return hc->ep_type == USB_ENDPOINT_XFER_BULK || 523 hc->ep_type == USB_ENDPOINT_XFER_CONTROL; 524 } 525 526 STATIC_INLINE bool dbg_qh(struct dwc2_qh *qh) 527 { 528 return qh->ep_type == USB_ENDPOINT_XFER_BULK || 529 qh->ep_type == USB_ENDPOINT_XFER_CONTROL; 530 } 531 532 533 STATIC_INLINE bool dbg_perio(void) { return false; } 534 #endif 535 536 /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */ 537 #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03)) 538 539 /* Packet size for any kind of endpoint descriptor */ 540 #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff) 541 542 /* 543 * Returns true if frame1 is less than or equal to frame2. The comparison is 544 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the 545 * frame number when the max frame number is reached. 546 */ 547 STATIC_INLINE int dwc2_frame_num_le(u16 frame1, u16 frame2) 548 { 549 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); 550 } 551 552 /* 553 * Returns true if frame1 is greater than frame2. The comparison is done 554 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame 555 * number when the max frame number is reached. 556 */ 557 STATIC_INLINE int dwc2_frame_num_gt(u16 frame1, u16 frame2) 558 { 559 return (frame1 != frame2) && 560 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); 561 } 562 563 /* 564 * Increments frame by the amount specified by inc. The addition is done 565 * modulo HFNUM_MAX_FRNUM. Returns the incremented value. 566 */ 567 STATIC_INLINE u16 dwc2_frame_num_inc(u16 frame, u16 inc) 568 { 569 return (frame + inc) & HFNUM_MAX_FRNUM; 570 } 571 572 STATIC_INLINE u16 dwc2_full_frame_num(u16 frame) 573 { 574 return (frame & HFNUM_MAX_FRNUM) >> 3; 575 } 576 577 STATIC_INLINE u16 dwc2_micro_frame_num(u16 frame) 578 { 579 return frame & 0x7; 580 } 581 582 /* 583 * Returns the Core Interrupt Status register contents, ANDed with the Core 584 * Interrupt Mask register contents 585 */ 586 STATIC_INLINE u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 587 { 588 return DWC2_READ_4(hsotg, GINTSTS) & DWC2_READ_4(hsotg, GINTMSK); 589 } 590 591 STATIC_INLINE u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 592 { 593 return dwc2_urb->status; 594 } 595 596 STATIC_INLINE u32 dwc2_hcd_urb_get_actual_length( 597 struct dwc2_hcd_urb *dwc2_urb) 598 { 599 return dwc2_urb->actual_length; 600 } 601 602 STATIC_INLINE u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) 603 { 604 return dwc2_urb->error_count; 605 } 606 607 STATIC_INLINE void dwc2_hcd_urb_set_iso_desc_params( 608 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset, 609 u32 length) 610 { 611 dwc2_urb->iso_descs[desc_num].offset = offset; 612 dwc2_urb->iso_descs[desc_num].length = length; 613 } 614 615 STATIC_INLINE u32 dwc2_hcd_urb_get_iso_desc_status( 616 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 617 { 618 return dwc2_urb->iso_descs[desc_num].status; 619 } 620 621 STATIC_INLINE u32 dwc2_hcd_urb_get_iso_desc_actual_length( 622 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 623 { 624 return dwc2_urb->iso_descs[desc_num].actual_length; 625 } 626 627 STATIC_INLINE int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, 628 struct usbd_xfer *xfer) 629 { 630 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 631 struct dwc2_qh *qh = dpipe->priv; 632 633 if (qh && qh->linked) 634 return 1; 635 636 return 0; 637 } 638 639 STATIC_INLINE u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, 640 struct dwc2_pipe *dpipe) 641 { 642 struct dwc2_qh *qh = dpipe->priv; 643 644 if (!qh) { 645 WARN_ON(1); 646 return 0; 647 } 648 649 return qh->usecs; 650 } 651 652 extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 653 struct dwc2_host_chan *chan, int chnum, 654 struct dwc2_qtd *qtd); 655 656 /* HCD Core API */ 657 658 /** 659 * dwc2_handle_hcd_intr() - Called on every hardware interrupt 660 * 661 * @hsotg: The DWC2 HCD 662 * 663 * Returns IRQ_HANDLED if interrupt is handled 664 * Return IRQ_NONE if interrupt is not handled 665 */ 666 extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); 667 668 /** 669 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation 670 * 671 * @hsotg: The DWC2 HCD 672 */ 673 extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); 674 675 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 676 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg); 677 678 /** 679 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, 680 * and 0 otherwise 681 * 682 * @hsotg: The DWC2 HCD 683 */ 684 extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); 685 686 /** 687 * dwc2_hcd_get_frame_number() - Returns current frame number 688 * 689 * @hsotg: The DWC2 HCD 690 */ 691 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 692 693 /** 694 * dwc2_hcd_dump_state() - Dumps hsotg state 695 * 696 * @hsotg: The DWC2 HCD 697 * 698 * NOTE: This function will be removed once the peripheral controller code 699 * is integrated and the driver is stable 700 */ 701 extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); 702 703 /** 704 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF 705 * 706 * @hsotg: The DWC2 HCD 707 * 708 * This can be used to determine average interrupt latency. Frame remaining is 709 * also shown for start transfer and two additional sample points. 710 * 711 * NOTE: This function will be removed once the peripheral controller code 712 * is integrated and the driver is stable 713 */ 714 extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg); 715 716 /* URB interface */ 717 718 /* Transfer flags */ 719 #define URB_GIVEBACK_ASAP 0x1 720 #define URB_SEND_ZERO_PACKET 0x2 721 722 /* Host driver callbacks */ 723 724 extern void dwc2_host_start(struct dwc2_hsotg *hsotg); 725 extern void dwc2_host_disconnect(struct dwc2_hsotg *hsotg); 726 extern void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 727 int *hub_addr, int *hub_port); 728 extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); 729 extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 730 int status); 731 732 #ifdef DEBUG 733 /* 734 * Macro to sample the remaining PHY clocks left in the current frame. This 735 * may be used during debugging to determine the average time it takes to 736 * execute sections of code. There are two possible sample points, "a" and 737 * "b", so the _letter_ argument must be one of these values. 738 * 739 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For 740 * example, "cat /sys/devices/lm0/hcd_frrem". 741 */ 742 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \ 743 do { \ 744 struct hfnum_data _hfnum_; \ 745 struct dwc2_qtd *_qtd_; \ 746 \ 747 _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \ 748 qtd_list_entry); \ 749 if (usb_pipeint(_qtd_->urb->pipe) && \ 750 (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \ 751 _hfnum_.d32 = DWC2_READ_4(hsotg, (_hcd_)->regs + HFNUM); \ 752 switch (_hfnum_.b.frnum & 0x7) { \ 753 case 7: \ 754 (_hcd_)->hfnum_7_samples_##_letter_++; \ 755 (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \ 756 _hfnum_.b.frrem; \ 757 break; \ 758 case 0: \ 759 (_hcd_)->hfnum_0_samples_##_letter_++; \ 760 (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \ 761 _hfnum_.b.frrem; \ 762 break; \ 763 default: \ 764 (_hcd_)->hfnum_other_samples_##_letter_++; \ 765 (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \ 766 _hfnum_.b.frrem; \ 767 break; \ 768 } \ 769 } \ 770 } while (0) 771 #else 772 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0) 773 #endif 774 775 776 void dwc2_wakeup_detected(void *); 777 778 int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *, struct dwc2_hcd_urb *); 779 void dwc2_hcd_reinit(struct dwc2_hsotg *); 780 int dwc2_hcd_hub_control(struct dwc2_hsotg *, u16, u16, u16, char *, u16); 781 struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *); 782 int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *, struct dwc2_hcd_urb *, void **, 783 gfp_t); 784 void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *, struct dwc2_hcd_urb *, 785 u8 ,u8, u8, u8, u16); 786 787 void dwc2_conn_id_status_change(void *); 788 void dwc2_hcd_start_func(void *); 789 void dwc2_hcd_reset_func(void *); 790 791 struct dwc2_hcd_urb * dwc2_hcd_urb_alloc(struct dwc2_hsotg *, int, gfp_t); 792 void dwc2_hcd_urb_free(struct dwc2_hsotg *, struct dwc2_hcd_urb *, int); 793 794 int _dwc2_hcd_start(struct dwc2_hsotg *); 795 796 int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *); 797 798 #endif /* __DWC2_HCD_H__ */ 799