1 /* $OpenBSD: dwc2_hcd.c,v 1.22 2020/03/21 12:08:31 patrick Exp $ */ 2 /* $NetBSD: dwc2_hcd.c,v 1.15 2014/11/24 10:14:14 skrll Exp $ */ 3 4 /* 5 * hcd.c - DesignWare HS OTG Controller host-mode routines 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * This file contains the core HCD code, and implements the Linux hc_driver 42 * API 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/signal.h> 49 #include <sys/proc.h> 50 #include <sys/pool.h> 51 #include <sys/task.h> 52 53 #include <machine/bus.h> 54 55 #include <dev/usb/usb.h> 56 #include <dev/usb/usbdi.h> 57 #include <dev/usb/usbdivar.h> 58 #include <dev/usb/usb_mem.h> 59 60 #include <dev/usb/dwc2/dwc2.h> 61 #include <dev/usb/dwc2/dwc2var.h> 62 63 #include <dev/usb/dwc2/dwc2_core.h> 64 #include <dev/usb/dwc2/dwc2_hcd.h> 65 66 /** 67 * dwc2_dump_channel_info() - Prints the state of a host channel 68 * 69 * @hsotg: Programming view of DWC_otg controller 70 * @chan: Pointer to the channel to dump 71 * 72 * Must be called with interrupt disabled and spinlock held 73 * 74 * NOTE: This function will be removed once the peripheral controller code 75 * is integrated and the driver is stable 76 */ 77 #ifdef VERBOSE_DEBUG 78 STATIC void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 79 struct dwc2_host_chan *chan) 80 { 81 int num_channels = hsotg->core_params->host_channels; 82 struct dwc2_qh *qh; 83 u32 hcchar; 84 u32 hcsplt; 85 u32 hctsiz; 86 u32 hc_dma; 87 int i; 88 89 if (chan == NULL) 90 return; 91 92 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 93 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chan->hc_num)); 94 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chan->hc_num)); 95 hc_dma = DWC2_READ_4(hsotg, HCDMA(chan->hc_num)); 96 97 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 98 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 99 hcchar, hcsplt); 100 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 101 hctsiz, hc_dma); 102 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 103 chan->dev_addr, chan->ep_num, chan->ep_is_in); 104 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 105 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 106 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 107 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 108 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 109 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 110 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 111 (unsigned long)chan->xfer_dma); 112 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 113 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 114 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 115 TAILQ_FOREACH(qh, &hsotg->non_periodic_sched_inactive, qh_list_entry) 116 dev_dbg(hsotg->dev, " %p\n", qh); 117 dev_dbg(hsotg->dev, " NP active sched:\n"); 118 TAILQ_FOREACH(qh, &hsotg->non_periodic_sched_active, qh_list_entry) 119 dev_dbg(hsotg->dev, " %p\n", qh); 120 dev_dbg(hsotg->dev, " Channels:\n"); 121 for (i = 0; i < num_channels; i++) { 122 struct dwc2_host_chan *ch = hsotg->hc_ptr_array[i]; 123 124 dev_dbg(hsotg->dev, " %2d: %p\n", i, ch); 125 } 126 } 127 #endif /* VERBOSE_DEBUG */ 128 129 /* 130 * Processes all the URBs in a single list of QHs. Completes them with 131 * -ETIMEDOUT and frees the QTD. 132 * 133 * Must be called with interrupt disabled and spinlock held 134 */ 135 STATIC void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 136 struct dwc2_qh_list *qh_list) 137 { 138 struct dwc2_qh *qh, *qh_tmp; 139 struct dwc2_qtd *qtd, *qtd_tmp; 140 141 TAILQ_FOREACH_SAFE(qh, qh_list, qh_list_entry, qh_tmp) { 142 TAILQ_FOREACH_SAFE(qtd, &qh->qtd_list, qtd_list_entry, qtd_tmp) { 143 dwc2_host_complete(hsotg, qtd, -ETIMEDOUT); 144 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 145 } 146 } 147 } 148 149 STATIC void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 150 struct dwc2_qh_list *qh_list) 151 { 152 struct dwc2_qtd *qtd, *qtd_tmp; 153 struct dwc2_qh *qh, *qh_tmp; 154 unsigned long flags; 155 156 if (TAILQ_EMPTY(qh_list)) { 157 /* The list hasn't been initialized yet */ 158 return; 159 } 160 161 spin_lock_irqsave(&hsotg->lock, flags); 162 163 /* Ensure there are no QTDs or URBs left */ 164 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 165 166 TAILQ_FOREACH_SAFE(qh, qh_list, qh_list_entry, qh_tmp) { 167 dwc2_hcd_qh_unlink(hsotg, qh); 168 169 /* Free each QTD in the QH's QTD list */ 170 TAILQ_FOREACH_SAFE(qtd, &qh->qtd_list, qtd_list_entry, qtd_tmp) { 171 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 172 } 173 174 spin_unlock_irqrestore(&hsotg->lock, flags); 175 dwc2_hcd_qh_free(hsotg, qh); 176 spin_lock_irqsave(&hsotg->lock, flags); 177 } 178 179 spin_unlock_irqrestore(&hsotg->lock, flags); 180 } 181 182 /* 183 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 184 * and periodic schedules. The QTD associated with each URB is removed from 185 * the schedule and freed. This function may be called when a disconnect is 186 * detected or when the HCD is being stopped. 187 * 188 * Must be called with interrupt disabled and spinlock held 189 */ 190 STATIC void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 191 { 192 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 193 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 194 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 195 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 196 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 197 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 198 } 199 200 /** 201 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 202 * 203 * @hsotg: Pointer to struct dwc2_hsotg 204 */ 205 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 206 { 207 u32 hprt0; 208 209 if (hsotg->op_state == OTG_STATE_B_HOST) { 210 /* 211 * Reset the port. During a HNP mode switch the reset 212 * needs to occur within 1ms and have a duration of at 213 * least 50ms. 214 */ 215 hprt0 = dwc2_read_hprt0(hsotg); 216 hprt0 |= HPRT0_RST; 217 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 218 } 219 220 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 221 msecs_to_jiffies(50)); 222 } 223 224 /* Must be called with interrupt disabled and spinlock held */ 225 STATIC void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 226 { 227 int num_channels = hsotg->core_params->host_channels; 228 struct dwc2_host_chan *channel; 229 u32 hcchar; 230 int i; 231 232 if (hsotg->core_params->dma_enable <= 0) { 233 /* Flush out any channel requests in slave mode */ 234 for (i = 0; i < num_channels; i++) { 235 channel = hsotg->hc_ptr_array[i]; 236 if (channel->in_freelist == 0) 237 continue; 238 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 239 if (hcchar & HCCHAR_CHENA) { 240 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 241 hcchar |= HCCHAR_CHDIS; 242 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 243 } 244 } 245 } 246 247 for (i = 0; i < num_channels; i++) { 248 channel = hsotg->hc_ptr_array[i]; 249 if (channel->in_freelist != 0) 250 continue; 251 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 252 if (hcchar & HCCHAR_CHENA) { 253 /* Halt the channel */ 254 hcchar |= HCCHAR_CHDIS; 255 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 256 } 257 258 dwc2_hc_cleanup(hsotg, channel); 259 LIST_INSERT_HEAD(&hsotg->free_hc_list, channel, hc_list_entry); 260 channel->in_freelist = 1; 261 /* 262 * Added for Descriptor DMA to prevent channel double cleanup in 263 * release_channel_ddma(), which is called from ep_disable when 264 * device disconnects 265 */ 266 channel->qh = NULL; 267 } 268 } 269 270 /** 271 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 272 * 273 * @hsotg: Pointer to struct dwc2_hsotg 274 * 275 * Must be called with interrupt disabled and spinlock held 276 */ 277 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) 278 { 279 u32 intr; 280 281 /* Set status flags for the hub driver */ 282 hsotg->flags.b.port_connect_status_change = 1; 283 hsotg->flags.b.port_connect_status = 0; 284 285 /* 286 * Shutdown any transfers in process by clearing the Tx FIFO Empty 287 * interrupt mask and status bits and disabling subsequent host 288 * channel interrupts. 289 */ 290 intr = DWC2_READ_4(hsotg, GINTMSK); 291 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 292 DWC2_WRITE_4(hsotg, GINTMSK, intr); 293 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 294 DWC2_WRITE_4(hsotg, GINTSTS, intr); 295 296 /* 297 * Turn off the vbus power only if the core has transitioned to device 298 * mode. If still in host mode, need to keep power on to detect a 299 * reconnection. 300 */ 301 if (dwc2_is_device_mode(hsotg)) { 302 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 303 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 304 DWC2_WRITE_4(hsotg, HPRT0, 0); 305 } 306 307 dwc2_disable_host_interrupts(hsotg); 308 } 309 310 /* Respond with an error status to all URBs in the schedule */ 311 dwc2_kill_all_urbs(hsotg); 312 313 if (dwc2_is_host_mode(hsotg)) 314 /* Clean up any host channels that were in use */ 315 dwc2_hcd_cleanup_channels(hsotg); 316 317 dwc2_host_disconnect(hsotg); 318 319 dwc2_root_intr(hsotg->hsotg_sc); 320 } 321 322 /** 323 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 324 * 325 * @hsotg: Pointer to struct dwc2_hsotg 326 */ 327 STATIC void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 328 { 329 if (hsotg->lx_state == DWC2_L2) 330 hsotg->flags.b.port_suspend_change = 1; 331 else 332 hsotg->flags.b.port_l1_change = 1; 333 334 dwc2_root_intr(hsotg->hsotg_sc); 335 } 336 337 /** 338 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 339 * 340 * @hsotg: Pointer to struct dwc2_hsotg 341 * 342 * Must be called with interrupt disabled and spinlock held 343 */ 344 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 345 { 346 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 347 348 /* 349 * The root hub should be disconnected before this function is called. 350 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 351 * and the QH lists (via ..._hcd_endpoint_disable). 352 */ 353 354 /* Turn off all host-specific interrupts */ 355 dwc2_disable_host_interrupts(hsotg); 356 357 /* Turn off the vbus power */ 358 dev_dbg(hsotg->dev, "PortPower off\n"); 359 DWC2_WRITE_4(hsotg, HPRT0, 0); 360 } 361 362 int 363 dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 364 void **ep_handle, gfp_t mem_flags) 365 { 366 struct dwc2_softc *sc = hsotg->hsotg_sc; 367 struct dwc2_qtd *qtd; 368 u32 intr_mask; 369 int retval; 370 int dev_speed; 371 372 if (!hsotg->flags.b.port_connect_status) { 373 /* No longer connected */ 374 dev_err(hsotg->dev, "Not connected\n"); 375 return -ENODEV; 376 } 377 378 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 379 380 /* Some core configurations cannot support LS traffic on a FS root port */ 381 if ((dev_speed == USB_SPEED_LOW) && 382 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 383 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 384 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 385 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 386 387 if (prtspd == HPRT0_SPD_FULL_SPEED) { 388 return -ENODEV; 389 } 390 } 391 392 qtd = pool_get(&sc->sc_qtdpool, PR_NOWAIT); 393 if (!qtd) 394 return -ENOMEM; 395 396 memset(qtd, 0, sizeof(*qtd)); 397 398 dwc2_hcd_qtd_init(qtd, urb); 399 retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle, 400 mem_flags); 401 if (retval) { 402 dev_err(hsotg->dev, 403 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 404 retval); 405 pool_put(&sc->sc_qtdpool, qtd); 406 return retval; 407 } 408 409 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 410 if (!(intr_mask & GINTSTS_SOF)) { 411 enum dwc2_transaction_type tr_type; 412 413 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 414 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 415 /* 416 * Do not schedule SG transactions until qtd has 417 * URB_GIVEBACK_ASAP set 418 */ 419 return 0; 420 421 tr_type = dwc2_hcd_select_transactions(hsotg); 422 if (tr_type != DWC2_TRANSACTION_NONE) 423 dwc2_hcd_queue_transactions(hsotg, tr_type); 424 } 425 426 return 0; 427 } 428 429 /* Must be called with interrupt disabled and spinlock held */ 430 int 431 dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 432 struct dwc2_hcd_urb *urb) 433 { 434 struct dwc2_qh *qh; 435 struct dwc2_qtd *urb_qtd; 436 437 urb_qtd = urb->qtd; 438 if (!urb_qtd) { 439 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 440 return -EINVAL; 441 } 442 443 qh = urb_qtd->qh; 444 if (!qh) { 445 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 446 return -EINVAL; 447 } 448 449 urb->priv = NULL; 450 451 if (urb_qtd->in_process && qh->channel) { 452 #ifdef VERBOSE_DEBUG 453 dwc2_dump_channel_info(hsotg, qh->channel); 454 #endif 455 /* The QTD is in process (it has been assigned to a channel) */ 456 if (hsotg->flags.b.port_connect_status) 457 /* 458 * If still connected (i.e. in host mode), halt the 459 * channel so it can be used for other transfers. If 460 * no longer connected, the host registers can't be 461 * written to halt the channel since the core is in 462 * device mode. 463 */ 464 dwc2_hc_halt(hsotg, qh->channel, 465 DWC2_HC_XFER_URB_DEQUEUE); 466 } 467 468 /* 469 * Free the QTD and clean up the associated QH. Leave the QH in the 470 * schedule if it has any remaining QTDs. 471 */ 472 if (hsotg->core_params->dma_desc_enable <= 0) { 473 u8 in_process = urb_qtd->in_process; 474 475 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 476 if (in_process) { 477 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 478 qh->channel = NULL; 479 } else if (TAILQ_EMPTY(&qh->qtd_list)) { 480 dwc2_hcd_qh_unlink(hsotg, qh); 481 } 482 } else { 483 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 484 } 485 486 return 0; 487 } 488 489 490 /* 491 * Initializes dynamic portions of the DWC_otg HCD state 492 * 493 * Must be called with interrupt disabled and spinlock held 494 */ 495 void 496 dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 497 { 498 struct dwc2_host_chan *chan, *chan_tmp; 499 int num_channels; 500 int i; 501 502 hsotg->flags.d32 = 0; 503 hsotg->non_periodic_qh_ptr = NULL; 504 505 if (hsotg->core_params->uframe_sched > 0) { 506 hsotg->available_host_channels = 507 hsotg->core_params->host_channels; 508 } else { 509 hsotg->non_periodic_channels = 0; 510 hsotg->periodic_channels = 0; 511 } 512 513 /* 514 * Put all channels in the free channel list and clean up channel 515 * states 516 */ 517 LIST_FOREACH_SAFE(chan, &hsotg->free_hc_list, hc_list_entry, chan_tmp) { 518 LIST_REMOVE(chan, hc_list_entry); 519 chan->in_freelist = 0; 520 } 521 522 num_channels = hsotg->core_params->host_channels; 523 for (i = 0; i < num_channels; i++) { 524 chan = hsotg->hc_ptr_array[i]; 525 LIST_INSERT_HEAD(&hsotg->free_hc_list, chan, hc_list_entry); 526 chan->in_freelist = 1; 527 dwc2_hc_cleanup(hsotg, chan); 528 } 529 530 /* Initialize the DWC core for host mode operation */ 531 dwc2_core_host_init(hsotg); 532 } 533 534 STATIC void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 535 struct dwc2_host_chan *chan, 536 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 537 { 538 int hub_addr, hub_port; 539 540 chan->do_split = 1; 541 chan->xact_pos = qtd->isoc_split_pos; 542 chan->complete_split = qtd->complete_split; 543 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 544 chan->hub_addr = (u8)hub_addr; 545 chan->hub_port = (u8)hub_port; 546 } 547 548 STATIC void *dwc2_hc_init_xfer_data(struct dwc2_hsotg *hsotg, 549 struct dwc2_host_chan *chan, 550 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 551 { 552 if (hsotg->core_params->dma_enable > 0) { 553 chan->xfer_dma = DMAADDR(urb->usbdma, urb->actual_length); 554 555 /* For non-dword aligned case */ 556 if (hsotg->core_params->dma_desc_enable <= 0 && 557 (chan->xfer_dma & 0x3)) 558 return (u8 *)urb->buf + urb->actual_length; 559 } else { 560 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 561 } 562 563 return NULL; 564 } 565 566 STATIC void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 567 struct dwc2_host_chan *chan, 568 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 569 { 570 struct dwc2_hcd_iso_packet_desc *frame_desc; 571 void *bufptr = NULL; 572 573 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 574 case USB_ENDPOINT_XFER_CONTROL: 575 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 576 577 switch (qtd->control_phase) { 578 case DWC2_CONTROL_SETUP: 579 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 580 chan->do_ping = 0; 581 chan->ep_is_in = 0; 582 chan->data_pid_start = DWC2_HC_PID_SETUP; 583 if (hsotg->core_params->dma_enable > 0) 584 chan->xfer_dma = urb->setup_dma; 585 else 586 chan->xfer_buf = urb->setup_packet; 587 chan->xfer_len = 8; 588 break; 589 590 case DWC2_CONTROL_DATA: 591 dev_vdbg(hsotg->dev, " Control data transaction\n"); 592 chan->data_pid_start = qtd->data_toggle; 593 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 594 break; 595 596 case DWC2_CONTROL_STATUS: 597 /* 598 * Direction is opposite of data direction or IN if no 599 * data 600 */ 601 dev_vdbg(hsotg->dev, " Control status transaction\n"); 602 if (urb->length == 0) 603 chan->ep_is_in = 1; 604 else 605 chan->ep_is_in = 606 dwc2_hcd_is_pipe_out(&urb->pipe_info); 607 if (chan->ep_is_in) 608 chan->do_ping = 0; 609 chan->data_pid_start = DWC2_HC_PID_DATA1; 610 chan->xfer_len = 0; 611 if (hsotg->core_params->dma_enable > 0) 612 chan->xfer_dma = hsotg->status_buf_dma; 613 else 614 chan->xfer_buf = hsotg->status_buf; 615 break; 616 } 617 break; 618 619 case USB_ENDPOINT_XFER_BULK: 620 chan->ep_type = USB_ENDPOINT_XFER_BULK; 621 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 622 break; 623 624 case USB_ENDPOINT_XFER_INT: 625 chan->ep_type = USB_ENDPOINT_XFER_INT; 626 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 627 break; 628 629 case USB_ENDPOINT_XFER_ISOC: 630 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 631 if (hsotg->core_params->dma_desc_enable > 0) 632 break; 633 634 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 635 frame_desc->status = 0; 636 637 if (hsotg->core_params->dma_enable > 0) { 638 chan->xfer_dma = urb->dma; 639 chan->xfer_dma += frame_desc->offset + 640 qtd->isoc_split_offset; 641 } else { 642 chan->xfer_buf = urb->buf; 643 chan->xfer_buf += frame_desc->offset + 644 qtd->isoc_split_offset; 645 } 646 647 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 648 649 /* For non-dword aligned buffers */ 650 if (hsotg->core_params->dma_enable > 0 && 651 (chan->xfer_dma & 0x3)) 652 bufptr = (u8 *)urb->buf + frame_desc->offset + 653 qtd->isoc_split_offset; 654 655 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 656 if (chan->xfer_len <= 188) 657 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 658 else 659 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 660 } 661 break; 662 } 663 664 return bufptr; 665 } 666 667 STATIC int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 668 struct dwc2_host_chan *chan, void *bufptr) 669 { 670 u32 buf_size; 671 672 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) 673 buf_size = hsotg->core_params->max_transfer_size; 674 else 675 buf_size = 4096; 676 677 if (!qh->dw_align_buf) { 678 int err; 679 680 qh->dw_align_buf = NULL; 681 qh->dw_align_buf_dma = 0; 682 err = usb_allocmem(&hsotg->hsotg_sc->sc_bus, buf_size, buf_size, 683 USB_DMA_COHERENT, &qh->dw_align_buf_usbdma); 684 if (!err) { 685 struct usb_dma *ud = &qh->dw_align_buf_usbdma; 686 687 qh->dw_align_buf = KERNADDR(ud, 0); 688 qh->dw_align_buf_dma = DMAADDR(ud, 0); 689 } 690 if (!qh->dw_align_buf) 691 return -ENOMEM; 692 } 693 694 if (!chan->ep_is_in && chan->xfer_len) { 695 usb_syncmem(chan->xfer_usbdma, 0, buf_size, 696 BUS_DMASYNC_POSTWRITE); 697 memcpy(qh->dw_align_buf, bufptr, chan->xfer_len); 698 usb_syncmem(chan->xfer_usbdma, 0, buf_size, 699 BUS_DMASYNC_PREWRITE); 700 } 701 702 chan->align_buf = qh->dw_align_buf_dma; 703 return 0; 704 } 705 706 /** 707 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 708 * channel and initializes the host channel to perform the transactions. The 709 * host channel is removed from the free list. 710 * 711 * @hsotg: The HCD state structure 712 * @qh: Transactions from the first QTD for this QH are selected and assigned 713 * to a free host channel 714 */ 715 STATIC int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 716 { 717 struct dwc2_host_chan *chan; 718 struct dwc2_hcd_urb *urb; 719 struct dwc2_qtd *qtd; 720 void *bufptr = NULL; 721 722 if (dbg_qh(qh)) 723 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 724 725 if (TAILQ_EMPTY(&qh->qtd_list)) { 726 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 727 return -ENOMEM; 728 } 729 730 if (LIST_EMPTY(&hsotg->free_hc_list)) { 731 dev_dbg(hsotg->dev, "No free channel to assign\n"); 732 return -ENOMEM; 733 } 734 735 chan = LIST_FIRST(&hsotg->free_hc_list); 736 737 /* Remove host channel from free list */ 738 LIST_REMOVE(chan, hc_list_entry); 739 chan->in_freelist = 0; 740 741 qtd = TAILQ_FIRST(&qh->qtd_list); 742 urb = qtd->urb; 743 qh->channel = chan; 744 qtd->in_process = 1; 745 746 /* 747 * Use usb_pipedevice to determine device address. This address is 748 * 0 before the SET_ADDRESS command and the correct address afterward. 749 */ 750 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 751 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 752 chan->speed = qh->dev_speed; 753 chan->max_packet = dwc2_max_packet(qh->maxp); 754 755 chan->xfer_started = 0; 756 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 757 chan->error_state = (qtd->error_count > 0); 758 chan->halt_on_queue = 0; 759 chan->halt_pending = 0; 760 chan->requests = 0; 761 762 /* 763 * The following values may be modified in the transfer type section 764 * below. The xfer_len value may be reduced when the transfer is 765 * started to accommodate the max widths of the XferSize and PktCnt 766 * fields in the HCTSIZn register. 767 */ 768 769 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 770 if (chan->ep_is_in) 771 chan->do_ping = 0; 772 else 773 chan->do_ping = qh->ping_state; 774 775 chan->data_pid_start = qh->data_toggle; 776 chan->multi_count = 1; 777 778 if (urb->actual_length > urb->length && 779 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 780 urb->actual_length = urb->length; 781 782 chan->xfer_len = urb->length - urb->actual_length; 783 chan->xfer_count = 0; 784 785 /* Set the split attributes if required */ 786 if (qh->do_split) 787 dwc2_hc_init_split(hsotg, chan, qtd, urb); 788 else 789 chan->do_split = 0; 790 791 /* Set the transfer attributes */ 792 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, urb); 793 794 /* Non DWORD-aligned buffer case */ 795 if (bufptr) { 796 dev_vdbg(hsotg->dev, "Non-aligned buffer%p\n", bufptr); 797 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, bufptr)) { 798 dev_err(hsotg->dev, 799 "%s: Failed to allocate memory to handle non-dword aligned buffer\n", 800 __func__); 801 /* Add channel back to free list */ 802 chan->align_buf = 0; 803 chan->multi_count = 0; 804 LIST_INSERT_HEAD(&hsotg->free_hc_list, chan, hc_list_entry); 805 chan->in_freelist = 1; 806 qtd->in_process = 0; 807 qh->channel = NULL; 808 return -ENOMEM; 809 } 810 } else { 811 chan->align_buf = 0; 812 } 813 814 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 815 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 816 /* 817 * This value may be modified when the transfer is started 818 * to reflect the actual transfer length 819 */ 820 chan->multi_count = dwc2_hb_mult(qh->maxp); 821 822 if (hsotg->core_params->dma_desc_enable > 0) 823 chan->desc_list_addr = qh->desc_list_dma; 824 825 dwc2_hc_init(hsotg, chan); 826 chan->qh = qh; 827 828 return 0; 829 } 830 831 /** 832 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 833 * schedule and assigns them to available host channels. Called from the HCD 834 * interrupt handler functions. 835 * 836 * @hsotg: The HCD state structure 837 * 838 * Return: The types of new transactions that were assigned to host channels 839 */ 840 enum dwc2_transaction_type dwc2_hcd_select_transactions( 841 struct dwc2_hsotg *hsotg) 842 { 843 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 844 struct dwc2_qh *qh, *qhn; 845 int num_channels; 846 847 #ifdef DWC2_DEBUG 848 dev_vdbg(hsotg->dev, " Select Transactions\n"); 849 #endif 850 851 /* Process entries in the periodic ready list */ 852 /* TAILQ_FOREACH_SAFE? */ 853 qh = TAILQ_FIRST(&hsotg->periodic_sched_ready); 854 while (qh != NULL) { 855 if (LIST_EMPTY(&hsotg->free_hc_list)) 856 break; 857 if (hsotg->core_params->uframe_sched > 0) { 858 if (hsotg->available_host_channels <= 1) 859 break; 860 hsotg->available_host_channels--; 861 } 862 if (dwc2_assign_and_init_hc(hsotg, qh)) 863 break; 864 865 /* 866 * Move the QH from the periodic ready schedule to the 867 * periodic assigned schedule 868 */ 869 qhn = TAILQ_NEXT(qh, qh_list_entry); 870 TAILQ_REMOVE(&hsotg->periodic_sched_ready, qh, qh_list_entry); 871 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_assigned, qh, qh_list_entry); 872 ret_val = DWC2_TRANSACTION_PERIODIC; 873 qh = qhn; 874 } 875 876 /* 877 * Process entries in the inactive portion of the non-periodic 878 * schedule. Some free host channels may not be used if they are 879 * reserved for periodic transfers. 880 */ 881 num_channels = hsotg->core_params->host_channels; 882 qh = TAILQ_FIRST(&hsotg->non_periodic_sched_inactive); 883 while (qh != NULL) { 884 if (hsotg->core_params->uframe_sched <= 0 && 885 hsotg->non_periodic_channels >= num_channels - 886 hsotg->periodic_channels) 887 break; 888 if (LIST_EMPTY(&hsotg->free_hc_list)) 889 break; 890 891 /* 892 * Check to see if this is a NAK'd retransmit, in which case 893 * ignore for retransmission. We hold off on bulk/control 894 * retransmissions to reduce NAK interrupt overhead for 895 * cheeky devices that just hold off using NAKs. 896 */ 897 if (qh->nak_frame != 0xffff && 898 dwc2_full_frame_num(qh->nak_frame) == 899 dwc2_full_frame_num(dwc2_hcd_get_frame_number(hsotg))) { 900 qh = TAILQ_NEXT(qh, qh_list_entry); 901 continue; 902 } else { 903 qh->nak_frame = 0xffff; 904 } 905 906 if (hsotg->core_params->uframe_sched > 0) { 907 if (hsotg->available_host_channels < 1) 908 break; 909 hsotg->available_host_channels--; 910 } 911 912 if (dwc2_assign_and_init_hc(hsotg, qh)) 913 break; 914 915 /* 916 * Move the QH from the non-periodic inactive schedule to the 917 * non-periodic active schedule 918 */ 919 qhn = TAILQ_NEXT(qh, qh_list_entry); 920 TAILQ_REMOVE(&hsotg->non_periodic_sched_inactive, qh, qh_list_entry); 921 TAILQ_INSERT_TAIL(&hsotg->non_periodic_sched_active, qh, qh_list_entry); 922 qh = qhn; 923 924 if (ret_val == DWC2_TRANSACTION_NONE) 925 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 926 else 927 ret_val = DWC2_TRANSACTION_ALL; 928 929 if (hsotg->core_params->uframe_sched <= 0) 930 hsotg->non_periodic_channels++; 931 } 932 933 return ret_val; 934 } 935 936 /** 937 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 938 * a host channel associated with either a periodic or non-periodic transfer 939 * 940 * @hsotg: The HCD state structure 941 * @chan: Host channel descriptor associated with either a periodic or 942 * non-periodic transfer 943 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 944 * for periodic transfers or the non-periodic Tx FIFO 945 * for non-periodic transfers 946 * 947 * Return: 1 if a request is queued and more requests may be needed to 948 * complete the transfer, 0 if no more requests are required for this 949 * transfer, -1 if there is insufficient space in the Tx FIFO 950 * 951 * This function assumes that there is space available in the appropriate 952 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 953 * it checks whether space is available in the appropriate Tx FIFO. 954 * 955 * Must be called with interrupt disabled and spinlock held 956 */ 957 STATIC int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 958 struct dwc2_host_chan *chan, 959 u16 fifo_dwords_avail) 960 { 961 int retval = 0; 962 963 if (hsotg->core_params->dma_enable > 0) { 964 if (hsotg->core_params->dma_desc_enable > 0) { 965 if (!chan->xfer_started || 966 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 967 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 968 chan->qh->ping_state = 0; 969 } 970 } else if (!chan->xfer_started) { 971 dwc2_hc_start_transfer(hsotg, chan); 972 chan->qh->ping_state = 0; 973 } 974 } else if (chan->halt_pending) { 975 /* Don't queue a request if the channel has been halted */ 976 } else if (chan->halt_on_queue) { 977 dwc2_hc_halt(hsotg, chan, chan->halt_status); 978 } else if (chan->do_ping) { 979 if (!chan->xfer_started) 980 dwc2_hc_start_transfer(hsotg, chan); 981 } else if (!chan->ep_is_in || 982 chan->data_pid_start == DWC2_HC_PID_SETUP) { 983 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 984 if (!chan->xfer_started) { 985 dwc2_hc_start_transfer(hsotg, chan); 986 retval = 1; 987 } else { 988 retval = dwc2_hc_continue_transfer(hsotg, chan); 989 } 990 } else { 991 retval = -1; 992 } 993 } else { 994 if (!chan->xfer_started) { 995 dwc2_hc_start_transfer(hsotg, chan); 996 retval = 1; 997 } else { 998 retval = dwc2_hc_continue_transfer(hsotg, chan); 999 } 1000 } 1001 1002 return retval; 1003 } 1004 1005 /* 1006 * Processes periodic channels for the next frame and queues transactions for 1007 * these channels to the DWC_otg controller. After queueing transactions, the 1008 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 1009 * to queue as Periodic Tx FIFO or request queue space becomes available. 1010 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 1011 * 1012 * Must be called with interrupt disabled and spinlock held 1013 */ 1014 STATIC void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1015 { 1016 struct dwc2_qh *qh, *qhn; 1017 u32 tx_status; 1018 u32 fspcavail; 1019 u32 gintmsk; 1020 int status; 1021 int no_queue_space = 0; 1022 int no_fifo_space = 0; 1023 u32 qspcavail; 1024 1025 if (dbg_perio()) 1026 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1027 1028 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1029 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1030 TXSTS_QSPCAVAIL_SHIFT; 1031 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1032 TXSTS_FSPCAVAIL_SHIFT; 1033 1034 if (dbg_perio()) { 1035 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1036 qspcavail); 1037 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1038 fspcavail); 1039 } 1040 1041 qh = TAILQ_FIRST(&hsotg->periodic_sched_assigned); 1042 while (qh != NULL) { 1043 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1044 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1045 TXSTS_QSPCAVAIL_SHIFT; 1046 if (qspcavail == 0) { 1047 no_queue_space = 1; 1048 break; 1049 } 1050 1051 if (!qh->channel) { 1052 qh = TAILQ_NEXT(qh, qh_list_entry); 1053 continue; 1054 } 1055 1056 /* Make sure EP's TT buffer is clean before queueing qtds */ 1057 if (qh->tt_buffer_dirty) { 1058 qh = TAILQ_NEXT(qh, qh_list_entry); 1059 continue; 1060 } 1061 1062 /* 1063 * Set a flag if we're queuing high-bandwidth in slave mode. 1064 * The flag prevents any halts to get into the request queue in 1065 * the middle of multiple high-bandwidth packets getting queued. 1066 */ 1067 if (hsotg->core_params->dma_enable <= 0 && 1068 qh->channel->multi_count > 1) 1069 hsotg->queuing_high_bandwidth = 1; 1070 1071 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1072 TXSTS_FSPCAVAIL_SHIFT; 1073 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1074 if (status < 0) { 1075 no_fifo_space = 1; 1076 break; 1077 } 1078 1079 /* 1080 * In Slave mode, stay on the current transfer until there is 1081 * nothing more to do or the high-bandwidth request count is 1082 * reached. In DMA mode, only need to queue one request. The 1083 * controller automatically handles multiple packets for 1084 * high-bandwidth transfers. 1085 */ 1086 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1087 qh->channel->requests == qh->channel->multi_count) { 1088 qhn = TAILQ_NEXT(qh, qh_list_entry); 1089 /* 1090 * Move the QH from the periodic assigned schedule to 1091 * the periodic queued schedule 1092 */ 1093 TAILQ_REMOVE(&hsotg->periodic_sched_assigned, qh, qh_list_entry); 1094 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_queued, qh, qh_list_entry); 1095 1096 /* done queuing high bandwidth */ 1097 hsotg->queuing_high_bandwidth = 0; 1098 1099 qh = qhn; 1100 } 1101 } 1102 1103 if (hsotg->core_params->dma_enable <= 0) { 1104 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1105 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1106 TXSTS_QSPCAVAIL_SHIFT; 1107 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1108 TXSTS_FSPCAVAIL_SHIFT; 1109 if (dbg_perio()) { 1110 dev_vdbg(hsotg->dev, 1111 " P Tx Req Queue Space Avail (after queue): %d\n", 1112 qspcavail); 1113 dev_vdbg(hsotg->dev, 1114 " P Tx FIFO Space Avail (after queue): %d\n", 1115 fspcavail); 1116 } 1117 1118 if (!TAILQ_EMPTY(&hsotg->periodic_sched_assigned) || 1119 no_queue_space || no_fifo_space) { 1120 /* 1121 * May need to queue more transactions as the request 1122 * queue or Tx FIFO empties. Enable the periodic Tx 1123 * FIFO empty interrupt. (Always use the half-empty 1124 * level to ensure that new requests are loaded as 1125 * soon as possible.) 1126 */ 1127 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1128 gintmsk |= GINTSTS_PTXFEMP; 1129 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1130 } else { 1131 /* 1132 * Disable the Tx FIFO empty interrupt since there are 1133 * no more transactions that need to be queued right 1134 * now. This function is called from interrupt 1135 * handlers to queue more transactions as transfer 1136 * states change. 1137 */ 1138 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1139 gintmsk &= ~GINTSTS_PTXFEMP; 1140 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1141 } 1142 } 1143 } 1144 1145 /* 1146 * Processes active non-periodic channels and queues transactions for these 1147 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1148 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1149 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1150 * FIFO Empty interrupt is disabled. 1151 * 1152 * Must be called with interrupt disabled and spinlock held 1153 */ 1154 STATIC void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1155 { 1156 struct dwc2_qh *qh; 1157 u32 tx_status; 1158 u32 qspcavail; 1159 u32 fspcavail; 1160 u32 gintmsk; 1161 int status; 1162 int no_queue_space = 0; 1163 int no_fifo_space = 0; 1164 int more_to_do = 0; 1165 1166 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1167 1168 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1169 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1170 TXSTS_QSPCAVAIL_SHIFT; 1171 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1172 TXSTS_FSPCAVAIL_SHIFT; 1173 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1174 qspcavail); 1175 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1176 fspcavail); 1177 1178 /* 1179 * Keep track of the starting point. Skip over the start-of-list 1180 * entry. 1181 */ 1182 if (hsotg->non_periodic_qh_ptr == NULL) { 1183 hsotg->non_periodic_qh_ptr = TAILQ_FIRST(&hsotg->non_periodic_sched_active); 1184 } 1185 qh = hsotg->non_periodic_qh_ptr; 1186 1187 /* 1188 * Process once through the active list or until no more space is 1189 * available in the request queue or the Tx FIFO 1190 */ 1191 do { 1192 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1193 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1194 TXSTS_QSPCAVAIL_SHIFT; 1195 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1196 no_queue_space = 1; 1197 break; 1198 } 1199 1200 if (!qh->channel) 1201 goto next; 1202 1203 /* Make sure EP's TT buffer is clean before queueing qtds */ 1204 if (qh->tt_buffer_dirty) 1205 goto next; 1206 1207 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1208 TXSTS_FSPCAVAIL_SHIFT; 1209 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1210 1211 if (status > 0) { 1212 more_to_do = 1; 1213 } else if (status < 0) { 1214 no_fifo_space = 1; 1215 break; 1216 } 1217 next: 1218 /* Advance to next QH, wrapping to the start if we hit the end */ 1219 qh = TAILQ_NEXT(qh, qh_list_entry); 1220 if (qh == NULL) 1221 qh = TAILQ_FIRST(&hsotg->non_periodic_sched_active); 1222 } while ((qh != hsotg->non_periodic_qh_ptr) && (hsotg->non_periodic_qh_ptr != NULL)); 1223 hsotg->non_periodic_qh_ptr = qh; 1224 1225 if (hsotg->core_params->dma_enable <= 0) { 1226 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1227 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1228 TXSTS_QSPCAVAIL_SHIFT; 1229 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1230 TXSTS_FSPCAVAIL_SHIFT; 1231 dev_vdbg(hsotg->dev, 1232 " NP Tx Req Queue Space Avail (after queue): %d\n", 1233 qspcavail); 1234 dev_vdbg(hsotg->dev, 1235 " NP Tx FIFO Space Avail (after queue): %d\n", 1236 fspcavail); 1237 1238 if (more_to_do || no_queue_space || no_fifo_space) { 1239 /* 1240 * May need to queue more transactions as the request 1241 * queue or Tx FIFO empties. Enable the non-periodic 1242 * Tx FIFO empty interrupt. (Always use the half-empty 1243 * level to ensure that new requests are loaded as 1244 * soon as possible.) 1245 */ 1246 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1247 gintmsk |= GINTSTS_NPTXFEMP; 1248 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1249 } else { 1250 /* 1251 * Disable the Tx FIFO empty interrupt since there are 1252 * no more transactions that need to be queued right 1253 * now. This function is called from interrupt 1254 * handlers to queue more transactions as transfer 1255 * states change. 1256 */ 1257 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1258 gintmsk &= ~GINTSTS_NPTXFEMP; 1259 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1260 } 1261 } 1262 } 1263 1264 /** 1265 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1266 * and queues transactions for these channels to the DWC_otg controller. Called 1267 * from the HCD interrupt handler functions. 1268 * 1269 * @hsotg: The HCD state structure 1270 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1271 * or both) 1272 * 1273 * Must be called with interrupt disabled and spinlock held 1274 */ 1275 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1276 enum dwc2_transaction_type tr_type) 1277 { 1278 #ifdef DWC2_DEBUG 1279 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1280 #endif 1281 /* Process host channels associated with periodic transfers */ 1282 if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1283 tr_type == DWC2_TRANSACTION_ALL) && 1284 !TAILQ_EMPTY(&hsotg->periodic_sched_assigned)) 1285 dwc2_process_periodic_channels(hsotg); 1286 1287 /* Process host channels associated with non-periodic transfers */ 1288 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1289 tr_type == DWC2_TRANSACTION_ALL) { 1290 if (!TAILQ_EMPTY(&hsotg->non_periodic_sched_active)) { 1291 dwc2_process_non_periodic_channels(hsotg); 1292 } else { 1293 /* 1294 * Ensure NP Tx FIFO empty interrupt is disabled when 1295 * there are no non-periodic transfers to process 1296 */ 1297 u32 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1298 1299 gintmsk &= ~GINTSTS_NPTXFEMP; 1300 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1301 } 1302 } 1303 } 1304 1305 1306 void 1307 dwc2_conn_id_status_change(void *data) 1308 { 1309 struct dwc2_hsotg *hsotg = data; 1310 u32 count = 0; 1311 u32 gotgctl; 1312 1313 dev_dbg(hsotg->dev, "%s()\n", __func__); 1314 1315 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 1316 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1317 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1318 !!(gotgctl & GOTGCTL_CONID_B)); 1319 1320 /* B-Device connector (Device Mode) */ 1321 if (gotgctl & GOTGCTL_CONID_B) { 1322 /* Wait for switch to device mode */ 1323 dev_dbg(hsotg->dev, "connId B\n"); 1324 while (!dwc2_is_device_mode(hsotg)) { 1325 dev_info(hsotg->dev, 1326 "Waiting for Peripheral Mode, Mode=%s\n", 1327 dwc2_is_host_mode(hsotg) ? "Host" : 1328 "Peripheral"); 1329 usleep_range(20000, 40000); 1330 if (++count > 250) 1331 break; 1332 } 1333 if (count > 250) 1334 dev_err(hsotg->dev, 1335 "Connection id status change timed out\n"); 1336 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1337 dwc2_core_init(hsotg, false); 1338 dwc2_enable_global_interrupts(hsotg); 1339 } else { 1340 /* A-Device connector (Host Mode) */ 1341 dev_dbg(hsotg->dev, "connId A\n"); 1342 while (!dwc2_is_host_mode(hsotg)) { 1343 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1344 dwc2_is_host_mode(hsotg) ? 1345 "Host" : "Peripheral"); 1346 usleep_range(20000, 40000); 1347 if (++count > 250) 1348 break; 1349 } 1350 if (count > 250) 1351 dev_err(hsotg->dev, 1352 "Connection id status change timed out\n"); 1353 hsotg->op_state = OTG_STATE_A_HOST; 1354 1355 /* Initialize the Core for Host mode */ 1356 dwc2_core_init(hsotg, false); 1357 dwc2_enable_global_interrupts(hsotg); 1358 dwc2_hcd_start(hsotg); 1359 } 1360 } 1361 1362 void dwc2_wakeup_detected(void * data) 1363 { 1364 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1365 u32 hprt0; 1366 1367 dev_dbg(hsotg->dev, "%s()\n", __func__); 1368 1369 /* 1370 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1371 * so that OPT tests pass with all PHYs.) 1372 */ 1373 hprt0 = dwc2_read_hprt0(hsotg); 1374 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1375 hprt0 &= ~HPRT0_RES; 1376 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1377 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1378 DWC2_READ_4(hsotg, HPRT0)); 1379 1380 dwc2_hcd_rem_wakeup(hsotg); 1381 1382 /* Change to L0 state */ 1383 hsotg->lx_state = DWC2_L0; 1384 } 1385 1386 /* Must NOT be called with interrupt disabled or spinlock held */ 1387 STATIC void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1388 { 1389 unsigned long flags; 1390 u32 hprt0; 1391 u32 pcgctl; 1392 u32 gotgctl; 1393 1394 dev_dbg(hsotg->dev, "%s()\n", __func__); 1395 1396 spin_lock_irqsave(&hsotg->lock, flags); 1397 1398 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1399 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 1400 gotgctl |= GOTGCTL_HSTSETHNPEN; 1401 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 1402 hsotg->op_state = OTG_STATE_A_SUSPEND; 1403 } 1404 1405 hprt0 = dwc2_read_hprt0(hsotg); 1406 hprt0 |= HPRT0_SUSP; 1407 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1408 1409 /* Update lx_state */ 1410 hsotg->lx_state = DWC2_L2; 1411 1412 /* Suspend the Phy Clock */ 1413 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1414 pcgctl |= PCGCTL_STOPPCLK; 1415 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1416 udelay(10); 1417 1418 /* For HNP the bus must be suspended for at least 200ms */ 1419 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1420 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1421 pcgctl &= ~PCGCTL_STOPPCLK; 1422 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1423 1424 spin_unlock_irqrestore(&hsotg->lock, flags); 1425 1426 usleep_range(200000, 250000); 1427 } else { 1428 spin_unlock_irqrestore(&hsotg->lock, flags); 1429 } 1430 } 1431 1432 /* Handles hub class-specific requests */ 1433 int 1434 dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1435 u16 wvalue, u16 windex, char *buf, u16 wlength) 1436 { 1437 usb_hub_descriptor_t *hub_desc; 1438 usb_port_status_t ps; 1439 int retval = 0; 1440 u32 hprt0; 1441 u32 port_status; 1442 u32 speed; 1443 u32 pcgctl; 1444 1445 switch (typereq) { 1446 case ClearHubFeature: 1447 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1448 1449 switch (wvalue) { 1450 case C_HUB_LOCAL_POWER: 1451 case C_HUB_OVER_CURRENT: 1452 /* Nothing required here */ 1453 break; 1454 1455 default: 1456 retval = -EINVAL; 1457 dev_err(hsotg->dev, 1458 "ClearHubFeature request %1xh unknown\n", 1459 wvalue); 1460 } 1461 break; 1462 1463 case ClearPortFeature: 1464 // if (wvalue != USB_PORT_FEAT_L1) 1465 if (!windex || windex > 1) 1466 goto error; 1467 switch (wvalue) { 1468 case USB_PORT_FEAT_ENABLE: 1469 dev_dbg(hsotg->dev, 1470 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1471 hprt0 = dwc2_read_hprt0(hsotg); 1472 hprt0 |= HPRT0_ENA; 1473 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1474 break; 1475 1476 case USB_PORT_FEAT_SUSPEND: 1477 dev_dbg(hsotg->dev, 1478 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1479 DWC2_WRITE_4(hsotg, PCGCTL, 0); 1480 usleep_range(20000, 40000); 1481 1482 hprt0 = dwc2_read_hprt0(hsotg); 1483 hprt0 |= HPRT0_RES; 1484 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1485 hprt0 &= ~HPRT0_SUSP; 1486 usleep_range(100000, 150000); 1487 1488 hprt0 &= ~HPRT0_RES; 1489 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1490 break; 1491 1492 case USB_PORT_FEAT_POWER: 1493 dev_dbg(hsotg->dev, 1494 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1495 hprt0 = dwc2_read_hprt0(hsotg); 1496 hprt0 &= ~HPRT0_PWR; 1497 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1498 break; 1499 1500 case USB_PORT_FEAT_INDICATOR: 1501 dev_dbg(hsotg->dev, 1502 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1503 /* Port indicator not supported */ 1504 break; 1505 1506 case USB_PORT_FEAT_C_CONNECTION: 1507 /* 1508 * Clears driver's internal Connect Status Change flag 1509 */ 1510 dev_dbg(hsotg->dev, 1511 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1512 hsotg->flags.b.port_connect_status_change = 0; 1513 break; 1514 1515 case USB_PORT_FEAT_C_RESET: 1516 /* Clears driver's internal Port Reset Change flag */ 1517 dev_dbg(hsotg->dev, 1518 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1519 hsotg->flags.b.port_reset_change = 0; 1520 break; 1521 1522 case USB_PORT_FEAT_C_ENABLE: 1523 /* 1524 * Clears the driver's internal Port Enable/Disable 1525 * Change flag 1526 */ 1527 dev_dbg(hsotg->dev, 1528 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1529 hsotg->flags.b.port_enable_change = 0; 1530 break; 1531 1532 case USB_PORT_FEAT_C_SUSPEND: 1533 /* 1534 * Clears the driver's internal Port Suspend Change 1535 * flag, which is set when resume signaling on the host 1536 * port is complete 1537 */ 1538 dev_dbg(hsotg->dev, 1539 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1540 hsotg->flags.b.port_suspend_change = 0; 1541 break; 1542 1543 case USB_PORT_FEAT_C_PORT_L1: 1544 dev_dbg(hsotg->dev, 1545 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1546 hsotg->flags.b.port_l1_change = 0; 1547 break; 1548 1549 case USB_PORT_FEAT_C_OVER_CURRENT: 1550 dev_dbg(hsotg->dev, 1551 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1552 hsotg->flags.b.port_over_current_change = 0; 1553 break; 1554 1555 default: 1556 retval = -EINVAL; 1557 dev_err(hsotg->dev, 1558 "ClearPortFeature request %1xh unknown or unsupported\n", 1559 wvalue); 1560 } 1561 break; 1562 1563 case GetHubDescriptor: 1564 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1565 hub_desc = (usb_hub_descriptor_t *)buf; 1566 hub_desc->bDescLength = 9; 1567 hub_desc->bDescriptorType = 0x29; 1568 hub_desc->bNbrPorts = 1; 1569 USETW(hub_desc->wHubCharacteristics, 0x08); 1570 hub_desc->bPwrOn2PwrGood = 1; 1571 hub_desc->bHubContrCurrent = 0; 1572 hub_desc->DeviceRemovable[0] = 0; 1573 hub_desc->DeviceRemovable[1] = 0xff; 1574 break; 1575 1576 case GetHubStatus: 1577 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1578 memset(buf, 0, 4); 1579 break; 1580 1581 case GetPortStatus: 1582 dev_vdbg(hsotg->dev, 1583 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1584 hsotg->flags.d32); 1585 if (!windex || windex > 1) 1586 goto error; 1587 1588 port_status = 0; 1589 if (hsotg->flags.b.port_connect_status_change) 1590 port_status |= USB_PORT_STAT_C_CONNECTION; 1591 if (hsotg->flags.b.port_enable_change) 1592 port_status |= USB_PORT_STAT_C_ENABLE; 1593 if (hsotg->flags.b.port_suspend_change) 1594 port_status |= USB_PORT_STAT_C_SUSPEND; 1595 if (hsotg->flags.b.port_l1_change) 1596 port_status |= USB_PORT_STAT_C_L1; 1597 if (hsotg->flags.b.port_reset_change) 1598 port_status |= USB_PORT_STAT_C_RESET; 1599 if (hsotg->flags.b.port_over_current_change) { 1600 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1601 port_status |= USB_PORT_STAT_C_OVERCURRENT; 1602 } 1603 USETW(ps.wPortChange, port_status); 1604 1605 dev_vdbg(hsotg->dev, "wPortChange=%04x\n", port_status); 1606 if (!hsotg->flags.b.port_connect_status) { 1607 /* 1608 * The port is disconnected, which means the core is 1609 * either in device mode or it soon will be. Just 1610 * return 0's for the remainder of the port status 1611 * since the port register can't be read if the core 1612 * is in device mode. 1613 */ 1614 USETW(ps.wPortStatus, 0); 1615 memcpy(buf, &ps, sizeof(ps)); 1616 break; 1617 } 1618 1619 port_status = 0; 1620 hprt0 = DWC2_READ_4(hsotg, HPRT0); 1621 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1622 1623 if (hprt0 & HPRT0_CONNSTS) 1624 port_status |= USB_PORT_STAT_CONNECTION; 1625 if (hprt0 & HPRT0_ENA) 1626 port_status |= USB_PORT_STAT_ENABLE; 1627 if (hprt0 & HPRT0_SUSP) 1628 port_status |= USB_PORT_STAT_SUSPEND; 1629 if (hprt0 & HPRT0_OVRCURRACT) 1630 port_status |= USB_PORT_STAT_OVERCURRENT; 1631 if (hprt0 & HPRT0_RST) 1632 port_status |= USB_PORT_STAT_RESET; 1633 if (hprt0 & HPRT0_PWR) 1634 port_status |= USB_PORT_STAT_POWER; 1635 1636 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1637 if (speed == HPRT0_SPD_HIGH_SPEED) 1638 port_status |= USB_PORT_STAT_HIGH_SPEED; 1639 else if (speed == HPRT0_SPD_LOW_SPEED) 1640 port_status |= USB_PORT_STAT_LOW_SPEED; 1641 1642 if (hprt0 & HPRT0_TSTCTL_MASK) 1643 port_status |= USB_PORT_STAT_TEST; 1644 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1645 USETW(ps.wPortStatus, port_status); 1646 1647 dev_vdbg(hsotg->dev, "wPortStatus=%04x\n", port_status); 1648 memcpy(buf, &ps, sizeof(ps)); 1649 break; 1650 1651 case SetHubFeature: 1652 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1653 /* No HUB features supported */ 1654 break; 1655 1656 case SetPortFeature: 1657 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1658 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1659 goto error; 1660 1661 if (!hsotg->flags.b.port_connect_status) { 1662 /* 1663 * The port is disconnected, which means the core is 1664 * either in device mode or it soon will be. Just 1665 * return without doing anything since the port 1666 * register can't be written if the core is in device 1667 * mode. 1668 */ 1669 break; 1670 } 1671 1672 switch (wvalue) { 1673 case USB_PORT_FEAT_SUSPEND: 1674 dev_dbg(hsotg->dev, 1675 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1676 if (windex != hsotg->otg_port) 1677 goto error; 1678 dwc2_port_suspend(hsotg, windex); 1679 break; 1680 1681 case USB_PORT_FEAT_POWER: 1682 dev_dbg(hsotg->dev, 1683 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1684 hprt0 = dwc2_read_hprt0(hsotg); 1685 hprt0 |= HPRT0_PWR; 1686 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1687 break; 1688 1689 case USB_PORT_FEAT_RESET: 1690 hprt0 = dwc2_read_hprt0(hsotg); 1691 dev_dbg(hsotg->dev, 1692 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1693 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1694 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1695 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1696 /* ??? Original driver does this */ 1697 DWC2_WRITE_4(hsotg, PCGCTL, 0); 1698 1699 hprt0 = dwc2_read_hprt0(hsotg); 1700 /* Clear suspend bit if resetting from suspend state */ 1701 hprt0 &= ~HPRT0_SUSP; 1702 1703 /* 1704 * When B-Host the Port reset bit is set in the Start 1705 * HCD Callback function, so that the reset is started 1706 * within 1ms of the HNP success interrupt 1707 */ 1708 if (!dwc2_hcd_is_b_host(hsotg)) { 1709 hprt0 |= HPRT0_PWR | HPRT0_RST; 1710 dev_dbg(hsotg->dev, 1711 "In host mode, hprt0=%08x\n", hprt0); 1712 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1713 } 1714 1715 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1716 usleep_range(50000, 70000); 1717 hprt0 &= ~HPRT0_RST; 1718 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1719 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1720 break; 1721 1722 case USB_PORT_FEAT_INDICATOR: 1723 dev_dbg(hsotg->dev, 1724 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1725 /* Not supported */ 1726 break; 1727 1728 default: 1729 retval = -EINVAL; 1730 dev_err(hsotg->dev, 1731 "SetPortFeature %1xh unknown or unsupported\n", 1732 wvalue); 1733 break; 1734 } 1735 break; 1736 1737 default: 1738 error: 1739 retval = -EINVAL; 1740 dev_dbg(hsotg->dev, 1741 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1742 typereq, windex, wvalue); 1743 break; 1744 } 1745 1746 return retval; 1747 } 1748 1749 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1750 { 1751 u32 hfnum = DWC2_READ_4(hsotg, HFNUM); 1752 1753 #ifdef DWC2_DEBUG 1754 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1755 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1756 #endif 1757 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1758 } 1759 1760 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1761 { 1762 return hsotg->op_state == OTG_STATE_B_HOST; 1763 } 1764 1765 struct dwc2_hcd_urb * 1766 dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, int iso_desc_count, 1767 gfp_t mem_flags) 1768 { 1769 struct dwc2_hcd_urb *urb; 1770 u32 size = sizeof(*urb) + iso_desc_count * 1771 sizeof(struct dwc2_hcd_iso_packet_desc); 1772 1773 urb = malloc(size, M_DEVBUF, M_ZERO | mem_flags); 1774 if (urb) 1775 urb->packet_count = iso_desc_count; 1776 return urb; 1777 } 1778 1779 void 1780 dwc2_hcd_urb_free(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 1781 int iso_desc_count) 1782 { 1783 1784 u32 size = sizeof(*urb) + iso_desc_count * 1785 sizeof(struct dwc2_hcd_iso_packet_desc); 1786 1787 free(urb, M_DEVBUF, size); 1788 } 1789 1790 void 1791 dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 1792 u8 dev_addr, u8 ep_num, u8 ep_type, u8 ep_dir, 1793 u16 mps) 1794 { 1795 if (dbg_perio() || 1796 ep_type == USB_ENDPOINT_XFER_BULK || 1797 ep_type == USB_ENDPOINT_XFER_CONTROL) 1798 dev_dbg(hsotg->dev, "urb=%p, xfer=%p\n", urb, urb->priv); 1799 urb->pipe_info.dev_addr = dev_addr; 1800 urb->pipe_info.ep_num = ep_num; 1801 urb->pipe_info.pipe_type = ep_type; 1802 urb->pipe_info.pipe_dir = ep_dir; 1803 urb->pipe_info.mps = mps; 1804 } 1805 1806 /* 1807 * NOTE: This function will be removed once the peripheral controller code 1808 * is integrated and the driver is stable 1809 */ 1810 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1811 { 1812 #ifdef DWC2_DEBUG 1813 struct dwc2_host_chan *chan; 1814 struct dwc2_hcd_urb *urb; 1815 struct dwc2_qtd *qtd; 1816 int num_channels; 1817 u32 np_tx_status; 1818 u32 p_tx_status; 1819 int i; 1820 1821 num_channels = hsotg->core_params->host_channels; 1822 dev_dbg(hsotg->dev, "\n"); 1823 dev_dbg(hsotg->dev, 1824 "************************************************************\n"); 1825 dev_dbg(hsotg->dev, "HCD State:\n"); 1826 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 1827 1828 for (i = 0; i < num_channels; i++) { 1829 chan = hsotg->hc_ptr_array[i]; 1830 dev_dbg(hsotg->dev, " Channel %d:\n", i); 1831 dev_dbg(hsotg->dev, 1832 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 1833 chan->dev_addr, chan->ep_num, chan->ep_is_in); 1834 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 1835 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 1836 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 1837 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 1838 chan->data_pid_start); 1839 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 1840 dev_dbg(hsotg->dev, " xfer_started: %d\n", 1841 chan->xfer_started); 1842 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 1843 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 1844 (unsigned long)chan->xfer_dma); 1845 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 1846 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 1847 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 1848 chan->halt_on_queue); 1849 dev_dbg(hsotg->dev, " halt_pending: %d\n", 1850 chan->halt_pending); 1851 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 1852 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 1853 dev_dbg(hsotg->dev, " complete_split: %d\n", 1854 chan->complete_split); 1855 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 1856 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 1857 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 1858 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 1859 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 1860 1861 if (chan->xfer_started) { 1862 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", 1863 DWC2_READ_4(hsotg, HFNUM)); 1864 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", 1865 DWC2_READ_4(hsotg, HCCHAR(i))); 1866 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", 1867 DWC2_READ_4(hsotg, HCTSIZ(i))); 1868 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", 1869 DWC2_READ_4(hsotg, HCINT(i))); 1870 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", 1871 DWC2_READ_4(hsotg, HCINTMSK(i))); 1872 } 1873 1874 if (!(chan->xfer_started && chan->qh)) 1875 continue; 1876 1877 TAILQ_FOREACH(qtd, &chan->qh->qtd_list, qtd_list_entry) { 1878 if (!qtd->in_process) 1879 break; 1880 urb = qtd->urb; 1881 dev_dbg(hsotg->dev, " URB Info:\n"); 1882 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 1883 qtd, urb); 1884 if (urb) { 1885 dev_dbg(hsotg->dev, 1886 " Dev: %d, EP: %d %s\n", 1887 dwc2_hcd_get_dev_addr(&urb->pipe_info), 1888 dwc2_hcd_get_ep_num(&urb->pipe_info), 1889 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1890 "IN" : "OUT"); 1891 dev_dbg(hsotg->dev, 1892 " Max packet size: %d\n", 1893 dwc2_hcd_get_mps(&urb->pipe_info)); 1894 dev_dbg(hsotg->dev, 1895 " transfer_buffer: %p\n", 1896 urb->buf); 1897 dev_dbg(hsotg->dev, 1898 " transfer_dma: %08lx\n", 1899 (unsigned long)urb->dma); 1900 dev_dbg(hsotg->dev, 1901 " transfer_buffer_length: %d\n", 1902 urb->length); 1903 dev_dbg(hsotg->dev, " actual_length: %d\n", 1904 urb->actual_length); 1905 } 1906 } 1907 } 1908 1909 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 1910 hsotg->non_periodic_channels); 1911 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 1912 hsotg->periodic_channels); 1913 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 1914 np_tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1915 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 1916 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 1917 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 1918 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 1919 p_tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1920 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 1921 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 1922 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 1923 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 1924 dwc2_hcd_dump_frrem(hsotg); 1925 1926 dwc2_dump_global_registers(hsotg); 1927 dwc2_dump_host_registers(hsotg); 1928 dev_dbg(hsotg->dev, 1929 "************************************************************\n"); 1930 dev_dbg(hsotg->dev, "\n"); 1931 #endif 1932 } 1933 1934 /* 1935 * NOTE: This function will be removed once the peripheral controller code 1936 * is integrated and the driver is stable 1937 */ 1938 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 1939 { 1940 #ifdef DWC2_DUMP_FRREM 1941 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 1942 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1943 hsotg->frrem_samples, hsotg->frrem_accum, 1944 hsotg->frrem_samples > 0 ? 1945 hsotg->frrem_accum / hsotg->frrem_samples : 0); 1946 dev_dbg(hsotg->dev, "\n"); 1947 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 1948 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1949 hsotg->hfnum_7_samples, 1950 hsotg->hfnum_7_frrem_accum, 1951 hsotg->hfnum_7_samples > 0 ? 1952 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 1953 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 1954 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1955 hsotg->hfnum_0_samples, 1956 hsotg->hfnum_0_frrem_accum, 1957 hsotg->hfnum_0_samples > 0 ? 1958 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 1959 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 1960 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1961 hsotg->hfnum_other_samples, 1962 hsotg->hfnum_other_frrem_accum, 1963 hsotg->hfnum_other_samples > 0 ? 1964 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 1965 0); 1966 dev_dbg(hsotg->dev, "\n"); 1967 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 1968 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1969 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 1970 hsotg->hfnum_7_samples_a > 0 ? 1971 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 1972 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 1973 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1974 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 1975 hsotg->hfnum_0_samples_a > 0 ? 1976 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 1977 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 1978 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1979 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 1980 hsotg->hfnum_other_samples_a > 0 ? 1981 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 1982 : 0); 1983 dev_dbg(hsotg->dev, "\n"); 1984 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 1985 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1986 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 1987 hsotg->hfnum_7_samples_b > 0 ? 1988 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 1989 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 1990 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1991 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 1992 (hsotg->hfnum_0_samples_b > 0) ? 1993 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 1994 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 1995 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1996 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 1997 (hsotg->hfnum_other_samples_b > 0) ? 1998 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 1999 : 0); 2000 #endif 2001 } 2002 2003 struct wrapper_priv_data { 2004 struct dwc2_hsotg *hsotg; 2005 }; 2006 2007 2008 void dwc2_host_start(struct dwc2_hsotg *hsotg) 2009 { 2010 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2011 2012 // hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2013 _dwc2_hcd_start(hsotg); 2014 } 2015 2016 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2017 { 2018 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2019 2020 // hcd->self.is_b_host = 0; 2021 } 2022 2023 2024 /* 2025 * Work queue function for starting the HCD when A-Cable is connected 2026 */ 2027 void 2028 dwc2_hcd_start_func(void *data) 2029 { 2030 struct dwc2_hsotg *hsotg = data; 2031 2032 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2033 dwc2_host_start(hsotg); 2034 } 2035 2036 /* 2037 * Reset work queue function 2038 */ 2039 void 2040 dwc2_hcd_reset_func(void *data) 2041 { 2042 struct dwc2_hsotg *hsotg = data; 2043 u32 hprt0; 2044 2045 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2046 hprt0 = dwc2_read_hprt0(hsotg); 2047 hprt0 &= ~HPRT0_RST; 2048 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 2049 hsotg->flags.b.port_reset_change = 1; 2050 2051 dwc2_root_intr(hsotg->hsotg_sc); 2052 } 2053 2054 /* 2055 * ========================================================================= 2056 * Linux HC Driver Functions 2057 * ========================================================================= 2058 */ 2059 2060 /* 2061 * Initializes the DWC_otg controller and its root hub and prepares it for host 2062 * mode operation. Activates the root port. Returns 0 on success and a negative 2063 * error code on failure. 2064 */ 2065 2066 2067 /* 2068 * Frees secondary storage associated with the dwc2_hsotg structure contained 2069 * in the struct usb_hcd field 2070 */ 2071 STATIC void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2072 { 2073 u32 ahbcfg; 2074 u32 dctl; 2075 int i; 2076 2077 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2078 2079 /* Free memory for QH/QTD lists */ 2080 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2081 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2082 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2083 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2084 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 2085 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 2086 2087 /* Free memory for the host channels */ 2088 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 2089 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 2090 2091 if (chan != NULL) { 2092 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 2093 i, chan); 2094 hsotg->hc_ptr_array[i] = NULL; 2095 free(chan, M_DEVBUF, sizeof(*chan)); 2096 } 2097 } 2098 2099 if (hsotg->core_params->dma_enable > 0) { 2100 if (hsotg->status_buf) { 2101 usb_freemem(&hsotg->hsotg_sc->sc_bus, 2102 &hsotg->status_buf_usbdma); 2103 hsotg->status_buf = NULL; 2104 } 2105 } else { 2106 free(hsotg->status_buf, M_DEVBUF, DWC2_HCD_STATUS_BUF_SIZE); 2107 hsotg->status_buf = NULL; 2108 } 2109 2110 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 2111 2112 /* Disable all interrupts */ 2113 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2114 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 2115 DWC2_WRITE_4(hsotg, GINTMSK, 0); 2116 2117 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 2118 dctl = DWC2_READ_4(hsotg, DCTL); 2119 dctl |= DCTL_SFTDISCON; 2120 DWC2_WRITE_4(hsotg, DCTL, dctl); 2121 } 2122 2123 if (hsotg->wq_otg) { 2124 taskq_destroy(hsotg->wq_otg); 2125 } 2126 2127 free(hsotg->core_params, M_DEVBUF, sizeof(*hsotg->core_params)); 2128 hsotg->core_params = NULL; 2129 timeout_del(&hsotg->wkp_timer); 2130 } 2131 2132 STATIC void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 2133 { 2134 /* Turn off all host-specific interrupts */ 2135 dwc2_disable_host_interrupts(hsotg); 2136 2137 dwc2_hcd_free(hsotg); 2138 } 2139 2140 /* 2141 * Sets all parameters to the given value. 2142 * 2143 * Assumes that the dwc2_core_params struct contains only integers. 2144 */ 2145 void dwc2_set_all_params(struct dwc2_core_params *params, int value) 2146 { 2147 int *p = (int *)params; 2148 size_t size = sizeof(*params) / sizeof(*p); 2149 int i; 2150 2151 for (i = 0; i < size; i++) 2152 p[i] = value; 2153 } 2154 2155 /* 2156 * Initializes the HCD. This function allocates memory for and initializes the 2157 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 2158 * USB bus with the core and calls the hc_driver->start() function. It returns 2159 * a negative error on failure. 2160 */ 2161 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, 2162 const struct dwc2_core_params *params) 2163 { 2164 struct dwc2_host_chan *channel; 2165 int i, num_channels; 2166 int retval; 2167 2168 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 2169 2170 /* Detect config values from hardware */ 2171 retval = dwc2_get_hwparams(hsotg); 2172 2173 if (retval) 2174 return retval; 2175 2176 retval = -ENOMEM; 2177 2178 dev_dbg(hsotg->dev, "hcfg=%08x\n", DWC2_READ_4(hsotg, HCFG)); 2179 2180 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2181 hsotg->frame_num_array = malloc(sizeof(*hsotg->frame_num_array) * 2182 FRAME_NUM_ARRAY_SIZE, M_DEVBUF, 2183 M_ZERO | M_WAITOK); 2184 if (!hsotg->frame_num_array) 2185 goto error1; 2186 hsotg->last_frame_num_array = malloc( 2187 sizeof(*hsotg->last_frame_num_array) * 2188 FRAME_NUM_ARRAY_SIZE, M_DEVBUF, M_ZERO | M_WAITOK); 2189 if (!hsotg->last_frame_num_array) 2190 goto error1; 2191 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 2192 #endif 2193 2194 hsotg->core_params = malloc(sizeof(*hsotg->core_params), M_DEVBUF, 2195 M_ZERO | M_WAITOK); 2196 if (!hsotg->core_params) 2197 goto error1; 2198 2199 dwc2_set_all_params(hsotg->core_params, -1); 2200 2201 /* Validate parameter values */ 2202 dwc2_set_parameters(hsotg, params); 2203 2204 spin_lock_init(&hsotg->lock); 2205 2206 /* 2207 * Disable the global interrupt until all the interrupt handlers are 2208 * installed 2209 */ 2210 dwc2_disable_global_interrupts(hsotg); 2211 2212 /* Initialize the DWC_otg core, and select the Phy type */ 2213 retval = dwc2_core_init(hsotg, true); 2214 if (retval) 2215 goto error2; 2216 2217 /* Create new workqueue and init work */ 2218 retval = -ENOMEM; 2219 hsotg->wq_otg = taskq_create("dwc2", 1, IPL_USB, 0); 2220 if (hsotg->wq_otg == NULL) { 2221 dev_err(hsotg->dev, "Failed to create workqueue\n"); 2222 goto error2; 2223 } 2224 2225 timeout_set(&hsotg->wkp_timer, dwc2_wakeup_detected, hsotg); 2226 2227 /* Initialize the non-periodic schedule */ 2228 TAILQ_INIT(&hsotg->non_periodic_sched_inactive); 2229 TAILQ_INIT(&hsotg->non_periodic_sched_active); 2230 2231 /* Initialize the periodic schedule */ 2232 TAILQ_INIT(&hsotg->periodic_sched_inactive); 2233 TAILQ_INIT(&hsotg->periodic_sched_ready); 2234 TAILQ_INIT(&hsotg->periodic_sched_assigned); 2235 TAILQ_INIT(&hsotg->periodic_sched_queued); 2236 2237 /* 2238 * Create a host channel descriptor for each host channel implemented 2239 * in the controller. Initialize the channel descriptor array. 2240 */ 2241 LIST_INIT(&hsotg->free_hc_list); 2242 num_channels = hsotg->core_params->host_channels; 2243 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 2244 2245 for (i = 0; i < num_channels; i++) { 2246 channel = malloc(sizeof(*channel), M_DEVBUF, M_ZERO | M_WAITOK); 2247 if (channel == NULL) 2248 goto error3; 2249 channel->hc_num = i; 2250 hsotg->hc_ptr_array[i] = channel; 2251 } 2252 2253 if (hsotg->core_params->uframe_sched > 0) 2254 dwc2_hcd_init_usecs(hsotg); 2255 2256 /* Initialize hsotg start work */ 2257 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func, hsotg); 2258 2259 /* Initialize port reset work */ 2260 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func, hsotg); 2261 2262 /* 2263 * Allocate space for storing data on status transactions. Normally no 2264 * data is sent, but this space acts as a bit bucket. This must be 2265 * done after usb_add_hcd since that function allocates the DMA buffer 2266 * pool. 2267 */ 2268 hsotg->status_buf = NULL; 2269 if (hsotg->core_params->dma_enable > 0) { 2270 retval = usb_allocmem(&hsotg->hsotg_sc->sc_bus, 2271 DWC2_HCD_STATUS_BUF_SIZE, 0, 2272 USB_DMA_COHERENT, 2273 &hsotg->status_buf_usbdma); 2274 if (!retval) { 2275 hsotg->status_buf = KERNADDR(&hsotg->status_buf_usbdma, 0); 2276 hsotg->status_buf_dma = DMAADDR(&hsotg->status_buf_usbdma, 0); 2277 } 2278 } else 2279 hsotg->status_buf = malloc(DWC2_HCD_STATUS_BUF_SIZE, M_DEVBUF, 2280 M_ZERO | M_WAITOK); 2281 2282 if (!hsotg->status_buf) 2283 goto error3; 2284 2285 hsotg->otg_port = 1; 2286 hsotg->frame_list = NULL; 2287 hsotg->frame_list_dma = 0; 2288 hsotg->periodic_qh_count = 0; 2289 2290 /* Initiate lx_state to L3 disconnected state */ 2291 hsotg->lx_state = DWC2_L3; 2292 2293 _dwc2_hcd_start(hsotg); 2294 2295 dwc2_hcd_dump_state(hsotg); 2296 2297 dwc2_enable_global_interrupts(hsotg); 2298 2299 return 0; 2300 2301 error3: 2302 dwc2_hcd_release(hsotg); 2303 error2: 2304 error1: 2305 free(hsotg->core_params, M_DEVBUF, sizeof(*hsotg->core_params)); 2306 2307 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2308 free(hsotg->last_frame_num_array, M_DEVBUF, 2309 sizeof(*hsotg->last_frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2310 free(hsotg->frame_num_array, M_DEVBUF, 2311 sizeof(*hsotg->frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2312 #endif 2313 2314 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 2315 return retval; 2316 } 2317 2318 int dwc2_hcd_dma_config(struct dwc2_hsotg *hsotg, 2319 struct dwc2_core_dma_config *config) 2320 { 2321 hsotg->core_dma_config = config; 2322 return 0; 2323 } 2324