1 /* $OpenBSD: dwc2_hcd.c,v 1.23 2021/07/22 18:32:33 mglocker Exp $ */ 2 /* $NetBSD: dwc2_hcd.c,v 1.15 2014/11/24 10:14:14 skrll Exp $ */ 3 4 /* 5 * hcd.c - DesignWare HS OTG Controller host-mode routines 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * This file contains the core HCD code, and implements the Linux hc_driver 42 * API 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/signal.h> 49 #include <sys/proc.h> 50 #include <sys/pool.h> 51 #include <sys/task.h> 52 53 #include <machine/bus.h> 54 55 #include <dev/usb/usb.h> 56 #include <dev/usb/usbdi.h> 57 #include <dev/usb/usbdivar.h> 58 #include <dev/usb/usb_mem.h> 59 60 #include <dev/usb/dwc2/dwc2.h> 61 #include <dev/usb/dwc2/dwc2var.h> 62 63 #include <dev/usb/dwc2/dwc2_core.h> 64 #include <dev/usb/dwc2/dwc2_hcd.h> 65 66 /** 67 * dwc2_dump_channel_info() - Prints the state of a host channel 68 * 69 * @hsotg: Programming view of DWC_otg controller 70 * @chan: Pointer to the channel to dump 71 * 72 * Must be called with interrupt disabled and spinlock held 73 * 74 * NOTE: This function will be removed once the peripheral controller code 75 * is integrated and the driver is stable 76 */ 77 #ifdef VERBOSE_DEBUG 78 STATIC void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 79 struct dwc2_host_chan *chan) 80 { 81 int num_channels = hsotg->core_params->host_channels; 82 struct dwc2_qh *qh; 83 u32 hcchar; 84 u32 hcsplt; 85 u32 hctsiz; 86 u32 hc_dma; 87 int i; 88 89 if (chan == NULL) 90 return; 91 92 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 93 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chan->hc_num)); 94 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chan->hc_num)); 95 hc_dma = DWC2_READ_4(hsotg, HCDMA(chan->hc_num)); 96 97 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 98 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 99 hcchar, hcsplt); 100 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 101 hctsiz, hc_dma); 102 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 103 chan->dev_addr, chan->ep_num, chan->ep_is_in); 104 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 105 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 106 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 107 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 108 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 109 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 110 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 111 (unsigned long)chan->xfer_dma); 112 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 113 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 114 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 115 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 116 qh_list_entry) 117 dev_dbg(hsotg->dev, " %p\n", qh); 118 dev_dbg(hsotg->dev, " NP waiting sched:\n"); 119 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting, 120 qh_list_entry) 121 dev_dbg(hsotg->dev, " %p\n", qh); 122 dev_dbg(hsotg->dev, " NP active sched:\n"); 123 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 124 qh_list_entry) 125 dev_dbg(hsotg->dev, " %p\n", qh); 126 dev_dbg(hsotg->dev, " Channels:\n"); 127 for (i = 0; i < num_channels; i++) { 128 struct dwc2_host_chan *ch = hsotg->hc_ptr_array[i]; 129 130 dev_dbg(hsotg->dev, " %2d: %p\n", i, ch); 131 } 132 } 133 #endif /* VERBOSE_DEBUG */ 134 135 /* 136 * Processes all the URBs in a single list of QHs. Completes them with 137 * -ETIMEDOUT and frees the QTD. 138 * 139 * Must be called with interrupt disabled and spinlock held 140 */ 141 STATIC void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 142 struct list_head *qh_list) 143 { 144 struct dwc2_qh *qh, *qh_tmp; 145 struct dwc2_qtd *qtd, *qtd_tmp; 146 147 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 148 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 149 qtd_list_entry) { 150 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 151 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 152 } 153 } 154 } 155 156 STATIC void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 157 struct list_head *qh_list) 158 { 159 struct dwc2_qtd *qtd, *qtd_tmp; 160 struct dwc2_qh *qh, *qh_tmp; 161 unsigned long flags; 162 163 if (!qh_list->next) 164 /* The list hasn't been initialized yet */ 165 return; 166 167 spin_lock_irqsave(&hsotg->lock, flags); 168 169 /* Ensure there are no QTDs or URBs left */ 170 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 171 172 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 173 dwc2_hcd_qh_unlink(hsotg, qh); 174 175 /* Free each QTD in the QH's QTD list */ 176 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 177 qtd_list_entry) 178 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 179 180 spin_unlock_irqrestore(&hsotg->lock, flags); 181 dwc2_hcd_qh_free(hsotg, qh); 182 spin_lock_irqsave(&hsotg->lock, flags); 183 } 184 185 spin_unlock_irqrestore(&hsotg->lock, flags); 186 } 187 188 /* 189 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 190 * and periodic schedules. The QTD associated with each URB is removed from 191 * the schedule and freed. This function may be called when a disconnect is 192 * detected or when the HCD is being stopped. 193 * 194 * Must be called with interrupt disabled and spinlock held 195 */ 196 STATIC void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 197 { 198 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 199 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting); 200 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 201 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 202 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 203 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 204 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 205 } 206 207 /** 208 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 209 * 210 * @hsotg: Pointer to struct dwc2_hsotg 211 */ 212 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 213 { 214 u32 hprt0; 215 216 if (hsotg->op_state == OTG_STATE_B_HOST) { 217 /* 218 * Reset the port. During a HNP mode switch the reset 219 * needs to occur within 1ms and have a duration of at 220 * least 50ms. 221 */ 222 hprt0 = dwc2_read_hprt0(hsotg); 223 hprt0 |= HPRT0_RST; 224 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 225 } 226 227 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 228 msecs_to_jiffies(50)); 229 } 230 231 /* Must be called with interrupt disabled and spinlock held */ 232 STATIC void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 233 { 234 int num_channels = hsotg->core_params->host_channels; 235 struct dwc2_host_chan *channel; 236 u32 hcchar; 237 int i; 238 239 if (hsotg->core_params->dma_enable <= 0) { 240 /* Flush out any channel requests in slave mode */ 241 for (i = 0; i < num_channels; i++) { 242 channel = hsotg->hc_ptr_array[i]; 243 if (!list_empty(&channel->hc_list_entry)) 244 continue; 245 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 246 if (hcchar & HCCHAR_CHENA) { 247 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 248 hcchar |= HCCHAR_CHDIS; 249 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 250 } 251 } 252 } 253 254 for (i = 0; i < num_channels; i++) { 255 channel = hsotg->hc_ptr_array[i]; 256 if (!list_empty(&channel->hc_list_entry)) 257 continue; 258 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 259 if (hcchar & HCCHAR_CHENA) { 260 /* Halt the channel */ 261 hcchar |= HCCHAR_CHDIS; 262 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 263 } 264 265 dwc2_hc_cleanup(hsotg, channel); 266 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 267 /* 268 * Added for Descriptor DMA to prevent channel double cleanup in 269 * release_channel_ddma(), which is called from ep_disable when 270 * device disconnects 271 */ 272 channel->qh = NULL; 273 } 274 /* All channels have been freed, mark them available */ 275 if (hsotg->core_params->uframe_sched > 0) { 276 hsotg->available_host_channels = 277 hsotg->core_params->host_channels; 278 } else { 279 hsotg->non_periodic_channels = 0; 280 hsotg->periodic_channels = 0; 281 } 282 } 283 284 /** 285 * dwc2_hcd_connect() - Handles connect of the HCD 286 * 287 * @hsotg: Pointer to struct dwc2_hsotg 288 * 289 * Must be called with interrupt disabled and spinlock held 290 */ 291 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 292 { 293 if (hsotg->lx_state != DWC2_L0) 294 usb_hcd_resume_root_hub(hsotg->priv); 295 296 hsotg->flags.b.port_connect_status_change = 1; 297 hsotg->flags.b.port_connect_status = 1; 298 } 299 300 /** 301 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 302 * 303 * @hsotg: Pointer to struct dwc2_hsotg 304 * @force: If true, we won't try to reconnect even if we see device connected. 305 * 306 * Must be called with interrupt disabled and spinlock held 307 */ 308 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 309 { 310 u32 intr; 311 u32 hprt0; 312 313 /* Set status flags for the hub driver */ 314 hsotg->flags.b.port_connect_status_change = 1; 315 hsotg->flags.b.port_connect_status = 0; 316 317 /* 318 * Shutdown any transfers in process by clearing the Tx FIFO Empty 319 * interrupt mask and status bits and disabling subsequent host 320 * channel interrupts. 321 */ 322 intr = DWC2_READ_4(hsotg, GINTMSK); 323 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 324 DWC2_WRITE_4(hsotg, GINTMSK, intr); 325 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 326 DWC2_WRITE_4(hsotg, GINTSTS, intr); 327 328 /* 329 * Turn off the vbus power only if the core has transitioned to device 330 * mode. If still in host mode, need to keep power on to detect a 331 * reconnection. 332 */ 333 if (dwc2_is_device_mode(hsotg)) { 334 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 335 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 336 DWC2_WRITE_4(hsotg, HPRT0, 0); 337 } 338 339 dwc2_disable_host_interrupts(hsotg); 340 } 341 342 /* Respond with an error status to all URBs in the schedule */ 343 dwc2_kill_all_urbs(hsotg); 344 345 if (dwc2_is_host_mode(hsotg)) 346 /* Clean up any host channels that were in use */ 347 dwc2_hcd_cleanup_channels(hsotg); 348 349 dwc2_host_disconnect(hsotg); 350 351 dwc2_root_intr(hsotg->hsotg_sc); 352 353 /* 354 * Add an extra check here to see if we're actually connected but 355 * we don't have a detection interrupt pending. This can happen if: 356 * 1. hardware sees connect 357 * 2. hardware sees disconnect 358 * 3. hardware sees connect 359 * 4. dwc2_port_intr() - clears connect interrupt 360 * 5. dwc2_handle_common_intr() - calls here 361 * 362 * Without the extra check here we will end calling disconnect 363 * and won't get any future interrupts to handle the connect. 364 */ 365 if (!force) { 366 hprt0 = DWC2_READ_4(hsotg, HPRT0); 367 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 368 dwc2_hcd_connect(hsotg); 369 } 370 } 371 372 /** 373 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 374 * 375 * @hsotg: Pointer to struct dwc2_hsotg 376 */ 377 STATIC void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 378 { 379 if (hsotg->bus_suspended) { 380 hsotg->flags.b.port_suspend_change = 1; 381 usb_hcd_resume_root_hub(hsotg->priv); 382 } 383 384 if (hsotg->lx_state == DWC2_L1) 385 hsotg->flags.b.port_l1_change = 1; 386 387 dwc2_root_intr(hsotg->hsotg_sc); 388 } 389 390 /** 391 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 392 * 393 * @hsotg: Pointer to struct dwc2_hsotg 394 * 395 * Must be called with interrupt disabled and spinlock held 396 */ 397 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 398 { 399 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 400 401 /* 402 * The root hub should be disconnected before this function is called. 403 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 404 * and the QH lists (via ..._hcd_endpoint_disable). 405 */ 406 407 /* Turn off all host-specific interrupts */ 408 dwc2_disable_host_interrupts(hsotg); 409 410 /* Turn off the vbus power */ 411 dev_dbg(hsotg->dev, "PortPower off\n"); 412 DWC2_WRITE_4(hsotg, HPRT0, 0); 413 } 414 415 /* Caller must hold driver lock */ 416 int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 417 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 418 struct dwc2_qtd *qtd) 419 { 420 u32 intr_mask; 421 int retval; 422 int dev_speed; 423 424 if (!hsotg->flags.b.port_connect_status) { 425 /* No longer connected */ 426 dev_err(hsotg->dev, "Not connected\n"); 427 return -ENODEV; 428 } 429 430 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 431 432 /* Some configurations cannot support LS traffic on a FS root port */ 433 if ((dev_speed == USB_SPEED_LOW) && 434 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 435 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 436 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 437 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 438 439 if (prtspd == HPRT0_SPD_FULL_SPEED) { 440 dev_err(hsotg->dev, 441 "DWC OTG HCD URB Enqueue unsupported\n"); 442 return -ENODEV; 443 } 444 } 445 446 if (!qtd) 447 return -EINVAL; 448 449 memset(qtd, 0, sizeof(*qtd)); 450 451 dwc2_hcd_qtd_init(qtd, urb); 452 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 453 if (retval) { 454 dev_err(hsotg->dev, 455 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 456 retval); 457 return retval; 458 } 459 460 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 461 if (!(intr_mask & GINTSTS_SOF)) { 462 enum dwc2_transaction_type tr_type; 463 464 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 465 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 466 /* 467 * Do not schedule SG transactions until qtd has 468 * URB_GIVEBACK_ASAP set 469 */ 470 return 0; 471 472 tr_type = dwc2_hcd_select_transactions(hsotg); 473 if (tr_type != DWC2_TRANSACTION_NONE) 474 dwc2_hcd_queue_transactions(hsotg, tr_type); 475 } 476 477 return 0; 478 } 479 480 /* Must be called with interrupt disabled and spinlock held */ 481 int 482 dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 483 struct dwc2_hcd_urb *urb) 484 { 485 struct dwc2_qh *qh; 486 struct dwc2_qtd *urb_qtd; 487 488 urb_qtd = urb->qtd; 489 if (!urb_qtd) { 490 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 491 return -EINVAL; 492 } 493 494 qh = urb_qtd->qh; 495 if (!qh) { 496 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 497 return -EINVAL; 498 } 499 500 urb->priv = NULL; 501 502 if (urb_qtd->in_process && qh->channel) { 503 #ifdef VERBOSE_DEBUG 504 dwc2_dump_channel_info(hsotg, qh->channel); 505 #endif 506 /* The QTD is in process (it has been assigned to a channel) */ 507 if (hsotg->flags.b.port_connect_status) 508 /* 509 * If still connected (i.e. in host mode), halt the 510 * channel so it can be used for other transfers. If 511 * no longer connected, the host registers can't be 512 * written to halt the channel since the core is in 513 * device mode. 514 */ 515 dwc2_hc_halt(hsotg, qh->channel, 516 DWC2_HC_XFER_URB_DEQUEUE); 517 } 518 519 /* 520 * Free the QTD and clean up the associated QH. Leave the QH in the 521 * schedule if it has any remaining QTDs. 522 */ 523 if (hsotg->core_params->dma_desc_enable <= 0) { 524 u8 in_process = urb_qtd->in_process; 525 526 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 527 if (in_process) { 528 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 529 qh->channel = NULL; 530 } else if (list_empty(&qh->qtd_list)) { 531 dwc2_hcd_qh_unlink(hsotg, qh); 532 } 533 } else { 534 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 535 } 536 537 return 0; 538 } 539 540 541 /* 542 * Initializes dynamic portions of the DWC_otg HCD state 543 * 544 * Must be called with interrupt disabled and spinlock held 545 */ 546 void 547 dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 548 { 549 struct dwc2_host_chan *chan, *chan_tmp; 550 int num_channels; 551 int i; 552 553 hsotg->flags.d32 = 0; 554 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 555 556 if (hsotg->core_params->uframe_sched > 0) { 557 hsotg->available_host_channels = 558 hsotg->core_params->host_channels; 559 } else { 560 hsotg->non_periodic_channels = 0; 561 hsotg->periodic_channels = 0; 562 } 563 564 /* 565 * Put all channels in the free channel list and clean up channel 566 * states 567 */ 568 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 569 hc_list_entry) 570 list_del_init(&chan->hc_list_entry); 571 572 num_channels = hsotg->core_params->host_channels; 573 for (i = 0; i < num_channels; i++) { 574 chan = hsotg->hc_ptr_array[i]; 575 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 576 dwc2_hc_cleanup(hsotg, chan); 577 } 578 579 /* Initialize the DWC core for host mode operation */ 580 dwc2_core_host_init(hsotg); 581 } 582 583 STATIC void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 584 struct dwc2_host_chan *chan, 585 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 586 { 587 int hub_addr, hub_port; 588 589 chan->do_split = 1; 590 chan->xact_pos = qtd->isoc_split_pos; 591 chan->complete_split = qtd->complete_split; 592 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 593 chan->hub_addr = (u8)hub_addr; 594 chan->hub_port = (u8)hub_port; 595 } 596 597 STATIC void *dwc2_hc_init_xfer_data(struct dwc2_hsotg *hsotg, 598 struct dwc2_host_chan *chan, 599 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 600 { 601 if (hsotg->core_params->dma_enable > 0) { 602 chan->xfer_dma = DMAADDR(urb->usbdma, urb->actual_length); 603 604 /* For non-dword aligned case */ 605 if (hsotg->core_params->dma_desc_enable <= 0 && 606 (chan->xfer_dma & 0x3)) 607 return (u8 *)urb->buf + urb->actual_length; 608 } else { 609 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 610 } 611 612 return NULL; 613 } 614 615 STATIC void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 616 struct dwc2_host_chan *chan, 617 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 618 { 619 struct dwc2_hcd_iso_packet_desc *frame_desc; 620 void *bufptr = NULL; 621 622 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 623 case USB_ENDPOINT_XFER_CONTROL: 624 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 625 626 switch (qtd->control_phase) { 627 case DWC2_CONTROL_SETUP: 628 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 629 chan->do_ping = 0; 630 chan->ep_is_in = 0; 631 chan->data_pid_start = DWC2_HC_PID_SETUP; 632 if (hsotg->core_params->dma_enable > 0) 633 chan->xfer_dma = urb->setup_dma; 634 else 635 chan->xfer_buf = urb->setup_packet; 636 chan->xfer_len = 8; 637 break; 638 639 case DWC2_CONTROL_DATA: 640 dev_vdbg(hsotg->dev, " Control data transaction\n"); 641 chan->data_pid_start = qtd->data_toggle; 642 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 643 break; 644 645 case DWC2_CONTROL_STATUS: 646 /* 647 * Direction is opposite of data direction or IN if no 648 * data 649 */ 650 dev_vdbg(hsotg->dev, " Control status transaction\n"); 651 if (urb->length == 0) 652 chan->ep_is_in = 1; 653 else 654 chan->ep_is_in = 655 dwc2_hcd_is_pipe_out(&urb->pipe_info); 656 if (chan->ep_is_in) 657 chan->do_ping = 0; 658 chan->data_pid_start = DWC2_HC_PID_DATA1; 659 chan->xfer_len = 0; 660 if (hsotg->core_params->dma_enable > 0) 661 chan->xfer_dma = hsotg->status_buf_dma; 662 else 663 chan->xfer_buf = hsotg->status_buf; 664 break; 665 } 666 break; 667 668 case USB_ENDPOINT_XFER_BULK: 669 chan->ep_type = USB_ENDPOINT_XFER_BULK; 670 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 671 break; 672 673 case USB_ENDPOINT_XFER_INT: 674 chan->ep_type = USB_ENDPOINT_XFER_INT; 675 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 676 break; 677 678 case USB_ENDPOINT_XFER_ISOC: 679 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 680 if (hsotg->core_params->dma_desc_enable > 0) 681 break; 682 683 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 684 frame_desc->status = 0; 685 686 if (hsotg->core_params->dma_enable > 0) { 687 chan->xfer_dma = urb->dma; 688 chan->xfer_dma += frame_desc->offset + 689 qtd->isoc_split_offset; 690 } else { 691 chan->xfer_buf = urb->buf; 692 chan->xfer_buf += frame_desc->offset + 693 qtd->isoc_split_offset; 694 } 695 696 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 697 698 /* For non-dword aligned buffers */ 699 if (hsotg->core_params->dma_enable > 0 && 700 (chan->xfer_dma & 0x3)) 701 bufptr = (u8 *)urb->buf + frame_desc->offset + 702 qtd->isoc_split_offset; 703 704 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 705 if (chan->xfer_len <= 188) 706 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 707 else 708 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 709 } 710 break; 711 } 712 713 return bufptr; 714 } 715 716 STATIC int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 717 struct dwc2_host_chan *chan, 718 struct dwc2_hcd_urb *urb, void *bufptr) 719 { 720 u32 buf_size; 721 722 if (!qh->dw_align_buf) { 723 int err; 724 725 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) 726 buf_size = hsotg->core_params->max_transfer_size; 727 else 728 /* 3072 = 3 max-size Isoc packets */ 729 buf_size = 3072; 730 731 qh->dw_align_buf = NULL; 732 qh->dw_align_buf_dma = 0; 733 err = usb_allocmem(&hsotg->hsotg_sc->sc_bus, buf_size, 0, 734 USB_DMA_COHERENT, &qh->dw_align_buf_usbdma); 735 if (!err) { 736 struct usb_dma *ud = &qh->dw_align_buf_usbdma; 737 738 qh->dw_align_buf = KERNADDR(ud, 0); 739 qh->dw_align_buf_dma = DMAADDR(ud, 0); 740 } 741 if (!qh->dw_align_buf) 742 return -ENOMEM; 743 qh->dw_align_buf_size = buf_size; 744 } 745 746 if (chan->xfer_len) { 747 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 748 void *usb_urb = urb->priv; 749 750 if (usb_urb) { 751 if (!chan->ep_is_in) { 752 memcpy(qh->dw_align_buf, bufptr, 753 chan->xfer_len); 754 } 755 } else { 756 dev_warn(hsotg->dev, "no URB in dwc2_urb\n"); 757 } 758 } 759 760 usb_syncmem(&qh->dw_align_buf_usbdma, 0, qh->dw_align_buf_size, 761 chan->ep_is_in ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 762 763 chan->align_buf = qh->dw_align_buf_dma; 764 return 0; 765 } 766 767 /** 768 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 769 * channel and initializes the host channel to perform the transactions. The 770 * host channel is removed from the free list. 771 * 772 * @hsotg: The HCD state structure 773 * @qh: Transactions from the first QTD for this QH are selected and assigned 774 * to a free host channel 775 */ 776 STATIC int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 777 { 778 struct dwc2_host_chan *chan; 779 struct dwc2_hcd_urb *urb; 780 struct dwc2_qtd *qtd; 781 void *bufptr = NULL; 782 783 if (dbg_qh(qh)) 784 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 785 786 if (list_empty(&qh->qtd_list)) { 787 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 788 return -ENOMEM; 789 } 790 791 if (list_empty(&hsotg->free_hc_list)) { 792 dev_dbg(hsotg->dev, "No free channel to assign\n"); 793 return -ENOMEM; 794 } 795 796 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 797 hc_list_entry); 798 799 /* Remove host channel from free list */ 800 list_del_init(&chan->hc_list_entry); 801 802 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 803 urb = qtd->urb; 804 qh->channel = chan; 805 qtd->in_process = 1; 806 807 /* 808 * Use usb_pipedevice to determine device address. This address is 809 * 0 before the SET_ADDRESS command and the correct address afterward. 810 */ 811 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 812 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 813 chan->speed = qh->dev_speed; 814 chan->max_packet = dwc2_max_packet(qh->maxp); 815 816 chan->xfer_started = 0; 817 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 818 chan->error_state = (qtd->error_count > 0); 819 chan->halt_on_queue = 0; 820 chan->halt_pending = 0; 821 chan->requests = 0; 822 823 /* 824 * The following values may be modified in the transfer type section 825 * below. The xfer_len value may be reduced when the transfer is 826 * started to accommodate the max widths of the XferSize and PktCnt 827 * fields in the HCTSIZn register. 828 */ 829 830 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 831 if (chan->ep_is_in) 832 chan->do_ping = 0; 833 else 834 chan->do_ping = qh->ping_state; 835 836 chan->data_pid_start = qh->data_toggle; 837 chan->multi_count = 1; 838 839 if (urb->actual_length > urb->length && 840 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 841 urb->actual_length = urb->length; 842 843 chan->xfer_len = urb->length - urb->actual_length; 844 chan->xfer_count = 0; 845 846 /* Set the split attributes if required */ 847 if (qh->do_split) 848 dwc2_hc_init_split(hsotg, chan, qtd, urb); 849 else 850 chan->do_split = 0; 851 852 /* Set the transfer attributes */ 853 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, urb); 854 855 /* Non DWORD-aligned buffer case */ 856 if (bufptr) { 857 dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); 858 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) { 859 dev_err(hsotg->dev, 860 "%s: Failed to allocate memory to handle non-dword aligned buffer\n", 861 __func__); 862 /* Add channel back to free list */ 863 chan->align_buf = 0; 864 chan->multi_count = 0; 865 list_add_tail(&chan->hc_list_entry, 866 &hsotg->free_hc_list); 867 qtd->in_process = 0; 868 qh->channel = NULL; 869 return -ENOMEM; 870 } 871 } else { 872 chan->align_buf = 0; 873 } 874 875 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 876 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 877 /* 878 * This value may be modified when the transfer is started 879 * to reflect the actual transfer length 880 */ 881 chan->multi_count = dwc2_hb_mult(qh->maxp); 882 883 if (hsotg->core_params->dma_desc_enable > 0) { 884 chan->desc_list_usbdma = qh->desc_list_usbdma; 885 chan->desc_list_addr = qh->desc_list_dma; 886 chan->desc_list_sz = qh->desc_list_sz; 887 } 888 889 dwc2_hc_init(hsotg, chan); 890 chan->qh = qh; 891 892 return 0; 893 } 894 895 /** 896 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 897 * schedule and assigns them to available host channels. Called from the HCD 898 * interrupt handler functions. 899 * 900 * @hsotg: The HCD state structure 901 * 902 * Return: The types of new transactions that were assigned to host channels 903 */ 904 enum dwc2_transaction_type dwc2_hcd_select_transactions( 905 struct dwc2_hsotg *hsotg) 906 { 907 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 908 struct list_head *qh_ptr; 909 struct dwc2_qh *qh; 910 int num_channels; 911 912 #ifdef DWC2_DEBUG_SOF 913 dev_vdbg(hsotg->dev, " Select Transactions\n"); 914 #endif 915 916 /* Process entries in the periodic ready list */ 917 qh_ptr = hsotg->periodic_sched_ready.next; 918 while (qh_ptr != &hsotg->periodic_sched_ready) { 919 if (list_empty(&hsotg->free_hc_list)) 920 break; 921 if (hsotg->core_params->uframe_sched > 0) { 922 if (hsotg->available_host_channels <= 1) 923 break; 924 hsotg->available_host_channels--; 925 } 926 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 927 if (dwc2_assign_and_init_hc(hsotg, qh)) 928 break; 929 930 /* 931 * Move the QH from the periodic ready schedule to the 932 * periodic assigned schedule 933 */ 934 qh_ptr = qh_ptr->next; 935 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned); 936 ret_val = DWC2_TRANSACTION_PERIODIC; 937 } 938 939 /* 940 * Process entries in the inactive portion of the non-periodic 941 * schedule. Some free host channels may not be used if they are 942 * reserved for periodic transfers. 943 */ 944 num_channels = hsotg->core_params->host_channels; 945 qh_ptr = hsotg->non_periodic_sched_inactive.next; 946 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 947 if (hsotg->core_params->uframe_sched <= 0 && 948 hsotg->non_periodic_channels >= num_channels - 949 hsotg->periodic_channels) 950 break; 951 if (list_empty(&hsotg->free_hc_list)) 952 break; 953 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 954 955 /* 956 * Check to see if this is a NAK'd retransmit, in which case 957 * ignore for retransmission. We hold off on bulk/control 958 * retransmissions to reduce NAK interrupt overhead for 959 * cheeky devices that just hold off using NAKs. 960 */ 961 if (qh->nak_frame != 0xffff && 962 dwc2_full_frame_num(qh->nak_frame) == 963 dwc2_full_frame_num(dwc2_hcd_get_frame_number(hsotg))) { 964 qh_ptr = qh_ptr->next; 965 continue; 966 } else { 967 qh->nak_frame = 0xffff; 968 } 969 970 if (hsotg->core_params->uframe_sched > 0) { 971 if (hsotg->available_host_channels < 1) 972 break; 973 hsotg->available_host_channels--; 974 } 975 976 if (dwc2_assign_and_init_hc(hsotg, qh)) 977 break; 978 979 /* 980 * Move the QH from the non-periodic inactive schedule to the 981 * non-periodic active schedule 982 */ 983 qh_ptr = qh_ptr->next; 984 list_move(&qh->qh_list_entry, 985 &hsotg->non_periodic_sched_active); 986 987 if (ret_val == DWC2_TRANSACTION_NONE) 988 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 989 else 990 ret_val = DWC2_TRANSACTION_ALL; 991 992 if (hsotg->core_params->uframe_sched <= 0) 993 hsotg->non_periodic_channels++; 994 } 995 996 return ret_val; 997 } 998 999 /** 1000 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 1001 * a host channel associated with either a periodic or non-periodic transfer 1002 * 1003 * @hsotg: The HCD state structure 1004 * @chan: Host channel descriptor associated with either a periodic or 1005 * non-periodic transfer 1006 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 1007 * for periodic transfers or the non-periodic Tx FIFO 1008 * for non-periodic transfers 1009 * 1010 * Return: 1 if a request is queued and more requests may be needed to 1011 * complete the transfer, 0 if no more requests are required for this 1012 * transfer, -1 if there is insufficient space in the Tx FIFO 1013 * 1014 * This function assumes that there is space available in the appropriate 1015 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 1016 * it checks whether space is available in the appropriate Tx FIFO. 1017 * 1018 * Must be called with interrupt disabled and spinlock held 1019 */ 1020 STATIC int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 1021 struct dwc2_host_chan *chan, 1022 u16 fifo_dwords_avail) 1023 { 1024 int retval = 0; 1025 1026 if (hsotg->core_params->dma_enable > 0) { 1027 if (hsotg->core_params->dma_desc_enable > 0) { 1028 if (!chan->xfer_started || 1029 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1030 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 1031 chan->qh->ping_state = 0; 1032 } 1033 } else if (!chan->xfer_started) { 1034 dwc2_hc_start_transfer(hsotg, chan); 1035 chan->qh->ping_state = 0; 1036 } 1037 } else if (chan->halt_pending) { 1038 /* Don't queue a request if the channel has been halted */ 1039 } else if (chan->halt_on_queue) { 1040 dwc2_hc_halt(hsotg, chan, chan->halt_status); 1041 } else if (chan->do_ping) { 1042 if (!chan->xfer_started) 1043 dwc2_hc_start_transfer(hsotg, chan); 1044 } else if (!chan->ep_is_in || 1045 chan->data_pid_start == DWC2_HC_PID_SETUP) { 1046 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 1047 if (!chan->xfer_started) { 1048 dwc2_hc_start_transfer(hsotg, chan); 1049 retval = 1; 1050 } else { 1051 retval = dwc2_hc_continue_transfer(hsotg, chan); 1052 } 1053 } else { 1054 retval = -1; 1055 } 1056 } else { 1057 if (!chan->xfer_started) { 1058 dwc2_hc_start_transfer(hsotg, chan); 1059 retval = 1; 1060 } else { 1061 retval = dwc2_hc_continue_transfer(hsotg, chan); 1062 } 1063 } 1064 1065 return retval; 1066 } 1067 1068 /* 1069 * Processes periodic channels for the next frame and queues transactions for 1070 * these channels to the DWC_otg controller. After queueing transactions, the 1071 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 1072 * to queue as Periodic Tx FIFO or request queue space becomes available. 1073 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 1074 * 1075 * Must be called with interrupt disabled and spinlock held 1076 */ 1077 STATIC void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1078 { 1079 struct list_head *qh_ptr; 1080 struct dwc2_qh *qh; 1081 u32 tx_status; 1082 u32 fspcavail; 1083 u32 gintmsk; 1084 int status; 1085 int no_queue_space = 0; 1086 int no_fifo_space = 0; 1087 u32 qspcavail; 1088 1089 if (dbg_perio()) 1090 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1091 1092 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1093 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1094 TXSTS_QSPCAVAIL_SHIFT; 1095 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1096 TXSTS_FSPCAVAIL_SHIFT; 1097 1098 if (dbg_perio()) { 1099 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1100 qspcavail); 1101 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1102 fspcavail); 1103 } 1104 1105 qh_ptr = hsotg->periodic_sched_assigned.next; 1106 while (qh_ptr != &hsotg->periodic_sched_assigned) { 1107 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1108 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1109 TXSTS_QSPCAVAIL_SHIFT; 1110 if (qspcavail == 0) { 1111 no_queue_space = 1; 1112 break; 1113 } 1114 1115 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 1116 if (!qh->channel) { 1117 qh_ptr = qh_ptr->next; 1118 continue; 1119 } 1120 1121 /* Make sure EP's TT buffer is clean before queueing qtds */ 1122 if (qh->tt_buffer_dirty) { 1123 qh_ptr = qh_ptr->next; 1124 continue; 1125 } 1126 1127 /* 1128 * Set a flag if we're queuing high-bandwidth in slave mode. 1129 * The flag prevents any halts to get into the request queue in 1130 * the middle of multiple high-bandwidth packets getting queued. 1131 */ 1132 if (hsotg->core_params->dma_enable <= 0 && 1133 qh->channel->multi_count > 1) 1134 hsotg->queuing_high_bandwidth = 1; 1135 1136 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1137 TXSTS_FSPCAVAIL_SHIFT; 1138 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1139 if (status < 0) { 1140 no_fifo_space = 1; 1141 break; 1142 } 1143 1144 /* 1145 * In Slave mode, stay on the current transfer until there is 1146 * nothing more to do or the high-bandwidth request count is 1147 * reached. In DMA mode, only need to queue one request. The 1148 * controller automatically handles multiple packets for 1149 * high-bandwidth transfers. 1150 */ 1151 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1152 qh->channel->requests == qh->channel->multi_count) { 1153 qh_ptr = qh_ptr->next; 1154 /* 1155 * Move the QH from the periodic assigned schedule to 1156 * the periodic queued schedule 1157 */ 1158 list_move(&qh->qh_list_entry, 1159 &hsotg->periodic_sched_queued); 1160 1161 /* done queuing high bandwidth */ 1162 hsotg->queuing_high_bandwidth = 0; 1163 } 1164 } 1165 1166 if (hsotg->core_params->dma_enable <= 0) { 1167 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1168 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1169 TXSTS_QSPCAVAIL_SHIFT; 1170 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1171 TXSTS_FSPCAVAIL_SHIFT; 1172 if (dbg_perio()) { 1173 dev_vdbg(hsotg->dev, 1174 " P Tx Req Queue Space Avail (after queue): %d\n", 1175 qspcavail); 1176 dev_vdbg(hsotg->dev, 1177 " P Tx FIFO Space Avail (after queue): %d\n", 1178 fspcavail); 1179 } 1180 1181 if (!list_empty(&hsotg->periodic_sched_assigned) || 1182 no_queue_space || no_fifo_space) { 1183 /* 1184 * May need to queue more transactions as the request 1185 * queue or Tx FIFO empties. Enable the periodic Tx 1186 * FIFO empty interrupt. (Always use the half-empty 1187 * level to ensure that new requests are loaded as 1188 * soon as possible.) 1189 */ 1190 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1191 gintmsk |= GINTSTS_PTXFEMP; 1192 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1193 } else { 1194 /* 1195 * Disable the Tx FIFO empty interrupt since there are 1196 * no more transactions that need to be queued right 1197 * now. This function is called from interrupt 1198 * handlers to queue more transactions as transfer 1199 * states change. 1200 */ 1201 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1202 gintmsk &= ~GINTSTS_PTXFEMP; 1203 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1204 } 1205 } 1206 } 1207 1208 /* 1209 * Processes active non-periodic channels and queues transactions for these 1210 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1211 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1212 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1213 * FIFO Empty interrupt is disabled. 1214 * 1215 * Must be called with interrupt disabled and spinlock held 1216 */ 1217 STATIC void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1218 { 1219 struct list_head *orig_qh_ptr; 1220 struct dwc2_qh *qh; 1221 u32 tx_status; 1222 u32 qspcavail; 1223 u32 fspcavail; 1224 u32 gintmsk; 1225 int status; 1226 int no_queue_space = 0; 1227 int no_fifo_space = 0; 1228 int more_to_do = 0; 1229 1230 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1231 1232 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1233 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1234 TXSTS_QSPCAVAIL_SHIFT; 1235 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1236 TXSTS_FSPCAVAIL_SHIFT; 1237 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1238 qspcavail); 1239 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1240 fspcavail); 1241 1242 /* 1243 * Keep track of the starting point. Skip over the start-of-list 1244 * entry. 1245 */ 1246 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 1247 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1248 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 1249 1250 /* 1251 * Process once through the active list or until no more space is 1252 * available in the request queue or the Tx FIFO 1253 */ 1254 do { 1255 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1256 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1257 TXSTS_QSPCAVAIL_SHIFT; 1258 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1259 no_queue_space = 1; 1260 break; 1261 } 1262 1263 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 1264 qh_list_entry); 1265 if (!qh->channel) 1266 goto next; 1267 1268 /* Make sure EP's TT buffer is clean before queueing qtds */ 1269 if (qh->tt_buffer_dirty) 1270 goto next; 1271 1272 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1273 TXSTS_FSPCAVAIL_SHIFT; 1274 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1275 1276 if (status > 0) { 1277 more_to_do = 1; 1278 } else if (status < 0) { 1279 no_fifo_space = 1; 1280 break; 1281 } 1282 next: 1283 /* Advance to next QH, skipping start-of-list entry */ 1284 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1285 if (hsotg->non_periodic_qh_ptr == 1286 &hsotg->non_periodic_sched_active) 1287 hsotg->non_periodic_qh_ptr = 1288 hsotg->non_periodic_qh_ptr->next; 1289 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 1290 1291 if (hsotg->core_params->dma_enable <= 0) { 1292 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1293 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1294 TXSTS_QSPCAVAIL_SHIFT; 1295 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1296 TXSTS_FSPCAVAIL_SHIFT; 1297 dev_vdbg(hsotg->dev, 1298 " NP Tx Req Queue Space Avail (after queue): %d\n", 1299 qspcavail); 1300 dev_vdbg(hsotg->dev, 1301 " NP Tx FIFO Space Avail (after queue): %d\n", 1302 fspcavail); 1303 1304 if (more_to_do || no_queue_space || no_fifo_space) { 1305 /* 1306 * May need to queue more transactions as the request 1307 * queue or Tx FIFO empties. Enable the non-periodic 1308 * Tx FIFO empty interrupt. (Always use the half-empty 1309 * level to ensure that new requests are loaded as 1310 * soon as possible.) 1311 */ 1312 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1313 gintmsk |= GINTSTS_NPTXFEMP; 1314 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1315 } else { 1316 /* 1317 * Disable the Tx FIFO empty interrupt since there are 1318 * no more transactions that need to be queued right 1319 * now. This function is called from interrupt 1320 * handlers to queue more transactions as transfer 1321 * states change. 1322 */ 1323 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1324 gintmsk &= ~GINTSTS_NPTXFEMP; 1325 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1326 } 1327 } 1328 } 1329 1330 /** 1331 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1332 * and queues transactions for these channels to the DWC_otg controller. Called 1333 * from the HCD interrupt handler functions. 1334 * 1335 * @hsotg: The HCD state structure 1336 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1337 * or both) 1338 * 1339 * Must be called with interrupt disabled and spinlock held 1340 */ 1341 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1342 enum dwc2_transaction_type tr_type) 1343 { 1344 #ifdef DWC2_DEBUG_SOF 1345 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1346 #endif 1347 /* Process host channels associated with periodic transfers */ 1348 if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1349 tr_type == DWC2_TRANSACTION_ALL) && 1350 !list_empty(&hsotg->periodic_sched_assigned)) 1351 dwc2_process_periodic_channels(hsotg); 1352 1353 /* Process host channels associated with non-periodic transfers */ 1354 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1355 tr_type == DWC2_TRANSACTION_ALL) { 1356 if (!list_empty(&hsotg->non_periodic_sched_active)) { 1357 dwc2_process_non_periodic_channels(hsotg); 1358 } else { 1359 /* 1360 * Ensure NP Tx FIFO empty interrupt is disabled when 1361 * there are no non-periodic transfers to process 1362 */ 1363 u32 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1364 1365 gintmsk &= ~GINTSTS_NPTXFEMP; 1366 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1367 } 1368 } 1369 } 1370 1371 1372 STATIC void dwc2_conn_id_status_change(void *data) 1373 { 1374 struct dwc2_hsotg *hsotg = data; 1375 u32 count = 0; 1376 u32 gotgctl; 1377 unsigned long flags; 1378 1379 dev_dbg(hsotg->dev, "%s()\n", __func__); 1380 1381 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 1382 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1383 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1384 !!(gotgctl & GOTGCTL_CONID_B)); 1385 1386 /* B-Device connector (Device Mode) */ 1387 if (gotgctl & GOTGCTL_CONID_B) { 1388 /* Wait for switch to device mode */ 1389 dev_dbg(hsotg->dev, "connId B\n"); 1390 while (!dwc2_is_device_mode(hsotg)) { 1391 dev_info(hsotg->dev, 1392 "Waiting for Peripheral Mode, Mode=%s\n", 1393 dwc2_is_host_mode(hsotg) ? "Host" : 1394 "Peripheral"); 1395 usleep_range(20000, 40000); 1396 if (++count > 250) 1397 break; 1398 } 1399 if (count > 250) 1400 dev_err(hsotg->dev, 1401 "Connection id status change timed out\n"); 1402 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1403 dwc2_core_init(hsotg, false); 1404 dwc2_enable_global_interrupts(hsotg); 1405 spin_lock_irqsave(&hsotg->lock, flags); 1406 dwc2_hsotg_core_init_disconnected(hsotg, false); 1407 spin_unlock_irqrestore(&hsotg->lock, flags); 1408 dwc2_hsotg_core_connect(hsotg); 1409 } else { 1410 /* A-Device connector (Host Mode) */ 1411 dev_dbg(hsotg->dev, "connId A\n"); 1412 while (!dwc2_is_host_mode(hsotg)) { 1413 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1414 dwc2_is_host_mode(hsotg) ? 1415 "Host" : "Peripheral"); 1416 usleep_range(20000, 40000); 1417 if (++count > 250) 1418 break; 1419 } 1420 if (count > 250) 1421 dev_err(hsotg->dev, 1422 "Connection id status change timed out\n"); 1423 hsotg->op_state = OTG_STATE_A_HOST; 1424 1425 /* Initialize the Core for Host mode */ 1426 dwc2_core_init(hsotg, false); 1427 dwc2_enable_global_interrupts(hsotg); 1428 dwc2_hcd_start(hsotg); 1429 } 1430 } 1431 1432 void dwc2_wakeup_detected(void *data) 1433 { 1434 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1435 u32 hprt0; 1436 1437 dev_dbg(hsotg->dev, "%s()\n", __func__); 1438 1439 /* 1440 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1441 * so that OPT tests pass with all PHYs.) 1442 */ 1443 hprt0 = dwc2_read_hprt0(hsotg); 1444 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1445 hprt0 &= ~HPRT0_RES; 1446 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1447 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1448 DWC2_READ_4(hsotg, HPRT0)); 1449 1450 dwc2_hcd_rem_wakeup(hsotg); 1451 hsotg->bus_suspended = 0; 1452 1453 /* Change to L0 state */ 1454 hsotg->lx_state = DWC2_L0; 1455 } 1456 1457 /* Must NOT be called with interrupt disabled or spinlock held */ 1458 STATIC void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1459 { 1460 unsigned long flags; 1461 u32 hprt0; 1462 u32 pcgctl; 1463 u32 gotgctl; 1464 1465 dev_dbg(hsotg->dev, "%s()\n", __func__); 1466 1467 spin_lock_irqsave(&hsotg->lock, flags); 1468 1469 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1470 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 1471 gotgctl |= GOTGCTL_HSTSETHNPEN; 1472 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 1473 hsotg->op_state = OTG_STATE_A_SUSPEND; 1474 } 1475 1476 hprt0 = dwc2_read_hprt0(hsotg); 1477 hprt0 |= HPRT0_SUSP; 1478 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1479 1480 hsotg->bus_suspended = 1; 1481 1482 /* 1483 * If hibernation is supported, Phy clock will be suspended 1484 * after registers are backuped. 1485 */ 1486 if (!hsotg->core_params->hibernation) { 1487 /* Suspend the Phy Clock */ 1488 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1489 pcgctl |= PCGCTL_STOPPCLK; 1490 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1491 udelay(10); 1492 } 1493 1494 /* For HNP the bus must be suspended for at least 200ms */ 1495 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1496 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1497 pcgctl &= ~PCGCTL_STOPPCLK; 1498 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1499 1500 spin_unlock_irqrestore(&hsotg->lock, flags); 1501 1502 usleep_range(200000, 250000); 1503 } else { 1504 spin_unlock_irqrestore(&hsotg->lock, flags); 1505 } 1506 } 1507 1508 /* Must NOT be called with interrupt disabled or spinlock held */ 1509 STATIC void dwc2_port_resume(struct dwc2_hsotg *hsotg) 1510 { 1511 struct dwc2_softc *sc = hsotg->hsotg_sc; 1512 unsigned long flags; 1513 u32 hprt0; 1514 u32 pcgctl; 1515 1516 spin_lock_irqsave(&hsotg->lock, flags); 1517 1518 /* 1519 * If hibernation is supported, Phy clock is already resumed 1520 * after registers restore. 1521 */ 1522 if (!hsotg->core_params->hibernation) { 1523 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1524 pcgctl &= ~PCGCTL_STOPPCLK; 1525 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1526 spin_unlock_irqrestore(&hsotg->lock, flags); 1527 usleep_range(20000, 40000); 1528 spin_lock_irqsave(&hsotg->lock, flags); 1529 } 1530 1531 hprt0 = dwc2_read_hprt0(hsotg); 1532 hprt0 |= HPRT0_RES; 1533 hprt0 &= ~HPRT0_SUSP; 1534 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1535 spin_unlock_irqrestore(&hsotg->lock, flags); 1536 1537 usb_delay_ms(&sc->sc_bus, USB_RESUME_TIMEOUT); 1538 1539 spin_lock_irqsave(&hsotg->lock, flags); 1540 hprt0 = dwc2_read_hprt0(hsotg); 1541 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 1542 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1543 hsotg->bus_suspended = 0; 1544 spin_unlock_irqrestore(&hsotg->lock, flags); 1545 } 1546 1547 /* Handles hub class-specific requests */ 1548 int 1549 dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1550 u16 wvalue, u16 windex, char *buf, u16 wlength) 1551 { 1552 usb_hub_descriptor_t *hub_desc; 1553 usb_port_status_t ps; 1554 int retval = 0; 1555 u32 hprt0; 1556 u32 port_status; 1557 u32 speed; 1558 u32 pcgctl; 1559 1560 switch (typereq) { 1561 case ClearHubFeature: 1562 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1563 1564 switch (wvalue) { 1565 case C_HUB_LOCAL_POWER: 1566 case C_HUB_OVER_CURRENT: 1567 /* Nothing required here */ 1568 break; 1569 1570 default: 1571 retval = -EINVAL; 1572 dev_err(hsotg->dev, 1573 "ClearHubFeature request %1xh unknown\n", 1574 wvalue); 1575 } 1576 break; 1577 1578 case ClearPortFeature: 1579 // if (wvalue != USB_PORT_FEAT_L1) 1580 if (!windex || windex > 1) 1581 goto error; 1582 switch (wvalue) { 1583 case USB_PORT_FEAT_ENABLE: 1584 dev_dbg(hsotg->dev, 1585 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1586 hprt0 = dwc2_read_hprt0(hsotg); 1587 hprt0 |= HPRT0_ENA; 1588 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1589 break; 1590 1591 case USB_PORT_FEAT_SUSPEND: 1592 dev_dbg(hsotg->dev, 1593 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1594 if (hsotg->bus_suspended) 1595 dwc2_port_resume(hsotg); 1596 break; 1597 1598 case USB_PORT_FEAT_POWER: 1599 dev_dbg(hsotg->dev, 1600 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1601 hprt0 = dwc2_read_hprt0(hsotg); 1602 hprt0 &= ~HPRT0_PWR; 1603 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1604 break; 1605 1606 case USB_PORT_FEAT_INDICATOR: 1607 dev_dbg(hsotg->dev, 1608 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1609 /* Port indicator not supported */ 1610 break; 1611 1612 case USB_PORT_FEAT_C_CONNECTION: 1613 /* 1614 * Clears driver's internal Connect Status Change flag 1615 */ 1616 dev_dbg(hsotg->dev, 1617 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1618 hsotg->flags.b.port_connect_status_change = 0; 1619 break; 1620 1621 case USB_PORT_FEAT_C_RESET: 1622 /* Clears driver's internal Port Reset Change flag */ 1623 dev_dbg(hsotg->dev, 1624 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1625 hsotg->flags.b.port_reset_change = 0; 1626 break; 1627 1628 case USB_PORT_FEAT_C_ENABLE: 1629 /* 1630 * Clears the driver's internal Port Enable/Disable 1631 * Change flag 1632 */ 1633 dev_dbg(hsotg->dev, 1634 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1635 hsotg->flags.b.port_enable_change = 0; 1636 break; 1637 1638 case USB_PORT_FEAT_C_SUSPEND: 1639 /* 1640 * Clears the driver's internal Port Suspend Change 1641 * flag, which is set when resume signaling on the host 1642 * port is complete 1643 */ 1644 dev_dbg(hsotg->dev, 1645 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1646 hsotg->flags.b.port_suspend_change = 0; 1647 break; 1648 1649 case USB_PORT_FEAT_C_PORT_L1: 1650 dev_dbg(hsotg->dev, 1651 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1652 hsotg->flags.b.port_l1_change = 0; 1653 break; 1654 1655 case USB_PORT_FEAT_C_OVER_CURRENT: 1656 dev_dbg(hsotg->dev, 1657 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1658 hsotg->flags.b.port_over_current_change = 0; 1659 break; 1660 1661 default: 1662 retval = -EINVAL; 1663 dev_err(hsotg->dev, 1664 "ClearPortFeature request %1xh unknown or unsupported\n", 1665 wvalue); 1666 } 1667 break; 1668 1669 case GetHubDescriptor: 1670 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1671 hub_desc = (usb_hub_descriptor_t *)buf; 1672 hub_desc->bDescLength = 9; 1673 hub_desc->bDescriptorType = USB_DT_HUB; 1674 hub_desc->bNbrPorts = 1; 1675 USETW(hub_desc->wHubCharacteristics, HUB_CHAR_COMMON_LPSM | 1676 HUB_CHAR_INDV_PORT_OCPM); 1677 hub_desc->bPwrOn2PwrGood = 1; 1678 hub_desc->bHubContrCurrent = 0; 1679 hub_desc->DeviceRemovable[0] = 0; 1680 hub_desc->DeviceRemovable[1] = 0xff; 1681 break; 1682 1683 case GetHubStatus: 1684 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1685 memset(buf, 0, 4); 1686 break; 1687 1688 case GetPortStatus: 1689 dev_vdbg(hsotg->dev, 1690 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1691 hsotg->flags.d32); 1692 if (!windex || windex > 1) 1693 goto error; 1694 1695 port_status = 0; 1696 if (hsotg->flags.b.port_connect_status_change) 1697 port_status |= USB_PORT_STAT_C_CONNECTION; 1698 if (hsotg->flags.b.port_enable_change) 1699 port_status |= USB_PORT_STAT_C_ENABLE; 1700 if (hsotg->flags.b.port_suspend_change) 1701 port_status |= USB_PORT_STAT_C_SUSPEND; 1702 if (hsotg->flags.b.port_l1_change) 1703 port_status |= USB_PORT_STAT_C_L1; 1704 if (hsotg->flags.b.port_reset_change) 1705 port_status |= USB_PORT_STAT_C_RESET; 1706 if (hsotg->flags.b.port_over_current_change) { 1707 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1708 port_status |= USB_PORT_STAT_C_OVERCURRENT; 1709 } 1710 USETW(ps.wPortChange, port_status); 1711 1712 dev_vdbg(hsotg->dev, "wPortChange=%04x\n", port_status); 1713 if (!hsotg->flags.b.port_connect_status) { 1714 /* 1715 * The port is disconnected, which means the core is 1716 * either in device mode or it soon will be. Just 1717 * return 0's for the remainder of the port status 1718 * since the port register can't be read if the core 1719 * is in device mode. 1720 */ 1721 USETW(ps.wPortStatus, 0); 1722 memcpy(buf, &ps, sizeof(ps)); 1723 break; 1724 } 1725 1726 port_status = 0; 1727 hprt0 = DWC2_READ_4(hsotg, HPRT0); 1728 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1729 1730 if (hprt0 & HPRT0_CONNSTS) 1731 port_status |= USB_PORT_STAT_CONNECTION; 1732 if (hprt0 & HPRT0_ENA) 1733 port_status |= USB_PORT_STAT_ENABLE; 1734 if (hprt0 & HPRT0_SUSP) 1735 port_status |= USB_PORT_STAT_SUSPEND; 1736 if (hprt0 & HPRT0_OVRCURRACT) 1737 port_status |= USB_PORT_STAT_OVERCURRENT; 1738 if (hprt0 & HPRT0_RST) 1739 port_status |= USB_PORT_STAT_RESET; 1740 if (hprt0 & HPRT0_PWR) 1741 port_status |= USB_PORT_STAT_POWER; 1742 1743 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1744 if (speed == HPRT0_SPD_HIGH_SPEED) 1745 port_status |= USB_PORT_STAT_HIGH_SPEED; 1746 else if (speed == HPRT0_SPD_LOW_SPEED) 1747 port_status |= USB_PORT_STAT_LOW_SPEED; 1748 1749 if (hprt0 & HPRT0_TSTCTL_MASK) 1750 port_status |= USB_PORT_STAT_TEST; 1751 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1752 USETW(ps.wPortStatus, port_status); 1753 1754 if (hsotg->core_params->dma_desc_fs_enable) { 1755 /* 1756 * Enable descriptor DMA only if a full speed 1757 * device is connected. 1758 */ 1759 if (hsotg->new_connection && 1760 ((port_status & 1761 (USB_PORT_STAT_CONNECTION | 1762 USB_PORT_STAT_HIGH_SPEED | 1763 USB_PORT_STAT_LOW_SPEED)) == 1764 USB_PORT_STAT_CONNECTION)) { 1765 u32 hcfg; 1766 1767 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 1768 hsotg->core_params->dma_desc_enable = 1; 1769 hcfg = DWC2_READ_4(hsotg, HCFG); 1770 hcfg |= HCFG_DESCDMA; 1771 DWC2_WRITE_4(hsotg, HCFG, hcfg); 1772 hsotg->new_connection = false; 1773 } 1774 } 1775 dev_vdbg(hsotg->dev, "wPortStatus=%04x\n", port_status); 1776 memcpy(buf, &ps, sizeof(ps)); 1777 break; 1778 1779 case SetHubFeature: 1780 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1781 /* No HUB features supported */ 1782 break; 1783 1784 case SetPortFeature: 1785 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1786 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1787 goto error; 1788 1789 if (!hsotg->flags.b.port_connect_status) { 1790 /* 1791 * The port is disconnected, which means the core is 1792 * either in device mode or it soon will be. Just 1793 * return without doing anything since the port 1794 * register can't be written if the core is in device 1795 * mode. 1796 */ 1797 break; 1798 } 1799 1800 switch (wvalue) { 1801 case USB_PORT_FEAT_SUSPEND: 1802 dev_dbg(hsotg->dev, 1803 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1804 if (windex != hsotg->otg_port) 1805 goto error; 1806 dwc2_port_suspend(hsotg, windex); 1807 break; 1808 1809 case USB_PORT_FEAT_POWER: 1810 dev_dbg(hsotg->dev, 1811 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1812 hprt0 = dwc2_read_hprt0(hsotg); 1813 hprt0 |= HPRT0_PWR; 1814 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1815 break; 1816 1817 case USB_PORT_FEAT_RESET: 1818 hprt0 = dwc2_read_hprt0(hsotg); 1819 dev_dbg(hsotg->dev, 1820 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1821 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1822 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1823 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1824 /* ??? Original driver does this */ 1825 DWC2_WRITE_4(hsotg, PCGCTL, 0); 1826 1827 hprt0 = dwc2_read_hprt0(hsotg); 1828 /* Clear suspend bit if resetting from suspend state */ 1829 hprt0 &= ~HPRT0_SUSP; 1830 1831 /* 1832 * When B-Host the Port reset bit is set in the Start 1833 * HCD Callback function, so that the reset is started 1834 * within 1ms of the HNP success interrupt 1835 */ 1836 if (!dwc2_hcd_is_b_host(hsotg)) { 1837 hprt0 |= HPRT0_PWR | HPRT0_RST; 1838 dev_dbg(hsotg->dev, 1839 "In host mode, hprt0=%08x\n", hprt0); 1840 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1841 } 1842 1843 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1844 usleep_range(50000, 70000); 1845 hprt0 &= ~HPRT0_RST; 1846 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1847 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1848 break; 1849 1850 case USB_PORT_FEAT_INDICATOR: 1851 dev_dbg(hsotg->dev, 1852 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1853 /* Not supported */ 1854 break; 1855 1856 case USB_PORT_FEAT_TEST: 1857 hprt0 = dwc2_read_hprt0(hsotg); 1858 dev_dbg(hsotg->dev, 1859 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 1860 hprt0 &= ~HPRT0_TSTCTL_MASK; 1861 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 1862 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1863 break; 1864 1865 default: 1866 retval = -EINVAL; 1867 dev_err(hsotg->dev, 1868 "SetPortFeature %1xh unknown or unsupported\n", 1869 wvalue); 1870 break; 1871 } 1872 break; 1873 1874 default: 1875 error: 1876 retval = -EINVAL; 1877 dev_dbg(hsotg->dev, 1878 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1879 typereq, windex, wvalue); 1880 break; 1881 } 1882 1883 return retval; 1884 } 1885 1886 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1887 { 1888 u32 hfnum = DWC2_READ_4(hsotg, HFNUM); 1889 1890 #ifdef DWC2_DEBUG_SOF 1891 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1892 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1893 #endif 1894 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1895 } 1896 1897 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1898 { 1899 return hsotg->op_state == OTG_STATE_B_HOST; 1900 } 1901 1902 struct dwc2_hcd_urb * 1903 dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, int iso_desc_count, 1904 gfp_t mem_flags) 1905 { 1906 struct dwc2_hcd_urb *urb; 1907 u32 size = sizeof(*urb) + iso_desc_count * 1908 sizeof(struct dwc2_hcd_iso_packet_desc); 1909 1910 urb = malloc(size, M_DEVBUF, M_ZERO | mem_flags); 1911 if (urb) 1912 urb->packet_count = iso_desc_count; 1913 return urb; 1914 } 1915 1916 void 1917 dwc2_hcd_urb_free(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 1918 int iso_desc_count) 1919 { 1920 1921 u32 size = sizeof(*urb) + iso_desc_count * 1922 sizeof(struct dwc2_hcd_iso_packet_desc); 1923 1924 free(urb, M_DEVBUF, size); 1925 } 1926 1927 void 1928 dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 1929 u8 dev_addr, u8 ep_num, u8 ep_type, u8 ep_dir, 1930 u16 mps) 1931 { 1932 if (dbg_perio() || 1933 ep_type == USB_ENDPOINT_XFER_BULK || 1934 ep_type == USB_ENDPOINT_XFER_CONTROL) 1935 dev_dbg(hsotg->dev, "urb=%p, xfer=%p\n", urb, urb->priv); 1936 urb->pipe_info.dev_addr = dev_addr; 1937 urb->pipe_info.ep_num = ep_num; 1938 urb->pipe_info.pipe_type = ep_type; 1939 urb->pipe_info.pipe_dir = ep_dir; 1940 urb->pipe_info.mps = mps; 1941 } 1942 1943 /* 1944 * NOTE: This function will be removed once the peripheral controller code 1945 * is integrated and the driver is stable 1946 */ 1947 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1948 { 1949 #ifdef DWC2_DEBUG 1950 struct dwc2_host_chan *chan; 1951 struct dwc2_hcd_urb *urb; 1952 struct dwc2_qtd *qtd; 1953 int num_channels; 1954 u32 np_tx_status; 1955 u32 p_tx_status; 1956 int i; 1957 1958 num_channels = hsotg->core_params->host_channels; 1959 dev_dbg(hsotg->dev, "\n"); 1960 dev_dbg(hsotg->dev, 1961 "************************************************************\n"); 1962 dev_dbg(hsotg->dev, "HCD State:\n"); 1963 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 1964 1965 for (i = 0; i < num_channels; i++) { 1966 chan = hsotg->hc_ptr_array[i]; 1967 dev_dbg(hsotg->dev, " Channel %d:\n", i); 1968 dev_dbg(hsotg->dev, 1969 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 1970 chan->dev_addr, chan->ep_num, chan->ep_is_in); 1971 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 1972 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 1973 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 1974 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 1975 chan->data_pid_start); 1976 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 1977 dev_dbg(hsotg->dev, " xfer_started: %d\n", 1978 chan->xfer_started); 1979 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 1980 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 1981 (unsigned long)chan->xfer_dma); 1982 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 1983 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 1984 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 1985 chan->halt_on_queue); 1986 dev_dbg(hsotg->dev, " halt_pending: %d\n", 1987 chan->halt_pending); 1988 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 1989 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 1990 dev_dbg(hsotg->dev, " complete_split: %d\n", 1991 chan->complete_split); 1992 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 1993 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 1994 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 1995 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 1996 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 1997 1998 if (chan->xfer_started) { 1999 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", 2000 DWC2_READ_4(hsotg, HFNUM)); 2001 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", 2002 DWC2_READ_4(hsotg, HCCHAR(i))); 2003 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", 2004 DWC2_READ_4(hsotg, HCTSIZ(i))); 2005 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", 2006 DWC2_READ_4(hsotg, HCINT(i))); 2007 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", 2008 DWC2_READ_4(hsotg, HCINTMSK(i))); 2009 } 2010 2011 if (!(chan->xfer_started && chan->qh)) 2012 continue; 2013 2014 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 2015 if (!qtd->in_process) 2016 break; 2017 urb = qtd->urb; 2018 dev_dbg(hsotg->dev, " URB Info:\n"); 2019 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 2020 qtd, urb); 2021 if (urb) { 2022 dev_dbg(hsotg->dev, 2023 " Dev: %d, EP: %d %s\n", 2024 dwc2_hcd_get_dev_addr(&urb->pipe_info), 2025 dwc2_hcd_get_ep_num(&urb->pipe_info), 2026 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 2027 "IN" : "OUT"); 2028 dev_dbg(hsotg->dev, 2029 " Max packet size: %d\n", 2030 dwc2_hcd_get_mps(&urb->pipe_info)); 2031 dev_dbg(hsotg->dev, 2032 " transfer_buffer: %p\n", 2033 urb->buf); 2034 dev_dbg(hsotg->dev, 2035 " transfer_dma: %08lx\n", 2036 (unsigned long)urb->dma); 2037 dev_dbg(hsotg->dev, 2038 " transfer_buffer_length: %d\n", 2039 urb->length); 2040 dev_dbg(hsotg->dev, " actual_length: %d\n", 2041 urb->actual_length); 2042 } 2043 } 2044 } 2045 2046 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 2047 hsotg->non_periodic_channels); 2048 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 2049 hsotg->periodic_channels); 2050 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 2051 np_tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 2052 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 2053 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2054 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 2055 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2056 p_tx_status = DWC2_READ_4(hsotg, HPTXSTS); 2057 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 2058 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2059 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 2060 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2061 dwc2_hcd_dump_frrem(hsotg); 2062 2063 dwc2_dump_global_registers(hsotg); 2064 dwc2_dump_host_registers(hsotg); 2065 dev_dbg(hsotg->dev, 2066 "************************************************************\n"); 2067 dev_dbg(hsotg->dev, "\n"); 2068 #endif 2069 } 2070 2071 /* 2072 * NOTE: This function will be removed once the peripheral controller code 2073 * is integrated and the driver is stable 2074 */ 2075 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 2076 { 2077 #ifdef DWC2_DUMP_FRREM 2078 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 2079 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2080 hsotg->frrem_samples, hsotg->frrem_accum, 2081 hsotg->frrem_samples > 0 ? 2082 hsotg->frrem_accum / hsotg->frrem_samples : 0); 2083 dev_dbg(hsotg->dev, "\n"); 2084 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 2085 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2086 hsotg->hfnum_7_samples, 2087 hsotg->hfnum_7_frrem_accum, 2088 hsotg->hfnum_7_samples > 0 ? 2089 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 2090 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 2091 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2092 hsotg->hfnum_0_samples, 2093 hsotg->hfnum_0_frrem_accum, 2094 hsotg->hfnum_0_samples > 0 ? 2095 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 2096 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 2097 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2098 hsotg->hfnum_other_samples, 2099 hsotg->hfnum_other_frrem_accum, 2100 hsotg->hfnum_other_samples > 0 ? 2101 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 2102 0); 2103 dev_dbg(hsotg->dev, "\n"); 2104 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 2105 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2106 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 2107 hsotg->hfnum_7_samples_a > 0 ? 2108 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 2109 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 2110 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2111 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 2112 hsotg->hfnum_0_samples_a > 0 ? 2113 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 2114 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 2115 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2116 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 2117 hsotg->hfnum_other_samples_a > 0 ? 2118 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 2119 : 0); 2120 dev_dbg(hsotg->dev, "\n"); 2121 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 2122 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2123 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 2124 hsotg->hfnum_7_samples_b > 0 ? 2125 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 2126 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 2127 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2128 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 2129 (hsotg->hfnum_0_samples_b > 0) ? 2130 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 2131 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 2132 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2133 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 2134 (hsotg->hfnum_other_samples_b > 0) ? 2135 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 2136 : 0); 2137 #endif 2138 } 2139 2140 struct wrapper_priv_data { 2141 struct dwc2_hsotg *hsotg; 2142 }; 2143 2144 2145 void dwc2_host_start(struct dwc2_hsotg *hsotg) 2146 { 2147 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2148 2149 // hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2150 _dwc2_hcd_start(hsotg); 2151 } 2152 2153 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2154 { 2155 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2156 2157 // hcd->self.is_b_host = 0; 2158 } 2159 2160 /* 2161 * Work queue function for starting the HCD when A-Cable is connected 2162 */ 2163 STATIC void dwc2_hcd_start_func(void *data) 2164 { 2165 struct dwc2_hsotg *hsotg = data; 2166 2167 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2168 dwc2_host_start(hsotg); 2169 } 2170 2171 /* 2172 * Reset work queue function 2173 */ 2174 STATIC void dwc2_hcd_reset_func(void *data) 2175 { 2176 struct dwc2_hsotg *hsotg = data; 2177 unsigned long flags; 2178 u32 hprt0; 2179 2180 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2181 2182 spin_lock_irqsave(&hsotg->lock, flags); 2183 2184 hprt0 = dwc2_read_hprt0(hsotg); 2185 hprt0 &= ~HPRT0_RST; 2186 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 2187 hsotg->flags.b.port_reset_change = 1; 2188 2189 dwc2_root_intr(hsotg->hsotg_sc); 2190 2191 spin_unlock_irqrestore(&hsotg->lock, flags); 2192 } 2193 2194 /* 2195 * ========================================================================= 2196 * Linux HC Driver Functions 2197 * ========================================================================= 2198 */ 2199 2200 /* 2201 * Initializes the DWC_otg controller and its root hub and prepares it for host 2202 * mode operation. Activates the root port. Returns 0 on success and a negative 2203 * error code on failure. 2204 */ 2205 2206 /* 2207 * Frees secondary storage associated with the dwc2_hsotg structure contained 2208 * in the struct usb_hcd field 2209 */ 2210 STATIC void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2211 { 2212 u32 ahbcfg; 2213 u32 dctl; 2214 int i; 2215 2216 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2217 2218 /* Free memory for QH/QTD lists */ 2219 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2220 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting); 2221 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2222 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2223 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2224 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 2225 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 2226 2227 /* Free memory for the host channels */ 2228 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 2229 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 2230 2231 if (chan != NULL) { 2232 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 2233 i, chan); 2234 hsotg->hc_ptr_array[i] = NULL; 2235 free(chan, M_DEVBUF, sizeof(*chan)); 2236 } 2237 } 2238 2239 if (hsotg->core_params->dma_enable > 0) { 2240 if (hsotg->status_buf) { 2241 usb_freemem(&hsotg->hsotg_sc->sc_bus, 2242 &hsotg->status_buf_usbdma); 2243 hsotg->status_buf = NULL; 2244 } 2245 } else { 2246 free(hsotg->status_buf, M_DEVBUF, DWC2_HCD_STATUS_BUF_SIZE); 2247 hsotg->status_buf = NULL; 2248 } 2249 2250 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 2251 2252 /* Disable all interrupts */ 2253 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2254 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 2255 DWC2_WRITE_4(hsotg, GINTMSK, 0); 2256 2257 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 2258 dctl = DWC2_READ_4(hsotg, DCTL); 2259 dctl |= DCTL_SFTDISCON; 2260 DWC2_WRITE_4(hsotg, DCTL, dctl); 2261 } 2262 2263 if (hsotg->wq_otg) { 2264 taskq_destroy(hsotg->wq_otg); 2265 } 2266 2267 free(hsotg->core_params, M_DEVBUF, sizeof(*hsotg->core_params)); 2268 hsotg->core_params = NULL; 2269 timeout_del(&hsotg->wkp_timer); 2270 } 2271 2272 STATIC void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 2273 { 2274 /* Turn off all host-specific interrupts */ 2275 dwc2_disable_host_interrupts(hsotg); 2276 2277 dwc2_hcd_free(hsotg); 2278 } 2279 2280 /* 2281 * Initializes the HCD. This function allocates memory for and initializes the 2282 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 2283 * USB bus with the core and calls the hc_driver->start() function. It returns 2284 * a negative error on failure. 2285 */ 2286 int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 2287 { 2288 struct dwc2_host_chan *channel; 2289 int i, num_channels; 2290 int retval; 2291 2292 if (usb_disabled()) 2293 return -ENODEV; 2294 2295 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 2296 2297 retval = -ENOMEM; 2298 2299 dev_dbg(hsotg->dev, "hcfg=%08x\n", DWC2_READ_4(hsotg, HCFG)); 2300 2301 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2302 hsotg->frame_num_array = malloc(sizeof(*hsotg->frame_num_array) * 2303 FRAME_NUM_ARRAY_SIZE, M_DEVBUF, 2304 M_ZERO | M_WAITOK); 2305 if (!hsotg->frame_num_array) 2306 goto error1; 2307 hsotg->last_frame_num_array = malloc( 2308 sizeof(*hsotg->last_frame_num_array) * 2309 FRAME_NUM_ARRAY_SIZE, M_DEVBUF, M_ZERO | M_WAITOK); 2310 if (!hsotg->last_frame_num_array) 2311 goto error1; 2312 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 2313 #endif 2314 2315 spin_lock_init(&hsotg->lock); 2316 2317 /* 2318 * Disable the global interrupt until all the interrupt handlers are 2319 * installed 2320 */ 2321 dwc2_disable_global_interrupts(hsotg); 2322 2323 /* Initialize the DWC_otg core, and select the Phy type */ 2324 retval = dwc2_core_init(hsotg, true); 2325 if (retval) 2326 goto error2; 2327 2328 /* Create new workqueue and init work */ 2329 retval = -ENOMEM; 2330 hsotg->wq_otg = taskq_create("dwc2", 1, IPL_USB, 0); 2331 if (!hsotg->wq_otg) { 2332 dev_err(hsotg->dev, "Failed to create workqueue\n"); 2333 goto error2; 2334 } 2335 task_set(&hsotg->wf_otg, dwc2_conn_id_status_change, hsotg); 2336 2337 timeout_set(&hsotg->wkp_timer, dwc2_wakeup_detected, hsotg); 2338 2339 /* Initialize the non-periodic schedule */ 2340 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 2341 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting); 2342 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 2343 2344 /* Initialize the periodic schedule */ 2345 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 2346 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 2347 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 2348 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 2349 2350 /* 2351 * Create a host channel descriptor for each host channel implemented 2352 * in the controller. Initialize the channel descriptor array. 2353 */ 2354 INIT_LIST_HEAD(&hsotg->free_hc_list); 2355 num_channels = hsotg->core_params->host_channels; 2356 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 2357 2358 for (i = 0; i < num_channels; i++) { 2359 channel = malloc(sizeof(*channel), M_DEVBUF, M_ZERO | M_WAITOK); 2360 if (channel == NULL) 2361 goto error3; 2362 channel->hc_num = i; 2363 hsotg->hc_ptr_array[i] = channel; 2364 } 2365 2366 if (hsotg->core_params->uframe_sched > 0) 2367 dwc2_hcd_init_usecs(hsotg); 2368 2369 /* Initialize hsotg start work */ 2370 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func, hsotg); 2371 2372 /* Initialize port reset work */ 2373 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func, hsotg); 2374 2375 /* 2376 * Allocate space for storing data on status transactions. Normally no 2377 * data is sent, but this space acts as a bit bucket. This must be 2378 * done after usb_add_hcd since that function allocates the DMA buffer 2379 * pool. 2380 */ 2381 hsotg->status_buf = NULL; 2382 if (hsotg->core_params->dma_enable > 0) { 2383 int error = usb_allocmem(&hsotg->hsotg_sc->sc_bus, 2384 DWC2_HCD_STATUS_BUF_SIZE, 0, USB_DMA_COHERENT, 2385 &hsotg->status_buf_usbdma); 2386 if (!error) { 2387 hsotg->status_buf = KERNADDR(&hsotg->status_buf_usbdma, 0); 2388 hsotg->status_buf_dma = DMAADDR(&hsotg->status_buf_usbdma, 0); 2389 } 2390 } else 2391 hsotg->status_buf = malloc(DWC2_HCD_STATUS_BUF_SIZE, M_DEVBUF, 2392 M_ZERO | M_WAITOK); 2393 2394 /* retval is already -ENOMEM */ 2395 if (!hsotg->status_buf) 2396 goto error3; 2397 2398 hsotg->otg_port = 1; 2399 hsotg->frame_list = NULL; 2400 hsotg->frame_list_dma = 0; 2401 hsotg->periodic_qh_count = 0; 2402 2403 /* Initiate lx_state to L3 disconnected state */ 2404 hsotg->lx_state = DWC2_L3; 2405 2406 _dwc2_hcd_start(hsotg); 2407 2408 dwc2_hcd_dump_state(hsotg); 2409 2410 dwc2_enable_global_interrupts(hsotg); 2411 2412 return 0; 2413 2414 error3: 2415 dwc2_hcd_release(hsotg); 2416 error2: 2417 if (hsotg->core_params != NULL) 2418 free(hsotg->core_params, M_DEVBUF, sizeof(*hsotg->core_params)); 2419 2420 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2421 if (hsotg->last_frame_num_array != NULL) 2422 free(hsotg->last_frame_num_array, M_DEVBUF, 2423 sizeof(*hsotg->last_frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2424 if (hsotg->frame_num_array != NULL) 2425 free(hsotg->frame_num_array, M_DEVBUF, 2426 sizeof(*hsotg->frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2427 #endif 2428 2429 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 2430 return retval; 2431 } 2432 2433 /* 2434 * Removes the HCD. 2435 * Frees memory and resources associated with the HCD and deregisters the bus. 2436 */ 2437 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 2438 { 2439 struct usb_hcd *hcd; 2440 2441 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 2442 2443 hcd = dwc2_hsotg_to_hcd(hsotg); 2444 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 2445 2446 if (!hcd) { 2447 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 2448 __func__); 2449 return; 2450 } 2451 hsotg->priv = NULL; 2452 2453 dwc2_hcd_release(hsotg); 2454 2455 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2456 free(hsotg->last_frame_num_array, M_DEVBUF, sizeof(*hsotg->last_frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2457 free(hsotg->frame_num_array, M_DEVBUF, sizeof(*hsotg->frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2458 #endif 2459 } 2460