1 /* $OpenBSD: dwc2_hcd.c,v 1.16 2015/06/28 11:48:18 jmatthew Exp $ */ 2 /* $NetBSD: dwc2_hcd.c,v 1.15 2014/11/24 10:14:14 skrll Exp $ */ 3 4 /* 5 * hcd.c - DesignWare HS OTG Controller host-mode routines 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * This file contains the core HCD code, and implements the Linux hc_driver 42 * API 43 */ 44 45 #if 0 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: dwc2_hcd.c,v 1.15 2014/11/24 10:14:14 skrll Exp $"); 48 #endif 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/types.h> 53 #include <sys/malloc.h> 54 #include <sys/signal.h> 55 #include <sys/proc.h> 56 #include <sys/pool.h> 57 #include <sys/task.h> 58 59 #include <machine/bus.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 66 #include <dev/usb/dwc2/dwc2.h> 67 #include <dev/usb/dwc2/dwc2var.h> 68 69 #include <dev/usb/dwc2/dwc2_core.h> 70 #include <dev/usb/dwc2/dwc2_hcd.h> 71 72 /** 73 * dwc2_dump_channel_info() - Prints the state of a host channel 74 * 75 * @hsotg: Programming view of DWC_otg controller 76 * @chan: Pointer to the channel to dump 77 * 78 * Must be called with interrupt disabled and spinlock held 79 * 80 * NOTE: This function will be removed once the peripheral controller code 81 * is integrated and the driver is stable 82 */ 83 #ifdef VERBOSE_DEBUG 84 STATIC void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 85 struct dwc2_host_chan *chan) 86 { 87 int num_channels = hsotg->core_params->host_channels; 88 struct dwc2_qh *qh; 89 u32 hcchar; 90 u32 hcsplt; 91 u32 hctsiz; 92 u32 hc_dma; 93 int i; 94 95 if (chan == NULL) 96 return; 97 98 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 99 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chan->hc_num)); 100 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chan->hc_num)); 101 hc_dma = DWC2_READ_4(hsotg, HCDMA(chan->hc_num)); 102 103 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 104 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 105 hcchar, hcsplt); 106 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 107 hctsiz, hc_dma); 108 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 109 chan->dev_addr, chan->ep_num, chan->ep_is_in); 110 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 111 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 112 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 113 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 114 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 115 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 116 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 117 (unsigned long)chan->xfer_dma); 118 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 119 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 120 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 121 TAILQ_FOREACH(qh, &hsotg->non_periodic_sched_inactive, qh_list_entry) 122 dev_dbg(hsotg->dev, " %p\n", qh); 123 dev_dbg(hsotg->dev, " NP active sched:\n"); 124 TAILQ_FOREACH(qh, &hsotg->non_periodic_sched_active, qh_list_entry) 125 dev_dbg(hsotg->dev, " %p\n", qh); 126 dev_dbg(hsotg->dev, " Channels:\n"); 127 for (i = 0; i < num_channels; i++) { 128 struct dwc2_host_chan *ch = hsotg->hc_ptr_array[i]; 129 130 dev_dbg(hsotg->dev, " %2d: %p\n", i, ch); 131 } 132 } 133 #endif /* VERBOSE_DEBUG */ 134 135 /* 136 * Processes all the URBs in a single list of QHs. Completes them with 137 * -ETIMEDOUT and frees the QTD. 138 * 139 * Must be called with interrupt disabled and spinlock held 140 */ 141 STATIC void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 142 struct dwc2_qh_list *qh_list) 143 { 144 struct dwc2_qh *qh, *qh_tmp; 145 struct dwc2_qtd *qtd, *qtd_tmp; 146 147 TAILQ_FOREACH_SAFE(qh, qh_list, qh_list_entry, qh_tmp) { 148 TAILQ_FOREACH_SAFE(qtd, &qh->qtd_list, qtd_list_entry, qtd_tmp) { 149 dwc2_host_complete(hsotg, qtd, -ETIMEDOUT); 150 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 151 } 152 } 153 } 154 155 STATIC void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 156 struct dwc2_qh_list *qh_list) 157 { 158 struct dwc2_qtd *qtd, *qtd_tmp; 159 struct dwc2_qh *qh, *qh_tmp; 160 unsigned long flags; 161 162 if (TAILQ_EMPTY(qh_list)) { 163 /* The list hasn't been initialized yet */ 164 return; 165 } 166 167 spin_lock_irqsave(&hsotg->lock, flags); 168 169 /* Ensure there are no QTDs or URBs left */ 170 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 171 172 TAILQ_FOREACH_SAFE(qh, qh_list, qh_list_entry, qh_tmp) { 173 dwc2_hcd_qh_unlink(hsotg, qh); 174 175 /* Free each QTD in the QH's QTD list */ 176 TAILQ_FOREACH_SAFE(qtd, &qh->qtd_list, qtd_list_entry, qtd_tmp) { 177 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 178 } 179 180 spin_unlock_irqrestore(&hsotg->lock, flags); 181 dwc2_hcd_qh_free(hsotg, qh); 182 spin_lock_irqsave(&hsotg->lock, flags); 183 } 184 185 spin_unlock_irqrestore(&hsotg->lock, flags); 186 } 187 188 /* 189 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 190 * and periodic schedules. The QTD associated with each URB is removed from 191 * the schedule and freed. This function may be called when a disconnect is 192 * detected or when the HCD is being stopped. 193 * 194 * Must be called with interrupt disabled and spinlock held 195 */ 196 STATIC void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 197 { 198 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 199 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 200 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 201 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 202 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 203 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 204 } 205 206 /** 207 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 208 * 209 * @hsotg: Pointer to struct dwc2_hsotg 210 */ 211 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 212 { 213 u32 hprt0; 214 215 if (hsotg->op_state == OTG_STATE_B_HOST) { 216 /* 217 * Reset the port. During a HNP mode switch the reset 218 * needs to occur within 1ms and have a duration of at 219 * least 50ms. 220 */ 221 hprt0 = dwc2_read_hprt0(hsotg); 222 hprt0 |= HPRT0_RST; 223 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 224 } 225 226 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 227 msecs_to_jiffies(50)); 228 } 229 230 /* Must be called with interrupt disabled and spinlock held */ 231 STATIC void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 232 { 233 int num_channels = hsotg->core_params->host_channels; 234 struct dwc2_host_chan *channel; 235 u32 hcchar; 236 int i; 237 238 if (hsotg->core_params->dma_enable <= 0) { 239 /* Flush out any channel requests in slave mode */ 240 for (i = 0; i < num_channels; i++) { 241 channel = hsotg->hc_ptr_array[i]; 242 if (channel->in_freelist == 0) 243 continue; 244 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 245 if (hcchar & HCCHAR_CHENA) { 246 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 247 hcchar |= HCCHAR_CHDIS; 248 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 249 } 250 } 251 } 252 253 for (i = 0; i < num_channels; i++) { 254 channel = hsotg->hc_ptr_array[i]; 255 if (channel->in_freelist != 0) 256 continue; 257 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 258 if (hcchar & HCCHAR_CHENA) { 259 /* Halt the channel */ 260 hcchar |= HCCHAR_CHDIS; 261 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 262 } 263 264 dwc2_hc_cleanup(hsotg, channel); 265 LIST_INSERT_HEAD(&hsotg->free_hc_list, channel, hc_list_entry); 266 channel->in_freelist = 1; 267 /* 268 * Added for Descriptor DMA to prevent channel double cleanup in 269 * release_channel_ddma(), which is called from ep_disable when 270 * device disconnects 271 */ 272 channel->qh = NULL; 273 } 274 } 275 276 /** 277 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 278 * 279 * @hsotg: Pointer to struct dwc2_hsotg 280 * 281 * Must be called with interrupt disabled and spinlock held 282 */ 283 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) 284 { 285 u32 intr; 286 287 /* Set status flags for the hub driver */ 288 hsotg->flags.b.port_connect_status_change = 1; 289 hsotg->flags.b.port_connect_status = 0; 290 291 /* 292 * Shutdown any transfers in process by clearing the Tx FIFO Empty 293 * interrupt mask and status bits and disabling subsequent host 294 * channel interrupts. 295 */ 296 intr = DWC2_READ_4(hsotg, GINTMSK); 297 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 298 DWC2_WRITE_4(hsotg, GINTMSK, intr); 299 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 300 DWC2_WRITE_4(hsotg, GINTSTS, intr); 301 302 /* 303 * Turn off the vbus power only if the core has transitioned to device 304 * mode. If still in host mode, need to keep power on to detect a 305 * reconnection. 306 */ 307 if (dwc2_is_device_mode(hsotg)) { 308 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 309 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 310 DWC2_WRITE_4(hsotg, HPRT0, 0); 311 } 312 313 dwc2_disable_host_interrupts(hsotg); 314 } 315 316 /* Respond with an error status to all URBs in the schedule */ 317 dwc2_kill_all_urbs(hsotg); 318 319 if (dwc2_is_host_mode(hsotg)) 320 /* Clean up any host channels that were in use */ 321 dwc2_hcd_cleanup_channels(hsotg); 322 323 dwc2_host_disconnect(hsotg); 324 325 dwc2_root_intr(hsotg->hsotg_sc); 326 } 327 328 /** 329 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 330 * 331 * @hsotg: Pointer to struct dwc2_hsotg 332 */ 333 STATIC void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 334 { 335 if (hsotg->lx_state == DWC2_L2) 336 hsotg->flags.b.port_suspend_change = 1; 337 else 338 hsotg->flags.b.port_l1_change = 1; 339 340 dwc2_root_intr(hsotg->hsotg_sc); 341 } 342 343 /** 344 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 345 * 346 * @hsotg: Pointer to struct dwc2_hsotg 347 * 348 * Must be called with interrupt disabled and spinlock held 349 */ 350 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 351 { 352 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 353 354 /* 355 * The root hub should be disconnected before this function is called. 356 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 357 * and the QH lists (via ..._hcd_endpoint_disable). 358 */ 359 360 /* Turn off all host-specific interrupts */ 361 dwc2_disable_host_interrupts(hsotg); 362 363 /* Turn off the vbus power */ 364 dev_dbg(hsotg->dev, "PortPower off\n"); 365 DWC2_WRITE_4(hsotg, HPRT0, 0); 366 } 367 368 int 369 dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 370 void **ep_handle, gfp_t mem_flags) 371 { 372 struct dwc2_softc *sc = hsotg->hsotg_sc; 373 struct dwc2_qtd *qtd; 374 u32 intr_mask; 375 int retval; 376 int dev_speed; 377 378 if (!hsotg->flags.b.port_connect_status) { 379 /* No longer connected */ 380 dev_err(hsotg->dev, "Not connected\n"); 381 return -ENODEV; 382 } 383 384 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 385 386 /* Some core configurations cannot support LS traffic on a FS root port */ 387 if ((dev_speed == USB_SPEED_LOW) && 388 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 389 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 390 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 391 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 392 393 if (prtspd == HPRT0_SPD_FULL_SPEED) { 394 return -ENODEV; 395 } 396 } 397 398 qtd = pool_get(&sc->sc_qtdpool, PR_NOWAIT); 399 if (!qtd) 400 return -ENOMEM; 401 402 memset(qtd, 0, sizeof(*qtd)); 403 404 dwc2_hcd_qtd_init(qtd, urb); 405 retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle, 406 mem_flags); 407 if (retval) { 408 dev_err(hsotg->dev, 409 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 410 retval); 411 pool_put(&sc->sc_qtdpool, qtd); 412 return retval; 413 } 414 415 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 416 if (!(intr_mask & GINTSTS_SOF)) { 417 enum dwc2_transaction_type tr_type; 418 419 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 420 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 421 /* 422 * Do not schedule SG transactions until qtd has 423 * URB_GIVEBACK_ASAP set 424 */ 425 return 0; 426 427 tr_type = dwc2_hcd_select_transactions(hsotg); 428 if (tr_type != DWC2_TRANSACTION_NONE) 429 dwc2_hcd_queue_transactions(hsotg, tr_type); 430 } 431 432 return 0; 433 } 434 435 /* Must be called with interrupt disabled and spinlock held */ 436 int 437 dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 438 struct dwc2_hcd_urb *urb) 439 { 440 struct dwc2_qh *qh; 441 struct dwc2_qtd *urb_qtd; 442 443 urb_qtd = urb->qtd; 444 if (!urb_qtd) { 445 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 446 return -EINVAL; 447 } 448 449 qh = urb_qtd->qh; 450 if (!qh) { 451 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 452 return -EINVAL; 453 } 454 455 urb->priv = NULL; 456 457 if (urb_qtd->in_process && qh->channel) { 458 #ifdef VERBOSE_DEBUG 459 dwc2_dump_channel_info(hsotg, qh->channel); 460 #endif 461 /* The QTD is in process (it has been assigned to a channel) */ 462 if (hsotg->flags.b.port_connect_status) 463 /* 464 * If still connected (i.e. in host mode), halt the 465 * channel so it can be used for other transfers. If 466 * no longer connected, the host registers can't be 467 * written to halt the channel since the core is in 468 * device mode. 469 */ 470 dwc2_hc_halt(hsotg, qh->channel, 471 DWC2_HC_XFER_URB_DEQUEUE); 472 } 473 474 /* 475 * Free the QTD and clean up the associated QH. Leave the QH in the 476 * schedule if it has any remaining QTDs. 477 */ 478 if (hsotg->core_params->dma_desc_enable <= 0) { 479 u8 in_process = urb_qtd->in_process; 480 481 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 482 if (in_process) { 483 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 484 qh->channel = NULL; 485 } else if (TAILQ_EMPTY(&qh->qtd_list)) { 486 dwc2_hcd_qh_unlink(hsotg, qh); 487 } 488 } else { 489 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 490 } 491 492 return 0; 493 } 494 495 496 /* 497 * Initializes dynamic portions of the DWC_otg HCD state 498 * 499 * Must be called with interrupt disabled and spinlock held 500 */ 501 void 502 dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 503 { 504 struct dwc2_host_chan *chan, *chan_tmp; 505 int num_channels; 506 int i; 507 508 hsotg->flags.d32 = 0; 509 hsotg->non_periodic_qh_ptr = NULL; 510 511 if (hsotg->core_params->uframe_sched > 0) { 512 hsotg->available_host_channels = 513 hsotg->core_params->host_channels; 514 } else { 515 hsotg->non_periodic_channels = 0; 516 hsotg->periodic_channels = 0; 517 } 518 519 /* 520 * Put all channels in the free channel list and clean up channel 521 * states 522 */ 523 LIST_FOREACH_SAFE(chan, &hsotg->free_hc_list, hc_list_entry, chan_tmp) { 524 LIST_REMOVE(chan, hc_list_entry); 525 chan->in_freelist = 0; 526 } 527 528 num_channels = hsotg->core_params->host_channels; 529 for (i = 0; i < num_channels; i++) { 530 chan = hsotg->hc_ptr_array[i]; 531 LIST_INSERT_HEAD(&hsotg->free_hc_list, chan, hc_list_entry); 532 chan->in_freelist = 1; 533 dwc2_hc_cleanup(hsotg, chan); 534 } 535 536 /* Initialize the DWC core for host mode operation */ 537 dwc2_core_host_init(hsotg); 538 } 539 540 STATIC void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 541 struct dwc2_host_chan *chan, 542 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 543 { 544 int hub_addr, hub_port; 545 546 chan->do_split = 1; 547 chan->xact_pos = qtd->isoc_split_pos; 548 chan->complete_split = qtd->complete_split; 549 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 550 chan->hub_addr = (u8)hub_addr; 551 chan->hub_port = (u8)hub_port; 552 } 553 554 STATIC void *dwc2_hc_init_xfer_data(struct dwc2_hsotg *hsotg, 555 struct dwc2_host_chan *chan, 556 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 557 { 558 if (hsotg->core_params->dma_enable > 0) { 559 chan->xfer_dma = DMAADDR(urb->usbdma, urb->actual_length); 560 561 /* For non-dword aligned case */ 562 if (hsotg->core_params->dma_desc_enable <= 0 && 563 (chan->xfer_dma & 0x3)) 564 return (u8 *)urb->buf + urb->actual_length; 565 } else { 566 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 567 } 568 569 return NULL; 570 } 571 572 STATIC void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 573 struct dwc2_host_chan *chan, 574 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 575 { 576 struct dwc2_hcd_iso_packet_desc *frame_desc; 577 void *bufptr = NULL; 578 579 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 580 case USB_ENDPOINT_XFER_CONTROL: 581 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 582 583 switch (qtd->control_phase) { 584 case DWC2_CONTROL_SETUP: 585 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 586 chan->do_ping = 0; 587 chan->ep_is_in = 0; 588 chan->data_pid_start = DWC2_HC_PID_SETUP; 589 if (hsotg->core_params->dma_enable > 0) 590 chan->xfer_dma = urb->setup_dma; 591 else 592 chan->xfer_buf = urb->setup_packet; 593 chan->xfer_len = 8; 594 break; 595 596 case DWC2_CONTROL_DATA: 597 dev_vdbg(hsotg->dev, " Control data transaction\n"); 598 chan->data_pid_start = qtd->data_toggle; 599 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 600 break; 601 602 case DWC2_CONTROL_STATUS: 603 /* 604 * Direction is opposite of data direction or IN if no 605 * data 606 */ 607 dev_vdbg(hsotg->dev, " Control status transaction\n"); 608 if (urb->length == 0) 609 chan->ep_is_in = 1; 610 else 611 chan->ep_is_in = 612 dwc2_hcd_is_pipe_out(&urb->pipe_info); 613 if (chan->ep_is_in) 614 chan->do_ping = 0; 615 chan->data_pid_start = DWC2_HC_PID_DATA1; 616 chan->xfer_len = 0; 617 if (hsotg->core_params->dma_enable > 0) 618 chan->xfer_dma = hsotg->status_buf_dma; 619 else 620 chan->xfer_buf = hsotg->status_buf; 621 break; 622 } 623 break; 624 625 case USB_ENDPOINT_XFER_BULK: 626 chan->ep_type = USB_ENDPOINT_XFER_BULK; 627 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 628 break; 629 630 case USB_ENDPOINT_XFER_INT: 631 chan->ep_type = USB_ENDPOINT_XFER_INT; 632 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 633 break; 634 635 case USB_ENDPOINT_XFER_ISOC: 636 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 637 if (hsotg->core_params->dma_desc_enable > 0) 638 break; 639 640 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 641 frame_desc->status = 0; 642 643 if (hsotg->core_params->dma_enable > 0) { 644 chan->xfer_dma = urb->dma; 645 chan->xfer_dma += frame_desc->offset + 646 qtd->isoc_split_offset; 647 } else { 648 chan->xfer_buf = urb->buf; 649 chan->xfer_buf += frame_desc->offset + 650 qtd->isoc_split_offset; 651 } 652 653 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 654 655 /* For non-dword aligned buffers */ 656 if (hsotg->core_params->dma_enable > 0 && 657 (chan->xfer_dma & 0x3)) 658 bufptr = (u8 *)urb->buf + frame_desc->offset + 659 qtd->isoc_split_offset; 660 661 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 662 if (chan->xfer_len <= 188) 663 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 664 else 665 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 666 } 667 break; 668 } 669 670 return bufptr; 671 } 672 673 STATIC int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 674 struct dwc2_host_chan *chan, void *bufptr) 675 { 676 u32 buf_size; 677 678 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) 679 buf_size = hsotg->core_params->max_transfer_size; 680 else 681 buf_size = 4096; 682 683 if (!qh->dw_align_buf) { 684 int err; 685 686 qh->dw_align_buf = NULL; 687 qh->dw_align_buf_dma = 0; 688 err = usb_allocmem(&hsotg->hsotg_sc->sc_bus, buf_size, buf_size, 689 &qh->dw_align_buf_usbdma); 690 if (!err) { 691 struct usb_dma *ud = &qh->dw_align_buf_usbdma; 692 693 qh->dw_align_buf = KERNADDR(ud, 0); 694 qh->dw_align_buf_dma = DMAADDR(ud, 0); 695 } 696 if (!qh->dw_align_buf) 697 return -ENOMEM; 698 } 699 700 if (!chan->ep_is_in && chan->xfer_len) { 701 usb_syncmem(chan->xfer_usbdma, 0, buf_size, 702 BUS_DMASYNC_POSTWRITE); 703 memcpy(qh->dw_align_buf, bufptr, chan->xfer_len); 704 usb_syncmem(chan->xfer_usbdma, 0, buf_size, 705 BUS_DMASYNC_PREWRITE); 706 } 707 708 chan->align_buf = qh->dw_align_buf_dma; 709 return 0; 710 } 711 712 /** 713 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 714 * channel and initializes the host channel to perform the transactions. The 715 * host channel is removed from the free list. 716 * 717 * @hsotg: The HCD state structure 718 * @qh: Transactions from the first QTD for this QH are selected and assigned 719 * to a free host channel 720 */ 721 STATIC int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 722 { 723 struct dwc2_host_chan *chan; 724 struct dwc2_hcd_urb *urb; 725 struct dwc2_qtd *qtd; 726 void *bufptr = NULL; 727 728 if (dbg_qh(qh)) 729 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 730 731 if (TAILQ_EMPTY(&qh->qtd_list)) { 732 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 733 return -ENOMEM; 734 } 735 736 if (LIST_EMPTY(&hsotg->free_hc_list)) { 737 dev_dbg(hsotg->dev, "No free channel to assign\n"); 738 return -ENOMEM; 739 } 740 741 chan = LIST_FIRST(&hsotg->free_hc_list); 742 743 /* Remove host channel from free list */ 744 LIST_REMOVE(chan, hc_list_entry); 745 chan->in_freelist = 0; 746 747 qtd = TAILQ_FIRST(&qh->qtd_list); 748 urb = qtd->urb; 749 qh->channel = chan; 750 qtd->in_process = 1; 751 752 /* 753 * Use usb_pipedevice to determine device address. This address is 754 * 0 before the SET_ADDRESS command and the correct address afterward. 755 */ 756 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 757 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 758 chan->speed = qh->dev_speed; 759 chan->max_packet = dwc2_max_packet(qh->maxp); 760 761 chan->xfer_started = 0; 762 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 763 chan->error_state = (qtd->error_count > 0); 764 chan->halt_on_queue = 0; 765 chan->halt_pending = 0; 766 chan->requests = 0; 767 768 /* 769 * The following values may be modified in the transfer type section 770 * below. The xfer_len value may be reduced when the transfer is 771 * started to accommodate the max widths of the XferSize and PktCnt 772 * fields in the HCTSIZn register. 773 */ 774 775 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 776 if (chan->ep_is_in) 777 chan->do_ping = 0; 778 else 779 chan->do_ping = qh->ping_state; 780 781 chan->data_pid_start = qh->data_toggle; 782 chan->multi_count = 1; 783 784 if (urb->actual_length > urb->length && 785 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 786 urb->actual_length = urb->length; 787 788 chan->xfer_len = urb->length - urb->actual_length; 789 chan->xfer_count = 0; 790 791 /* Set the split attributes if required */ 792 if (qh->do_split) 793 dwc2_hc_init_split(hsotg, chan, qtd, urb); 794 else 795 chan->do_split = 0; 796 797 /* Set the transfer attributes */ 798 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, urb); 799 800 /* Non DWORD-aligned buffer case */ 801 if (bufptr) { 802 dev_vdbg(hsotg->dev, "Non-aligned buffer%p\n", bufptr); 803 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, bufptr)) { 804 dev_err(hsotg->dev, 805 "%s: Failed to allocate memory to handle non-dword aligned buffer\n", 806 __func__); 807 /* Add channel back to free list */ 808 chan->align_buf = 0; 809 chan->multi_count = 0; 810 LIST_INSERT_HEAD(&hsotg->free_hc_list, chan, hc_list_entry); 811 chan->in_freelist = 1; 812 qtd->in_process = 0; 813 qh->channel = NULL; 814 return -ENOMEM; 815 } 816 } else { 817 chan->align_buf = 0; 818 } 819 820 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 821 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 822 /* 823 * This value may be modified when the transfer is started 824 * to reflect the actual transfer length 825 */ 826 chan->multi_count = dwc2_hb_mult(qh->maxp); 827 828 if (hsotg->core_params->dma_desc_enable > 0) 829 chan->desc_list_addr = qh->desc_list_dma; 830 831 dwc2_hc_init(hsotg, chan); 832 chan->qh = qh; 833 834 return 0; 835 } 836 837 /** 838 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 839 * schedule and assigns them to available host channels. Called from the HCD 840 * interrupt handler functions. 841 * 842 * @hsotg: The HCD state structure 843 * 844 * Return: The types of new transactions that were assigned to host channels 845 */ 846 enum dwc2_transaction_type dwc2_hcd_select_transactions( 847 struct dwc2_hsotg *hsotg) 848 { 849 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 850 struct dwc2_qh *qh, *qhn; 851 int num_channels; 852 853 #ifdef DWC2_DEBUG 854 dev_vdbg(hsotg->dev, " Select Transactions\n"); 855 #endif 856 857 /* Process entries in the periodic ready list */ 858 /* TAILQ_FOREACH_SAFE? */ 859 qh = TAILQ_FIRST(&hsotg->periodic_sched_ready); 860 while (qh != NULL) { 861 if (LIST_EMPTY(&hsotg->free_hc_list)) 862 break; 863 if (hsotg->core_params->uframe_sched > 0) { 864 if (hsotg->available_host_channels <= 1) 865 break; 866 hsotg->available_host_channels--; 867 } 868 if (dwc2_assign_and_init_hc(hsotg, qh)) 869 break; 870 871 /* 872 * Move the QH from the periodic ready schedule to the 873 * periodic assigned schedule 874 */ 875 qhn = TAILQ_NEXT(qh, qh_list_entry); 876 TAILQ_REMOVE(&hsotg->periodic_sched_ready, qh, qh_list_entry); 877 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_assigned, qh, qh_list_entry); 878 ret_val = DWC2_TRANSACTION_PERIODIC; 879 qh = qhn; 880 } 881 882 /* 883 * Process entries in the inactive portion of the non-periodic 884 * schedule. Some free host channels may not be used if they are 885 * reserved for periodic transfers. 886 */ 887 num_channels = hsotg->core_params->host_channels; 888 qh = TAILQ_FIRST(&hsotg->non_periodic_sched_inactive); 889 while (qh != NULL) { 890 if (hsotg->core_params->uframe_sched <= 0 && 891 hsotg->non_periodic_channels >= num_channels - 892 hsotg->periodic_channels) 893 break; 894 if (LIST_EMPTY(&hsotg->free_hc_list)) 895 break; 896 897 /* 898 * Check to see if this is a NAK'd retransmit, in which case 899 * ignore for retransmission. We hold off on bulk/control 900 * retransmissions to reduce NAK interrupt overhead for 901 * cheeky devices that just hold off using NAKs. 902 */ 903 if (qh->nak_frame != 0xffff && 904 dwc2_full_frame_num(qh->nak_frame) == 905 dwc2_full_frame_num(dwc2_hcd_get_frame_number(hsotg))) { 906 qh = TAILQ_NEXT(qh, qh_list_entry); 907 continue; 908 } else { 909 qh->nak_frame = 0xffff; 910 } 911 912 if (hsotg->core_params->uframe_sched > 0) { 913 if (hsotg->available_host_channels < 1) 914 break; 915 hsotg->available_host_channels--; 916 } 917 918 if (dwc2_assign_and_init_hc(hsotg, qh)) 919 break; 920 921 /* 922 * Move the QH from the non-periodic inactive schedule to the 923 * non-periodic active schedule 924 */ 925 qhn = TAILQ_NEXT(qh, qh_list_entry); 926 TAILQ_REMOVE(&hsotg->non_periodic_sched_inactive, qh, qh_list_entry); 927 TAILQ_INSERT_TAIL(&hsotg->non_periodic_sched_active, qh, qh_list_entry); 928 qh = qhn; 929 930 if (ret_val == DWC2_TRANSACTION_NONE) 931 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 932 else 933 ret_val = DWC2_TRANSACTION_ALL; 934 935 if (hsotg->core_params->uframe_sched <= 0) 936 hsotg->non_periodic_channels++; 937 } 938 939 return ret_val; 940 } 941 942 /** 943 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 944 * a host channel associated with either a periodic or non-periodic transfer 945 * 946 * @hsotg: The HCD state structure 947 * @chan: Host channel descriptor associated with either a periodic or 948 * non-periodic transfer 949 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 950 * for periodic transfers or the non-periodic Tx FIFO 951 * for non-periodic transfers 952 * 953 * Return: 1 if a request is queued and more requests may be needed to 954 * complete the transfer, 0 if no more requests are required for this 955 * transfer, -1 if there is insufficient space in the Tx FIFO 956 * 957 * This function assumes that there is space available in the appropriate 958 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 959 * it checks whether space is available in the appropriate Tx FIFO. 960 * 961 * Must be called with interrupt disabled and spinlock held 962 */ 963 STATIC int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 964 struct dwc2_host_chan *chan, 965 u16 fifo_dwords_avail) 966 { 967 int retval = 0; 968 969 if (hsotg->core_params->dma_enable > 0) { 970 if (hsotg->core_params->dma_desc_enable > 0) { 971 if (!chan->xfer_started || 972 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 973 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 974 chan->qh->ping_state = 0; 975 } 976 } else if (!chan->xfer_started) { 977 dwc2_hc_start_transfer(hsotg, chan); 978 chan->qh->ping_state = 0; 979 } 980 } else if (chan->halt_pending) { 981 /* Don't queue a request if the channel has been halted */ 982 } else if (chan->halt_on_queue) { 983 dwc2_hc_halt(hsotg, chan, chan->halt_status); 984 } else if (chan->do_ping) { 985 if (!chan->xfer_started) 986 dwc2_hc_start_transfer(hsotg, chan); 987 } else if (!chan->ep_is_in || 988 chan->data_pid_start == DWC2_HC_PID_SETUP) { 989 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 990 if (!chan->xfer_started) { 991 dwc2_hc_start_transfer(hsotg, chan); 992 retval = 1; 993 } else { 994 retval = dwc2_hc_continue_transfer(hsotg, chan); 995 } 996 } else { 997 retval = -1; 998 } 999 } else { 1000 if (!chan->xfer_started) { 1001 dwc2_hc_start_transfer(hsotg, chan); 1002 retval = 1; 1003 } else { 1004 retval = dwc2_hc_continue_transfer(hsotg, chan); 1005 } 1006 } 1007 1008 return retval; 1009 } 1010 1011 /* 1012 * Processes periodic channels for the next frame and queues transactions for 1013 * these channels to the DWC_otg controller. After queueing transactions, the 1014 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 1015 * to queue as Periodic Tx FIFO or request queue space becomes available. 1016 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 1017 * 1018 * Must be called with interrupt disabled and spinlock held 1019 */ 1020 STATIC void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1021 { 1022 struct dwc2_qh *qh, *qhn; 1023 u32 tx_status; 1024 u32 fspcavail; 1025 u32 gintmsk; 1026 int status; 1027 int no_queue_space = 0; 1028 int no_fifo_space = 0; 1029 u32 qspcavail; 1030 1031 if (dbg_perio()) 1032 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1033 1034 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1035 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1036 TXSTS_QSPCAVAIL_SHIFT; 1037 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1038 TXSTS_FSPCAVAIL_SHIFT; 1039 1040 if (dbg_perio()) { 1041 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1042 qspcavail); 1043 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1044 fspcavail); 1045 } 1046 1047 qh = TAILQ_FIRST(&hsotg->periodic_sched_assigned); 1048 while (qh != NULL) { 1049 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1050 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1051 TXSTS_QSPCAVAIL_SHIFT; 1052 if (qspcavail == 0) { 1053 no_queue_space = 1; 1054 break; 1055 } 1056 1057 if (!qh->channel) { 1058 qh = TAILQ_NEXT(qh, qh_list_entry); 1059 continue; 1060 } 1061 1062 /* Make sure EP's TT buffer is clean before queueing qtds */ 1063 if (qh->tt_buffer_dirty) { 1064 qh = TAILQ_NEXT(qh, qh_list_entry); 1065 continue; 1066 } 1067 1068 /* 1069 * Set a flag if we're queuing high-bandwidth in slave mode. 1070 * The flag prevents any halts to get into the request queue in 1071 * the middle of multiple high-bandwidth packets getting queued. 1072 */ 1073 if (hsotg->core_params->dma_enable <= 0 && 1074 qh->channel->multi_count > 1) 1075 hsotg->queuing_high_bandwidth = 1; 1076 1077 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1078 TXSTS_FSPCAVAIL_SHIFT; 1079 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1080 if (status < 0) { 1081 no_fifo_space = 1; 1082 break; 1083 } 1084 1085 /* 1086 * In Slave mode, stay on the current transfer until there is 1087 * nothing more to do or the high-bandwidth request count is 1088 * reached. In DMA mode, only need to queue one request. The 1089 * controller automatically handles multiple packets for 1090 * high-bandwidth transfers. 1091 */ 1092 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1093 qh->channel->requests == qh->channel->multi_count) { 1094 qhn = TAILQ_NEXT(qh, qh_list_entry); 1095 /* 1096 * Move the QH from the periodic assigned schedule to 1097 * the periodic queued schedule 1098 */ 1099 TAILQ_REMOVE(&hsotg->periodic_sched_assigned, qh, qh_list_entry); 1100 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_queued, qh, qh_list_entry); 1101 1102 /* done queuing high bandwidth */ 1103 hsotg->queuing_high_bandwidth = 0; 1104 1105 qh = qhn; 1106 } 1107 } 1108 1109 if (hsotg->core_params->dma_enable <= 0) { 1110 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1111 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1112 TXSTS_QSPCAVAIL_SHIFT; 1113 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1114 TXSTS_FSPCAVAIL_SHIFT; 1115 if (dbg_perio()) { 1116 dev_vdbg(hsotg->dev, 1117 " P Tx Req Queue Space Avail (after queue): %d\n", 1118 qspcavail); 1119 dev_vdbg(hsotg->dev, 1120 " P Tx FIFO Space Avail (after queue): %d\n", 1121 fspcavail); 1122 } 1123 1124 if (!TAILQ_EMPTY(&hsotg->periodic_sched_assigned) || 1125 no_queue_space || no_fifo_space) { 1126 /* 1127 * May need to queue more transactions as the request 1128 * queue or Tx FIFO empties. Enable the periodic Tx 1129 * FIFO empty interrupt. (Always use the half-empty 1130 * level to ensure that new requests are loaded as 1131 * soon as possible.) 1132 */ 1133 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1134 gintmsk |= GINTSTS_PTXFEMP; 1135 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1136 } else { 1137 /* 1138 * Disable the Tx FIFO empty interrupt since there are 1139 * no more transactions that need to be queued right 1140 * now. This function is called from interrupt 1141 * handlers to queue more transactions as transfer 1142 * states change. 1143 */ 1144 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1145 gintmsk &= ~GINTSTS_PTXFEMP; 1146 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1147 } 1148 } 1149 } 1150 1151 /* 1152 * Processes active non-periodic channels and queues transactions for these 1153 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1154 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1155 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1156 * FIFO Empty interrupt is disabled. 1157 * 1158 * Must be called with interrupt disabled and spinlock held 1159 */ 1160 STATIC void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1161 { 1162 struct dwc2_qh *qh; 1163 u32 tx_status; 1164 u32 qspcavail; 1165 u32 fspcavail; 1166 u32 gintmsk; 1167 int status; 1168 int no_queue_space = 0; 1169 int no_fifo_space = 0; 1170 int more_to_do = 0; 1171 1172 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1173 1174 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1175 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1176 TXSTS_QSPCAVAIL_SHIFT; 1177 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1178 TXSTS_FSPCAVAIL_SHIFT; 1179 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1180 qspcavail); 1181 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1182 fspcavail); 1183 1184 /* 1185 * Keep track of the starting point. Skip over the start-of-list 1186 * entry. 1187 */ 1188 if (hsotg->non_periodic_qh_ptr == NULL) { 1189 hsotg->non_periodic_qh_ptr = TAILQ_FIRST(&hsotg->non_periodic_sched_active); 1190 } 1191 qh = hsotg->non_periodic_qh_ptr; 1192 1193 /* 1194 * Process once through the active list or until no more space is 1195 * available in the request queue or the Tx FIFO 1196 */ 1197 do { 1198 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1199 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1200 TXSTS_QSPCAVAIL_SHIFT; 1201 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1202 no_queue_space = 1; 1203 break; 1204 } 1205 1206 if (!qh->channel) 1207 goto next; 1208 1209 /* Make sure EP's TT buffer is clean before queueing qtds */ 1210 if (qh->tt_buffer_dirty) 1211 goto next; 1212 1213 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1214 TXSTS_FSPCAVAIL_SHIFT; 1215 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1216 1217 if (status > 0) { 1218 more_to_do = 1; 1219 } else if (status < 0) { 1220 no_fifo_space = 1; 1221 break; 1222 } 1223 next: 1224 /* Advance to next QH, wrapping to the start if we hit the end */ 1225 qh = TAILQ_NEXT(qh, qh_list_entry); 1226 if (qh == NULL) 1227 qh = TAILQ_FIRST(&hsotg->non_periodic_sched_active); 1228 } while ((qh != hsotg->non_periodic_qh_ptr) && (hsotg->non_periodic_qh_ptr != NULL)); 1229 hsotg->non_periodic_qh_ptr = qh; 1230 1231 if (hsotg->core_params->dma_enable <= 0) { 1232 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1233 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1234 TXSTS_QSPCAVAIL_SHIFT; 1235 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1236 TXSTS_FSPCAVAIL_SHIFT; 1237 dev_vdbg(hsotg->dev, 1238 " NP Tx Req Queue Space Avail (after queue): %d\n", 1239 qspcavail); 1240 dev_vdbg(hsotg->dev, 1241 " NP Tx FIFO Space Avail (after queue): %d\n", 1242 fspcavail); 1243 1244 if (more_to_do || no_queue_space || no_fifo_space) { 1245 /* 1246 * May need to queue more transactions as the request 1247 * queue or Tx FIFO empties. Enable the non-periodic 1248 * Tx FIFO empty interrupt. (Always use the half-empty 1249 * level to ensure that new requests are loaded as 1250 * soon as possible.) 1251 */ 1252 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1253 gintmsk |= GINTSTS_NPTXFEMP; 1254 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1255 } else { 1256 /* 1257 * Disable the Tx FIFO empty interrupt since there are 1258 * no more transactions that need to be queued right 1259 * now. This function is called from interrupt 1260 * handlers to queue more transactions as transfer 1261 * states change. 1262 */ 1263 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1264 gintmsk &= ~GINTSTS_NPTXFEMP; 1265 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1266 } 1267 } 1268 } 1269 1270 /** 1271 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1272 * and queues transactions for these channels to the DWC_otg controller. Called 1273 * from the HCD interrupt handler functions. 1274 * 1275 * @hsotg: The HCD state structure 1276 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1277 * or both) 1278 * 1279 * Must be called with interrupt disabled and spinlock held 1280 */ 1281 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1282 enum dwc2_transaction_type tr_type) 1283 { 1284 #ifdef DWC2_DEBUG 1285 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1286 #endif 1287 /* Process host channels associated with periodic transfers */ 1288 if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1289 tr_type == DWC2_TRANSACTION_ALL) && 1290 !TAILQ_EMPTY(&hsotg->periodic_sched_assigned)) 1291 dwc2_process_periodic_channels(hsotg); 1292 1293 /* Process host channels associated with non-periodic transfers */ 1294 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1295 tr_type == DWC2_TRANSACTION_ALL) { 1296 if (!TAILQ_EMPTY(&hsotg->non_periodic_sched_active)) { 1297 dwc2_process_non_periodic_channels(hsotg); 1298 } else { 1299 /* 1300 * Ensure NP Tx FIFO empty interrupt is disabled when 1301 * there are no non-periodic transfers to process 1302 */ 1303 u32 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1304 1305 gintmsk &= ~GINTSTS_NPTXFEMP; 1306 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1307 } 1308 } 1309 } 1310 1311 1312 void 1313 dwc2_conn_id_status_change(void *data) 1314 { 1315 struct dwc2_hsotg *hsotg = data; 1316 u32 count = 0; 1317 u32 gotgctl; 1318 1319 dev_dbg(hsotg->dev, "%s()\n", __func__); 1320 1321 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 1322 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1323 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1324 !!(gotgctl & GOTGCTL_CONID_B)); 1325 1326 /* B-Device connector (Device Mode) */ 1327 if (gotgctl & GOTGCTL_CONID_B) { 1328 /* Wait for switch to device mode */ 1329 dev_dbg(hsotg->dev, "connId B\n"); 1330 while (!dwc2_is_device_mode(hsotg)) { 1331 dev_info(hsotg->dev, 1332 "Waiting for Peripheral Mode, Mode=%s\n", 1333 dwc2_is_host_mode(hsotg) ? "Host" : 1334 "Peripheral"); 1335 usleep_range(20000, 40000); 1336 if (++count > 250) 1337 break; 1338 } 1339 if (count > 250) 1340 dev_err(hsotg->dev, 1341 "Connection id status change timed out\n"); 1342 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1343 dwc2_core_init(hsotg, false); 1344 dwc2_enable_global_interrupts(hsotg); 1345 } else { 1346 /* A-Device connector (Host Mode) */ 1347 dev_dbg(hsotg->dev, "connId A\n"); 1348 while (!dwc2_is_host_mode(hsotg)) { 1349 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1350 dwc2_is_host_mode(hsotg) ? 1351 "Host" : "Peripheral"); 1352 usleep_range(20000, 40000); 1353 if (++count > 250) 1354 break; 1355 } 1356 if (count > 250) 1357 dev_err(hsotg->dev, 1358 "Connection id status change timed out\n"); 1359 hsotg->op_state = OTG_STATE_A_HOST; 1360 1361 /* Initialize the Core for Host mode */ 1362 dwc2_core_init(hsotg, false); 1363 dwc2_enable_global_interrupts(hsotg); 1364 dwc2_hcd_start(hsotg); 1365 } 1366 } 1367 1368 void dwc2_wakeup_detected(void * data) 1369 { 1370 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1371 u32 hprt0; 1372 1373 dev_dbg(hsotg->dev, "%s()\n", __func__); 1374 1375 /* 1376 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1377 * so that OPT tests pass with all PHYs.) 1378 */ 1379 hprt0 = dwc2_read_hprt0(hsotg); 1380 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1381 hprt0 &= ~HPRT0_RES; 1382 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1383 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1384 DWC2_READ_4(hsotg, HPRT0)); 1385 1386 dwc2_hcd_rem_wakeup(hsotg); 1387 1388 /* Change to L0 state */ 1389 hsotg->lx_state = DWC2_L0; 1390 } 1391 1392 /* Must NOT be called with interrupt disabled or spinlock held */ 1393 STATIC void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1394 { 1395 unsigned long flags; 1396 u32 hprt0; 1397 u32 pcgctl; 1398 u32 gotgctl; 1399 1400 dev_dbg(hsotg->dev, "%s()\n", __func__); 1401 1402 spin_lock_irqsave(&hsotg->lock, flags); 1403 1404 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1405 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 1406 gotgctl |= GOTGCTL_HSTSETHNPEN; 1407 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 1408 hsotg->op_state = OTG_STATE_A_SUSPEND; 1409 } 1410 1411 hprt0 = dwc2_read_hprt0(hsotg); 1412 hprt0 |= HPRT0_SUSP; 1413 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1414 1415 /* Update lx_state */ 1416 hsotg->lx_state = DWC2_L2; 1417 1418 /* Suspend the Phy Clock */ 1419 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1420 pcgctl |= PCGCTL_STOPPCLK; 1421 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1422 udelay(10); 1423 1424 /* For HNP the bus must be suspended for at least 200ms */ 1425 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1426 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1427 pcgctl &= ~PCGCTL_STOPPCLK; 1428 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1429 1430 spin_unlock_irqrestore(&hsotg->lock, flags); 1431 1432 usleep_range(200000, 250000); 1433 } else { 1434 spin_unlock_irqrestore(&hsotg->lock, flags); 1435 } 1436 } 1437 1438 /* Handles hub class-specific requests */ 1439 int 1440 dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1441 u16 wvalue, u16 windex, char *buf, u16 wlength) 1442 { 1443 usb_hub_descriptor_t *hub_desc; 1444 usb_port_status_t ps; 1445 int retval = 0; 1446 u32 hprt0; 1447 u32 port_status; 1448 u32 speed; 1449 u32 pcgctl; 1450 1451 switch (typereq) { 1452 case ClearHubFeature: 1453 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1454 1455 switch (wvalue) { 1456 case C_HUB_LOCAL_POWER: 1457 case C_HUB_OVER_CURRENT: 1458 /* Nothing required here */ 1459 break; 1460 1461 default: 1462 retval = -EINVAL; 1463 dev_err(hsotg->dev, 1464 "ClearHubFeature request %1xh unknown\n", 1465 wvalue); 1466 } 1467 break; 1468 1469 case ClearPortFeature: 1470 // if (wvalue != USB_PORT_FEAT_L1) 1471 if (!windex || windex > 1) 1472 goto error; 1473 switch (wvalue) { 1474 case USB_PORT_FEAT_ENABLE: 1475 dev_dbg(hsotg->dev, 1476 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1477 hprt0 = dwc2_read_hprt0(hsotg); 1478 hprt0 |= HPRT0_ENA; 1479 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1480 break; 1481 1482 case USB_PORT_FEAT_SUSPEND: 1483 dev_dbg(hsotg->dev, 1484 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1485 DWC2_WRITE_4(hsotg, PCGCTL, 0); 1486 usleep_range(20000, 40000); 1487 1488 hprt0 = dwc2_read_hprt0(hsotg); 1489 hprt0 |= HPRT0_RES; 1490 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1491 hprt0 &= ~HPRT0_SUSP; 1492 usleep_range(100000, 150000); 1493 1494 hprt0 &= ~HPRT0_RES; 1495 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1496 break; 1497 1498 case USB_PORT_FEAT_POWER: 1499 dev_dbg(hsotg->dev, 1500 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1501 hprt0 = dwc2_read_hprt0(hsotg); 1502 hprt0 &= ~HPRT0_PWR; 1503 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1504 break; 1505 1506 case USB_PORT_FEAT_INDICATOR: 1507 dev_dbg(hsotg->dev, 1508 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1509 /* Port indicator not supported */ 1510 break; 1511 1512 case USB_PORT_FEAT_C_CONNECTION: 1513 /* 1514 * Clears driver's internal Connect Status Change flag 1515 */ 1516 dev_dbg(hsotg->dev, 1517 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1518 hsotg->flags.b.port_connect_status_change = 0; 1519 break; 1520 1521 case USB_PORT_FEAT_C_RESET: 1522 /* Clears driver's internal Port Reset Change flag */ 1523 dev_dbg(hsotg->dev, 1524 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1525 hsotg->flags.b.port_reset_change = 0; 1526 break; 1527 1528 case USB_PORT_FEAT_C_ENABLE: 1529 /* 1530 * Clears the driver's internal Port Enable/Disable 1531 * Change flag 1532 */ 1533 dev_dbg(hsotg->dev, 1534 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1535 hsotg->flags.b.port_enable_change = 0; 1536 break; 1537 1538 case USB_PORT_FEAT_C_SUSPEND: 1539 /* 1540 * Clears the driver's internal Port Suspend Change 1541 * flag, which is set when resume signaling on the host 1542 * port is complete 1543 */ 1544 dev_dbg(hsotg->dev, 1545 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1546 hsotg->flags.b.port_suspend_change = 0; 1547 break; 1548 1549 case USB_PORT_FEAT_C_PORT_L1: 1550 dev_dbg(hsotg->dev, 1551 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1552 hsotg->flags.b.port_l1_change = 0; 1553 break; 1554 1555 case USB_PORT_FEAT_C_OVER_CURRENT: 1556 dev_dbg(hsotg->dev, 1557 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1558 hsotg->flags.b.port_over_current_change = 0; 1559 break; 1560 1561 default: 1562 retval = -EINVAL; 1563 dev_err(hsotg->dev, 1564 "ClearPortFeature request %1xh unknown or unsupported\n", 1565 wvalue); 1566 } 1567 break; 1568 1569 case GetHubDescriptor: 1570 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1571 hub_desc = (usb_hub_descriptor_t *)buf; 1572 hub_desc->bDescLength = 9; 1573 hub_desc->bDescriptorType = 0x29; 1574 hub_desc->bNbrPorts = 1; 1575 USETW(hub_desc->wHubCharacteristics, 0x08); 1576 hub_desc->bPwrOn2PwrGood = 1; 1577 hub_desc->bHubContrCurrent = 0; 1578 hub_desc->DeviceRemovable[0] = 0; 1579 hub_desc->DeviceRemovable[1] = 0xff; 1580 break; 1581 1582 case GetHubStatus: 1583 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1584 memset(buf, 0, 4); 1585 break; 1586 1587 case GetPortStatus: 1588 dev_vdbg(hsotg->dev, 1589 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1590 hsotg->flags.d32); 1591 if (!windex || windex > 1) 1592 goto error; 1593 1594 port_status = 0; 1595 if (hsotg->flags.b.port_connect_status_change) 1596 port_status |= USB_PORT_STAT_C_CONNECTION; 1597 if (hsotg->flags.b.port_enable_change) 1598 port_status |= USB_PORT_STAT_C_ENABLE; 1599 if (hsotg->flags.b.port_suspend_change) 1600 port_status |= USB_PORT_STAT_C_SUSPEND; 1601 if (hsotg->flags.b.port_l1_change) 1602 port_status |= USB_PORT_STAT_C_L1; 1603 if (hsotg->flags.b.port_reset_change) 1604 port_status |= USB_PORT_STAT_C_RESET; 1605 if (hsotg->flags.b.port_over_current_change) { 1606 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1607 port_status |= USB_PORT_STAT_C_OVERCURRENT; 1608 } 1609 USETW(ps.wPortChange, port_status); 1610 1611 dev_vdbg(hsotg->dev, "wPortChange=%04x\n", port_status); 1612 if (!hsotg->flags.b.port_connect_status) { 1613 /* 1614 * The port is disconnected, which means the core is 1615 * either in device mode or it soon will be. Just 1616 * return 0's for the remainder of the port status 1617 * since the port register can't be read if the core 1618 * is in device mode. 1619 */ 1620 USETW(ps.wPortStatus, 0); 1621 memcpy(buf, &ps, sizeof(ps)); 1622 break; 1623 } 1624 1625 port_status = 0; 1626 hprt0 = DWC2_READ_4(hsotg, HPRT0); 1627 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1628 1629 if (hprt0 & HPRT0_CONNSTS) 1630 port_status |= USB_PORT_STAT_CONNECTION; 1631 if (hprt0 & HPRT0_ENA) 1632 port_status |= USB_PORT_STAT_ENABLE; 1633 if (hprt0 & HPRT0_SUSP) 1634 port_status |= USB_PORT_STAT_SUSPEND; 1635 if (hprt0 & HPRT0_OVRCURRACT) 1636 port_status |= USB_PORT_STAT_OVERCURRENT; 1637 if (hprt0 & HPRT0_RST) 1638 port_status |= USB_PORT_STAT_RESET; 1639 if (hprt0 & HPRT0_PWR) 1640 port_status |= USB_PORT_STAT_POWER; 1641 1642 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1643 if (speed == HPRT0_SPD_HIGH_SPEED) 1644 port_status |= USB_PORT_STAT_HIGH_SPEED; 1645 else if (speed == HPRT0_SPD_LOW_SPEED) 1646 port_status |= USB_PORT_STAT_LOW_SPEED; 1647 1648 if (hprt0 & HPRT0_TSTCTL_MASK) 1649 port_status |= USB_PORT_STAT_TEST; 1650 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1651 USETW(ps.wPortStatus, port_status); 1652 1653 dev_vdbg(hsotg->dev, "wPortStatus=%04x\n", port_status); 1654 memcpy(buf, &ps, sizeof(ps)); 1655 break; 1656 1657 case SetHubFeature: 1658 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1659 /* No HUB features supported */ 1660 break; 1661 1662 case SetPortFeature: 1663 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1664 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1665 goto error; 1666 1667 if (!hsotg->flags.b.port_connect_status) { 1668 /* 1669 * The port is disconnected, which means the core is 1670 * either in device mode or it soon will be. Just 1671 * return without doing anything since the port 1672 * register can't be written if the core is in device 1673 * mode. 1674 */ 1675 break; 1676 } 1677 1678 switch (wvalue) { 1679 case USB_PORT_FEAT_SUSPEND: 1680 dev_dbg(hsotg->dev, 1681 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1682 if (windex != hsotg->otg_port) 1683 goto error; 1684 dwc2_port_suspend(hsotg, windex); 1685 break; 1686 1687 case USB_PORT_FEAT_POWER: 1688 dev_dbg(hsotg->dev, 1689 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1690 hprt0 = dwc2_read_hprt0(hsotg); 1691 hprt0 |= HPRT0_PWR; 1692 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1693 break; 1694 1695 case USB_PORT_FEAT_RESET: 1696 hprt0 = dwc2_read_hprt0(hsotg); 1697 dev_dbg(hsotg->dev, 1698 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1699 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1700 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1701 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1702 /* ??? Original driver does this */ 1703 DWC2_WRITE_4(hsotg, PCGCTL, 0); 1704 1705 hprt0 = dwc2_read_hprt0(hsotg); 1706 /* Clear suspend bit if resetting from suspend state */ 1707 hprt0 &= ~HPRT0_SUSP; 1708 1709 /* 1710 * When B-Host the Port reset bit is set in the Start 1711 * HCD Callback function, so that the reset is started 1712 * within 1ms of the HNP success interrupt 1713 */ 1714 if (!dwc2_hcd_is_b_host(hsotg)) { 1715 hprt0 |= HPRT0_PWR | HPRT0_RST; 1716 dev_dbg(hsotg->dev, 1717 "In host mode, hprt0=%08x\n", hprt0); 1718 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1719 } 1720 1721 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1722 usleep_range(50000, 70000); 1723 hprt0 &= ~HPRT0_RST; 1724 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1725 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1726 break; 1727 1728 case USB_PORT_FEAT_INDICATOR: 1729 dev_dbg(hsotg->dev, 1730 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1731 /* Not supported */ 1732 break; 1733 1734 default: 1735 retval = -EINVAL; 1736 dev_err(hsotg->dev, 1737 "SetPortFeature %1xh unknown or unsupported\n", 1738 wvalue); 1739 break; 1740 } 1741 break; 1742 1743 default: 1744 error: 1745 retval = -EINVAL; 1746 dev_dbg(hsotg->dev, 1747 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1748 typereq, windex, wvalue); 1749 break; 1750 } 1751 1752 return retval; 1753 } 1754 1755 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1756 { 1757 u32 hfnum = DWC2_READ_4(hsotg, HFNUM); 1758 1759 #ifdef DWC2_DEBUG 1760 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1761 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1762 #endif 1763 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1764 } 1765 1766 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1767 { 1768 return hsotg->op_state == OTG_STATE_B_HOST; 1769 } 1770 1771 struct dwc2_hcd_urb * 1772 dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, int iso_desc_count, 1773 gfp_t mem_flags) 1774 { 1775 struct dwc2_hcd_urb *urb; 1776 u32 size = sizeof(*urb) + iso_desc_count * 1777 sizeof(struct dwc2_hcd_iso_packet_desc); 1778 1779 urb = malloc(size, M_DEVBUF, M_ZERO | mem_flags); 1780 if (urb) 1781 urb->packet_count = iso_desc_count; 1782 return urb; 1783 } 1784 1785 void 1786 dwc2_hcd_urb_free(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 1787 int iso_desc_count) 1788 { 1789 1790 u32 size = sizeof(*urb) + iso_desc_count * 1791 sizeof(struct dwc2_hcd_iso_packet_desc); 1792 1793 free(urb, M_DEVBUF, size); 1794 } 1795 1796 void 1797 dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 1798 u8 dev_addr, u8 ep_num, u8 ep_type, u8 ep_dir, 1799 u16 mps) 1800 { 1801 if (dbg_perio() || 1802 ep_type == USB_ENDPOINT_XFER_BULK || 1803 ep_type == USB_ENDPOINT_XFER_CONTROL) 1804 dev_dbg(hsotg->dev, "urb=%p, xfer=%p\n", urb, urb->priv); 1805 urb->pipe_info.dev_addr = dev_addr; 1806 urb->pipe_info.ep_num = ep_num; 1807 urb->pipe_info.pipe_type = ep_type; 1808 urb->pipe_info.pipe_dir = ep_dir; 1809 urb->pipe_info.mps = mps; 1810 } 1811 1812 /* 1813 * NOTE: This function will be removed once the peripheral controller code 1814 * is integrated and the driver is stable 1815 */ 1816 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1817 { 1818 #ifdef DWC2_DEBUG 1819 struct dwc2_host_chan *chan; 1820 struct dwc2_hcd_urb *urb; 1821 struct dwc2_qtd *qtd; 1822 int num_channels; 1823 u32 np_tx_status; 1824 u32 p_tx_status; 1825 int i; 1826 1827 num_channels = hsotg->core_params->host_channels; 1828 dev_dbg(hsotg->dev, "\n"); 1829 dev_dbg(hsotg->dev, 1830 "************************************************************\n"); 1831 dev_dbg(hsotg->dev, "HCD State:\n"); 1832 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 1833 1834 for (i = 0; i < num_channels; i++) { 1835 chan = hsotg->hc_ptr_array[i]; 1836 dev_dbg(hsotg->dev, " Channel %d:\n", i); 1837 dev_dbg(hsotg->dev, 1838 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 1839 chan->dev_addr, chan->ep_num, chan->ep_is_in); 1840 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 1841 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 1842 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 1843 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 1844 chan->data_pid_start); 1845 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 1846 dev_dbg(hsotg->dev, " xfer_started: %d\n", 1847 chan->xfer_started); 1848 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 1849 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 1850 (unsigned long)chan->xfer_dma); 1851 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 1852 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 1853 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 1854 chan->halt_on_queue); 1855 dev_dbg(hsotg->dev, " halt_pending: %d\n", 1856 chan->halt_pending); 1857 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 1858 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 1859 dev_dbg(hsotg->dev, " complete_split: %d\n", 1860 chan->complete_split); 1861 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 1862 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 1863 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 1864 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 1865 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 1866 1867 if (chan->xfer_started) { 1868 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", 1869 DWC2_READ_4(hsotg, HFNUM)); 1870 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", 1871 DWC2_READ_4(hsotg, HCCHAR(i))); 1872 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", 1873 DWC2_READ_4(hsotg, HCTSIZ(i))); 1874 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", 1875 DWC2_READ_4(hsotg, HCINT(i))); 1876 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", 1877 DWC2_READ_4(hsotg, HCINTMSK(i))); 1878 } 1879 1880 if (!(chan->xfer_started && chan->qh)) 1881 continue; 1882 1883 TAILQ_FOREACH(qtd, &chan->qh->qtd_list, qtd_list_entry) { 1884 if (!qtd->in_process) 1885 break; 1886 urb = qtd->urb; 1887 dev_dbg(hsotg->dev, " URB Info:\n"); 1888 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 1889 qtd, urb); 1890 if (urb) { 1891 dev_dbg(hsotg->dev, 1892 " Dev: %d, EP: %d %s\n", 1893 dwc2_hcd_get_dev_addr(&urb->pipe_info), 1894 dwc2_hcd_get_ep_num(&urb->pipe_info), 1895 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1896 "IN" : "OUT"); 1897 dev_dbg(hsotg->dev, 1898 " Max packet size: %d\n", 1899 dwc2_hcd_get_mps(&urb->pipe_info)); 1900 dev_dbg(hsotg->dev, 1901 " transfer_buffer: %p\n", 1902 urb->buf); 1903 dev_dbg(hsotg->dev, 1904 " transfer_dma: %08lx\n", 1905 (unsigned long)urb->dma); 1906 dev_dbg(hsotg->dev, 1907 " transfer_buffer_length: %d\n", 1908 urb->length); 1909 dev_dbg(hsotg->dev, " actual_length: %d\n", 1910 urb->actual_length); 1911 } 1912 } 1913 } 1914 1915 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 1916 hsotg->non_periodic_channels); 1917 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 1918 hsotg->periodic_channels); 1919 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 1920 np_tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1921 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 1922 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 1923 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 1924 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 1925 p_tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1926 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 1927 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 1928 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 1929 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 1930 dwc2_hcd_dump_frrem(hsotg); 1931 1932 dwc2_dump_global_registers(hsotg); 1933 dwc2_dump_host_registers(hsotg); 1934 dev_dbg(hsotg->dev, 1935 "************************************************************\n"); 1936 dev_dbg(hsotg->dev, "\n"); 1937 #endif 1938 } 1939 1940 /* 1941 * NOTE: This function will be removed once the peripheral controller code 1942 * is integrated and the driver is stable 1943 */ 1944 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 1945 { 1946 #ifdef DWC2_DUMP_FRREM 1947 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 1948 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1949 hsotg->frrem_samples, hsotg->frrem_accum, 1950 hsotg->frrem_samples > 0 ? 1951 hsotg->frrem_accum / hsotg->frrem_samples : 0); 1952 dev_dbg(hsotg->dev, "\n"); 1953 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 1954 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1955 hsotg->hfnum_7_samples, 1956 hsotg->hfnum_7_frrem_accum, 1957 hsotg->hfnum_7_samples > 0 ? 1958 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 1959 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 1960 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1961 hsotg->hfnum_0_samples, 1962 hsotg->hfnum_0_frrem_accum, 1963 hsotg->hfnum_0_samples > 0 ? 1964 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 1965 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 1966 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1967 hsotg->hfnum_other_samples, 1968 hsotg->hfnum_other_frrem_accum, 1969 hsotg->hfnum_other_samples > 0 ? 1970 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 1971 0); 1972 dev_dbg(hsotg->dev, "\n"); 1973 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 1974 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1975 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 1976 hsotg->hfnum_7_samples_a > 0 ? 1977 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 1978 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 1979 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1980 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 1981 hsotg->hfnum_0_samples_a > 0 ? 1982 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 1983 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 1984 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1985 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 1986 hsotg->hfnum_other_samples_a > 0 ? 1987 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 1988 : 0); 1989 dev_dbg(hsotg->dev, "\n"); 1990 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 1991 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1992 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 1993 hsotg->hfnum_7_samples_b > 0 ? 1994 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 1995 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 1996 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1997 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 1998 (hsotg->hfnum_0_samples_b > 0) ? 1999 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 2000 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 2001 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2002 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 2003 (hsotg->hfnum_other_samples_b > 0) ? 2004 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 2005 : 0); 2006 #endif 2007 } 2008 2009 struct wrapper_priv_data { 2010 struct dwc2_hsotg *hsotg; 2011 }; 2012 2013 2014 void dwc2_host_start(struct dwc2_hsotg *hsotg) 2015 { 2016 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2017 2018 // hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2019 _dwc2_hcd_start(hsotg); 2020 } 2021 2022 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2023 { 2024 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2025 2026 // hcd->self.is_b_host = 0; 2027 } 2028 2029 2030 /* 2031 * Work queue function for starting the HCD when A-Cable is connected 2032 */ 2033 void 2034 dwc2_hcd_start_func(void *data) 2035 { 2036 struct dwc2_hsotg *hsotg = data; 2037 2038 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2039 dwc2_host_start(hsotg); 2040 } 2041 2042 /* 2043 * Reset work queue function 2044 */ 2045 void 2046 dwc2_hcd_reset_func(void *data) 2047 { 2048 struct dwc2_hsotg *hsotg = data; 2049 u32 hprt0; 2050 2051 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2052 hprt0 = dwc2_read_hprt0(hsotg); 2053 hprt0 &= ~HPRT0_RST; 2054 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 2055 hsotg->flags.b.port_reset_change = 1; 2056 2057 dwc2_root_intr(hsotg->hsotg_sc); 2058 } 2059 2060 /* 2061 * ========================================================================= 2062 * Linux HC Driver Functions 2063 * ========================================================================= 2064 */ 2065 2066 /* 2067 * Initializes the DWC_otg controller and its root hub and prepares it for host 2068 * mode operation. Activates the root port. Returns 0 on success and a negative 2069 * error code on failure. 2070 */ 2071 2072 2073 /* 2074 * Frees secondary storage associated with the dwc2_hsotg structure contained 2075 * in the struct usb_hcd field 2076 */ 2077 STATIC void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2078 { 2079 u32 ahbcfg; 2080 u32 dctl; 2081 int i; 2082 2083 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2084 2085 /* Free memory for QH/QTD lists */ 2086 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2087 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2088 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2089 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2090 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 2091 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 2092 2093 /* Free memory for the host channels */ 2094 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 2095 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 2096 2097 if (chan != NULL) { 2098 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 2099 i, chan); 2100 hsotg->hc_ptr_array[i] = NULL; 2101 free(chan, M_DEVBUF, sizeof(*chan)); 2102 } 2103 } 2104 2105 if (hsotg->core_params->dma_enable > 0) { 2106 if (hsotg->status_buf) { 2107 usb_freemem(&hsotg->hsotg_sc->sc_bus, 2108 &hsotg->status_buf_usbdma); 2109 hsotg->status_buf = NULL; 2110 } 2111 } else { 2112 free(hsotg->status_buf, M_DEVBUF, DWC2_HCD_STATUS_BUF_SIZE); 2113 hsotg->status_buf = NULL; 2114 } 2115 2116 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 2117 2118 /* Disable all interrupts */ 2119 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2120 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 2121 DWC2_WRITE_4(hsotg, GINTMSK, 0); 2122 2123 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 2124 dctl = DWC2_READ_4(hsotg, DCTL); 2125 dctl |= DCTL_SFTDISCON; 2126 DWC2_WRITE_4(hsotg, DCTL, dctl); 2127 } 2128 2129 if (hsotg->wq_otg) { 2130 taskq_destroy(hsotg->wq_otg); 2131 } 2132 2133 free(hsotg->core_params, M_DEVBUF, sizeof(*hsotg->core_params)); 2134 hsotg->core_params = NULL; 2135 timeout_del(&hsotg->wkp_timer); 2136 } 2137 2138 STATIC void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 2139 { 2140 /* Turn off all host-specific interrupts */ 2141 dwc2_disable_host_interrupts(hsotg); 2142 2143 dwc2_hcd_free(hsotg); 2144 } 2145 2146 /* 2147 * Sets all parameters to the given value. 2148 * 2149 * Assumes that the dwc2_core_params struct contains only integers. 2150 */ 2151 void dwc2_set_all_params(struct dwc2_core_params *params, int value) 2152 { 2153 int *p = (int *)params; 2154 size_t size = sizeof(*params) / sizeof(*p); 2155 int i; 2156 2157 for (i = 0; i < size; i++) 2158 p[i] = value; 2159 } 2160 2161 /* 2162 * Initializes the HCD. This function allocates memory for and initializes the 2163 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 2164 * USB bus with the core and calls the hc_driver->start() function. It returns 2165 * a negative error on failure. 2166 */ 2167 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, 2168 const struct dwc2_core_params *params) 2169 { 2170 struct dwc2_host_chan *channel; 2171 int i, num_channels; 2172 int retval; 2173 2174 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 2175 2176 /* Detect config values from hardware */ 2177 retval = dwc2_get_hwparams(hsotg); 2178 2179 if (retval) 2180 return retval; 2181 2182 retval = -ENOMEM; 2183 2184 dev_dbg(hsotg->dev, "hcfg=%08x\n", DWC2_READ_4(hsotg, HCFG)); 2185 2186 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2187 hsotg->frame_num_array = malloc(sizeof(*hsotg->frame_num_array) * 2188 FRAME_NUM_ARRAY_SIZE, M_DEVBUF, 2189 M_ZERO | M_WAITOK); 2190 if (!hsotg->frame_num_array) 2191 goto error1; 2192 hsotg->last_frame_num_array = malloc( 2193 sizeof(*hsotg->last_frame_num_array) * 2194 FRAME_NUM_ARRAY_SIZE, M_DEVBUF, M_ZERO | M_WAITOK); 2195 if (!hsotg->last_frame_num_array) 2196 goto error1; 2197 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 2198 #endif 2199 2200 hsotg->core_params = malloc(sizeof(*hsotg->core_params), M_DEVBUF, 2201 M_ZERO | M_WAITOK); 2202 if (!hsotg->core_params) 2203 goto error1; 2204 2205 dwc2_set_all_params(hsotg->core_params, -1); 2206 2207 /* Validate parameter values */ 2208 dwc2_set_parameters(hsotg, params); 2209 2210 spin_lock_init(&hsotg->lock); 2211 2212 /* 2213 * Disable the global interrupt until all the interrupt handlers are 2214 * installed 2215 */ 2216 dwc2_disable_global_interrupts(hsotg); 2217 2218 /* Initialize the DWC_otg core, and select the Phy type */ 2219 retval = dwc2_core_init(hsotg, true); 2220 if (retval) 2221 goto error2; 2222 2223 /* Create new workqueue and init work */ 2224 retval = -ENOMEM; 2225 hsotg->wq_otg = taskq_create("dwc2", 1, IPL_USB, 0); 2226 if (hsotg->wq_otg == NULL) { 2227 dev_err(hsotg->dev, "Failed to create workqueue\n"); 2228 goto error2; 2229 } 2230 2231 timeout_set(&hsotg->wkp_timer, dwc2_wakeup_detected, hsotg); 2232 2233 /* Initialize the non-periodic schedule */ 2234 TAILQ_INIT(&hsotg->non_periodic_sched_inactive); 2235 TAILQ_INIT(&hsotg->non_periodic_sched_active); 2236 2237 /* Initialize the periodic schedule */ 2238 TAILQ_INIT(&hsotg->periodic_sched_inactive); 2239 TAILQ_INIT(&hsotg->periodic_sched_ready); 2240 TAILQ_INIT(&hsotg->periodic_sched_assigned); 2241 TAILQ_INIT(&hsotg->periodic_sched_queued); 2242 2243 /* 2244 * Create a host channel descriptor for each host channel implemented 2245 * in the controller. Initialize the channel descriptor array. 2246 */ 2247 LIST_INIT(&hsotg->free_hc_list); 2248 num_channels = hsotg->core_params->host_channels; 2249 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 2250 2251 for (i = 0; i < num_channels; i++) { 2252 channel = malloc(sizeof(*channel), M_DEVBUF, M_ZERO | M_WAITOK); 2253 if (channel == NULL) 2254 goto error3; 2255 channel->hc_num = i; 2256 hsotg->hc_ptr_array[i] = channel; 2257 } 2258 2259 if (hsotg->core_params->uframe_sched > 0) 2260 dwc2_hcd_init_usecs(hsotg); 2261 2262 /* Initialize hsotg start work */ 2263 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func, hsotg); 2264 2265 /* Initialize port reset work */ 2266 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func, hsotg); 2267 2268 /* 2269 * Allocate space for storing data on status transactions. Normally no 2270 * data is sent, but this space acts as a bit bucket. This must be 2271 * done after usb_add_hcd since that function allocates the DMA buffer 2272 * pool. 2273 */ 2274 hsotg->status_buf = NULL; 2275 if (hsotg->core_params->dma_enable > 0) { 2276 retval = usb_allocmem(&hsotg->hsotg_sc->sc_bus, 2277 DWC2_HCD_STATUS_BUF_SIZE, 0, 2278 &hsotg->status_buf_usbdma); 2279 if (!retval) { 2280 hsotg->status_buf = KERNADDR(&hsotg->status_buf_usbdma, 0); 2281 hsotg->status_buf_dma = DMAADDR(&hsotg->status_buf_usbdma, 0); 2282 } 2283 } else 2284 hsotg->status_buf = malloc(DWC2_HCD_STATUS_BUF_SIZE, M_DEVBUF, 2285 M_ZERO | M_WAITOK); 2286 2287 if (!hsotg->status_buf) 2288 goto error3; 2289 2290 hsotg->otg_port = 1; 2291 hsotg->frame_list = NULL; 2292 hsotg->frame_list_dma = 0; 2293 hsotg->periodic_qh_count = 0; 2294 2295 /* Initiate lx_state to L3 disconnected state */ 2296 hsotg->lx_state = DWC2_L3; 2297 2298 _dwc2_hcd_start(hsotg); 2299 2300 dwc2_hcd_dump_state(hsotg); 2301 2302 dwc2_enable_global_interrupts(hsotg); 2303 2304 return 0; 2305 2306 error3: 2307 dwc2_hcd_release(hsotg); 2308 error2: 2309 error1: 2310 free(hsotg->core_params, M_DEVBUF, sizeof(*hsotg->core_params)); 2311 2312 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2313 free(hsotg->last_frame_num_array, M_DEVBUF, 2314 sizeof(*hsotg->last_frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2315 free(hsotg->frame_num_array, M_DEVBUF, 2316 sizeof(*hsotg->frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2317 #endif 2318 2319 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 2320 return retval; 2321 } 2322 2323 int dwc2_hcd_dma_config(struct dwc2_hsotg *hsotg, 2324 struct dwc2_core_dma_config *config) 2325 { 2326 hsotg->core_dma_config = config; 2327 return 0; 2328 } 2329