1 /* $OpenBSD: dwc2_coreintr.c,v 1.10 2017/06/29 17:36:16 deraadt Exp $ */ 2 /* $NetBSD: dwc2_coreintr.c,v 1.8 2014/04/04 05:40:57 skrll Exp $ */ 3 4 /* 5 * core_intr.c - DesignWare HS OTG Controller common interrupt handling 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * This file contains the common interrupt handlers 42 */ 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/mutex.h> 48 #include <sys/pool.h> 49 #include <sys/timeout.h> 50 51 #include <lib/libkern/libkern.h> 52 53 #include <machine/bus.h> 54 55 #include <dev/usb/usb.h> 56 #include <dev/usb/usbdi.h> 57 #include <dev/usb/usbdivar.h> 58 #include <dev/usb/usb_mem.h> 59 60 #include <dev/usb/dwc2/dwc2.h> 61 #include <dev/usb/dwc2/dwc2var.h> 62 63 #include <dev/usb/dwc2/dwc2_core.h> 64 #include <dev/usb/dwc2/dwc2_hcd.h> 65 66 #ifdef DWC2_DEBUG 67 STATIC const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg) 68 { 69 switch (hsotg->op_state) { 70 case OTG_STATE_A_HOST: 71 return "a_host"; 72 case OTG_STATE_A_SUSPEND: 73 return "a_suspend"; 74 case OTG_STATE_A_PERIPHERAL: 75 return "a_peripheral"; 76 case OTG_STATE_B_PERIPHERAL: 77 return "b_peripheral"; 78 case OTG_STATE_B_HOST: 79 return "b_host"; 80 default: 81 return "unknown"; 82 } 83 } 84 #endif 85 86 /** 87 * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts. 88 * When the PRTINT interrupt fires, there are certain status bits in the Host 89 * Port that needs to get cleared. 90 * 91 * @hsotg: Programming view of DWC_otg controller 92 */ 93 STATIC void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) 94 { 95 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 96 97 if (hprt0 & HPRT0_ENACHG) { 98 hprt0 &= ~HPRT0_ENA; 99 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 100 } 101 102 /* Clear interrupt */ 103 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_PRTINT); 104 } 105 106 /** 107 * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message 108 * 109 * @hsotg: Programming view of DWC_otg controller 110 */ 111 STATIC void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg) 112 { 113 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n", 114 dwc2_is_host_mode(hsotg) ? "Host" : "Device"); 115 116 /* Clear interrupt */ 117 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_MODEMIS); 118 } 119 120 /** 121 * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG 122 * Interrupt Register (GOTGINT) to determine what interrupt has occurred. 123 * 124 * @hsotg: Programming view of DWC_otg controller 125 */ 126 STATIC void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) 127 { 128 u32 gotgint; 129 u32 gotgctl; 130 u32 gintmsk; 131 132 gotgint = DWC2_READ_4(hsotg, GOTGINT); 133 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 134 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, 135 dwc2_op_state_str(hsotg)); 136 137 if (gotgint & GOTGINT_SES_END_DET) { 138 dev_dbg(hsotg->dev, 139 " ++OTG Interrupt: Session End Detected++ (%s)\n", 140 dwc2_op_state_str(hsotg)); 141 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 142 143 if (hsotg->op_state == OTG_STATE_B_HOST) { 144 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 145 } else { 146 /* 147 * If not B_HOST and Device HNP still set, HNP did 148 * not succeed! 149 */ 150 if (gotgctl & GOTGCTL_DEVHNPEN) { 151 dev_dbg(hsotg->dev, "Session End Detected\n"); 152 dev_err(hsotg->dev, 153 "Device Not Connected/Responding!\n"); 154 } 155 156 /* 157 * If Session End Detected the B-Cable has been 158 * disconnected 159 */ 160 /* Reset to a clean state */ 161 hsotg->lx_state = DWC2_L0; 162 } 163 164 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 165 gotgctl &= ~GOTGCTL_DEVHNPEN; 166 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 167 } 168 169 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) { 170 dev_dbg(hsotg->dev, 171 " ++OTG Interrupt: Session Request Success Status Change++\n"); 172 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 173 if (gotgctl & GOTGCTL_SESREQSCS) { 174 if (hsotg->core_params->phy_type == 175 DWC2_PHY_TYPE_PARAM_FS 176 && hsotg->core_params->i2c_enable > 0) { 177 hsotg->srp_success = 1; 178 } else { 179 /* Clear Session Request */ 180 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 181 gotgctl &= ~GOTGCTL_SESREQ; 182 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 183 } 184 } 185 } 186 187 if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) { 188 /* 189 * Print statements during the HNP interrupt handling 190 * can cause it to fail 191 */ 192 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 193 /* 194 * WA for 3.00a- HW is not setting cur_mode, even sometimes 195 * this does not help 196 */ 197 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) 198 udelay(100); 199 if (gotgctl & GOTGCTL_HSTNEGSCS) { 200 if (dwc2_is_host_mode(hsotg)) { 201 hsotg->op_state = OTG_STATE_B_HOST; 202 /* 203 * Need to disable SOF interrupt immediately. 204 * When switching from device to host, the PCD 205 * interrupt handler won't handle the interrupt 206 * if host mode is already set. The HCD 207 * interrupt handler won't get called if the 208 * HCD state is HALT. This means that the 209 * interrupt does not get handled and Linux 210 * complains loudly. 211 */ 212 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 213 gintmsk &= ~GINTSTS_SOF; 214 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 215 216 /* 217 * Call callback function with spin lock 218 * released 219 */ 220 spin_unlock(&hsotg->lock); 221 222 /* Initialize the Core for Host mode */ 223 dwc2_hcd_start(hsotg); 224 spin_lock(&hsotg->lock); 225 hsotg->op_state = OTG_STATE_B_HOST; 226 } 227 } else { 228 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 229 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN); 230 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 231 dev_dbg(hsotg->dev, "HNP Failed\n"); 232 dev_err(hsotg->dev, 233 "Device Not Connected/Responding\n"); 234 } 235 } 236 237 if (gotgint & GOTGINT_HST_NEG_DET) { 238 /* 239 * The disconnect interrupt is set at the same time as 240 * Host Negotiation Detected. During the mode switch all 241 * interrupts are cleared so the disconnect interrupt 242 * handler will not get executed. 243 */ 244 dev_dbg(hsotg->dev, 245 " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n", 246 (dwc2_is_host_mode(hsotg) ? "Host" : "Device")); 247 if (dwc2_is_device_mode(hsotg)) { 248 dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n", 249 hsotg->op_state); 250 spin_unlock(&hsotg->lock); 251 dwc2_hcd_disconnect(hsotg); 252 spin_lock(&hsotg->lock); 253 hsotg->op_state = OTG_STATE_A_PERIPHERAL; 254 } else { 255 /* Need to disable SOF interrupt immediately */ 256 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 257 gintmsk &= ~GINTSTS_SOF; 258 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 259 spin_unlock(&hsotg->lock); 260 dwc2_hcd_start(hsotg); 261 spin_lock(&hsotg->lock); 262 hsotg->op_state = OTG_STATE_A_HOST; 263 } 264 } 265 266 if (gotgint & GOTGINT_A_DEV_TOUT_CHG) 267 dev_dbg(hsotg->dev, 268 " ++OTG Interrupt: A-Device Timeout Change++\n"); 269 if (gotgint & GOTGINT_DBNCE_DONE) 270 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n"); 271 272 /* Clear GOTGINT */ 273 DWC2_WRITE_4(hsotg, GOTGINT, gotgint); 274 } 275 276 /** 277 * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status 278 * Change Interrupt 279 * 280 * @hsotg: Programming view of DWC_otg controller 281 * 282 * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a 283 * Device to Host Mode transition or a Host to Device Mode transition. This only 284 * occurs when the cable is connected/removed from the PHY connector. 285 */ 286 STATIC void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) 287 { 288 u32 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 289 290 /* Need to disable SOF interrupt immediately */ 291 gintmsk &= ~GINTSTS_SOF; 292 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 293 294 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", 295 dwc2_is_host_mode(hsotg) ? "Host" : "Device"); 296 297 /* 298 * Need to schedule a work, as there are possible DELAY function calls. 299 * Release lock before scheduling workq as it holds spinlock during 300 * scheduling. 301 */ 302 spin_unlock(&hsotg->lock); 303 task_set(&hsotg->wf_otg, dwc2_conn_id_status_change, hsotg); 304 task_add(hsotg->wq_otg, &hsotg->wf_otg); 305 spin_lock(&hsotg->lock); 306 307 /* Clear interrupt */ 308 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_CONIDSTSCHNG); 309 } 310 311 /** 312 * dwc2_handle_session_req_intr() - This interrupt indicates that a device is 313 * initiating the Session Request Protocol to request the host to turn on bus 314 * power so a new session can begin 315 * 316 * @hsotg: Programming view of DWC_otg controller 317 * 318 * This handler responds by turning on bus power. If the DWC_otg controller is 319 * in low power mode, this handler brings the controller out of low power mode 320 * before turning on bus power. 321 */ 322 STATIC void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) 323 { 324 dev_dbg(hsotg->dev, "++Session Request Interrupt++\n"); 325 326 /* Clear interrupt */ 327 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_SESSREQINT); 328 } 329 330 /* 331 * This interrupt indicates that the DWC_otg controller has detected a 332 * resume or remote wakeup sequence. If the DWC_otg controller is in 333 * low power mode, the handler must brings the controller out of low 334 * power mode. The controller automatically begins resume signaling. 335 * The handler schedules a time to stop resume signaling. 336 */ 337 STATIC void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) 338 { 339 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n"); 340 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state); 341 342 if (dwc2_is_device_mode(hsotg)) { 343 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", DWC2_READ_4(hsotg, DSTS)); 344 if (hsotg->lx_state == DWC2_L2) { 345 u32 dctl = DWC2_READ_4(hsotg, DCTL); 346 347 /* Clear Remote Wakeup Signaling */ 348 dctl &= ~DCTL_RMTWKUPSIG; 349 DWC2_WRITE_4(hsotg, DCTL, dctl); 350 } 351 /* Change to L0 state */ 352 hsotg->lx_state = DWC2_L0; 353 } else { 354 if (hsotg->lx_state != DWC2_L1) { 355 u32 pcgcctl = DWC2_READ_4(hsotg, PCGCTL); 356 357 /* Restart the Phy Clock */ 358 pcgcctl &= ~PCGCTL_STOPPCLK; 359 DWC2_WRITE_4(hsotg, PCGCTL, pcgcctl); 360 timeout_reset(&hsotg->wkp_timer, mstohz(71), 361 dwc2_wakeup_detected, hsotg); 362 } else { 363 /* Change to L0 state */ 364 hsotg->lx_state = DWC2_L0; 365 } 366 } 367 368 /* Clear interrupt */ 369 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_WKUPINT); 370 } 371 372 /* 373 * This interrupt indicates that a device has been disconnected from the 374 * root port 375 */ 376 STATIC void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg) 377 { 378 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n", 379 dwc2_is_host_mode(hsotg) ? "Host" : "Device", 380 dwc2_op_state_str(hsotg)); 381 382 /* Change to L3 (OFF) state */ 383 hsotg->lx_state = DWC2_L3; 384 385 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_DISCONNINT); 386 } 387 388 /* 389 * This interrupt indicates that SUSPEND state has been detected on the USB. 390 * 391 * For HNP the USB Suspend interrupt signals the change from "a_peripheral" 392 * to "a_host". 393 * 394 * When power management is enabled the core will be put in low power mode. 395 */ 396 STATIC void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) 397 { 398 dev_dbg(hsotg->dev, "USB SUSPEND\n"); 399 400 if (dwc2_is_device_mode(hsotg)) { 401 #ifdef DWC2_DEBUG 402 u32 dsts; 403 404 /* 405 * Check the Device status register to determine if the Suspend 406 * state is active 407 */ 408 dsts = DWC2_READ_4(hsotg, DSTS); 409 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts); 410 dev_dbg(hsotg->dev, 411 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n", 412 !!(dsts & DSTS_SUSPSTS), 413 hsotg->hw_params.power_optimized); 414 #endif 415 } else { 416 if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) { 417 dev_dbg(hsotg->dev, "a_peripheral->a_host\n"); 418 419 /* Clear the a_peripheral flag, back to a_host */ 420 spin_unlock(&hsotg->lock); 421 dwc2_hcd_start(hsotg); 422 spin_lock(&hsotg->lock); 423 hsotg->op_state = OTG_STATE_A_HOST; 424 } 425 } 426 427 /* Change to L2 (suspend) state */ 428 hsotg->lx_state = DWC2_L2; 429 430 /* Clear interrupt */ 431 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_USBSUSP); 432 } 433 434 #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \ 435 GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \ 436 GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \ 437 GINTSTS_USBSUSP | GINTSTS_PRTINT) 438 439 /* 440 * This function returns the Core Interrupt register 441 */ 442 STATIC u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg) 443 { 444 u32 gintsts; 445 u32 gintmsk; 446 u32 gahbcfg; 447 u32 gintmsk_common = GINTMSK_COMMON; 448 449 gintsts = DWC2_READ_4(hsotg, GINTSTS); 450 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 451 gahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 452 453 /* If any common interrupts set */ 454 if (gintsts & gintmsk_common) 455 dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n", 456 gintsts, gintmsk); 457 458 if (gahbcfg & GAHBCFG_GLBL_INTR_EN) 459 return gintsts & gintmsk & gintmsk_common; 460 else 461 return 0; 462 } 463 464 /* 465 * Common interrupt handler 466 * 467 * The common interrupts are those that occur in both Host and Device mode. 468 * This handler handles the following interrupts: 469 * - Mode Mismatch Interrupt 470 * - OTG Interrupt 471 * - Connector ID Status Change Interrupt 472 * - Disconnect Interrupt 473 * - Session Request Interrupt 474 * - Resume / Remote Wakeup Detected Interrupt 475 * - Suspend Interrupt 476 */ 477 irqreturn_t dwc2_handle_common_intr(void *dev) 478 { 479 struct dwc2_hsotg *hsotg = dev; 480 u32 gintsts; 481 irqreturn_t retval = IRQ_NONE; 482 483 if (!dwc2_is_controller_alive(hsotg)) { 484 dev_warn(hsotg->dev, "Controller is dead\n"); 485 goto out; 486 } 487 488 MUTEX_ASSERT_LOCKED(&hsotg->lock); 489 490 gintsts = dwc2_read_common_intr(hsotg); 491 if (gintsts & ~GINTSTS_PRTINT) 492 retval = IRQ_HANDLED; 493 494 if (gintsts & GINTSTS_MODEMIS) 495 dwc2_handle_mode_mismatch_intr(hsotg); 496 if (gintsts & GINTSTS_OTGINT) 497 dwc2_handle_otg_intr(hsotg); 498 if (gintsts & GINTSTS_CONIDSTSCHNG) 499 dwc2_handle_conn_id_status_change_intr(hsotg); 500 if (gintsts & GINTSTS_DISCONNINT) 501 dwc2_handle_disconnect_intr(hsotg); 502 if (gintsts & GINTSTS_SESSREQINT) 503 dwc2_handle_session_req_intr(hsotg); 504 if (gintsts & GINTSTS_WKUPINT) 505 dwc2_handle_wakeup_detected_intr(hsotg); 506 if (gintsts & GINTSTS_USBSUSP) 507 dwc2_handle_usb_suspend_intr(hsotg); 508 509 if (gintsts & GINTSTS_PRTINT) { 510 /* 511 * The port interrupt occurs while in device mode with HPRT0 512 * Port Enable/Disable 513 */ 514 if (dwc2_is_device_mode(hsotg)) { 515 dev_dbg(hsotg->dev, 516 " --Port interrupt received in Device mode--\n"); 517 dwc2_handle_usb_port_intr(hsotg); 518 retval = IRQ_HANDLED; 519 } 520 } 521 522 out: 523 return retval; 524 } 525