1 /* $OpenBSD: dwc2_coreintr.c,v 1.11 2021/07/22 18:32:33 mglocker Exp $ */ 2 /* $NetBSD: dwc2_coreintr.c,v 1.8 2014/04/04 05:40:57 skrll Exp $ */ 3 4 /* 5 * core_intr.c - DesignWare HS OTG Controller common interrupt handling 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * This file contains the common interrupt handlers 42 */ 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/mutex.h> 48 #include <sys/pool.h> 49 #include <sys/timeout.h> 50 51 #include <lib/libkern/libkern.h> 52 53 #include <machine/bus.h> 54 55 #include <dev/usb/usb.h> 56 #include <dev/usb/usbdi.h> 57 #include <dev/usb/usbdivar.h> 58 #include <dev/usb/usb_mem.h> 59 60 #include <dev/usb/dwc2/dwc2.h> 61 #include <dev/usb/dwc2/dwc2var.h> 62 63 #include <dev/usb/dwc2/dwc2_core.h> 64 #include <dev/usb/dwc2/dwc2_hcd.h> 65 66 #ifdef DWC2_DEBUG 67 STATIC const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg) 68 { 69 switch (hsotg->op_state) { 70 case OTG_STATE_A_HOST: 71 return "a_host"; 72 case OTG_STATE_A_SUSPEND: 73 return "a_suspend"; 74 case OTG_STATE_A_PERIPHERAL: 75 return "a_peripheral"; 76 case OTG_STATE_B_PERIPHERAL: 77 return "b_peripheral"; 78 case OTG_STATE_B_HOST: 79 return "b_host"; 80 default: 81 return "unknown"; 82 } 83 } 84 #endif 85 86 /** 87 * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts. 88 * When the PRTINT interrupt fires, there are certain status bits in the Host 89 * Port that needs to get cleared. 90 * 91 * @hsotg: Programming view of DWC_otg controller 92 */ 93 STATIC void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) 94 { 95 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 96 97 if (hprt0 & HPRT0_ENACHG) { 98 hprt0 &= ~HPRT0_ENA; 99 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 100 } 101 } 102 103 /** 104 * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message 105 * 106 * @hsotg: Programming view of DWC_otg controller 107 */ 108 STATIC void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg) 109 { 110 /* Clear interrupt */ 111 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_MODEMIS); 112 113 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n", 114 dwc2_is_host_mode(hsotg) ? "Host" : "Device"); 115 } 116 117 /** 118 * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG 119 * Interrupt Register (GOTGINT) to determine what interrupt has occurred. 120 * 121 * @hsotg: Programming view of DWC_otg controller 122 */ 123 STATIC void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) 124 { 125 u32 gotgint; 126 u32 gotgctl; 127 u32 gintmsk; 128 129 gotgint = DWC2_READ_4(hsotg, GOTGINT); 130 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 131 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, 132 dwc2_op_state_str(hsotg)); 133 134 if (gotgint & GOTGINT_SES_END_DET) { 135 dev_dbg(hsotg->dev, 136 " ++OTG Interrupt: Session End Detected++ (%s)\n", 137 dwc2_op_state_str(hsotg)); 138 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 139 140 if (dwc2_is_device_mode(hsotg)) 141 dwc2_hsotg_disconnect(hsotg); 142 143 if (hsotg->op_state == OTG_STATE_B_HOST) { 144 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 145 } else { 146 /* 147 * If not B_HOST and Device HNP still set, HNP did 148 * not succeed! 149 */ 150 if (gotgctl & GOTGCTL_DEVHNPEN) { 151 dev_dbg(hsotg->dev, "Session End Detected\n"); 152 dev_err(hsotg->dev, 153 "Device Not Connected/Responding!\n"); 154 } 155 156 /* 157 * If Session End Detected the B-Cable has been 158 * disconnected 159 */ 160 /* Reset to a clean state */ 161 hsotg->lx_state = DWC2_L0; 162 } 163 164 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 165 gotgctl &= ~GOTGCTL_DEVHNPEN; 166 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 167 } 168 169 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) { 170 dev_dbg(hsotg->dev, 171 " ++OTG Interrupt: Session Request Success Status Change++\n"); 172 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 173 if (gotgctl & GOTGCTL_SESREQSCS) { 174 if (hsotg->core_params->phy_type == 175 DWC2_PHY_TYPE_PARAM_FS 176 && hsotg->core_params->i2c_enable > 0) { 177 hsotg->srp_success = 1; 178 } else { 179 /* Clear Session Request */ 180 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 181 gotgctl &= ~GOTGCTL_SESREQ; 182 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 183 } 184 } 185 } 186 187 if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) { 188 /* 189 * Print statements during the HNP interrupt handling 190 * can cause it to fail 191 */ 192 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 193 /* 194 * WA for 3.00a- HW is not setting cur_mode, even sometimes 195 * this does not help 196 */ 197 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) 198 udelay(100); 199 if (gotgctl & GOTGCTL_HSTNEGSCS) { 200 if (dwc2_is_host_mode(hsotg)) { 201 hsotg->op_state = OTG_STATE_B_HOST; 202 /* 203 * Need to disable SOF interrupt immediately. 204 * When switching from device to host, the PCD 205 * interrupt handler won't handle the interrupt 206 * if host mode is already set. The HCD 207 * interrupt handler won't get called if the 208 * HCD state is HALT. This means that the 209 * interrupt does not get handled and Linux 210 * complains loudly. 211 */ 212 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 213 gintmsk &= ~GINTSTS_SOF; 214 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 215 216 /* 217 * Call callback function with spin lock 218 * released 219 */ 220 spin_unlock(&hsotg->lock); 221 222 /* Initialize the Core for Host mode */ 223 dwc2_hcd_start(hsotg); 224 spin_lock(&hsotg->lock); 225 hsotg->op_state = OTG_STATE_B_HOST; 226 } 227 } else { 228 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 229 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN); 230 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 231 dev_dbg(hsotg->dev, "HNP Failed\n"); 232 dev_err(hsotg->dev, 233 "Device Not Connected/Responding\n"); 234 } 235 } 236 237 if (gotgint & GOTGINT_HST_NEG_DET) { 238 /* 239 * The disconnect interrupt is set at the same time as 240 * Host Negotiation Detected. During the mode switch all 241 * interrupts are cleared so the disconnect interrupt 242 * handler will not get executed. 243 */ 244 dev_dbg(hsotg->dev, 245 " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n", 246 (dwc2_is_host_mode(hsotg) ? "Host" : "Device")); 247 if (dwc2_is_device_mode(hsotg)) { 248 dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n", 249 hsotg->op_state); 250 spin_unlock(&hsotg->lock); 251 dwc2_hcd_disconnect(hsotg, false); 252 spin_lock(&hsotg->lock); 253 hsotg->op_state = OTG_STATE_A_PERIPHERAL; 254 } else { 255 /* Need to disable SOF interrupt immediately */ 256 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 257 gintmsk &= ~GINTSTS_SOF; 258 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 259 spin_unlock(&hsotg->lock); 260 dwc2_hcd_start(hsotg); 261 spin_lock(&hsotg->lock); 262 hsotg->op_state = OTG_STATE_A_HOST; 263 } 264 } 265 266 if (gotgint & GOTGINT_A_DEV_TOUT_CHG) 267 dev_dbg(hsotg->dev, 268 " ++OTG Interrupt: A-Device Timeout Change++\n"); 269 if (gotgint & GOTGINT_DBNCE_DONE) 270 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n"); 271 272 /* Clear GOTGINT */ 273 DWC2_WRITE_4(hsotg, GOTGINT, gotgint); 274 } 275 276 /** 277 * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status 278 * Change Interrupt 279 * 280 * @hsotg: Programming view of DWC_otg controller 281 * 282 * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a 283 * Device to Host Mode transition or a Host to Device Mode transition. This only 284 * occurs when the cable is connected/removed from the PHY connector. 285 */ 286 STATIC void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) 287 { 288 u32 gintmsk; 289 290 /* Clear interrupt */ 291 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_CONIDSTSCHNG); 292 293 /* Need to disable SOF interrupt immediately */ 294 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 295 gintmsk &= ~GINTSTS_SOF; 296 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 297 298 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", 299 dwc2_is_host_mode(hsotg) ? "Host" : "Device"); 300 301 /* 302 * Need to schedule a work, as there are possible DELAY function calls. 303 * Release lock before scheduling workq as it holds spinlock during 304 * scheduling. 305 */ 306 if (hsotg->wq_otg) { 307 spin_unlock(&hsotg->lock); 308 task_add(hsotg->wq_otg, &hsotg->wf_otg); 309 spin_lock(&hsotg->lock); 310 } 311 } 312 313 /** 314 * dwc2_handle_session_req_intr() - This interrupt indicates that a device is 315 * initiating the Session Request Protocol to request the host to turn on bus 316 * power so a new session can begin 317 * 318 * @hsotg: Programming view of DWC_otg controller 319 * 320 * This handler responds by turning on bus power. If the DWC_otg controller is 321 * in low power mode, this handler brings the controller out of low power mode 322 * before turning on bus power. 323 */ 324 STATIC void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) 325 { 326 int ret; 327 328 /* Clear interrupt */ 329 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_SESSREQINT); 330 331 dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n", 332 hsotg->lx_state); 333 334 if (dwc2_is_device_mode(hsotg)) { 335 if (hsotg->lx_state == DWC2_L2) { 336 ret = dwc2_exit_hibernation(hsotg, true); 337 if (ret && (ret != -ENOTSUP)) 338 dev_err(hsotg->dev, 339 "exit hibernation failed\n"); 340 } 341 342 /* 343 * Report disconnect if there is any previous session 344 * established 345 */ 346 dwc2_hsotg_disconnect(hsotg); 347 } 348 } 349 350 /* 351 * This interrupt indicates that the DWC_otg controller has detected a 352 * resume or remote wakeup sequence. If the DWC_otg controller is in 353 * low power mode, the handler must brings the controller out of low 354 * power mode. The controller automatically begins resume signaling. 355 * The handler schedules a time to stop resume signaling. 356 */ 357 STATIC void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) 358 { 359 int ret; 360 361 /* Clear interrupt */ 362 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_WKUPINT); 363 364 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n"); 365 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state); 366 367 if (dwc2_is_device_mode(hsotg)) { 368 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", DWC2_READ_4(hsotg, DSTS)); 369 if (hsotg->lx_state == DWC2_L2) { 370 u32 dctl = DWC2_READ_4(hsotg, DCTL); 371 372 /* Clear Remote Wakeup Signaling */ 373 dctl &= ~DCTL_RMTWKUPSIG; 374 DWC2_WRITE_4(hsotg, DCTL, dctl); 375 ret = dwc2_exit_hibernation(hsotg, true); 376 if (ret && (ret != -ENOTSUP)) 377 dev_err(hsotg->dev, "exit hibernation failed\n"); 378 379 call_gadget(hsotg, resume); 380 } 381 /* Change to L0 state */ 382 hsotg->lx_state = DWC2_L0; 383 } else { 384 if (hsotg->core_params->hibernation) 385 return; 386 387 if (hsotg->lx_state != DWC2_L1) { 388 u32 pcgcctl = DWC2_READ_4(hsotg, PCGCTL); 389 390 /* Restart the Phy Clock */ 391 pcgcctl &= ~PCGCTL_STOPPCLK; 392 DWC2_WRITE_4(hsotg, PCGCTL, pcgcctl); 393 timeout_set(&hsotg->wkp_timer, dwc2_wakeup_detected, 394 hsotg); 395 timeout_add_msec(&hsotg->wkp_timer, 71); 396 } else { 397 /* Change to L0 state */ 398 hsotg->lx_state = DWC2_L0; 399 } 400 } 401 } 402 403 /* 404 * This interrupt indicates that a device has been disconnected from the 405 * root port 406 */ 407 STATIC void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg) 408 { 409 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_DISCONNINT); 410 411 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n", 412 dwc2_is_host_mode(hsotg) ? "Host" : "Device", 413 dwc2_op_state_str(hsotg)); 414 415 if (hsotg->op_state == OTG_STATE_A_HOST) 416 dwc2_hcd_disconnect(hsotg, false); 417 } 418 419 /* 420 * This interrupt indicates that SUSPEND state has been detected on the USB. 421 * 422 * For HNP the USB Suspend interrupt signals the change from "a_peripheral" 423 * to "a_host". 424 * 425 * When power management is enabled the core will be put in low power mode. 426 */ 427 STATIC void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) 428 { 429 u32 dsts; 430 int ret; 431 432 /* Clear interrupt */ 433 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_USBSUSP); 434 435 dev_dbg(hsotg->dev, "USB SUSPEND\n"); 436 437 if (dwc2_is_device_mode(hsotg)) { 438 /* 439 * Check the Device status register to determine if the Suspend 440 * state is active 441 */ 442 dsts = DWC2_READ_4(hsotg, DSTS); 443 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts); 444 dev_dbg(hsotg->dev, 445 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n", 446 !!(dsts & DSTS_SUSPSTS), 447 hsotg->hw_params.power_optimized); 448 if ((dsts & DSTS_SUSPSTS) && hsotg->hw_params.power_optimized) { 449 /* Ignore suspend request before enumeration */ 450 if (!dwc2_is_device_connected(hsotg)) { 451 dev_dbg(hsotg->dev, 452 "ignore suspend request before enumeration\n"); 453 return; 454 } 455 456 ret = dwc2_enter_hibernation(hsotg); 457 if (ret) { 458 if (ret != -ENOTSUP) 459 dev_err(hsotg->dev, 460 "enter hibernation failed\n"); 461 goto skip_power_saving; 462 } 463 464 udelay(100); 465 466 /* Ask phy to be suspended */ 467 if (hsotg->uphy != NULL) 468 usb_phy_set_suspend(hsotg->uphy, true); 469 skip_power_saving: 470 /* 471 * Change to L2 (suspend) state before releasing 472 * spinlock 473 */ 474 hsotg->lx_state = DWC2_L2; 475 476 /* Call gadget suspend callback */ 477 call_gadget(hsotg, suspend); 478 } 479 } else { 480 if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) { 481 dev_dbg(hsotg->dev, "a_peripheral->a_host\n"); 482 483 /* Change to L2 (suspend) state */ 484 hsotg->lx_state = DWC2_L2; 485 /* Clear the a_peripheral flag, back to a_host */ 486 spin_unlock(&hsotg->lock); 487 dwc2_hcd_start(hsotg); 488 spin_lock(&hsotg->lock); 489 hsotg->op_state = OTG_STATE_A_HOST; 490 } 491 } 492 } 493 494 #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \ 495 GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \ 496 GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \ 497 GINTSTS_USBSUSP | GINTSTS_PRTINT) 498 499 /* 500 * This function returns the Core Interrupt register 501 */ 502 STATIC u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg) 503 { 504 u32 gintsts; 505 u32 gintmsk; 506 u32 gahbcfg; 507 u32 gintmsk_common = GINTMSK_COMMON; 508 509 gintsts = DWC2_READ_4(hsotg, GINTSTS); 510 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 511 gahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 512 513 /* If any common interrupts set */ 514 if (gintsts & gintmsk_common) 515 dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n", 516 gintsts, gintmsk); 517 518 if (gahbcfg & GAHBCFG_GLBL_INTR_EN) 519 return gintsts & gintmsk & gintmsk_common; 520 else 521 return 0; 522 } 523 524 /* 525 * Common interrupt handler 526 * 527 * The common interrupts are those that occur in both Host and Device mode. 528 * This handler handles the following interrupts: 529 * - Mode Mismatch Interrupt 530 * - OTG Interrupt 531 * - Connector ID Status Change Interrupt 532 * - Disconnect Interrupt 533 * - Session Request Interrupt 534 * - Resume / Remote Wakeup Detected Interrupt 535 * - Suspend Interrupt 536 */ 537 irqreturn_t dwc2_handle_common_intr(void *dev) 538 { 539 struct dwc2_hsotg *hsotg = dev; 540 u32 gintsts; 541 irqreturn_t retval = IRQ_NONE; 542 543 if (!dwc2_is_controller_alive(hsotg)) { 544 dev_warn(hsotg->dev, "Controller is dead\n"); 545 goto out; 546 } 547 548 MUTEX_ASSERT_LOCKED(&hsotg->lock); 549 550 gintsts = dwc2_read_common_intr(hsotg); 551 if (gintsts & ~GINTSTS_PRTINT) 552 retval = IRQ_HANDLED; 553 554 if (gintsts & GINTSTS_MODEMIS) 555 dwc2_handle_mode_mismatch_intr(hsotg); 556 if (gintsts & GINTSTS_OTGINT) 557 dwc2_handle_otg_intr(hsotg); 558 if (gintsts & GINTSTS_CONIDSTSCHNG) 559 dwc2_handle_conn_id_status_change_intr(hsotg); 560 if (gintsts & GINTSTS_DISCONNINT) 561 dwc2_handle_disconnect_intr(hsotg); 562 if (gintsts & GINTSTS_SESSREQINT) 563 dwc2_handle_session_req_intr(hsotg); 564 if (gintsts & GINTSTS_WKUPINT) 565 dwc2_handle_wakeup_detected_intr(hsotg); 566 if (gintsts & GINTSTS_USBSUSP) 567 dwc2_handle_usb_suspend_intr(hsotg); 568 569 if (gintsts & GINTSTS_PRTINT) { 570 /* 571 * The port interrupt occurs while in device mode with HPRT0 572 * Port Enable/Disable 573 */ 574 if (dwc2_is_device_mode(hsotg)) { 575 dev_dbg(hsotg->dev, 576 " --Port interrupt received in Device mode--\n"); 577 dwc2_handle_usb_port_intr(hsotg); 578 retval = IRQ_HANDLED; 579 } 580 } 581 582 out: 583 return retval; 584 } 585