1 /* $OpenBSD: dwc2_coreintr.c,v 1.8 2015/06/28 11:48:18 jmatthew Exp $ */ 2 /* $NetBSD: dwc2_coreintr.c,v 1.8 2014/04/04 05:40:57 skrll Exp $ */ 3 4 /* 5 * core_intr.c - DesignWare HS OTG Controller common interrupt handling 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * This file contains the common interrupt handlers 42 */ 43 44 #if 0 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: dwc2_coreintr.c,v 1.8 2014/04/04 05:40:57 skrll Exp $"); 47 #endif 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/mutex.h> 53 #include <sys/pool.h> 54 #include <sys/timeout.h> 55 56 #include <lib/libkern/libkern.h> 57 58 #include <machine/bus.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 #include <dev/usb/usbdivar.h> 63 #include <dev/usb/usb_mem.h> 64 65 #include <dev/usb/dwc2/dwc2.h> 66 #include <dev/usb/dwc2/dwc2var.h> 67 68 #include <dev/usb/dwc2/dwc2_core.h> 69 #include <dev/usb/dwc2/dwc2_hcd.h> 70 71 #ifdef DWC2_DEBUG 72 STATIC const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg) 73 { 74 switch (hsotg->op_state) { 75 case OTG_STATE_A_HOST: 76 return "a_host"; 77 case OTG_STATE_A_SUSPEND: 78 return "a_suspend"; 79 case OTG_STATE_A_PERIPHERAL: 80 return "a_peripheral"; 81 case OTG_STATE_B_PERIPHERAL: 82 return "b_peripheral"; 83 case OTG_STATE_B_HOST: 84 return "b_host"; 85 default: 86 return "unknown"; 87 } 88 } 89 #endif 90 91 /** 92 * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts. 93 * When the PRTINT interrupt fires, there are certain status bits in the Host 94 * Port that needs to get cleared. 95 * 96 * @hsotg: Programming view of DWC_otg controller 97 */ 98 STATIC void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) 99 { 100 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 101 102 if (hprt0 & HPRT0_ENACHG) { 103 hprt0 &= ~HPRT0_ENA; 104 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 105 } 106 107 /* Clear interrupt */ 108 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_PRTINT); 109 } 110 111 /** 112 * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message 113 * 114 * @hsotg: Programming view of DWC_otg controller 115 */ 116 STATIC void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg) 117 { 118 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n", 119 dwc2_is_host_mode(hsotg) ? "Host" : "Device"); 120 121 /* Clear interrupt */ 122 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_MODEMIS); 123 } 124 125 /** 126 * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG 127 * Interrupt Register (GOTGINT) to determine what interrupt has occurred. 128 * 129 * @hsotg: Programming view of DWC_otg controller 130 */ 131 STATIC void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) 132 { 133 u32 gotgint; 134 u32 gotgctl; 135 u32 gintmsk; 136 137 gotgint = DWC2_READ_4(hsotg, GOTGINT); 138 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 139 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, 140 dwc2_op_state_str(hsotg)); 141 142 if (gotgint & GOTGINT_SES_END_DET) { 143 dev_dbg(hsotg->dev, 144 " ++OTG Interrupt: Session End Detected++ (%s)\n", 145 dwc2_op_state_str(hsotg)); 146 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 147 148 if (hsotg->op_state == OTG_STATE_B_HOST) { 149 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 150 } else { 151 /* 152 * If not B_HOST and Device HNP still set, HNP did 153 * not succeed! 154 */ 155 if (gotgctl & GOTGCTL_DEVHNPEN) { 156 dev_dbg(hsotg->dev, "Session End Detected\n"); 157 dev_err(hsotg->dev, 158 "Device Not Connected/Responding!\n"); 159 } 160 161 /* 162 * If Session End Detected the B-Cable has been 163 * disconnected 164 */ 165 /* Reset to a clean state */ 166 hsotg->lx_state = DWC2_L0; 167 } 168 169 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 170 gotgctl &= ~GOTGCTL_DEVHNPEN; 171 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 172 } 173 174 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) { 175 dev_dbg(hsotg->dev, 176 " ++OTG Interrupt: Session Request Success Status Change++\n"); 177 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 178 if (gotgctl & GOTGCTL_SESREQSCS) { 179 if (hsotg->core_params->phy_type == 180 DWC2_PHY_TYPE_PARAM_FS 181 && hsotg->core_params->i2c_enable > 0) { 182 hsotg->srp_success = 1; 183 } else { 184 /* Clear Session Request */ 185 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 186 gotgctl &= ~GOTGCTL_SESREQ; 187 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 188 } 189 } 190 } 191 192 if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) { 193 /* 194 * Print statements during the HNP interrupt handling 195 * can cause it to fail 196 */ 197 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 198 /* 199 * WA for 3.00a- HW is not setting cur_mode, even sometimes 200 * this does not help 201 */ 202 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) 203 udelay(100); 204 if (gotgctl & GOTGCTL_HSTNEGSCS) { 205 if (dwc2_is_host_mode(hsotg)) { 206 hsotg->op_state = OTG_STATE_B_HOST; 207 /* 208 * Need to disable SOF interrupt immediately. 209 * When switching from device to host, the PCD 210 * interrupt handler won't handle the interrupt 211 * if host mode is already set. The HCD 212 * interrupt handler won't get called if the 213 * HCD state is HALT. This means that the 214 * interrupt does not get handled and Linux 215 * complains loudly. 216 */ 217 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 218 gintmsk &= ~GINTSTS_SOF; 219 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 220 221 /* 222 * Call callback function with spin lock 223 * released 224 */ 225 spin_unlock(&hsotg->lock); 226 227 /* Initialize the Core for Host mode */ 228 dwc2_hcd_start(hsotg); 229 spin_lock(&hsotg->lock); 230 hsotg->op_state = OTG_STATE_B_HOST; 231 } 232 } else { 233 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 234 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN); 235 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 236 dev_dbg(hsotg->dev, "HNP Failed\n"); 237 dev_err(hsotg->dev, 238 "Device Not Connected/Responding\n"); 239 } 240 } 241 242 if (gotgint & GOTGINT_HST_NEG_DET) { 243 /* 244 * The disconnect interrupt is set at the same time as 245 * Host Negotiation Detected. During the mode switch all 246 * interrupts are cleared so the disconnect interrupt 247 * handler will not get executed. 248 */ 249 dev_dbg(hsotg->dev, 250 " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n", 251 (dwc2_is_host_mode(hsotg) ? "Host" : "Device")); 252 if (dwc2_is_device_mode(hsotg)) { 253 dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n", 254 hsotg->op_state); 255 spin_unlock(&hsotg->lock); 256 dwc2_hcd_disconnect(hsotg); 257 spin_lock(&hsotg->lock); 258 hsotg->op_state = OTG_STATE_A_PERIPHERAL; 259 } else { 260 /* Need to disable SOF interrupt immediately */ 261 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 262 gintmsk &= ~GINTSTS_SOF; 263 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 264 spin_unlock(&hsotg->lock); 265 dwc2_hcd_start(hsotg); 266 spin_lock(&hsotg->lock); 267 hsotg->op_state = OTG_STATE_A_HOST; 268 } 269 } 270 271 if (gotgint & GOTGINT_A_DEV_TOUT_CHG) 272 dev_dbg(hsotg->dev, 273 " ++OTG Interrupt: A-Device Timeout Change++\n"); 274 if (gotgint & GOTGINT_DBNCE_DONE) 275 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n"); 276 277 /* Clear GOTGINT */ 278 DWC2_WRITE_4(hsotg, GOTGINT, gotgint); 279 } 280 281 /** 282 * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status 283 * Change Interrupt 284 * 285 * @hsotg: Programming view of DWC_otg controller 286 * 287 * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a 288 * Device to Host Mode transition or a Host to Device Mode transition. This only 289 * occurs when the cable is connected/removed from the PHY connector. 290 */ 291 STATIC void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) 292 { 293 u32 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 294 295 /* Need to disable SOF interrupt immediately */ 296 gintmsk &= ~GINTSTS_SOF; 297 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 298 299 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", 300 dwc2_is_host_mode(hsotg) ? "Host" : "Device"); 301 302 /* 303 * Need to schedule a work, as there are possible DELAY function calls. 304 * Release lock before scheduling workq as it holds spinlock during 305 * scheduling. 306 */ 307 spin_unlock(&hsotg->lock); 308 task_set(&hsotg->wf_otg, dwc2_conn_id_status_change, hsotg); 309 task_add(hsotg->wq_otg, &hsotg->wf_otg); 310 spin_lock(&hsotg->lock); 311 312 /* Clear interrupt */ 313 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_CONIDSTSCHNG); 314 } 315 316 /** 317 * dwc2_handle_session_req_intr() - This interrupt indicates that a device is 318 * initiating the Session Request Protocol to request the host to turn on bus 319 * power so a new session can begin 320 * 321 * @hsotg: Programming view of DWC_otg controller 322 * 323 * This handler responds by turning on bus power. If the DWC_otg controller is 324 * in low power mode, this handler brings the controller out of low power mode 325 * before turning on bus power. 326 */ 327 STATIC void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) 328 { 329 dev_dbg(hsotg->dev, "++Session Request Interrupt++\n"); 330 331 /* Clear interrupt */ 332 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_SESSREQINT); 333 } 334 335 /* 336 * This interrupt indicates that the DWC_otg controller has detected a 337 * resume or remote wakeup sequence. If the DWC_otg controller is in 338 * low power mode, the handler must brings the controller out of low 339 * power mode. The controller automatically begins resume signaling. 340 * The handler schedules a time to stop resume signaling. 341 */ 342 STATIC void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) 343 { 344 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n"); 345 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state); 346 347 if (dwc2_is_device_mode(hsotg)) { 348 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", DWC2_READ_4(hsotg, DSTS)); 349 if (hsotg->lx_state == DWC2_L2) { 350 u32 dctl = DWC2_READ_4(hsotg, DCTL); 351 352 /* Clear Remote Wakeup Signaling */ 353 dctl &= ~DCTL_RMTWKUPSIG; 354 DWC2_WRITE_4(hsotg, DCTL, dctl); 355 } 356 /* Change to L0 state */ 357 hsotg->lx_state = DWC2_L0; 358 } else { 359 if (hsotg->lx_state != DWC2_L1) { 360 u32 pcgcctl = DWC2_READ_4(hsotg, PCGCTL); 361 362 /* Restart the Phy Clock */ 363 pcgcctl &= ~PCGCTL_STOPPCLK; 364 DWC2_WRITE_4(hsotg, PCGCTL, pcgcctl); 365 timeout_reset(&hsotg->wkp_timer, mstohz(71), 366 dwc2_wakeup_detected, hsotg); 367 } else { 368 /* Change to L0 state */ 369 hsotg->lx_state = DWC2_L0; 370 } 371 } 372 373 /* Clear interrupt */ 374 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_WKUPINT); 375 } 376 377 /* 378 * This interrupt indicates that a device has been disconnected from the 379 * root port 380 */ 381 STATIC void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg) 382 { 383 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n", 384 dwc2_is_host_mode(hsotg) ? "Host" : "Device", 385 dwc2_op_state_str(hsotg)); 386 387 /* Change to L3 (OFF) state */ 388 hsotg->lx_state = DWC2_L3; 389 390 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_DISCONNINT); 391 } 392 393 /* 394 * This interrupt indicates that SUSPEND state has been detected on the USB. 395 * 396 * For HNP the USB Suspend interrupt signals the change from "a_peripheral" 397 * to "a_host". 398 * 399 * When power management is enabled the core will be put in low power mode. 400 */ 401 STATIC void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) 402 { 403 dev_dbg(hsotg->dev, "USB SUSPEND\n"); 404 405 if (dwc2_is_device_mode(hsotg)) { 406 #ifdef DWC2_DEBUG 407 u32 dsts; 408 409 /* 410 * Check the Device status register to determine if the Suspend 411 * state is active 412 */ 413 dsts = DWC2_READ_4(hsotg, DSTS); 414 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts); 415 dev_dbg(hsotg->dev, 416 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n", 417 !!(dsts & DSTS_SUSPSTS), 418 hsotg->hw_params.power_optimized); 419 #endif 420 } else { 421 if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) { 422 dev_dbg(hsotg->dev, "a_peripheral->a_host\n"); 423 424 /* Clear the a_peripheral flag, back to a_host */ 425 spin_unlock(&hsotg->lock); 426 dwc2_hcd_start(hsotg); 427 spin_lock(&hsotg->lock); 428 hsotg->op_state = OTG_STATE_A_HOST; 429 } 430 } 431 432 /* Change to L2 (suspend) state */ 433 hsotg->lx_state = DWC2_L2; 434 435 /* Clear interrupt */ 436 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_USBSUSP); 437 } 438 439 #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \ 440 GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \ 441 GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \ 442 GINTSTS_USBSUSP | GINTSTS_PRTINT) 443 444 /* 445 * This function returns the Core Interrupt register 446 */ 447 STATIC u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg) 448 { 449 u32 gintsts; 450 u32 gintmsk; 451 u32 gahbcfg; 452 u32 gintmsk_common = GINTMSK_COMMON; 453 454 gintsts = DWC2_READ_4(hsotg, GINTSTS); 455 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 456 gahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 457 458 /* If any common interrupts set */ 459 if (gintsts & gintmsk_common) 460 dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n", 461 gintsts, gintmsk); 462 463 if (gahbcfg & GAHBCFG_GLBL_INTR_EN) 464 return gintsts & gintmsk & gintmsk_common; 465 else 466 return 0; 467 } 468 469 /* 470 * Common interrupt handler 471 * 472 * The common interrupts are those that occur in both Host and Device mode. 473 * This handler handles the following interrupts: 474 * - Mode Mismatch Interrupt 475 * - OTG Interrupt 476 * - Connector ID Status Change Interrupt 477 * - Disconnect Interrupt 478 * - Session Request Interrupt 479 * - Resume / Remote Wakeup Detected Interrupt 480 * - Suspend Interrupt 481 */ 482 irqreturn_t dwc2_handle_common_intr(void *dev) 483 { 484 struct dwc2_hsotg *hsotg = dev; 485 u32 gintsts; 486 irqreturn_t retval = IRQ_NONE; 487 488 if (!dwc2_is_controller_alive(hsotg)) { 489 dev_warn(hsotg->dev, "Controller is dead\n"); 490 goto out; 491 } 492 493 KASSERT(mtx_owned(&hsotg->lock)); 494 495 gintsts = dwc2_read_common_intr(hsotg); 496 if (gintsts & ~GINTSTS_PRTINT) 497 retval = IRQ_HANDLED; 498 499 if (gintsts & GINTSTS_MODEMIS) 500 dwc2_handle_mode_mismatch_intr(hsotg); 501 if (gintsts & GINTSTS_OTGINT) 502 dwc2_handle_otg_intr(hsotg); 503 if (gintsts & GINTSTS_CONIDSTSCHNG) 504 dwc2_handle_conn_id_status_change_intr(hsotg); 505 if (gintsts & GINTSTS_DISCONNINT) 506 dwc2_handle_disconnect_intr(hsotg); 507 if (gintsts & GINTSTS_SESSREQINT) 508 dwc2_handle_session_req_intr(hsotg); 509 if (gintsts & GINTSTS_WKUPINT) 510 dwc2_handle_wakeup_detected_intr(hsotg); 511 if (gintsts & GINTSTS_USBSUSP) 512 dwc2_handle_usb_suspend_intr(hsotg); 513 514 if (gintsts & GINTSTS_PRTINT) { 515 /* 516 * The port interrupt occurs while in device mode with HPRT0 517 * Port Enable/Disable 518 */ 519 if (dwc2_is_device_mode(hsotg)) { 520 dev_dbg(hsotg->dev, 521 " --Port interrupt received in Device mode--\n"); 522 dwc2_handle_usb_port_intr(hsotg); 523 retval = IRQ_HANDLED; 524 } 525 } 526 527 out: 528 return retval; 529 } 530