1 /* $OpenBSD: dwc2_core.h,v 1.11 2021/07/27 13:36:59 mglocker Exp $ */ 2 /* $NetBSD: dwc2_core.h,v 1.5 2014/04/03 06:34:58 skrll Exp $ */ 3 4 /* 5 * core.h - DesignWare HS OTG Controller common declarations 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef __DWC2_CORE_H__ 41 #define __DWC2_CORE_H__ 42 43 #include <sys/stdint.h> 44 #include <sys/task.h> 45 #include <sys/pool.h> 46 #include <sys/queue.h> 47 #include <sys/device.h> 48 49 #include <machine/intr.h> 50 #include <machine/bus.h> 51 52 #include <dev/usb/dwc2/dwc2_hw.h> 53 54 #include <dev/usb/dwc2/list.h> 55 56 /* Maximum number of Endpoints/HostChannels */ 57 #define MAX_EPS_CHANNELS 16 58 59 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 60 61 /* dwc2-hsotg declarations */ 62 STATIC const char * const dwc2_hsotg_supply_names[] = { 63 "vusb_d", /* digital USB supply, 1.2V */ 64 "vusb_a", /* analog USB supply, 1.1V */ 65 }; 66 67 /* 68 * EP0_MPS_LIMIT 69 * 70 * Unfortunately there seems to be a limit of the amount of data that can 71 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 72 * packets (which practically means 1 packet and 63 bytes of data) when the 73 * MPS is set to 64. 74 * 75 * This means if we are wanting to move >127 bytes of data, we need to 76 * split the transactions up, but just doing one packet at a time does 77 * not work (this may be an implicit DATA0 PID on first packet of the 78 * transaction) and doing 2 packets is outside the controller's limits. 79 * 80 * If we try to lower the MPS size for EP0, then no transfers work properly 81 * for EP0, and the system will fail basic enumeration. As no cause for this 82 * has currently been found, we cannot support any large IN transfers for 83 * EP0. 84 */ 85 #define EP0_MPS_LIMIT 64 86 87 struct dwc2_hsotg; 88 struct dwc2_hsotg_req; 89 90 /** 91 * struct dwc2_hsotg_ep - driver endpoint definition. 92 * @ep: The gadget layer representation of the endpoint. 93 * @name: The driver generated name for the endpoint. 94 * @queue: Queue of requests for this endpoint. 95 * @parent: Reference back to the parent device structure. 96 * @req: The current request that the endpoint is processing. This is 97 * used to indicate an request has been loaded onto the endpoint 98 * and has yet to be completed (maybe due to data move, or simply 99 * awaiting an ack from the core all the data has been completed). 100 * @debugfs: File entry for debugfs file for this endpoint. 101 * @lock: State lock to protect contents of endpoint. 102 * @dir_in: Set to true if this endpoint is of the IN direction, which 103 * means that it is sending data to the Host. 104 * @index: The index for the endpoint registers. 105 * @mc: Multi Count - number of transactions per microframe 106 * @interval - Interval for periodic endpoints 107 * @name: The name array passed to the USB core. 108 * @halted: Set if the endpoint has been halted. 109 * @periodic: Set if this is a periodic ep, such as Interrupt 110 * @isochronous: Set if this is a isochronous ep 111 * @send_zlp: Set if we need to send a zero-length packet. 112 * @total_data: The total number of data bytes done. 113 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 114 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 115 * @last_load: The offset of data for the last start of request. 116 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 117 * 118 * This is the driver's state for each registered enpoint, allowing it 119 * to keep track of transactions that need doing. Each endpoint has a 120 * lock to protect the state, to try and avoid using an overall lock 121 * for the host controller as much as possible. 122 * 123 * For periodic IN endpoints, we have fifo_size and fifo_load to try 124 * and keep track of the amount of data in the periodic FIFO for each 125 * of these as we don't have a status register that tells us how much 126 * is in each of them. (note, this may actually be useless information 127 * as in shared-fifo mode periodic in acts like a single-frame packet 128 * buffer than a fifo) 129 */ 130 struct dwc2_hsotg_ep { 131 struct usb_ep ep; 132 struct list_head queue; 133 struct dwc2_hsotg *parent; 134 struct dwc2_hsotg_req *req; 135 struct dentry *debugfs; 136 137 unsigned long total_data; 138 unsigned int size_loaded; 139 unsigned int last_load; 140 unsigned int fifo_load; 141 unsigned short fifo_size; 142 unsigned short fifo_index; 143 144 unsigned char dir_in; 145 unsigned char index; 146 unsigned char mc; 147 unsigned char interval; 148 149 unsigned int halted:1; 150 unsigned int periodic:1; 151 unsigned int isochronous:1; 152 unsigned int send_zlp:1; 153 unsigned int has_correct_parity:1; 154 155 char name[10]; 156 }; 157 158 /** 159 * struct dwc2_hsotg_req - data transfer request 160 * @req: The USB gadget request 161 * @queue: The list of requests for the endpoint this is queued for. 162 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 163 */ 164 struct dwc2_hsotg_req { 165 struct usb_request req; 166 struct list_head queue; 167 void *saved_req_buf; 168 }; 169 170 #define call_gadget(_hs, _entry) \ 171 do { \ 172 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 173 (_hs)->driver && (_hs)->driver->_entry) { \ 174 spin_unlock(&_hs->lock); \ 175 (_hs)->driver->_entry(&(_hs)->gadget); \ 176 spin_lock(&_hs->lock); \ 177 } \ 178 } while (0) 179 #else 180 #define call_gadget(_hs, _entry) do {} while (0) 181 #endif 182 183 struct dwc2_hsotg; 184 struct dwc2_host_chan; 185 186 /* Device States */ 187 enum dwc2_lx_state { 188 DWC2_L0, /* On state */ 189 DWC2_L1, /* LPM sleep state */ 190 DWC2_L2, /* USB suspend state */ 191 DWC2_L3, /* Off state */ 192 }; 193 194 /* 195 * Gadget periodic tx fifo sizes as used by legacy driver 196 * EP0 is not included 197 */ 198 #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ 199 768, 0, 0, 0, 0, 0, 0, 0} 200 201 /* Gadget ep0 states */ 202 enum dwc2_ep0_state { 203 DWC2_EP0_SETUP, 204 DWC2_EP0_DATA_IN, 205 DWC2_EP0_DATA_OUT, 206 DWC2_EP0_STATUS_IN, 207 DWC2_EP0_STATUS_OUT, 208 }; 209 210 /** 211 * struct dwc2_core_params - Parameters for configuring the core 212 * 213 * @otg_cap: Specifies the OTG capabilities. 214 * 0 - HNP and SRP capable 215 * 1 - SRP Only capable 216 * 2 - No HNP/SRP capable (always available) 217 * Defaults to best available option (0, 1, then 2) 218 * @otg_ver: OTG version supported 219 * 0 - 1.3 (default) 220 * 1 - 2.0 221 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 222 * the data FIFOs. The driver will automatically detect the 223 * value for this parameter if none is specified. 224 * 0 - Slave (always available) 225 * 1 - DMA (default, if available) 226 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 227 * address DMA mode or descriptor DMA mode for accessing 228 * the data FIFOs. The driver will automatically detect the 229 * value for this if none is specified. 230 * 0 - Address DMA 231 * 1 - Descriptor DMA (default, if available) 232 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 233 * address DMA mode or descriptor DMA mode for accessing 234 * the data FIFOs in Full Speed mode only. The driver 235 * will automatically detect the value for this if none is 236 * specified. 237 * 0 - Address DMA 238 * 1 - Descriptor DMA in FS (default, if available) 239 * @speed: Specifies the maximum speed of operation in host and 240 * device mode. The actual speed depends on the speed of 241 * the attached device and the value of phy_type. 242 * 0 - High Speed 243 * (default when phy_type is UTMI+ or ULPI) 244 * 1 - Full Speed 245 * (default when phy_type is Full Speed) 246 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 247 * 1 - Allow dynamic FIFO sizing (default, if available) 248 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 249 * are enabled 250 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 251 * dynamic FIFO sizing is enabled 252 * 16 to 32768 253 * Actual maximum value is autodetected and also 254 * the default. 255 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 256 * in host mode when dynamic FIFO sizing is enabled 257 * 16 to 32768 258 * Actual maximum value is autodetected and also 259 * the default. 260 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 261 * host mode when dynamic FIFO sizing is enabled 262 * 16 to 32768 263 * Actual maximum value is autodetected and also 264 * the default. 265 * @max_transfer_size: The maximum transfer size supported, in bytes 266 * 2047 to 65,535 267 * Actual maximum value is autodetected and also 268 * the default. 269 * @max_packet_count: The maximum number of packets in a transfer 270 * 15 to 511 271 * Actual maximum value is autodetected and also 272 * the default. 273 * @host_channels: The number of host channel registers to use 274 * 1 to 16 275 * Actual maximum value is autodetected and also 276 * the default. 277 * @phy_type: Specifies the type of PHY interface to use. By default, 278 * the driver will automatically detect the phy_type. 279 * 0 - Full Speed Phy 280 * 1 - UTMI+ Phy 281 * 2 - ULPI Phy 282 * Defaults to best available option (2, 1, then 0) 283 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 284 * is applicable for a phy_type of UTMI+ or ULPI. (For a 285 * ULPI phy_type, this parameter indicates the data width 286 * between the MAC and the ULPI Wrapper.) Also, this 287 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 288 * parameter was set to "8 and 16 bits", meaning that the 289 * core has been configured to work at either data path 290 * width. 291 * 8 or 16 (default 16 if available) 292 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 293 * data rate. This parameter is only applicable if phy_type 294 * is ULPI. 295 * 0 - single data rate ULPI interface with 8 bit wide 296 * data bus (default) 297 * 1 - double data rate ULPI interface with 4 bit wide 298 * data bus 299 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 300 * external supply to drive the VBus 301 * 0 - Internal supply (default) 302 * 1 - External supply 303 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 304 * speed PHY. This parameter is only applicable if phy_type 305 * is FS. 306 * 0 - No (default) 307 * 1 - Yes 308 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 309 * 0 - No (default) 310 * 1 - Yes 311 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 312 * when attached to a Full Speed or Low Speed device in 313 * host mode. 314 * 0 - Don't support low power mode (default) 315 * 1 - Support low power mode 316 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 317 * when connected to a Low Speed device in host 318 * mode. This parameter is applicable only if 319 * host_support_fs_ls_low_power is enabled. 320 * 0 - 48 MHz 321 * (default when phy_type is UTMI+ or ULPI) 322 * 1 - 6 MHz 323 * (default when phy_type is Full Speed) 324 * @ts_dline: Enable Term Select Dline pulsing 325 * 0 - No (default) 326 * 1 - Yes 327 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 328 * 0 - No (default for core < 2.92a) 329 * 1 - Yes (default for core >= 2.92a) 330 * @ahbcfg: This field allows the default value of the GAHBCFG 331 * register to be overridden 332 * -1 - GAHBCFG value will be set to 0x06 333 * (INCR4, default) 334 * all others - GAHBCFG value will be overridden with 335 * this value 336 * Not all bits can be controlled like this, the 337 * bits defined by GAHBCFG_CTRL_MASK are controlled 338 * by the driver and are ignored in this 339 * configuration value. 340 * @uframe_sched: True to enable the microframe scheduler 341 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 342 * Disable CONIDSTSCHNG controller interrupt in such 343 * case. 344 * 0 - No (default) 345 * 1 - Yes 346 * @hibernation: Specifies whether the controller support hibernation. 347 * If hibernation is enabled, the controller will enter 348 * hibernation in both peripheral and host mode when 349 * needed. 350 * 0 - No (default) 351 * 1 - Yes 352 * 353 * The following parameters may be specified when starting the module. These 354 * parameters define how the DWC_otg controller should be configured. A 355 * value of -1 (or any other out of range value) for any parameter means 356 * to read the value from hardware (if possible) or use the builtin 357 * default described above. 358 */ 359 struct dwc2_core_params { 360 /* 361 * Don't add any non-int members here, this will break 362 * dwc2_set_all_params! 363 */ 364 int otg_cap; 365 int otg_ver; 366 int dma_enable; 367 int dma_desc_enable; 368 int dma_desc_fs_enable; 369 int speed; 370 int enable_dynamic_fifo; 371 int en_multiple_tx_fifo; 372 int host_rx_fifo_size; 373 int host_nperio_tx_fifo_size; 374 int host_perio_tx_fifo_size; 375 int max_transfer_size; 376 int max_packet_count; 377 int host_channels; 378 int phy_type; 379 int phy_utmi_width; 380 int phy_ulpi_ddr; 381 int phy_ulpi_ext_vbus; 382 int i2c_enable; 383 int ulpi_fs_ls; 384 int host_support_fs_ls_low_power; 385 int host_ls_low_power_phy_clk; 386 int ts_dline; 387 int reload_ctl; 388 int ahbcfg; 389 int uframe_sched; 390 int external_id_pin_ctl; 391 int hibernation; 392 }; 393 394 /** 395 * struct dwc2_hw_params - Autodetected parameters. 396 * 397 * These parameters are the various parameters read from hardware 398 * registers during initialization. They typically contain the best 399 * supported or maximum value that can be configured in the 400 * corresponding dwc2_core_params value. 401 * 402 * The values that are not in dwc2_core_params are documented below. 403 * 404 * @op_mode Mode of Operation 405 * 0 - HNP- and SRP-Capable OTG (Host & Device) 406 * 1 - SRP-Capable OTG (Host & Device) 407 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 408 * 3 - SRP-Capable Device 409 * 4 - Non-OTG Device 410 * 5 - SRP-Capable Host 411 * 6 - Non-OTG Host 412 * @arch Architecture 413 * 0 - Slave only 414 * 1 - External DMA 415 * 2 - Internal DMA 416 * @power_optimized Are power optimizations enabled? 417 * @num_dev_ep Number of device endpoints available 418 * @num_dev_perio_in_ep Number of device periodic IN endpoints 419 * available 420 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 421 * Depth 422 * 0 to 30 423 * @host_perio_tx_q_depth 424 * Host Mode Periodic Request Queue Depth 425 * 2, 4 or 8 426 * @nperio_tx_q_depth 427 * Non-Periodic Request Queue Depth 428 * 2, 4 or 8 429 * @hs_phy_type High-speed PHY interface type 430 * 0 - High-speed interface not supported 431 * 1 - UTMI+ 432 * 2 - ULPI 433 * 3 - UTMI+ and ULPI 434 * @fs_phy_type Full-speed PHY interface type 435 * 0 - Full speed interface not supported 436 * 1 - Dedicated full speed interface 437 * 2 - FS pins shared with UTMI+ pins 438 * 3 - FS pins shared with ULPI pins 439 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 440 * @utmi_phy_data_width UTMI+ PHY data width 441 * 0 - 8 bits 442 * 1 - 16 bits 443 * 2 - 8 or 16 bits 444 * @snpsid: Value from SNPSID register 445 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 446 */ 447 struct dwc2_hw_params { 448 unsigned op_mode:3; 449 unsigned arch:2; 450 unsigned dma_desc_enable:1; 451 unsigned dma_desc_fs_enable:1; 452 unsigned enable_dynamic_fifo:1; 453 unsigned en_multiple_tx_fifo:1; 454 unsigned host_rx_fifo_size:16; 455 unsigned host_nperio_tx_fifo_size:16; 456 unsigned dev_nperio_tx_fifo_size:16; 457 unsigned host_perio_tx_fifo_size:16; 458 unsigned nperio_tx_q_depth:3; 459 unsigned host_perio_tx_q_depth:3; 460 unsigned dev_token_q_depth:5; 461 unsigned max_transfer_size:26; 462 unsigned max_packet_count:11; 463 unsigned host_channels:5; 464 unsigned hs_phy_type:2; 465 unsigned fs_phy_type:2; 466 unsigned i2c_enable:1; 467 unsigned num_dev_ep:4; 468 unsigned num_dev_perio_in_ep:4; 469 unsigned total_fifo_size:16; 470 unsigned power_optimized:1; 471 unsigned utmi_phy_data_width:2; 472 u32 snpsid; 473 u32 dev_ep_dirs; 474 }; 475 476 /* Size of control and EP0 buffers */ 477 #define DWC2_CTRL_BUFF_SIZE 8 478 479 /** 480 * struct dwc2_gregs_backup - Holds global registers state before entering partial 481 * power down 482 * @gotgctl: Backup of GOTGCTL register 483 * @gintmsk: Backup of GINTMSK register 484 * @gahbcfg: Backup of GAHBCFG register 485 * @gusbcfg: Backup of GUSBCFG register 486 * @grxfsiz: Backup of GRXFSIZ register 487 * @gnptxfsiz: Backup of GNPTXFSIZ register 488 * @gi2cctl: Backup of GI2CCTL register 489 * @hptxfsiz: Backup of HPTXFSIZ register 490 * @gdfifocfg: Backup of GDFIFOCFG register 491 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 492 * @gpwrdn: Backup of GPWRDN register 493 */ 494 struct dwc2_gregs_backup { 495 u32 gotgctl; 496 u32 gintmsk; 497 u32 gahbcfg; 498 u32 gusbcfg; 499 u32 grxfsiz; 500 u32 gnptxfsiz; 501 u32 gi2cctl; 502 u32 hptxfsiz; 503 u32 pcgcctl; 504 u32 gdfifocfg; 505 u32 dtxfsiz[MAX_EPS_CHANNELS]; 506 u32 gpwrdn; 507 bool valid; 508 }; 509 510 /** 511 * struct dwc2_dregs_backup - Holds device registers state before entering partial 512 * power down 513 * @dcfg: Backup of DCFG register 514 * @dctl: Backup of DCTL register 515 * @daintmsk: Backup of DAINTMSK register 516 * @diepmsk: Backup of DIEPMSK register 517 * @doepmsk: Backup of DOEPMSK register 518 * @diepctl: Backup of DIEPCTL register 519 * @dieptsiz: Backup of DIEPTSIZ register 520 * @diepdma: Backup of DIEPDMA register 521 * @doepctl: Backup of DOEPCTL register 522 * @doeptsiz: Backup of DOEPTSIZ register 523 * @doepdma: Backup of DOEPDMA register 524 */ 525 struct dwc2_dregs_backup { 526 u32 dcfg; 527 u32 dctl; 528 u32 daintmsk; 529 u32 diepmsk; 530 u32 doepmsk; 531 u32 diepctl[MAX_EPS_CHANNELS]; 532 u32 dieptsiz[MAX_EPS_CHANNELS]; 533 u32 diepdma[MAX_EPS_CHANNELS]; 534 u32 doepctl[MAX_EPS_CHANNELS]; 535 u32 doeptsiz[MAX_EPS_CHANNELS]; 536 u32 doepdma[MAX_EPS_CHANNELS]; 537 bool valid; 538 }; 539 540 /** 541 * struct dwc2_hregs_backup - Holds host registers state before entering partial 542 * power down 543 * @hcfg: Backup of HCFG register 544 * @haintmsk: Backup of HAINTMSK register 545 * @hcintmsk: Backup of HCINTMSK register 546 * @hptr0: Backup of HPTR0 register 547 * @hfir: Backup of HFIR register 548 */ 549 struct dwc2_hregs_backup { 550 u32 hcfg; 551 u32 haintmsk; 552 u32 hcintmsk[MAX_EPS_CHANNELS]; 553 u32 hprt0; 554 u32 hfir; 555 bool valid; 556 }; 557 558 /** 559 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 560 * and periodic schedules 561 * 562 * These are common for both host and peripheral modes: 563 * 564 * @dev: The struct device pointer 565 * @regs: Pointer to controller regs 566 * @hw_params: Parameters that were autodetected from the 567 * hardware registers 568 * @core_params: Parameters that define how the core should be configured 569 * @op_state: The operational State, during transitions (a_host=> 570 * a_peripheral and b_device=>b_host) this may not match 571 * the core, but allows the software to determine 572 * transitions 573 * @dr_mode: Requested mode of operation, one of following: 574 * - USB_DR_MODE_PERIPHERAL 575 * - USB_DR_MODE_HOST 576 * - USB_DR_MODE_OTG 577 * @hcd_enabled Host mode sub-driver initialization indicator. 578 * @gadget_enabled Peripheral mode sub-driver initialization indicator. 579 * @ll_hw_enabled Status of low-level hardware resources. 580 * @phy: The otg phy transceiver structure for phy control. 581 * @uphy: The otg phy transceiver structure for old USB phy control. 582 * @plat: The platform specific configuration data. This can be removed once 583 * all SoCs support usb transceiver. 584 * @supplies: Definition of USB power supplies 585 * @phyif: PHY interface width 586 * @lock: Spinlock that protects all the driver data structures 587 * @priv: Stores a pointer to the struct usb_hcd 588 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 589 * transfer are in process of being queued 590 * @srp_success: Stores status of SRP request in the case of a FS PHY 591 * with an I2C interface 592 * @wq_otg: Workqueue object used for handling of some interrupts 593 * @wf_otg: Work object for handling Connector ID Status Change 594 * interrupt 595 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 596 * @lx_state: Lx state of connected device 597 * @gregs_backup: Backup of global registers during suspend 598 * @dregs_backup: Backup of device registers during suspend 599 * @hregs_backup: Backup of host registers during suspend 600 * 601 * These are for host mode: 602 * 603 * @flags: Flags for handling root port state changes 604 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 605 * Transfers associated with these QHs are not currently 606 * assigned to a host channel. 607 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 608 * Transfers associated with these QHs are currently 609 * assigned to a host channel. 610 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 611 * non-periodic schedule 612 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 613 * list of QHs for periodic transfers that are _not_ 614 * scheduled for the next frame. Each QH in the list has an 615 * interval counter that determines when it needs to be 616 * scheduled for execution. This scheduling mechanism 617 * allows only a simple calculation for periodic bandwidth 618 * used (i.e. must assume that all periodic transfers may 619 * need to execute in the same frame). However, it greatly 620 * simplifies scheduling and should be sufficient for the 621 * vast majority of OTG hosts, which need to connect to a 622 * small number of peripherals at one time. Items move from 623 * this list to periodic_sched_ready when the QH interval 624 * counter is 0 at SOF. 625 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 626 * the next frame, but have not yet been assigned to host 627 * channels. Items move from this list to 628 * periodic_sched_assigned as host channels become 629 * available during the current frame. 630 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 631 * frame that are assigned to host channels. Items move 632 * from this list to periodic_sched_queued as the 633 * transactions for the QH are queued to the DWC_otg 634 * controller. 635 * @periodic_sched_queued: List of periodic QHs that have been queued for 636 * execution. Items move from this list to either 637 * periodic_sched_inactive or periodic_sched_ready when the 638 * channel associated with the transfer is released. If the 639 * interval for the QH is 1, the item moves to 640 * periodic_sched_ready because it must be rescheduled for 641 * the next frame. Otherwise, the item moves to 642 * periodic_sched_inactive. 643 * @split_order: List keeping track of channels doing splits, in order. 644 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 645 * This value is in microseconds per (micro)frame. The 646 * assumption is that all periodic transfers may occur in 647 * the same (micro)frame. 648 * @frame_usecs: Internal variable used by the microframe scheduler 649 * @frame_number: Frame number read from the core at SOF. The value ranges 650 * from 0 to HFNUM_MAX_FRNUM. 651 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 652 * SOF enable/disable. 653 * @free_hc_list: Free host channels in the controller. This is a list of 654 * struct dwc2_host_chan items. 655 * @periodic_channels: Number of host channels assigned to periodic transfers. 656 * Currently assuming that there is a dedicated host 657 * channel for each periodic transaction and at least one 658 * host channel is available for non-periodic transactions. 659 * @non_periodic_channels: Number of host channels assigned to non-periodic 660 * transfers 661 * @available_host_channels Number of host channels available for the microframe 662 * scheduler to use 663 * @hc_ptr_array: Array of pointers to the host channel descriptors. 664 * Allows accessing a host channel descriptor given the 665 * host channel number. This is useful in interrupt 666 * handlers. 667 * @status_buf: Buffer used for data received during the status phase of 668 * a control transfer. 669 * @status_buf_dma: DMA address for status_buf 670 * @start_work: Delayed work for handling host A-cable connection 671 * @reset_work: Delayed work for handling a port reset 672 * @otg_port: OTG port number 673 * @frame_list: Frame list 674 * @frame_list_dma: Frame list DMA address 675 * @frame_list_sz: Frame list size 676 * @desc_gen_cache: Kmem cache for generic descriptors 677 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 678 * 679 * These are for peripheral mode: 680 * 681 * @driver: USB gadget driver 682 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 683 * @num_of_eps: Number of available EPs (excluding EP0) 684 * @debug_root: Root directrory for debugfs. 685 * @debug_file: Main status file for debugfs. 686 * @debug_testmode: Testmode status file for debugfs. 687 * @debug_fifo: FIFO status file for debugfs. 688 * @ep0_reply: Request used for ep0 reply. 689 * @ep0_buff: Buffer for EP0 reply data, if needed. 690 * @ctrl_buff: Buffer for EP0 control requests. 691 * @ctrl_req: Request for EP0 control packets. 692 * @ep0_state: EP0 control transfers state 693 * @test_mode: USB test mode requested by the host 694 * @eps: The endpoints being supplied to the gadget framework 695 * @g_using_dma: Indicate if dma usage is enabled 696 * @g_rx_fifo_sz: Contains rx fifo size value 697 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value 698 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints 699 */ 700 struct dwc2_hsotg { 701 struct device *dev; 702 struct dwc2_softc *hsotg_sc; 703 /** Params detected from hardware */ 704 struct dwc2_hw_params hw_params; 705 /** Params to actually use */ 706 struct dwc2_core_params *core_params; 707 enum usb_otg_state op_state; 708 enum usb_dr_mode dr_mode; 709 unsigned int hcd_enabled:1; 710 unsigned int gadget_enabled:1; 711 unsigned int ll_hw_enabled:1; 712 713 spinlock_t lock; 714 void *priv; 715 struct usb_phy *uphy; 716 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 717 struct phy *phy; 718 struct usb_phy *uphy; 719 struct dwc2_hsotg_plat *plat; 720 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)]; 721 u32 phyif; 722 723 int irq; 724 struct clk *clk; 725 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 726 727 unsigned int queuing_high_bandwidth:1; 728 unsigned int srp_success:1; 729 730 struct taskq *wq_otg; 731 struct task wf_otg; 732 struct timeout wkp_timer; 733 enum dwc2_lx_state lx_state; 734 struct dwc2_gregs_backup gr_backup; 735 struct dwc2_dregs_backup dr_backup; 736 struct dwc2_hregs_backup hr_backup; 737 738 struct dentry *debug_root; 739 struct debugfs_regset32 *regset; 740 741 /* DWC OTG HW Release versions */ 742 #define DWC2_CORE_REV_2_71a 0x4f54271a 743 #define DWC2_CORE_REV_2_90a 0x4f54290a 744 #define DWC2_CORE_REV_2_92a 0x4f54292a 745 #define DWC2_CORE_REV_2_94a 0x4f54294a 746 #define DWC2_CORE_REV_3_00a 0x4f54300a 747 748 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 749 union dwc2_hcd_internal_flags { 750 u32 d32; 751 struct { 752 unsigned port_connect_status_change:1; 753 unsigned port_connect_status:1; 754 unsigned port_reset_change:1; 755 unsigned port_enable_change:1; 756 unsigned port_suspend_change:1; 757 unsigned port_over_current_change:1; 758 unsigned port_l1_change:1; 759 unsigned reserved:25; 760 } b; 761 } flags; 762 763 struct list_head non_periodic_sched_inactive; 764 struct list_head non_periodic_sched_waiting; 765 struct list_head non_periodic_sched_active; 766 struct list_head *non_periodic_qh_ptr; 767 struct list_head periodic_sched_inactive; 768 struct list_head periodic_sched_ready; 769 struct list_head periodic_sched_assigned; 770 struct list_head periodic_sched_queued; 771 struct list_head split_order; 772 u16 periodic_usecs; 773 u16 frame_usecs[8]; 774 u16 frame_number; 775 u16 periodic_qh_count; 776 bool bus_suspended; 777 bool new_connection; 778 779 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 780 #define FRAME_NUM_ARRAY_SIZE 1000 781 u16 last_frame_num; 782 u16 *frame_num_array; 783 u16 *last_frame_num_array; 784 int frame_num_idx; 785 int dumped_frame_num_array; 786 #endif 787 788 struct list_head free_hc_list; 789 int periodic_channels; 790 int non_periodic_channels; 791 int available_host_channels; 792 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 793 struct usb_dma status_buf_usbdma; 794 u8 *status_buf; 795 dma_addr_t status_buf_dma; 796 #define DWC2_HCD_STATUS_BUF_SIZE 64 797 798 struct delayed_work start_work; 799 struct delayed_work reset_work; 800 u8 otg_port; 801 struct usb_dma frame_list_usbdma; 802 u32 *frame_list; 803 dma_addr_t frame_list_dma; 804 u32 frame_list_sz; 805 struct kmem_cache *desc_gen_cache; 806 struct kmem_cache *desc_hsisoc_cache; 807 808 #ifdef DEBUG 809 u32 frrem_samples; 810 u64 frrem_accum; 811 812 u32 hfnum_7_samples_a; 813 u64 hfnum_7_frrem_accum_a; 814 u32 hfnum_0_samples_a; 815 u64 hfnum_0_frrem_accum_a; 816 u32 hfnum_other_samples_a; 817 u64 hfnum_other_frrem_accum_a; 818 819 u32 hfnum_7_samples_b; 820 u64 hfnum_7_frrem_accum_b; 821 u32 hfnum_0_samples_b; 822 u64 hfnum_0_frrem_accum_b; 823 u32 hfnum_other_samples_b; 824 u64 hfnum_other_frrem_accum_b; 825 #endif 826 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 827 828 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 829 /* Gadget structures */ 830 struct usb_gadget_driver *driver; 831 int fifo_mem; 832 unsigned int dedicated_fifos:1; 833 unsigned char num_of_eps; 834 u32 fifo_map; 835 836 struct usb_request *ep0_reply; 837 struct usb_request *ctrl_req; 838 void *ep0_buff; 839 void *ctrl_buff; 840 enum dwc2_ep0_state ep0_state; 841 u8 test_mode; 842 843 struct usb_gadget gadget; 844 unsigned int enabled:1; 845 unsigned int connected:1; 846 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 847 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 848 u32 g_using_dma; 849 u32 g_rx_fifo_sz; 850 u32 g_np_g_tx_fifo_sz; 851 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; 852 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 853 }; 854 855 /* Reasons for halting a host channel */ 856 enum dwc2_halt_status { 857 DWC2_HC_XFER_NO_HALT_STATUS, 858 DWC2_HC_XFER_COMPLETE, 859 DWC2_HC_XFER_URB_COMPLETE, 860 DWC2_HC_XFER_ACK, 861 DWC2_HC_XFER_NAK, 862 DWC2_HC_XFER_NYET, 863 DWC2_HC_XFER_STALL, 864 DWC2_HC_XFER_XACT_ERR, 865 DWC2_HC_XFER_FRAME_OVERRUN, 866 DWC2_HC_XFER_BABBLE_ERR, 867 DWC2_HC_XFER_DATA_TOGGLE_ERR, 868 DWC2_HC_XFER_AHB_ERR, 869 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 870 DWC2_HC_XFER_URB_DEQUEUE, 871 }; 872 873 /* 874 * The following functions support initialization of the core driver component 875 * and the DWC_otg controller 876 */ 877 extern int dwc2_core_reset(struct dwc2_hsotg *hsotg); 878 extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); 879 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 880 extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 881 extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 882 883 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 884 885 /* 886 * Host core Functions. 887 * The following functions support managing the DWC_otg controller in host 888 * mode. 889 */ 890 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 891 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 892 enum dwc2_halt_status halt_status); 893 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 894 struct dwc2_host_chan *chan); 895 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 896 struct dwc2_host_chan *chan); 897 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 898 struct dwc2_host_chan *chan); 899 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 900 struct dwc2_host_chan *chan); 901 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 902 struct dwc2_host_chan *chan); 903 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 904 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 905 906 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 907 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 908 909 /* 910 * Common core Functions. 911 * The following functions support managing the DWC_otg controller in either 912 * device or host mode. 913 */ 914 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 915 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 916 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 917 918 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); 919 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 920 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 921 922 /* This function should be called on every hardware interrupt. */ 923 extern irqreturn_t dwc2_handle_common_intr(void *dev); 924 925 /* OTG Core Parameters */ 926 927 /* 928 * Specifies the OTG capabilities. The driver will automatically 929 * detect the value for this parameter if none is specified. 930 * 0 - HNP and SRP capable (default) 931 * 1 - SRP Only capable 932 * 2 - No HNP/SRP capable 933 */ 934 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 935 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 936 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 937 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 938 939 /* 940 * Specifies whether to use slave or DMA mode for accessing the data 941 * FIFOs. The driver will automatically detect the value for this 942 * parameter if none is specified. 943 * 0 - Slave 944 * 1 - DMA (default, if available) 945 */ 946 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 947 948 /* 949 * When DMA mode is enabled specifies whether to use 950 * address DMA or DMA Descritor mode for accessing the data 951 * FIFOs in device mode. The driver will automatically detect 952 * the value for this parameter if none is specified. 953 * 0 - address DMA 954 * 1 - DMA Descriptor(default, if available) 955 */ 956 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 957 958 /* 959 * When DMA mode is enabled specifies whether to use 960 * address DMA or DMA Descritor mode with full speed devices 961 * for accessing the data FIFOs in host mode. 962 * 0 - address DMA 963 * 1 - FS DMA Descriptor(default, if available) 964 */ 965 extern void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, 966 int val); 967 968 /* 969 * Specifies the maximum speed of operation in host and device mode. 970 * The actual speed depends on the speed of the attached device and 971 * the value of phy_type. The actual speed depends on the speed of the 972 * attached device. 973 * 0 - High Speed (default) 974 * 1 - Full Speed 975 */ 976 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 977 #define DWC2_SPEED_PARAM_HIGH 0 978 #define DWC2_SPEED_PARAM_FULL 1 979 980 /* 981 * Specifies whether low power mode is supported when attached 982 * to a Full Speed or Low Speed device in host mode. 983 * 984 * 0 - Don't support low power mode (default) 985 * 1 - Support low power mode 986 */ 987 extern void dwc2_set_param_host_support_fs_ls_low_power( 988 struct dwc2_hsotg *hsotg, int val); 989 990 /* 991 * Specifies the PHY clock rate in low power mode when connected to a 992 * Low Speed device in host mode. This parameter is applicable only if 993 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 994 * then defaults to 6 MHZ otherwise 48 MHZ. 995 * 996 * 0 - 48 MHz 997 * 1 - 6 MHz 998 */ 999 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 1000 int val); 1001 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 1002 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 1003 1004 /* 1005 * 0 - Use cC FIFO size parameters 1006 * 1 - Allow dynamic FIFO sizing (default) 1007 */ 1008 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 1009 int val); 1010 1011 /* 1012 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 1013 * FIFO sizing is enabled. 1014 * 16 to 32768 (default 1024) 1015 */ 1016 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 1017 1018 /* 1019 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 1020 * when Dynamic FIFO sizing is enabled in the core. 1021 * 16 to 32768 (default 256) 1022 */ 1023 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1024 int val); 1025 1026 /* 1027 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 1028 * FIFO sizing is enabled. 1029 * 16 to 32768 (default 256) 1030 */ 1031 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1032 int val); 1033 1034 /* 1035 * The maximum transfer size supported in bytes. 1036 * 2047 to 65,535 (default 65,535) 1037 */ 1038 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 1039 1040 /* 1041 * The maximum number of packets in a transfer. 1042 * 15 to 511 (default 511) 1043 */ 1044 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 1045 1046 /* 1047 * The number of host channel registers to use. 1048 * 1 to 16 (default 11) 1049 * Note: The FPGA configuration supports a maximum of 11 host channels. 1050 */ 1051 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 1052 1053 /* 1054 * Specifies the type of PHY interface to use. By default, the driver 1055 * will automatically detect the phy_type. 1056 * 1057 * 0 - Full Speed PHY 1058 * 1 - UTMI+ (default) 1059 * 2 - ULPI 1060 */ 1061 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 1062 #define DWC2_PHY_TYPE_PARAM_FS 0 1063 #define DWC2_PHY_TYPE_PARAM_UTMI 1 1064 #define DWC2_PHY_TYPE_PARAM_ULPI 2 1065 1066 /* 1067 * Specifies the UTMI+ Data Width. This parameter is 1068 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 1069 * PHY_TYPE, this parameter indicates the data width between 1070 * the MAC and the ULPI Wrapper.) Also, this parameter is 1071 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 1072 * to "8 and 16 bits", meaning that the core has been 1073 * configured to work at either data path width. 1074 * 1075 * 8 or 16 bits (default 16) 1076 */ 1077 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 1078 1079 /* 1080 * Specifies whether the ULPI operates at double or single 1081 * data rate. This parameter is only applicable if PHY_TYPE is 1082 * ULPI. 1083 * 1084 * 0 - single data rate ULPI interface with 8 bit wide data 1085 * bus (default) 1086 * 1 - double data rate ULPI interface with 4 bit wide data 1087 * bus 1088 */ 1089 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 1090 1091 /* 1092 * Specifies whether to use the internal or external supply to 1093 * drive the vbus with a ULPI phy. 1094 */ 1095 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 1096 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 1097 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 1098 1099 /* 1100 * Specifies whether to use the I2Cinterface for full speed PHY. This 1101 * parameter is only applicable if PHY_TYPE is FS. 1102 * 0 - No (default) 1103 * 1 - Yes 1104 */ 1105 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 1106 1107 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 1108 1109 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 1110 1111 /* 1112 * Specifies whether dedicated transmit FIFOs are 1113 * enabled for non periodic IN endpoints in device mode 1114 * 0 - No 1115 * 1 - Yes 1116 */ 1117 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 1118 int val); 1119 1120 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 1121 1122 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 1123 1124 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 1125 1126 extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 1127 const struct dwc2_core_params *params); 1128 1129 extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); 1130 1131 extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1132 1133 extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1134 extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1135 1136 /* 1137 * The following functions check the controller's OTG operation mode 1138 * capability (GHWCFG2.OTG_MODE). 1139 * 1140 * These functions can be used before the internal hsotg->hw_params 1141 * are read in and cached so they always read directly from the 1142 * GHWCFG2 register. 1143 */ 1144 unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg); 1145 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 1146 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 1147 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 1148 1149 /* 1150 * Returns the mode of operation, host or device 1151 */ 1152 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1153 { 1154 return (DWC2_READ_4(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1155 } 1156 1157 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1158 { 1159 return (DWC2_READ_4(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1160 } 1161 1162 /* 1163 * Dump core registers and SPRAM 1164 */ 1165 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1166 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1167 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1168 1169 /* 1170 * Return OTG version - either 1.3 or 2.0 1171 */ 1172 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 1173 1174 /* Gadget defines */ 1175 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1176 extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1177 extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1178 extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1179 extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 1180 extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1181 bool reset); 1182 extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1183 extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1184 extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1185 #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1186 #else 1187 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1188 { return 0; } 1189 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1190 { return 0; } 1191 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1192 { return 0; } 1193 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1194 { return 0; } 1195 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1196 bool reset) {} 1197 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1198 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1199 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1200 int testmode) 1201 { return 0; } 1202 #define dwc2_is_device_connected(hsotg) (0) 1203 #endif 1204 1205 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1206 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1207 extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 1208 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1209 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1210 #else 1211 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1212 { return 0; } 1213 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 1214 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1215 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1216 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1217 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 1218 { return 0; } 1219 #endif 1220 1221 #endif /* __DWC2_CORE_H__ */ 1222