1 /* $OpenBSD: dwc2_core.h,v 1.12 2022/09/04 08:42:39 mglocker Exp $ */ 2 /* $NetBSD: dwc2_core.h,v 1.5 2014/04/03 06:34:58 skrll Exp $ */ 3 4 /* 5 * core.h - DesignWare HS OTG Controller common declarations 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef __DWC2_CORE_H__ 41 #define __DWC2_CORE_H__ 42 43 #include <sys/stdint.h> 44 #include <sys/task.h> 45 #include <sys/pool.h> 46 #include <sys/queue.h> 47 #include <sys/device.h> 48 49 #include <machine/intr.h> 50 #include <machine/bus.h> 51 52 #include <dev/usb/dwc2/dwc2_hw.h> 53 54 #include <dev/usb/dwc2/list.h> 55 56 /* 57 * Suggested defines for tracers: 58 * - no_printk: Disable tracing 59 * - pr_info: Print this info to the console 60 * - trace_printk: Print this info to trace buffer (good for verbose logging) 61 */ 62 63 #ifdef DWC2_DEBUG 64 /* Detailed scheduler tracing, but won't overwhelm console */ 65 #define dwc2_sch_dbg(hsotg,fmt,...) do { \ 66 if (dwc2debug >= 1) { \ 67 printf("%s: " fmt, device_xname(hsotg->dev), \ 68 ## __VA_ARGS__); \ 69 } \ 70 } while (0) 71 72 /* Verbose scheduler tracing */ 73 #define dwc2_sch_vdbg(hsotg,fmt,...) do { \ 74 if (dwc2debug >= 2) { \ 75 printf("%s: " fmt, device_xname(hsotg->dev), \ 76 ## __VA_ARGS__); \ 77 } \ 78 } while (0) 79 #else 80 #define dwc2_sch_dbg(...) do { } while (0) 81 #define dwc2_sch_vdbg(...) do { } while (0) 82 #endif 83 84 /* Maximum number of Endpoints/HostChannels */ 85 #define MAX_EPS_CHANNELS 16 86 87 #if 0 88 /* dwc2-hsotg declarations */ 89 STATIC const char * const dwc2_hsotg_supply_names[] = { 90 "vusb_d", /* digital USB supply, 1.2V */ 91 "vusb_a", /* analog USB supply, 1.1V */ 92 }; 93 94 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) 95 #endif 96 97 /* 98 * EP0_MPS_LIMIT 99 * 100 * Unfortunately there seems to be a limit of the amount of data that can 101 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 102 * packets (which practically means 1 packet and 63 bytes of data) when the 103 * MPS is set to 64. 104 * 105 * This means if we are wanting to move >127 bytes of data, we need to 106 * split the transactions up, but just doing one packet at a time does 107 * not work (this may be an implicit DATA0 PID on first packet of the 108 * transaction) and doing 2 packets is outside the controller's limits. 109 * 110 * If we try to lower the MPS size for EP0, then no transfers work properly 111 * for EP0, and the system will fail basic enumeration. As no cause for this 112 * has currently been found, we cannot support any large IN transfers for 113 * EP0. 114 */ 115 #define EP0_MPS_LIMIT 64 116 117 struct dwc2_hsotg; 118 struct dwc2_hsotg_req; 119 120 /** 121 * struct dwc2_hsotg_ep - driver endpoint definition. 122 * @ep: The gadget layer representation of the endpoint. 123 * @name: The driver generated name for the endpoint. 124 * @queue: Queue of requests for this endpoint. 125 * @parent: Reference back to the parent device structure. 126 * @req: The current request that the endpoint is processing. This is 127 * used to indicate an request has been loaded onto the endpoint 128 * and has yet to be completed (maybe due to data move, or simply 129 * awaiting an ack from the core all the data has been completed). 130 * @debugfs: File entry for debugfs file for this endpoint. 131 * @dir_in: Set to true if this endpoint is of the IN direction, which 132 * means that it is sending data to the Host. 133 * @map_dir: Set to the value of dir_in when the DMA buffer is mapped. 134 * @index: The index for the endpoint registers. 135 * @mc: Multi Count - number of transactions per microframe 136 * @interval: Interval for periodic endpoints, in frames or microframes. 137 * @name: The name array passed to the USB core. 138 * @halted: Set if the endpoint has been halted. 139 * @periodic: Set if this is a periodic ep, such as Interrupt 140 * @isochronous: Set if this is a isochronous ep 141 * @send_zlp: Set if we need to send a zero-length packet. 142 * @wedged: Set if ep is wedged. 143 * @desc_list_dma: The DMA address of descriptor chain currently in use. 144 * @desc_list: Pointer to descriptor DMA chain head currently in use. 145 * @desc_count: Count of entries within the DMA descriptor chain of EP. 146 * @next_desc: index of next free descriptor in the ISOC chain under SW control. 147 * @compl_desc: index of next descriptor to be completed by xFerComplete 148 * @total_data: The total number of data bytes done. 149 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 150 * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0. 151 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 152 * @last_load: The offset of data for the last start of request. 153 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 154 * @target_frame: Targeted frame num to setup next ISOC transfer 155 * @frame_overrun: Indicates SOF number overrun in DSTS 156 * 157 * This is the driver's state for each registered endpoint, allowing it 158 * to keep track of transactions that need doing. Each endpoint has a 159 * lock to protect the state, to try and avoid using an overall lock 160 * for the host controller as much as possible. 161 * 162 * For periodic IN endpoints, we have fifo_size and fifo_load to try 163 * and keep track of the amount of data in the periodic FIFO for each 164 * of these as we don't have a status register that tells us how much 165 * is in each of them. (note, this may actually be useless information 166 * as in shared-fifo mode periodic in acts like a single-frame packet 167 * buffer than a fifo) 168 */ 169 struct dwc2_hsotg_ep { 170 // struct usb_ep ep; 171 struct list_head queue; 172 struct dwc2_hsotg *parent; 173 struct dwc2_hsotg_req *req; 174 struct dentry *debugfs; 175 176 unsigned long total_data; 177 unsigned int size_loaded; 178 unsigned int last_load; 179 unsigned int fifo_load; 180 unsigned short fifo_size; 181 unsigned short fifo_index; 182 183 unsigned char dir_in; 184 unsigned char map_dir; 185 unsigned char index; 186 unsigned char mc; 187 u16 interval; 188 189 unsigned int halted:1; 190 unsigned int periodic:1; 191 unsigned int isochronous:1; 192 unsigned int send_zlp:1; 193 unsigned int wedged:1; 194 unsigned int target_frame; 195 #define TARGET_FRAME_INITIAL 0xFFFFFFFF 196 bool frame_overrun; 197 198 // dma_addr_t desc_list_dma; 199 struct dwc2_dma_desc *desc_list; 200 u8 desc_count; 201 202 unsigned int next_desc; 203 unsigned int compl_desc; 204 205 char name[10]; 206 }; 207 208 /** 209 * struct dwc2_hsotg_req - data transfer request 210 * @req: The USB gadget request 211 * @queue: The list of requests for the endpoint this is queued for. 212 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 213 */ 214 struct dwc2_hsotg_req { 215 // struct usb_request req; 216 struct list_head queue; 217 void *saved_req_buf; 218 }; 219 220 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 221 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 222 #define call_gadget(_hs, _entry) \ 223 do { \ 224 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 225 (_hs)->driver && (_hs)->driver->_entry) { \ 226 spin_unlock(&_hs->lock); \ 227 (_hs)->driver->_entry(&(_hs)->gadget); \ 228 spin_lock(&_hs->lock); \ 229 } \ 230 } while (0) 231 #else 232 #define call_gadget(_hs, _entry) do {} while (0) 233 #endif 234 235 struct dwc2_hsotg; 236 struct dwc2_host_chan; 237 238 /* Device States */ 239 enum dwc2_lx_state { 240 DWC2_L0, /* On state */ 241 DWC2_L1, /* LPM sleep state */ 242 DWC2_L2, /* USB suspend state */ 243 DWC2_L3, /* Off state */ 244 }; 245 246 /* Gadget ep0 states */ 247 enum dwc2_ep0_state { 248 DWC2_EP0_SETUP, 249 DWC2_EP0_DATA_IN, 250 DWC2_EP0_DATA_OUT, 251 DWC2_EP0_STATUS_IN, 252 DWC2_EP0_STATUS_OUT, 253 }; 254 255 /** XXX: From Linux USB stack. 256 * struct usb_otg_caps - describes the otg capabilities of the device 257 * @otg_rev: The OTG revision number the device is compliant with, it's 258 * in binary-coded decimal (i.e. 2.0 is 0200H). 259 * @hnp_support: Indicates if the device supports HNP. 260 * @srp_support: Indicates if the device supports SRP. 261 * @adp_support: Indicates if the device supports ADP. 262 */ 263 struct usb_otg_caps { 264 u16 otg_rev; 265 bool hnp_support; 266 bool srp_support; 267 bool adp_support; 268 }; 269 270 /** 271 * struct dwc2_core_params - Parameters for configuring the core 272 * 273 * @otg_caps: Specifies the OTG capabilities. OTG caps from the platform parameters, 274 * used to setup the: 275 * - HNP and SRP capable 276 * - SRP Only capable 277 * - No HNP/SRP capable (always available) 278 * Defaults to best available option 279 * - OTG revision number the device is compliant with, in binary-coded 280 * decimal (i.e. 2.0 is 0200H). (see struct usb_otg_caps) 281 * @host_dma: Specifies whether to use slave or DMA mode for accessing 282 * the data FIFOs. The driver will automatically detect the 283 * value for this parameter if none is specified. 284 * 0 - Slave (always available) 285 * 1 - DMA (default, if available) 286 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 287 * address DMA mode or descriptor DMA mode for accessing 288 * the data FIFOs. The driver will automatically detect the 289 * value for this if none is specified. 290 * 0 - Address DMA 291 * 1 - Descriptor DMA (default, if available) 292 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 293 * address DMA mode or descriptor DMA mode for accessing 294 * the data FIFOs in Full Speed mode only. The driver 295 * will automatically detect the value for this if none is 296 * specified. 297 * 0 - Address DMA 298 * 1 - Descriptor DMA in FS (default, if available) 299 * @speed: Specifies the maximum speed of operation in host and 300 * device mode. The actual speed depends on the speed of 301 * the attached device and the value of phy_type. 302 * 0 - High Speed 303 * (default when phy_type is UTMI+ or ULPI) 304 * 1 - Full Speed 305 * (default when phy_type is Full Speed) 306 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 307 * 1 - Allow dynamic FIFO sizing (default, if available) 308 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 309 * are enabled for non-periodic IN endpoints in device 310 * mode. 311 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 312 * dynamic FIFO sizing is enabled 313 * 16 to 32768 314 * Actual maximum value is autodetected and also 315 * the default. 316 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 317 * in host mode when dynamic FIFO sizing is enabled 318 * 16 to 32768 319 * Actual maximum value is autodetected and also 320 * the default. 321 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 322 * host mode when dynamic FIFO sizing is enabled 323 * 16 to 32768 324 * Actual maximum value is autodetected and also 325 * the default. 326 * @max_transfer_size: The maximum transfer size supported, in bytes 327 * 2047 to 65,535 328 * Actual maximum value is autodetected and also 329 * the default. 330 * @max_packet_count: The maximum number of packets in a transfer 331 * 15 to 511 332 * Actual maximum value is autodetected and also 333 * the default. 334 * @host_channels: The number of host channel registers to use 335 * 1 to 16 336 * Actual maximum value is autodetected and also 337 * the default. 338 * @phy_type: Specifies the type of PHY interface to use. By default, 339 * the driver will automatically detect the phy_type. 340 * 0 - Full Speed Phy 341 * 1 - UTMI+ Phy 342 * 2 - ULPI Phy 343 * Defaults to best available option (2, 1, then 0) 344 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 345 * is applicable for a phy_type of UTMI+ or ULPI. (For a 346 * ULPI phy_type, this parameter indicates the data width 347 * between the MAC and the ULPI Wrapper.) Also, this 348 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 349 * parameter was set to "8 and 16 bits", meaning that the 350 * core has been configured to work at either data path 351 * width. 352 * 8 or 16 (default 16 if available) 353 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 354 * data rate. This parameter is only applicable if phy_type 355 * is ULPI. 356 * 0 - single data rate ULPI interface with 8 bit wide 357 * data bus (default) 358 * 1 - double data rate ULPI interface with 4 bit wide 359 * data bus 360 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 361 * external supply to drive the VBus 362 * 0 - Internal supply (default) 363 * 1 - External supply 364 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 365 * speed PHY. This parameter is only applicable if phy_type 366 * is FS. 367 * 0 - No (default) 368 * 1 - Yes 369 * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled. 370 * 0 - Disable (default) 371 * 1 - Enable 372 * @acg_enable: For enabling Active Clock Gating in the controller 373 * 0 - No 374 * 1 - Yes 375 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 376 * 0 - No (default) 377 * 1 - Yes 378 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 379 * when attached to a Full Speed or Low Speed device in 380 * host mode. 381 * 0 - Don't support low power mode (default) 382 * 1 - Support low power mode 383 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 384 * when connected to a Low Speed device in host 385 * mode. This parameter is applicable only if 386 * host_support_fs_ls_low_power is enabled. 387 * 0 - 48 MHz 388 * (default when phy_type is UTMI+ or ULPI) 389 * 1 - 6 MHz 390 * (default when phy_type is Full Speed) 391 * @oc_disable: Flag to disable overcurrent condition. 392 * 0 - Allow overcurrent condition to get detected 393 * 1 - Disable overcurrent condtion to get detected 394 * @ts_dline: Enable Term Select Dline pulsing 395 * 0 - No (default) 396 * 1 - Yes 397 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 398 * 0 - No (default for core < 2.92a) 399 * 1 - Yes (default for core >= 2.92a) 400 * @ahbcfg: This field allows the default value of the GAHBCFG 401 * register to be overridden 402 * -1 - GAHBCFG value will be set to 0x06 403 * (INCR, default) 404 * all others - GAHBCFG value will be overridden with 405 * this value 406 * Not all bits can be controlled like this, the 407 * bits defined by GAHBCFG_CTRL_MASK are controlled 408 * by the driver and are ignored in this 409 * configuration value. 410 * @uframe_sched: True to enable the microframe scheduler 411 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 412 * Disable CONIDSTSCHNG controller interrupt in such 413 * case. 414 * 0 - No (default) 415 * 1 - Yes 416 * @power_down: Specifies whether the controller support power_down. 417 * If power_down is enabled, the controller will enter 418 * power_down in both peripheral and host mode when 419 * needed. 420 * 0 - No (default) 421 * 1 - Partial power down 422 * 2 - Hibernation 423 * @no_clock_gating: Specifies whether to avoid clock gating feature. 424 * 0 - No (use clock gating) 425 * 1 - Yes (avoid it) 426 * @lpm: Enable LPM support. 427 * 0 - No 428 * 1 - Yes 429 * @lpm_clock_gating: Enable core PHY clock gating. 430 * 0 - No 431 * 1 - Yes 432 * @besl: Enable LPM Errata support. 433 * 0 - No 434 * 1 - Yes 435 * @hird_threshold_en: HIRD or HIRD Threshold enable. 436 * 0 - No 437 * 1 - Yes 438 * @hird_threshold: Value of BESL or HIRD Threshold. 439 * @ref_clk_per: Indicates in terms of pico seconds the period 440 * of ref_clk. 441 * 62500 - 16MHz 442 * 58823 - 17MHz 443 * 52083 - 19.2MHz 444 * 50000 - 20MHz 445 * 41666 - 24MHz 446 * 33333 - 30MHz (default) 447 * 25000 - 40MHz 448 * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which 449 * the controller should generate an interrupt if the 450 * device had been in L1 state until that period. 451 * This is used by SW to initiate Remote WakeUp in the 452 * controller so as to sync to the uF number from the host. 453 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO 454 * register. 455 * 0 - Deactivate the transceiver (default) 456 * 1 - Activate the transceiver 457 * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level 458 * detection using GGPIO register. 459 * 0 - Deactivate the external level detection (default) 460 * 1 - Activate the external level detection 461 * @activate_ingenic_overcurrent_detection: Activate Ingenic overcurrent 462 * detection. 463 * 0 - Deactivate the overcurrent detection 464 * 1 - Activate the overcurrent detection (default) 465 * @g_dma: Enables gadget dma usage (default: autodetect). 466 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). 467 * @g_rx_fifo_size: The periodic rx fifo size for the device, in 468 * DWORDS from 16-32768 (default: 2048 if 469 * possible, otherwise autodetect). 470 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in 471 * DWORDS from 16-32768 (default: 1024 if 472 * possible, otherwise autodetect). 473 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo 474 * mode. Each value corresponds to one EP 475 * starting from EP1 (max 15 values). Sizes are 476 * in DWORDS with possible values from 477 * 16-32768 (default: 256, 256, 256, 256, 768, 478 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). 479 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL 480 * while full&low speed device connect. And change speed 481 * back to DWC2_SPEED_PARAM_HIGH while device is gone. 482 * 0 - No (default) 483 * 1 - Yes 484 * @service_interval: Enable service interval based scheduling. 485 * 0 - No 486 * 1 - Yes 487 * 488 * The following parameters may be specified when starting the module. These 489 * parameters define how the DWC_otg controller should be configured. A 490 * value of -1 (or any other out of range value) for any parameter means 491 * to read the value from hardware (if possible) or use the builtin 492 * default described above. 493 */ 494 struct dwc2_core_params { 495 struct usb_otg_caps otg_caps; 496 u8 phy_type; 497 #define DWC2_PHY_TYPE_PARAM_FS 0 498 #define DWC2_PHY_TYPE_PARAM_UTMI 1 499 #define DWC2_PHY_TYPE_PARAM_ULPI 2 500 501 u8 speed; 502 #define DWC2_SPEED_PARAM_HIGH 0 503 #define DWC2_SPEED_PARAM_FULL 1 504 #define DWC2_SPEED_PARAM_LOW 2 505 506 u8 phy_utmi_width; 507 bool phy_ulpi_ddr; 508 bool phy_ulpi_ext_vbus; 509 bool enable_dynamic_fifo; 510 bool en_multiple_tx_fifo; 511 bool i2c_enable; 512 bool acg_enable; 513 bool ulpi_fs_ls; 514 bool ts_dline; 515 bool reload_ctl; 516 bool uframe_sched; 517 bool external_id_pin_ctl; 518 519 int power_down; 520 #define DWC2_POWER_DOWN_PARAM_NONE 0 521 #define DWC2_POWER_DOWN_PARAM_PARTIAL 1 522 #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2 523 bool no_clock_gating; 524 525 bool lpm; 526 bool lpm_clock_gating; 527 bool besl; 528 bool hird_threshold_en; 529 bool service_interval; 530 u8 hird_threshold; 531 bool activate_stm_fs_transceiver; 532 bool activate_stm_id_vb_detection; 533 bool activate_ingenic_overcurrent_detection; 534 bool ipg_isoc_en; 535 u16 max_packet_count; 536 u32 max_transfer_size; 537 u32 ahbcfg; 538 539 /* GREFCLK parameters */ 540 u32 ref_clk_per; 541 u16 sof_cnt_wkup_alert; 542 543 /* Host parameters */ 544 bool host_dma; 545 bool dma_desc_enable; 546 bool dma_desc_fs_enable; 547 bool host_support_fs_ls_low_power; 548 bool host_ls_low_power_phy_clk; 549 bool oc_disable; 550 551 u8 host_channels; 552 u16 host_rx_fifo_size; 553 u16 host_nperio_tx_fifo_size; 554 u16 host_perio_tx_fifo_size; 555 556 /* Gadget parameters */ 557 bool g_dma; 558 bool g_dma_desc; 559 u32 g_rx_fifo_size; 560 u32 g_np_tx_fifo_size; 561 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 562 563 bool change_speed_quirk; 564 }; 565 566 /** 567 * struct dwc2_hw_params - Autodetected parameters. 568 * 569 * These parameters are the various parameters read from hardware 570 * registers during initialization. They typically contain the best 571 * supported or maximum value that can be configured in the 572 * corresponding dwc2_core_params value. 573 * 574 * The values that are not in dwc2_core_params are documented below. 575 * 576 * @op_mode: Mode of Operation 577 * 0 - HNP- and SRP-Capable OTG (Host & Device) 578 * 1 - SRP-Capable OTG (Host & Device) 579 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 580 * 3 - SRP-Capable Device 581 * 4 - Non-OTG Device 582 * 5 - SRP-Capable Host 583 * 6 - Non-OTG Host 584 * @arch: Architecture 585 * 0 - Slave only 586 * 1 - External DMA 587 * 2 - Internal DMA 588 * @ipg_isoc_en: This feature indicates that the controller supports 589 * the worst-case scenario of Rx followed by Rx 590 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi 591 * specification for any token following ISOC OUT token. 592 * 0 - Don't support 593 * 1 - Support 594 * @power_optimized: Are power optimizations enabled? 595 * @num_dev_ep: Number of device endpoints available 596 * @num_dev_in_eps: Number of device IN endpoints available 597 * @num_dev_perio_in_ep: Number of device periodic IN endpoints 598 * available 599 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue 600 * Depth 601 * 0 to 30 602 * @host_perio_tx_q_depth: 603 * Host Mode Periodic Request Queue Depth 604 * 2, 4 or 8 605 * @nperio_tx_q_depth: 606 * Non-Periodic Request Queue Depth 607 * 2, 4 or 8 608 * @hs_phy_type: High-speed PHY interface type 609 * 0 - High-speed interface not supported 610 * 1 - UTMI+ 611 * 2 - ULPI 612 * 3 - UTMI+ and ULPI 613 * @fs_phy_type: Full-speed PHY interface type 614 * 0 - Full speed interface not supported 615 * 1 - Dedicated full speed interface 616 * 2 - FS pins shared with UTMI+ pins 617 * 3 - FS pins shared with ULPI pins 618 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 619 * @hibernation: Is hibernation enabled? 620 * @utmi_phy_data_width: UTMI+ PHY data width 621 * 0 - 8 bits 622 * 1 - 16 bits 623 * 2 - 8 or 16 bits 624 * @snpsid: Value from SNPSID register 625 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 626 * @g_tx_fifo_size: Power-on values of TxFIFO sizes 627 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 628 * address DMA mode or descriptor DMA mode for accessing 629 * the data FIFOs. The driver will automatically detect the 630 * value for this if none is specified. 631 * 0 - Address DMA 632 * 1 - Descriptor DMA (default, if available) 633 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 634 * 1 - Allow dynamic FIFO sizing (default, if available) 635 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 636 * are enabled for non-periodic IN endpoints in device 637 * mode. 638 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 639 * in host mode when dynamic FIFO sizing is enabled 640 * 16 to 32768 641 * Actual maximum value is autodetected and also 642 * the default. 643 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 644 * host mode when dynamic FIFO sizing is enabled 645 * 16 to 32768 646 * Actual maximum value is autodetected and also 647 * the default. 648 * @max_transfer_size: The maximum transfer size supported, in bytes 649 * 2047 to 65,535 650 * Actual maximum value is autodetected and also 651 * the default. 652 * @max_packet_count: The maximum number of packets in a transfer 653 * 15 to 511 654 * Actual maximum value is autodetected and also 655 * the default. 656 * @host_channels: The number of host channel registers to use 657 * 1 to 16 658 * Actual maximum value is autodetected and also 659 * the default. 660 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 661 * in device mode when dynamic FIFO sizing is enabled 662 * 16 to 32768 663 * Actual maximum value is autodetected and also 664 * the default. 665 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 666 * speed PHY. This parameter is only applicable if phy_type 667 * is FS. 668 * 0 - No (default) 669 * 1 - Yes 670 * @acg_enable: For enabling Active Clock Gating in the controller 671 * 0 - Disable 672 * 1 - Enable 673 * @lpm_mode: For enabling Link Power Management in the controller 674 * 0 - Disable 675 * 1 - Enable 676 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic 677 * FIFO sizing is enabled 16 to 32768 678 * Actual maximum value is autodetected and also 679 * the default. 680 * @service_interval_mode: For enabling service interval based scheduling in the 681 * controller. 682 * 0 - Disable 683 * 1 - Enable 684 */ 685 struct dwc2_hw_params { 686 unsigned op_mode:3; 687 unsigned arch:2; 688 unsigned dma_desc_enable:1; 689 unsigned enable_dynamic_fifo:1; 690 unsigned en_multiple_tx_fifo:1; 691 unsigned rx_fifo_size:16; 692 unsigned host_nperio_tx_fifo_size:16; 693 unsigned dev_nperio_tx_fifo_size:16; 694 unsigned host_perio_tx_fifo_size:16; 695 unsigned nperio_tx_q_depth:3; 696 unsigned host_perio_tx_q_depth:3; 697 unsigned dev_token_q_depth:5; 698 unsigned max_transfer_size:26; 699 unsigned max_packet_count:11; 700 unsigned host_channels:5; 701 unsigned hs_phy_type:2; 702 unsigned fs_phy_type:2; 703 unsigned i2c_enable:1; 704 unsigned acg_enable:1; 705 unsigned num_dev_ep:4; 706 unsigned num_dev_in_eps : 4; 707 unsigned num_dev_perio_in_ep:4; 708 unsigned total_fifo_size:16; 709 unsigned power_optimized:1; 710 unsigned hibernation:1; 711 unsigned utmi_phy_data_width:2; 712 unsigned lpm_mode:1; 713 unsigned ipg_isoc_en:1; 714 unsigned service_interval_mode:1; 715 u32 snpsid; 716 u32 dev_ep_dirs; 717 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 718 }; 719 720 /* Size of control and EP0 buffers */ 721 #define DWC2_CTRL_BUFF_SIZE 8 722 723 /** 724 * struct dwc2_gregs_backup - Holds global registers state before 725 * entering partial power down 726 * @gotgctl: Backup of GOTGCTL register 727 * @gintmsk: Backup of GINTMSK register 728 * @gahbcfg: Backup of GAHBCFG register 729 * @gusbcfg: Backup of GUSBCFG register 730 * @grxfsiz: Backup of GRXFSIZ register 731 * @gnptxfsiz: Backup of GNPTXFSIZ register 732 * @gi2cctl: Backup of GI2CCTL register 733 * @glpmcfg: Backup of GLPMCFG register 734 * @gdfifocfg: Backup of GDFIFOCFG register 735 * @pcgcctl: Backup of PCGCCTL register 736 * @pcgcctl1: Backup of PCGCCTL1 register 737 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 738 * @gpwrdn: Backup of GPWRDN register 739 * @valid: True if registers values backuped. 740 */ 741 struct dwc2_gregs_backup { 742 u32 gotgctl; 743 u32 gintmsk; 744 u32 gahbcfg; 745 u32 gusbcfg; 746 u32 grxfsiz; 747 u32 gnptxfsiz; 748 u32 gi2cctl; 749 u32 glpmcfg; 750 u32 pcgcctl; 751 u32 pcgcctl1; 752 u32 gdfifocfg; 753 u32 gpwrdn; 754 bool valid; 755 }; 756 757 /** 758 * struct dwc2_dregs_backup - Holds device registers state before 759 * entering partial power down 760 * @dcfg: Backup of DCFG register 761 * @dctl: Backup of DCTL register 762 * @daintmsk: Backup of DAINTMSK register 763 * @diepmsk: Backup of DIEPMSK register 764 * @doepmsk: Backup of DOEPMSK register 765 * @diepctl: Backup of DIEPCTL register 766 * @dieptsiz: Backup of DIEPTSIZ register 767 * @diepdma: Backup of DIEPDMA register 768 * @doepctl: Backup of DOEPCTL register 769 * @doeptsiz: Backup of DOEPTSIZ register 770 * @doepdma: Backup of DOEPDMA register 771 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 772 * @valid: True if registers values backuped. 773 */ 774 struct dwc2_dregs_backup { 775 u32 dcfg; 776 u32 dctl; 777 u32 daintmsk; 778 u32 diepmsk; 779 u32 doepmsk; 780 u32 diepctl[MAX_EPS_CHANNELS]; 781 u32 dieptsiz[MAX_EPS_CHANNELS]; 782 u32 diepdma[MAX_EPS_CHANNELS]; 783 u32 doepctl[MAX_EPS_CHANNELS]; 784 u32 doeptsiz[MAX_EPS_CHANNELS]; 785 u32 doepdma[MAX_EPS_CHANNELS]; 786 u32 dtxfsiz[MAX_EPS_CHANNELS]; 787 bool valid; 788 }; 789 790 /** 791 * struct dwc2_hregs_backup - Holds host registers state before 792 * entering partial power down 793 * @hcfg: Backup of HCFG register 794 * @haintmsk: Backup of HAINTMSK register 795 * @hcintmsk: Backup of HCINTMSK register 796 * @hprt0: Backup of HPTR0 register 797 * @hfir: Backup of HFIR register 798 * @hptxfsiz: Backup of HPTXFSIZ register 799 * @valid: True if registers values backuped. 800 */ 801 struct dwc2_hregs_backup { 802 u32 hcfg; 803 u32 haintmsk; 804 u32 hcintmsk[MAX_EPS_CHANNELS]; 805 u32 hprt0; 806 u32 hfir; 807 u32 hptxfsiz; 808 bool valid; 809 }; 810 811 /* 812 * Constants related to high speed periodic scheduling 813 * 814 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 815 * reservation point of view it's assumed that the schedule goes right back to 816 * the beginning after the end of the schedule. 817 * 818 * What does that mean for scheduling things with a long interval? It means 819 * we'll reserve time for them in every possible microframe that they could 820 * ever be scheduled in. ...but we'll still only actually schedule them as 821 * often as they were requested. 822 * 823 * We keep our schedule in a "bitmap" structure. This simplifies having 824 * to keep track of and merge intervals: we just let the bitmap code do most 825 * of the heavy lifting. In a way scheduling is much like memory allocation. 826 * 827 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 828 * supposed to schedule for periodic transfers). That's according to spec. 829 * 830 * Note that though we only schedule 80% of each microframe, the bitmap that we 831 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 832 * space for each uFrame). 833 * 834 * Requirements: 835 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 836 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 837 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 838 * be bugs). The 8 comes from the USB spec: number of microframes per frame. 839 */ 840 #define DWC2_US_PER_UFRAME 125 841 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 842 843 #define DWC2_HS_SCHEDULE_UFRAMES 8 844 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 845 DWC2_HS_PERIODIC_US_PER_UFRAME) 846 847 /* 848 * Constants related to low speed scheduling 849 * 850 * For high speed we schedule every 1us. For low speed that's a bit overkill, 851 * so we make up a unit called a "slice" that's worth 25us. There are 40 852 * slices in a full frame and we can schedule 36 of those (90%) for periodic 853 * transfers. 854 * 855 * Our low speed schedule can be as short as 1 frame or could be longer. When 856 * we only schedule 1 frame it means that we'll need to reserve a time every 857 * frame even for things that only transfer very rarely, so something that runs 858 * every 2048 frames will get time reserved in every frame. Our low speed 859 * schedule can be longer and we'll be able to handle more overlap, but that 860 * will come at increased memory cost and increased time to schedule. 861 * 862 * Note: one other advantage of a short low speed schedule is that if we mess 863 * up and miss scheduling we can jump in and use any of the slots that we 864 * happened to reserve. 865 * 866 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 867 * the schedule. There will be one schedule per TT. 868 * 869 * Requirements: 870 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 871 */ 872 #define DWC2_US_PER_SLICE 25 873 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 874 875 #define DWC2_ROUND_US_TO_SLICE(us) \ 876 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 877 DWC2_US_PER_SLICE) 878 879 #define DWC2_LS_PERIODIC_US_PER_FRAME \ 880 900 881 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 882 (DWC2_LS_PERIODIC_US_PER_FRAME / \ 883 DWC2_US_PER_SLICE) 884 885 #define DWC2_LS_SCHEDULE_FRAMES 1 886 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 887 DWC2_LS_PERIODIC_SLICES_PER_FRAME) 888 889 /** 890 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 891 * and periodic schedules 892 * 893 * These are common for both host and peripheral modes: 894 * 895 * @dev: The struct device pointer 896 * @regs: Pointer to controller regs 897 * @hw_params: Parameters that were autodetected from the 898 * hardware registers 899 * @params: Parameters that define how the core should be configured 900 * @op_state: The operational State, during transitions (a_host=> 901 * a_peripheral and b_device=>b_host) this may not match 902 * the core, but allows the software to determine 903 * transitions 904 * @dr_mode: Requested mode of operation, one of following: 905 * - USB_DR_MODE_PERIPHERAL 906 * - USB_DR_MODE_HOST 907 * - USB_DR_MODE_OTG 908 * @role_sw: usb_role_switch handle 909 * @role_sw_default_mode: default operation mode of controller while usb role 910 * is USB_ROLE_NONE 911 * @hcd_enabled: Host mode sub-driver initialization indicator. 912 * @gadget_enabled: Peripheral mode sub-driver initialization indicator. 913 * @ll_hw_enabled: Status of low-level hardware resources. 914 * @hibernated: True if core is hibernated 915 * @in_ppd: True if core is partial power down mode. 916 * @bus_suspended: True if bus is suspended 917 * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a 918 * remote wakeup. 919 * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend. 920 * @need_phy_for_wake: Quirk saying that we should keep the PHY on at 921 * suspend if we need USB to wake us up. 922 * @frame_number: Frame number read from the core. For both device 923 * and host modes. The value ranges are from 0 924 * to HFNUM_MAX_FRNUM. 925 * @phy: The otg phy transceiver structure for phy control. 926 * @uphy: The otg phy transceiver structure for old USB phy 927 * control. 928 * @plat: The platform specific configuration data. This can be 929 * removed once all SoCs support usb transceiver. 930 * @supplies: Definition of USB power supplies 931 * @vbus_supply: Regulator supplying vbus. 932 * @usb33d: Optional 3.3v regulator used on some stm32 devices to 933 * supply ID and VBUS detection hardware. 934 * @lock: Spinlock that protects all the driver data structures 935 * @priv: Stores a pointer to the struct usb_hcd 936 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 937 * transfer are in process of being queued 938 * @srp_success: Stores status of SRP request in the case of a FS PHY 939 * with an I2C interface 940 * @wq_otg: Workqueue object used for handling of some interrupts 941 * @wf_otg: Work object for handling Connector ID Status Change 942 * interrupt 943 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 944 * @lx_state: Lx state of connected device 945 * @gr_backup: Backup of global registers during suspend 946 * @dr_backup: Backup of device registers during suspend 947 * @hr_backup: Backup of host registers during suspend 948 * @needs_byte_swap: Specifies whether the opposite endianness. 949 * 950 * These are for host mode: 951 * 952 * @flags: Flags for handling root port state changes 953 * @flags.d32: Contain all root port flags 954 * @flags.b: Separate root port flags from each other 955 * @flags.b.port_connect_status_change: True if root port connect status 956 * changed 957 * @flags.b.port_connect_status: True if device connected to root port 958 * @flags.b.port_reset_change: True if root port reset status changed 959 * @flags.b.port_enable_change: True if root port enable status changed 960 * @flags.b.port_suspend_change: True if root port suspend status changed 961 * @flags.b.port_over_current_change: True if root port over current state 962 * changed. 963 * @flags.b.port_l1_change: True if root port l1 status changed 964 * @flags.b.reserved: Reserved bits of root port register 965 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 966 * Transfers associated with these QHs are not currently 967 * assigned to a host channel. 968 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 969 * Transfers associated with these QHs are currently 970 * assigned to a host channel. 971 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 972 * non-periodic schedule 973 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule. 974 * Transfers associated with these QHs are not currently 975 * assigned to a host channel. 976 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 977 * list of QHs for periodic transfers that are _not_ 978 * scheduled for the next frame. Each QH in the list has an 979 * interval counter that determines when it needs to be 980 * scheduled for execution. This scheduling mechanism 981 * allows only a simple calculation for periodic bandwidth 982 * used (i.e. must assume that all periodic transfers may 983 * need to execute in the same frame). However, it greatly 984 * simplifies scheduling and should be sufficient for the 985 * vast majority of OTG hosts, which need to connect to a 986 * small number of peripherals at one time. Items move from 987 * this list to periodic_sched_ready when the QH interval 988 * counter is 0 at SOF. 989 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 990 * the next frame, but have not yet been assigned to host 991 * channels. Items move from this list to 992 * periodic_sched_assigned as host channels become 993 * available during the current frame. 994 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 995 * frame that are assigned to host channels. Items move 996 * from this list to periodic_sched_queued as the 997 * transactions for the QH are queued to the DWC_otg 998 * controller. 999 * @periodic_sched_queued: List of periodic QHs that have been queued for 1000 * execution. Items move from this list to either 1001 * periodic_sched_inactive or periodic_sched_ready when the 1002 * channel associated with the transfer is released. If the 1003 * interval for the QH is 1, the item moves to 1004 * periodic_sched_ready because it must be rescheduled for 1005 * the next frame. Otherwise, the item moves to 1006 * periodic_sched_inactive. 1007 * @split_order: List keeping track of channels doing splits, in order. 1008 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 1009 * This value is in microseconds per (micro)frame. The 1010 * assumption is that all periodic transfers may occur in 1011 * the same (micro)frame. 1012 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 1013 * host is in high speed mode; low speed schedules are 1014 * stored elsewhere since we need one per TT. 1015 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 1016 * SOF enable/disable. 1017 * @free_hc_list: Free host channels in the controller. This is a list of 1018 * struct dwc2_host_chan items. 1019 * @periodic_channels: Number of host channels assigned to periodic transfers. 1020 * Currently assuming that there is a dedicated host 1021 * channel for each periodic transaction and at least one 1022 * host channel is available for non-periodic transactions. 1023 * @non_periodic_channels: Number of host channels assigned to non-periodic 1024 * transfers 1025 * @available_host_channels: Number of host channels available for the 1026 * microframe scheduler to use 1027 * @hc_ptr_array: Array of pointers to the host channel descriptors. 1028 * Allows accessing a host channel descriptor given the 1029 * host channel number. This is useful in interrupt 1030 * handlers. 1031 * @status_buf: Buffer used for data received during the status phase of 1032 * a control transfer. 1033 * @status_buf_dma: DMA address for status_buf 1034 * @start_work: Delayed work for handling host A-cable connection 1035 * @reset_work: Delayed work for handling a port reset 1036 * @phy_reset_work: Work structure for doing a PHY reset 1037 * @otg_port: OTG port number 1038 * @frame_list: Frame list 1039 * @frame_list_dma: Frame list DMA address 1040 * @frame_list_sz: Frame list size 1041 * @desc_gen_cache: Kmem cache for generic descriptors 1042 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 1043 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf 1044 * 1045 * These are for peripheral mode: 1046 * 1047 * @driver: USB gadget driver 1048 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 1049 * @num_of_eps: Number of available EPs (excluding EP0) 1050 * @debug_root: Root directrory for debugfs. 1051 * @ep0_reply: Request used for ep0 reply. 1052 * @ep0_buff: Buffer for EP0 reply data, if needed. 1053 * @ctrl_buff: Buffer for EP0 control requests. 1054 * @ctrl_req: Request for EP0 control packets. 1055 * @ep0_state: EP0 control transfers state 1056 * @delayed_status: true when gadget driver asks for delayed status 1057 * @test_mode: USB test mode requested by the host 1058 * @remote_wakeup_allowed: True if device is allowed to wake-up host by 1059 * remote-wakeup signalling 1060 * @setup_desc_dma: EP0 setup stage desc chain DMA address 1061 * @setup_desc: EP0 setup stage desc chain pointer 1062 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address 1063 * @ctrl_in_desc: EP0 IN data phase desc chain pointer 1064 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address 1065 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer 1066 * @irq: Interrupt request line number 1067 * @clk: Pointer to otg clock 1068 * @reset: Pointer to dwc2 reset controller 1069 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10. 1070 * @regset: A pointer to a struct debugfs_regset32, which contains 1071 * a pointer to an array of register definitions, the 1072 * array size and the base address where the register bank 1073 * is to be found. 1074 * @last_frame_num: Number of last frame. Range from 0 to 32768 1075 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 1076 * defined, for missed SOFs tracking. Array holds that 1077 * frame numbers, which not equal to last_frame_num +1 1078 * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 1079 * defined, for missed SOFs tracking. 1080 * If current_frame_number != last_frame_num+1 1081 * then last_frame_num added to this array 1082 * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array 1083 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed 1084 * 0 - if missed SOFs frame numbers not dumbed 1085 * @fifo_mem: Total internal RAM for FIFOs (bytes) 1086 * @fifo_map: Each bit intend for concrete fifo. If that bit is set, 1087 * then that fifo is used 1088 * @gadget: Represents a usb gadget device 1089 * @connected: Used in slave mode. True if device connected with host 1090 * @eps_in: The IN endpoints being supplied to the gadget framework 1091 * @eps_out: The OUT endpoints being supplied to the gadget framework 1092 * @new_connection: Used in host mode. True if there are new connected 1093 * device 1094 * @enabled: Indicates the enabling state of controller 1095 * 1096 */ 1097 struct dwc2_hsotg { 1098 struct device *dev; 1099 // void __iomem *regs; 1100 struct dwc2_softc *hsotg_sc; 1101 /** Params detected from hardware */ 1102 struct dwc2_hw_params hw_params; 1103 /** Params to actually use */ 1104 struct dwc2_core_params params; 1105 enum usb_otg_state op_state; 1106 enum usb_dr_mode dr_mode; 1107 // struct usb_role_switch *role_sw; 1108 // enum usb_dr_mode role_sw_default_mode; 1109 unsigned int hcd_enabled:1; 1110 unsigned int gadget_enabled:1; 1111 unsigned int ll_hw_enabled:1; 1112 unsigned int hibernated:1; 1113 unsigned int in_ppd:1; 1114 bool bus_suspended; 1115 unsigned int reset_phy_on_wake:1; 1116 unsigned int need_phy_for_wake:1; 1117 unsigned int phy_off_for_suspend:1; 1118 u16 frame_number; 1119 1120 struct phy *phy; 1121 struct usb_phy *uphy; 1122 struct dwc2_hsotg_plat *plat; 1123 // struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; 1124 struct regulator *vbus_supply; 1125 struct regulator *usb33d; 1126 1127 spinlock_t lock; 1128 void *priv; 1129 int irq; 1130 // struct clk clk; 1131 // struct reset_control *reset; 1132 // struct reset_control *reset_ecc; 1133 1134 unsigned int queuing_high_bandwidth:1; 1135 unsigned int srp_success:1; 1136 1137 struct taskq *wq_otg; 1138 struct task wf_otg; 1139 struct timeout wkp_timer; 1140 enum dwc2_lx_state lx_state; 1141 struct dwc2_gregs_backup gr_backup; 1142 struct dwc2_dregs_backup dr_backup; 1143 struct dwc2_hregs_backup hr_backup; 1144 1145 struct dentry *debug_root; 1146 struct debugfs_regset32 *regset; 1147 bool needs_byte_swap; 1148 1149 /* DWC OTG HW Release versions */ 1150 #define DWC2_CORE_REV_2_71a 0x4f54271a 1151 #define DWC2_CORE_REV_2_72a 0x4f54272a 1152 #define DWC2_CORE_REV_2_80a 0x4f54280a 1153 #define DWC2_CORE_REV_2_90a 0x4f54290a 1154 #define DWC2_CORE_REV_2_91a 0x4f54291a 1155 #define DWC2_CORE_REV_2_92a 0x4f54292a 1156 #define DWC2_CORE_REV_2_94a 0x4f54294a 1157 #define DWC2_CORE_REV_3_00a 0x4f54300a 1158 #define DWC2_CORE_REV_3_10a 0x4f54310a 1159 #define DWC2_CORE_REV_4_00a 0x4f54400a 1160 #define DWC2_CORE_REV_4_20a 0x4f54420a 1161 #define DWC2_FS_IOT_REV_1_00a 0x5531100a 1162 #define DWC2_HS_IOT_REV_1_00a 0x5532100a 1163 #define DWC2_CORE_REV_MASK 0x0000ffff 1164 1165 /* DWC OTG HW Core ID */ 1166 #define DWC2_OTG_ID 0x4f540000 1167 #define DWC2_FS_IOT_ID 0x55310000 1168 #define DWC2_HS_IOT_ID 0x55320000 1169 1170 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1171 union dwc2_hcd_internal_flags { 1172 u32 d32; 1173 struct { 1174 unsigned port_connect_status_change:1; 1175 unsigned port_connect_status:1; 1176 unsigned port_reset_change:1; 1177 unsigned port_enable_change:1; 1178 unsigned port_suspend_change:1; 1179 unsigned port_over_current_change:1; 1180 unsigned port_l1_change:1; 1181 unsigned reserved:25; 1182 } b; 1183 } flags; 1184 1185 struct list_head non_periodic_sched_inactive; 1186 struct list_head non_periodic_sched_waiting; 1187 struct list_head non_periodic_sched_active; 1188 struct list_head *non_periodic_qh_ptr; 1189 struct list_head periodic_sched_inactive; 1190 struct list_head periodic_sched_ready; 1191 struct list_head periodic_sched_assigned; 1192 struct list_head periodic_sched_queued; 1193 struct list_head split_order; 1194 u16 periodic_usecs; 1195 unsigned long hs_periodic_bitmap[ 1196 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 1197 u16 periodic_qh_count; 1198 bool new_connection; 1199 1200 u16 last_frame_num; 1201 1202 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 1203 #define FRAME_NUM_ARRAY_SIZE 1000 1204 u16 *frame_num_array; 1205 u16 *last_frame_num_array; 1206 int frame_num_idx; 1207 int dumped_frame_num_array; 1208 #endif 1209 1210 struct list_head free_hc_list; 1211 int periodic_channels; 1212 int non_periodic_channels; 1213 int available_host_channels; 1214 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 1215 u8 *status_buf; 1216 struct usb_dma status_buf_dma_usb; 1217 dma_addr_t status_buf_dma; 1218 #define DWC2_HCD_STATUS_BUF_SIZE 64 1219 1220 struct delayed_work start_work; 1221 struct delayed_work reset_work; 1222 // struct work_struct phy_reset_work; 1223 u8 otg_port; 1224 struct usb_dma frame_list_usbdma; 1225 u32 *frame_list; 1226 dma_addr_t frame_list_dma; 1227 u32 frame_list_sz; 1228 struct kmem_cache *desc_gen_cache; 1229 struct kmem_cache *desc_hsisoc_cache; 1230 struct kmem_cache *unaligned_cache; 1231 #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024 1232 1233 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 1234 1235 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1236 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1237 /* Gadget structures */ 1238 struct usb_gadget_driver *driver; 1239 int fifo_mem; 1240 unsigned int dedicated_fifos:1; 1241 unsigned char num_of_eps; 1242 u32 fifo_map; 1243 1244 struct usb_request *ep0_reply; 1245 struct usb_request *ctrl_req; 1246 void *ep0_buff; 1247 void *ctrl_buff; 1248 enum dwc2_ep0_state ep0_state; 1249 unsigned delayed_status : 1; 1250 u8 test_mode; 1251 1252 // dma_addr_t setup_desc_dma[2]; 1253 // struct dwc2_dma_desc *setup_desc[2]; 1254 // dma_addr_t ctrl_in_desc_dma; 1255 // struct dwc2_dma_desc *ctrl_in_desc; 1256 // dma_addr_t ctrl_out_desc_dma; 1257 // struct dwc2_dma_desc *ctrl_out_desc; 1258 1259 struct usb_gadget gadget; 1260 unsigned int enabled:1; 1261 unsigned int connected:1; 1262 unsigned int remote_wakeup_allowed:1; 1263 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 1264 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1265 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1266 }; 1267 1268 #define dwc2_readl(hsotg, reg) \ 1269 bus_space_read_4((hsotg)->hsotg_sc->sc_iot, (hsotg)->hsotg_sc->sc_ioh, \ 1270 (reg)) 1271 #define dwc2_writel(hsotg, data, reg) \ 1272 bus_space_write_4((hsotg)->hsotg_sc->sc_iot, (hsotg)->hsotg_sc->sc_ioh, \ 1273 (reg), (data)) 1274 1275 #ifdef DWC2_LOG_WRITES 1276 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset); 1277 #endif 1278 1279 #if 0 1280 static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset, 1281 void *buffer, unsigned int count) 1282 { 1283 if (count) { 1284 u32 *buf = buffer; 1285 1286 do { 1287 u32 x = dwc2_readl(hsotg, offset); 1288 *buf++ = x; 1289 } while (--count); 1290 } 1291 } 1292 1293 static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset, 1294 const void *buffer, unsigned int count) 1295 { 1296 if (count) { 1297 const u32 *buf = buffer; 1298 1299 do { 1300 dwc2_writel(hsotg, *buf++, offset); 1301 } while (--count); 1302 } 1303 } 1304 #endif 1305 1306 /* Reasons for halting a host channel */ 1307 enum dwc2_halt_status { 1308 DWC2_HC_XFER_NO_HALT_STATUS, 1309 DWC2_HC_XFER_COMPLETE, 1310 DWC2_HC_XFER_URB_COMPLETE, 1311 DWC2_HC_XFER_ACK, 1312 DWC2_HC_XFER_NAK, 1313 DWC2_HC_XFER_NYET, 1314 DWC2_HC_XFER_STALL, 1315 DWC2_HC_XFER_XACT_ERR, 1316 DWC2_HC_XFER_FRAME_OVERRUN, 1317 DWC2_HC_XFER_BABBLE_ERR, 1318 DWC2_HC_XFER_DATA_TOGGLE_ERR, 1319 DWC2_HC_XFER_AHB_ERR, 1320 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1321 DWC2_HC_XFER_URB_DEQUEUE, 1322 }; 1323 1324 /* Core version information */ 1325 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) 1326 { 1327 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; 1328 } 1329 1330 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) 1331 { 1332 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; 1333 } 1334 1335 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) 1336 { 1337 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; 1338 } 1339 1340 /* 1341 * The following functions support initialization of the core driver component 1342 * and the DWC_otg controller 1343 */ 1344 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); 1345 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1346 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup, 1347 bool restore); 1348 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host); 1349 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 1350 int reset, int is_host); 1351 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg); 1352 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy); 1353 1354 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host); 1355 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 1356 1357 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1358 1359 int dwc2_check_core_version(struct dwc2_hsotg *hsotg); 1360 1361 /* 1362 * Common core Functions. 1363 * The following functions support managing the DWC_otg controller in either 1364 * device or host mode. 1365 */ 1366 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 1367 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 1368 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1369 1370 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 1371 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1372 1373 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 1374 int is_host); 1375 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg); 1376 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg); 1377 1378 void dwc2_enable_acg(struct dwc2_hsotg *hsotg); 1379 1380 /* This function should be called on every hardware interrupt. */ 1381 irqreturn_t dwc2_handle_common_intr(void *dev); 1382 1383 /* The device ID match table */ 1384 //extern const struct of_device_id dwc2_of_match_table[]; 1385 //extern const struct acpi_device_id dwc2_acpi_match[]; 1386 1387 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1388 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1389 1390 /* Common polling functions */ 1391 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 1392 u32 timeout); 1393 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 1394 u32 timeout); 1395 /* Parameters */ 1396 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1397 int dwc2_init_params(struct dwc2_hsotg *hsotg); 1398 void dwc2_set_default_params(struct dwc2_hsotg *); 1399 void dwc2_check_params(struct dwc2_hsotg *); 1400 1401 /* 1402 * The following functions check the controller's OTG operation mode 1403 * capability (GHWCFG2.OTG_MODE). 1404 * 1405 * These functions can be used before the internal hsotg->hw_params 1406 * are read in and cached so they always read directly from the 1407 * GHWCFG2 register. 1408 */ 1409 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); 1410 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 1411 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 1412 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 1413 1414 /* 1415 * Returns the mode of operation, host or device 1416 */ 1417 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1418 { 1419 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1420 } 1421 1422 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1423 { 1424 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1425 } 1426 1427 int dwc2_drd_init(struct dwc2_hsotg *hsotg); 1428 void dwc2_drd_suspend(struct dwc2_hsotg *hsotg); 1429 void dwc2_drd_resume(struct dwc2_hsotg *hsotg); 1430 void dwc2_drd_exit(struct dwc2_hsotg *hsotg); 1431 1432 /* 1433 * Dump core registers and SPRAM 1434 */ 1435 void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1436 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1437 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1438 1439 /* Gadget defines */ 1440 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1441 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1442 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1443 int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1444 int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1445 int dwc2_gadget_init(struct dwc2_hsotg *hsotg); 1446 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1447 bool reset); 1448 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg); 1449 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1450 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1451 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1452 #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1453 #define dwc2_is_device_enabled(hsotg) (hsotg->enabled) 1454 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 1455 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup); 1456 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg); 1457 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1458 int rem_wakeup, int reset); 1459 int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1460 int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1461 bool restore); 1462 void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg); 1463 void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, 1464 int rem_wakeup); 1465 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); 1466 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); 1467 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); 1468 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg); 1469 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg); 1470 static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) 1471 { hsotg->fifo_map = 0; } 1472 #else 1473 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1474 { return 0; } 1475 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1476 { return 0; } 1477 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1478 { return 0; } 1479 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg) 1480 { return 0; } 1481 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1482 bool reset) {} 1483 static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {} 1484 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1485 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1486 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1487 int testmode) 1488 { return 0; } 1489 #define dwc2_is_device_connected(hsotg) (0) 1490 #define dwc2_is_device_enabled(hsotg) (0) 1491 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 1492 { return 0; } 1493 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, 1494 int remote_wakeup) 1495 { return 0; } 1496 static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) 1497 { return 0; } 1498 static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1499 int rem_wakeup, int reset) 1500 { return 0; } 1501 static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg) 1502 { return 0; } 1503 static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1504 bool restore) 1505 { return 0; } 1506 static inline void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) {} 1507 static inline void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, 1508 int rem_wakeup) {} 1509 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 1510 { return 0; } 1511 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 1512 { return 0; } 1513 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 1514 { return 0; } 1515 static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {} 1516 static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {} 1517 static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) {} 1518 #endif 1519 1520 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1521 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1522 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 1523 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 1524 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1525 void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1526 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); 1527 int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex); 1528 int dwc2_port_resume(struct dwc2_hsotg *hsotg); 1529 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 1530 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1531 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); 1532 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1533 int rem_wakeup, int reset); 1534 int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1535 int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1536 int rem_wakeup, bool restore); 1537 void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg); 1538 void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup); 1539 bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2); 1540 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) 1541 { 1542 // schedule_work(&hsotg->phy_reset_work); 1543 } 1544 #else 1545 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1546 { return 0; } 1547 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1548 int us) 1549 { return 0; } 1550 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 1551 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1552 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1553 //static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1554 static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 1555 { return 0; } 1556 static inline int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1557 { return 0; } 1558 static inline int dwc2_port_resume(struct dwc2_hsotg *hsotg) 1559 { return 0; } 1560 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 1561 { return 0; } 1562 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 1563 { return 0; } 1564 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 1565 { return 0; } 1566 static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) 1567 { return 0; } 1568 static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1569 int rem_wakeup, int reset) 1570 { return 0; } 1571 static inline int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg) 1572 { return 0; } 1573 static inline int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1574 int rem_wakeup, bool restore) 1575 { return 0; } 1576 static inline void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) {} 1577 static inline void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, 1578 int rem_wakeup) {} 1579 static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2) 1580 { return false; } 1581 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {} 1582 1583 #endif 1584 1585 #endif /* __DWC2_CORE_H__ */ 1586