1 /* $OpenBSD: dwc2_core.c,v 1.6 2015/06/28 11:48:18 jmatthew Exp $ */ 2 /* $NetBSD: dwc2_core.c,v 1.6 2014/04/03 06:34:58 skrll Exp $ */ 3 4 /* 5 * core.c - DesignWare HS OTG Controller common routines 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * The Core code provides basic services for accessing and managing the 42 * DWC_otg hardware. These services are used by both the Host Controller 43 * Driver and the Peripheral Controller Driver. 44 */ 45 46 #if 0 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: dwc2_core.c,v 1.6 2014/04/03 06:34:58 skrll Exp $"); 49 #endif 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/types.h> 54 #include <sys/signal.h> 55 #include <sys/proc.h> 56 #include <sys/timeout.h> 57 #include <sys/mutex.h> 58 #include <sys/pool.h> 59 #include <sys/task.h> 60 61 #include <machine/bus.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 #include <dev/usb/usbdivar.h> 66 #include <dev/usb/usb_mem.h> 67 68 #include <dev/usb/dwc2/dwc2.h> 69 #include <dev/usb/dwc2/dwc2var.h> 70 71 #include <dev/usb/dwc2/dwc2_core.h> 72 #include <dev/usb/dwc2/dwc2_hcd.h> 73 74 /** 75 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, 76 * used in both device and host modes 77 * 78 * @hsotg: Programming view of the DWC_otg controller 79 */ 80 STATIC void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 81 { 82 u32 intmsk; 83 84 /* Clear any pending OTG Interrupts */ 85 DWC2_WRITE_4(hsotg, GOTGINT, 0xffffffff); 86 87 /* Clear any pending interrupts */ 88 DWC2_WRITE_4(hsotg, GINTSTS, 0xffffffff); 89 90 /* Enable the interrupts in the GINTMSK */ 91 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 92 93 if (hsotg->core_params->dma_enable <= 0) 94 intmsk |= GINTSTS_RXFLVL; 95 96 intmsk |= GINTSTS_CONIDSTSCHNG | GINTSTS_WKUPINT | GINTSTS_USBSUSP | 97 GINTSTS_SESSREQINT; 98 99 DWC2_WRITE_4(hsotg, GINTMSK, intmsk); 100 } 101 102 /* 103 * Initializes the FSLSPClkSel field of the HCFG register depending on the 104 * PHY type 105 */ 106 STATIC void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 107 { 108 u32 hcfg, val; 109 110 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 111 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 112 hsotg->core_params->ulpi_fs_ls > 0) || 113 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { 114 /* Full speed PHY */ 115 val = HCFG_FSLSPCLKSEL_48_MHZ; 116 } else { 117 /* High speed PHY running at full speed or high speed */ 118 val = HCFG_FSLSPCLKSEL_30_60_MHZ; 119 } 120 121 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 122 hcfg = DWC2_READ_4(hsotg, HCFG); 123 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 124 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 125 DWC2_WRITE_4(hsotg, HCFG, hcfg); 126 } 127 128 /* 129 * Do core a soft reset of the core. Be careful with this because it 130 * resets all the internal state machines of the core. 131 */ 132 STATIC int dwc2_core_reset(struct dwc2_hsotg *hsotg) 133 { 134 u32 greset; 135 int count = 0; 136 137 dev_vdbg(hsotg->dev, "%s()\n", __func__); 138 139 /* Wait for AHB master IDLE state */ 140 do { 141 usleep_range(20000, 40000); 142 greset = DWC2_READ_4(hsotg, GRSTCTL); 143 if (++count > 50) { 144 dev_warn(hsotg->dev, 145 "%s() HANG! AHB Idle GRSTCTL=%0x\n", 146 __func__, greset); 147 return -EBUSY; 148 } 149 } while (!(greset & GRSTCTL_AHBIDLE)); 150 151 /* Core Soft Reset */ 152 count = 0; 153 greset |= GRSTCTL_CSFTRST; 154 DWC2_WRITE_4(hsotg, GRSTCTL, greset); 155 do { 156 usleep_range(20000, 40000); 157 greset = DWC2_READ_4(hsotg, GRSTCTL); 158 if (++count > 50) { 159 dev_warn(hsotg->dev, 160 "%s() HANG! Soft Reset GRSTCTL=%0x\n", 161 __func__, greset); 162 return -EBUSY; 163 } 164 } while (greset & GRSTCTL_CSFTRST); 165 166 /* 167 * NOTE: This long sleep is _very_ important, otherwise the core will 168 * not stay in host mode after a connector ID change! 169 */ 170 usleep_range(150000, 200000); 171 172 return 0; 173 } 174 175 STATIC int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 176 { 177 u32 usbcfg, i2cctl; 178 int retval = 0; 179 180 /* 181 * core_init() is now called on every switch so only call the 182 * following for the first time through 183 */ 184 if (select_phy) { 185 dev_dbg(hsotg->dev, "FS PHY selected\n"); 186 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 187 usbcfg |= GUSBCFG_PHYSEL; 188 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 189 190 /* Reset after a PHY select */ 191 retval = dwc2_core_reset(hsotg); 192 if (retval) { 193 dev_err(hsotg->dev, "%s() Reset failed, aborting", 194 __func__); 195 return retval; 196 } 197 } 198 199 /* 200 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 201 * do this on HNP Dev/Host mode switches (done in dev_init and 202 * host_init). 203 */ 204 if (dwc2_is_host_mode(hsotg)) 205 dwc2_init_fs_ls_pclk_sel(hsotg); 206 207 if (hsotg->core_params->i2c_enable > 0) { 208 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 209 210 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 211 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 212 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 213 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 214 215 /* Program GI2CCTL.I2CEn */ 216 i2cctl = DWC2_READ_4(hsotg, GI2CCTL); 217 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 218 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 219 i2cctl &= ~GI2CCTL_I2CEN; 220 DWC2_WRITE_4(hsotg, GI2CCTL, i2cctl); 221 i2cctl |= GI2CCTL_I2CEN; 222 DWC2_WRITE_4(hsotg, GI2CCTL, i2cctl); 223 } 224 225 return retval; 226 } 227 228 STATIC int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 229 { 230 u32 usbcfg; 231 int retval = 0; 232 233 if (!select_phy) 234 return 0; 235 236 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 237 238 /* 239 * HS PHY parameters. These parameters are preserved during soft reset 240 * so only program the first time. Do a soft reset immediately after 241 * setting phyif. 242 */ 243 switch (hsotg->core_params->phy_type) { 244 case DWC2_PHY_TYPE_PARAM_ULPI: 245 /* ULPI interface */ 246 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 247 usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 248 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 249 if (hsotg->core_params->phy_ulpi_ddr > 0) 250 usbcfg |= GUSBCFG_DDRSEL; 251 break; 252 case DWC2_PHY_TYPE_PARAM_UTMI: 253 /* UTMI+ interface */ 254 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 255 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 256 if (hsotg->core_params->phy_utmi_width == 16) 257 usbcfg |= GUSBCFG_PHYIF16; 258 break; 259 default: 260 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 261 break; 262 } 263 264 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 265 266 /* Reset after setting the PHY parameters */ 267 retval = dwc2_core_reset(hsotg); 268 if (retval) { 269 dev_err(hsotg->dev, "%s() Reset failed, aborting", 270 __func__); 271 return retval; 272 } 273 274 return retval; 275 } 276 277 STATIC int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 278 { 279 u32 usbcfg; 280 int retval = 0; 281 282 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL && 283 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { 284 /* If FS mode with FS PHY */ 285 retval = dwc2_fs_phy_init(hsotg, select_phy); 286 if (retval) 287 return retval; 288 } else { 289 /* High speed PHY */ 290 retval = dwc2_hs_phy_init(hsotg, select_phy); 291 if (retval) 292 return retval; 293 } 294 295 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 296 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 297 hsotg->core_params->ulpi_fs_ls > 0) { 298 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 299 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 300 usbcfg |= GUSBCFG_ULPI_FS_LS; 301 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 302 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 303 } else { 304 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 305 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 306 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 307 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 308 } 309 310 return retval; 311 } 312 313 STATIC int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 314 { 315 u32 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 316 317 switch (hsotg->hw_params.arch) { 318 case GHWCFG2_EXT_DMA_ARCH: 319 dev_err(hsotg->dev, "External DMA Mode\n"); 320 if (hsotg->core_params->ahbcfg != -1) { 321 ahbcfg &= GAHBCFG_CTRL_MASK; 322 ahbcfg |= hsotg->core_params->ahbcfg & 323 ~GAHBCFG_CTRL_MASK; 324 } 325 break; 326 327 case GHWCFG2_INT_DMA_ARCH: 328 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); 329 if (hsotg->core_params->ahbcfg != -1) { 330 ahbcfg &= GAHBCFG_CTRL_MASK; 331 ahbcfg |= hsotg->core_params->ahbcfg & 332 ~GAHBCFG_CTRL_MASK; 333 } 334 break; 335 336 case GHWCFG2_SLAVE_ONLY_ARCH: 337 default: 338 dev_dbg(hsotg->dev, "Slave Only Mode\n"); 339 break; 340 } 341 342 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n", 343 hsotg->core_params->dma_enable, 344 hsotg->core_params->dma_desc_enable); 345 346 if (hsotg->core_params->dma_enable > 0) { 347 if (hsotg->core_params->dma_desc_enable > 0) 348 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); 349 else 350 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); 351 } else { 352 dev_dbg(hsotg->dev, "Using Slave mode\n"); 353 hsotg->core_params->dma_desc_enable = 0; 354 } 355 356 if (hsotg->core_params->dma_enable > 0) 357 ahbcfg |= GAHBCFG_DMA_EN; 358 359 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 360 361 return 0; 362 } 363 364 STATIC void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 365 { 366 u32 usbcfg; 367 368 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 369 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 370 371 switch (hsotg->hw_params.op_mode) { 372 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 373 if (hsotg->core_params->otg_cap == 374 DWC2_CAP_PARAM_HNP_SRP_CAPABLE) 375 usbcfg |= GUSBCFG_HNPCAP; 376 if (hsotg->core_params->otg_cap != 377 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 378 usbcfg |= GUSBCFG_SRPCAP; 379 break; 380 381 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 382 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 383 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 384 if (hsotg->core_params->otg_cap != 385 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 386 usbcfg |= GUSBCFG_SRPCAP; 387 break; 388 389 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: 390 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: 391 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: 392 default: 393 break; 394 } 395 396 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 397 } 398 399 /** 400 * dwc2_core_init() - Initializes the DWC_otg controller registers and 401 * prepares the core for device mode or host mode operation 402 * 403 * @hsotg: Programming view of the DWC_otg controller 404 * @select_phy: If true then also set the Phy type 405 * @irq: If >= 0, the irq to register 406 */ 407 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy) 408 { 409 u32 usbcfg, otgctl; 410 int retval; 411 412 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 413 414 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 415 416 /* Set ULPI External VBUS bit if needed */ 417 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 418 if (hsotg->core_params->phy_ulpi_ext_vbus == 419 DWC2_PHY_ULPI_EXTERNAL_VBUS) 420 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; 421 422 /* Set external TS Dline pulsing bit if needed */ 423 usbcfg &= ~GUSBCFG_TERMSELDLPULSE; 424 if (hsotg->core_params->ts_dline > 0) 425 usbcfg |= GUSBCFG_TERMSELDLPULSE; 426 427 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 428 429 /* Reset the Controller */ 430 retval = dwc2_core_reset(hsotg); 431 if (retval) { 432 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", 433 __func__); 434 return retval; 435 } 436 437 /* 438 * This needs to happen in FS mode before any other programming occurs 439 */ 440 retval = dwc2_phy_init(hsotg, select_phy); 441 if (retval) 442 return retval; 443 444 /* Program the GAHBCFG Register */ 445 retval = dwc2_gahbcfg_init(hsotg); 446 if (retval) 447 return retval; 448 449 /* Program the GUSBCFG register */ 450 dwc2_gusbcfg_init(hsotg); 451 452 /* Program the GOTGCTL register */ 453 otgctl = DWC2_READ_4(hsotg, GOTGCTL); 454 otgctl &= ~GOTGCTL_OTGVER; 455 if (hsotg->core_params->otg_ver > 0) 456 otgctl |= GOTGCTL_OTGVER; 457 DWC2_WRITE_4(hsotg, GOTGCTL, otgctl); 458 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); 459 460 /* Clear the SRP success bit for FS-I2c */ 461 hsotg->srp_success = 0; 462 463 /* Enable common interrupts */ 464 dwc2_enable_common_interrupts(hsotg); 465 466 /* 467 * Do device or host intialization based on mode during PCD and 468 * HCD initialization 469 */ 470 if (dwc2_is_host_mode(hsotg)) { 471 dev_dbg(hsotg->dev, "Host Mode\n"); 472 hsotg->op_state = OTG_STATE_A_HOST; 473 } else { 474 dev_dbg(hsotg->dev, "Device Mode\n"); 475 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 476 } 477 478 return 0; 479 } 480 481 /** 482 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts 483 * 484 * @hsotg: Programming view of DWC_otg controller 485 */ 486 void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) 487 { 488 u32 intmsk; 489 490 dev_dbg(hsotg->dev, "%s()\n", __func__); 491 492 /* Disable all interrupts */ 493 DWC2_WRITE_4(hsotg, GINTMSK, 0); 494 DWC2_WRITE_4(hsotg, HAINTMSK, 0); 495 496 /* Enable the common interrupts */ 497 dwc2_enable_common_interrupts(hsotg); 498 499 /* Enable host mode interrupts without disturbing common interrupts */ 500 intmsk = DWC2_READ_4(hsotg, GINTMSK); 501 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 502 DWC2_WRITE_4(hsotg, GINTMSK, intmsk); 503 } 504 505 /** 506 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts 507 * 508 * @hsotg: Programming view of DWC_otg controller 509 */ 510 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 511 { 512 u32 intmsk = DWC2_READ_4(hsotg, GINTMSK); 513 514 /* Disable host mode interrupts without disturbing common interrupts */ 515 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 516 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); 517 DWC2_WRITE_4(hsotg, GINTMSK, intmsk); 518 } 519 520 STATIC void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 521 { 522 struct dwc2_core_params *params = hsotg->core_params; 523 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; 524 525 if (!params->enable_dynamic_fifo) 526 return; 527 528 /* Rx FIFO */ 529 grxfsiz = DWC2_READ_4(hsotg, GRXFSIZ); 530 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 531 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 532 grxfsiz |= params->host_rx_fifo_size << 533 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 534 DWC2_WRITE_4(hsotg, GRXFSIZ, grxfsiz); 535 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", DWC2_READ_4(hsotg, GRXFSIZ)); 536 537 /* Non-periodic Tx FIFO */ 538 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 539 DWC2_READ_4(hsotg, GNPTXFSIZ)); 540 nptxfsiz = params->host_nperio_tx_fifo_size << 541 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 542 nptxfsiz |= params->host_rx_fifo_size << 543 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 544 DWC2_WRITE_4(hsotg, GNPTXFSIZ, nptxfsiz); 545 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 546 DWC2_READ_4(hsotg, GNPTXFSIZ)); 547 548 /* Periodic Tx FIFO */ 549 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 550 DWC2_READ_4(hsotg, HPTXFSIZ)); 551 hptxfsiz = params->host_perio_tx_fifo_size << 552 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 553 hptxfsiz |= (params->host_rx_fifo_size + 554 params->host_nperio_tx_fifo_size) << 555 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 556 DWC2_WRITE_4(hsotg, HPTXFSIZ, hptxfsiz); 557 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 558 DWC2_READ_4(hsotg, HPTXFSIZ)); 559 560 if (hsotg->core_params->en_multiple_tx_fifo > 0 && 561 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { 562 /* 563 * Global DFIFOCFG calculation for Host mode - 564 * include RxFIFO, NPTXFIFO and HPTXFIFO 565 */ 566 dfifocfg = DWC2_READ_4(hsotg, GDFIFOCFG); 567 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 568 dfifocfg |= (params->host_rx_fifo_size + 569 params->host_nperio_tx_fifo_size + 570 params->host_perio_tx_fifo_size) << 571 GDFIFOCFG_EPINFOBASE_SHIFT & 572 GDFIFOCFG_EPINFOBASE_MASK; 573 DWC2_WRITE_4(hsotg, GDFIFOCFG, dfifocfg); 574 } 575 } 576 577 /** 578 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for 579 * Host mode 580 * 581 * @hsotg: Programming view of DWC_otg controller 582 * 583 * This function flushes the Tx and Rx FIFOs and flushes any entries in the 584 * request queues. Host channels are reset to ensure that they are ready for 585 * performing transfers. 586 */ 587 void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 588 { 589 u32 hcfg, hfir, otgctl; 590 591 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 592 593 /* Restart the Phy Clock */ 594 DWC2_WRITE_4(hsotg, PCGCTL, 0); 595 596 /* Initialize Host Configuration Register */ 597 dwc2_init_fs_ls_pclk_sel(hsotg); 598 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) { 599 hcfg = DWC2_READ_4(hsotg, HCFG); 600 hcfg |= HCFG_FSLSSUPP; 601 DWC2_WRITE_4(hsotg, HCFG, hcfg); 602 } 603 604 /* 605 * This bit allows dynamic reloading of the HFIR register during 606 * runtime. This bit needs to be programmed during initial configuration 607 * and its value must not be changed during runtime. 608 */ 609 if (hsotg->core_params->reload_ctl > 0) { 610 hfir = DWC2_READ_4(hsotg, HFIR); 611 hfir |= HFIR_RLDCTRL; 612 DWC2_WRITE_4(hsotg, HFIR, hfir); 613 } 614 615 if (hsotg->core_params->dma_desc_enable > 0) { 616 u32 op_mode = hsotg->hw_params.op_mode; 617 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || 618 !hsotg->hw_params.dma_desc_enable || 619 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || 620 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || 621 op_mode == GHWCFG2_OP_MODE_UNDEFINED) { 622 dev_err(hsotg->dev, 623 "Hardware does not support descriptor DMA mode -\n"); 624 dev_err(hsotg->dev, 625 "falling back to buffer DMA mode.\n"); 626 hsotg->core_params->dma_desc_enable = 0; 627 } else { 628 hcfg = DWC2_READ_4(hsotg, HCFG); 629 hcfg |= HCFG_DESCDMA; 630 DWC2_WRITE_4(hsotg, HCFG, hcfg); 631 } 632 } 633 634 /* Configure data FIFO sizes */ 635 dwc2_config_fifos(hsotg); 636 637 /* TODO - check this */ 638 /* Clear Host Set HNP Enable in the OTG Control Register */ 639 otgctl = DWC2_READ_4(hsotg, GOTGCTL); 640 otgctl &= ~GOTGCTL_HSTSETHNPEN; 641 DWC2_WRITE_4(hsotg, GOTGCTL, otgctl); 642 643 /* Make sure the FIFOs are flushed */ 644 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 645 dwc2_flush_rx_fifo(hsotg); 646 647 /* Clear Host Set HNP Enable in the OTG Control Register */ 648 otgctl = DWC2_READ_4(hsotg, GOTGCTL); 649 otgctl &= ~GOTGCTL_HSTSETHNPEN; 650 DWC2_WRITE_4(hsotg, GOTGCTL, otgctl); 651 652 if (hsotg->core_params->dma_desc_enable <= 0) { 653 int num_channels, i; 654 u32 hcchar; 655 656 /* Flush out any leftover queued requests */ 657 num_channels = hsotg->core_params->host_channels; 658 for (i = 0; i < num_channels; i++) { 659 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 660 hcchar &= ~HCCHAR_CHENA; 661 hcchar |= HCCHAR_CHDIS; 662 hcchar &= ~HCCHAR_EPDIR; 663 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 664 } 665 666 /* Halt all channels to put them into a known state */ 667 for (i = 0; i < num_channels; i++) { 668 int count = 0; 669 670 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 671 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 672 hcchar &= ~HCCHAR_EPDIR; 673 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 674 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 675 __func__, i); 676 do { 677 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 678 if (++count > 1000) { 679 dev_err(hsotg->dev, 680 "Unable to clear enable on channel %d\n", 681 i); 682 break; 683 } 684 udelay(1); 685 } while (hcchar & HCCHAR_CHENA); 686 } 687 } 688 689 /* Turn on the vbus power */ 690 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); 691 if (hsotg->op_state == OTG_STATE_A_HOST) { 692 u32 hprt0 = dwc2_read_hprt0(hsotg); 693 694 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", 695 !!(hprt0 & HPRT0_PWR)); 696 if (!(hprt0 & HPRT0_PWR)) { 697 hprt0 |= HPRT0_PWR; 698 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 699 } 700 } 701 702 dwc2_enable_host_interrupts(hsotg); 703 } 704 705 STATIC void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 706 struct dwc2_host_chan *chan) 707 { 708 u32 hcintmsk = HCINTMSK_CHHLTD; 709 710 switch (chan->ep_type) { 711 case USB_ENDPOINT_XFER_CONTROL: 712 case USB_ENDPOINT_XFER_BULK: 713 dev_vdbg(hsotg->dev, "control/bulk\n"); 714 hcintmsk |= HCINTMSK_XFERCOMPL; 715 hcintmsk |= HCINTMSK_STALL; 716 hcintmsk |= HCINTMSK_XACTERR; 717 hcintmsk |= HCINTMSK_DATATGLERR; 718 if (chan->ep_is_in) { 719 hcintmsk |= HCINTMSK_BBLERR; 720 } else { 721 hcintmsk |= HCINTMSK_NAK; 722 hcintmsk |= HCINTMSK_NYET; 723 if (chan->do_ping) 724 hcintmsk |= HCINTMSK_ACK; 725 } 726 727 if (chan->do_split) { 728 hcintmsk |= HCINTMSK_NAK; 729 if (chan->complete_split) 730 hcintmsk |= HCINTMSK_NYET; 731 else 732 hcintmsk |= HCINTMSK_ACK; 733 } 734 735 if (chan->error_state) 736 hcintmsk |= HCINTMSK_ACK; 737 break; 738 739 case USB_ENDPOINT_XFER_INT: 740 if (dbg_perio()) 741 dev_vdbg(hsotg->dev, "intr\n"); 742 hcintmsk |= HCINTMSK_XFERCOMPL; 743 hcintmsk |= HCINTMSK_NAK; 744 hcintmsk |= HCINTMSK_STALL; 745 hcintmsk |= HCINTMSK_XACTERR; 746 hcintmsk |= HCINTMSK_DATATGLERR; 747 hcintmsk |= HCINTMSK_FRMOVRUN; 748 749 if (chan->ep_is_in) 750 hcintmsk |= HCINTMSK_BBLERR; 751 if (chan->error_state) 752 hcintmsk |= HCINTMSK_ACK; 753 if (chan->do_split) { 754 if (chan->complete_split) 755 hcintmsk |= HCINTMSK_NYET; 756 else 757 hcintmsk |= HCINTMSK_ACK; 758 } 759 break; 760 761 case USB_ENDPOINT_XFER_ISOC: 762 if (dbg_perio()) 763 dev_vdbg(hsotg->dev, "isoc\n"); 764 hcintmsk |= HCINTMSK_XFERCOMPL; 765 hcintmsk |= HCINTMSK_FRMOVRUN; 766 hcintmsk |= HCINTMSK_ACK; 767 768 if (chan->ep_is_in) { 769 hcintmsk |= HCINTMSK_XACTERR; 770 hcintmsk |= HCINTMSK_BBLERR; 771 } 772 break; 773 default: 774 dev_err(hsotg->dev, "## Unknown EP type ##\n"); 775 break; 776 } 777 778 DWC2_WRITE_4(hsotg, HCINTMSK(chan->hc_num), hcintmsk); 779 if (dbg_hc(chan)) 780 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 781 } 782 783 STATIC void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 784 struct dwc2_host_chan *chan) 785 { 786 u32 hcintmsk = HCINTMSK_CHHLTD; 787 788 /* 789 * For Descriptor DMA mode core halts the channel on AHB error. 790 * Interrupt is not required. 791 */ 792 if (hsotg->core_params->dma_desc_enable <= 0) { 793 if (dbg_hc(chan)) 794 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 795 hcintmsk |= HCINTMSK_AHBERR; 796 } else { 797 if (dbg_hc(chan)) 798 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); 799 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 800 hcintmsk |= HCINTMSK_XFERCOMPL; 801 } 802 803 if (chan->error_state && !chan->do_split && 804 chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 805 if (dbg_hc(chan)) 806 dev_vdbg(hsotg->dev, "setting ACK\n"); 807 hcintmsk |= HCINTMSK_ACK; 808 if (chan->ep_is_in) { 809 hcintmsk |= HCINTMSK_DATATGLERR; 810 if (chan->ep_type != USB_ENDPOINT_XFER_INT) 811 hcintmsk |= HCINTMSK_NAK; 812 } 813 } 814 815 DWC2_WRITE_4(hsotg, HCINTMSK(chan->hc_num), hcintmsk); 816 if (dbg_hc(chan)) 817 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 818 } 819 820 STATIC void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 821 struct dwc2_host_chan *chan) 822 { 823 u32 intmsk; 824 825 if (hsotg->core_params->dma_enable > 0) { 826 if (dbg_hc(chan)) 827 dev_vdbg(hsotg->dev, "DMA enabled\n"); 828 dwc2_hc_enable_dma_ints(hsotg, chan); 829 } else { 830 if (dbg_hc(chan)) 831 dev_vdbg(hsotg->dev, "DMA disabled\n"); 832 dwc2_hc_enable_slave_ints(hsotg, chan); 833 } 834 835 /* Enable the top level host channel interrupt */ 836 intmsk = DWC2_READ_4(hsotg, HAINTMSK); 837 intmsk |= 1 << chan->hc_num; 838 DWC2_WRITE_4(hsotg, HAINTMSK, intmsk); 839 if (dbg_hc(chan)) 840 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 841 842 /* Make sure host channel interrupts are enabled */ 843 intmsk = DWC2_READ_4(hsotg, GINTMSK); 844 intmsk |= GINTSTS_HCHINT; 845 DWC2_WRITE_4(hsotg, GINTMSK, intmsk); 846 if (dbg_hc(chan)) 847 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 848 } 849 850 /** 851 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from 852 * a specific endpoint 853 * 854 * @hsotg: Programming view of DWC_otg controller 855 * @chan: Information needed to initialize the host channel 856 * 857 * The HCCHARn register is set up with the characteristics specified in chan. 858 * Host channel interrupts that may need to be serviced while this transfer is 859 * in progress are enabled. 860 */ 861 void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 862 { 863 u8 hc_num = chan->hc_num; 864 u32 hcintmsk; 865 u32 hcchar; 866 u32 hcsplt = 0; 867 868 if (dbg_hc(chan)) 869 dev_vdbg(hsotg->dev, "%s()\n", __func__); 870 871 /* Clear old interrupt conditions for this host channel */ 872 hcintmsk = 0xffffffff; 873 hcintmsk &= ~HCINTMSK_RESERVED14_31; 874 DWC2_WRITE_4(hsotg, HCINT(hc_num), hcintmsk); 875 876 /* Enable channel interrupts required for this transfer */ 877 dwc2_hc_enable_ints(hsotg, chan); 878 879 /* 880 * Program the HCCHARn register with the endpoint characteristics for 881 * the current transfer 882 */ 883 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; 884 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; 885 if (chan->ep_is_in) 886 hcchar |= HCCHAR_EPDIR; 887 if (chan->speed == USB_SPEED_LOW) 888 hcchar |= HCCHAR_LSPDDEV; 889 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 890 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 891 DWC2_WRITE_4(hsotg, HCCHAR(hc_num), hcchar); 892 if (dbg_hc(chan)) { 893 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 894 hc_num, hcchar); 895 896 dev_vdbg(hsotg->dev, "%s: Channel %d\n", 897 __func__, hc_num); 898 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", 899 chan->dev_addr); 900 dev_vdbg(hsotg->dev, " Ep Num: %d\n", 901 chan->ep_num); 902 dev_vdbg(hsotg->dev, " Is In: %d\n", 903 chan->ep_is_in); 904 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", 905 chan->speed == USB_SPEED_LOW); 906 dev_vdbg(hsotg->dev, " Ep Type: %d\n", 907 chan->ep_type); 908 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", 909 chan->max_packet); 910 } 911 912 /* Program the HCSPLT register for SPLITs */ 913 if (chan->do_split) { 914 if (dbg_hc(chan)) 915 dev_vdbg(hsotg->dev, 916 "Programming HC %d with split --> %s\n", 917 hc_num, 918 chan->complete_split ? "CSPLIT" : "SSPLIT"); 919 if (chan->complete_split) 920 hcsplt |= HCSPLT_COMPSPLT; 921 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & 922 HCSPLT_XACTPOS_MASK; 923 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & 924 HCSPLT_HUBADDR_MASK; 925 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & 926 HCSPLT_PRTADDR_MASK; 927 if (dbg_hc(chan)) { 928 dev_vdbg(hsotg->dev, " comp split %d\n", 929 chan->complete_split); 930 dev_vdbg(hsotg->dev, " xact pos %d\n", 931 chan->xact_pos); 932 dev_vdbg(hsotg->dev, " hub addr %d\n", 933 chan->hub_addr); 934 dev_vdbg(hsotg->dev, " hub port %d\n", 935 chan->hub_port); 936 dev_vdbg(hsotg->dev, " is_in %d\n", 937 chan->ep_is_in); 938 dev_vdbg(hsotg->dev, " Max Pkt %d\n", 939 chan->max_packet); 940 dev_vdbg(hsotg->dev, " xferlen %d\n", 941 chan->xfer_len); 942 } 943 } 944 945 DWC2_WRITE_4(hsotg, HCSPLT(hc_num), hcsplt); 946 } 947 948 /** 949 * dwc2_hc_halt() - Attempts to halt a host channel 950 * 951 * @hsotg: Controller register interface 952 * @chan: Host channel to halt 953 * @halt_status: Reason for halting the channel 954 * 955 * This function should only be called in Slave mode or to abort a transfer in 956 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the 957 * controller halts the channel when the transfer is complete or a condition 958 * occurs that requires application intervention. 959 * 960 * In slave mode, checks for a free request queue entry, then sets the Channel 961 * Enable and Channel Disable bits of the Host Channel Characteristics 962 * register of the specified channel to intiate the halt. If there is no free 963 * request queue entry, sets only the Channel Disable bit of the HCCHARn 964 * register to flush requests for this channel. In the latter case, sets a 965 * flag to indicate that the host channel needs to be halted when a request 966 * queue slot is open. 967 * 968 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the 969 * HCCHARn register. The controller ensures there is space in the request 970 * queue before submitting the halt request. 971 * 972 * Some time may elapse before the core flushes any posted requests for this 973 * host channel and halts. The Channel Halted interrupt handler completes the 974 * deactivation of the host channel. 975 */ 976 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 977 enum dwc2_halt_status halt_status) 978 { 979 u32 nptxsts, hptxsts, hcchar; 980 981 if (dbg_hc(chan)) 982 dev_vdbg(hsotg->dev, "%s()\n", __func__); 983 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) 984 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); 985 986 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || 987 halt_status == DWC2_HC_XFER_AHB_ERR) { 988 /* 989 * Disable all channel interrupts except Ch Halted. The QTD 990 * and QH state associated with this transfer has been cleared 991 * (in the case of URB_DEQUEUE), so the channel needs to be 992 * shut down carefully to prevent crashes. 993 */ 994 u32 hcintmsk = HCINTMSK_CHHLTD; 995 996 dev_vdbg(hsotg->dev, "dequeue/error\n"); 997 DWC2_WRITE_4(hsotg, HCINTMSK(chan->hc_num), hcintmsk); 998 999 /* 1000 * Make sure no other interrupts besides halt are currently 1001 * pending. Handling another interrupt could cause a crash due 1002 * to the QTD and QH state. 1003 */ 1004 DWC2_WRITE_4(hsotg, HCINT(chan->hc_num), ~hcintmsk); 1005 1006 /* 1007 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 1008 * even if the channel was already halted for some other 1009 * reason 1010 */ 1011 chan->halt_status = halt_status; 1012 1013 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1014 if (!(hcchar & HCCHAR_CHENA)) { 1015 /* 1016 * The channel is either already halted or it hasn't 1017 * started yet. In DMA mode, the transfer may halt if 1018 * it finishes normally or a condition occurs that 1019 * requires driver intervention. Don't want to halt 1020 * the channel again. In either Slave or DMA mode, 1021 * it's possible that the transfer has been assigned 1022 * to a channel, but not started yet when an URB is 1023 * dequeued. Don't want to halt a channel that hasn't 1024 * started yet. 1025 */ 1026 return; 1027 } 1028 } 1029 if (chan->halt_pending) { 1030 /* 1031 * A halt has already been issued for this channel. This might 1032 * happen when a transfer is aborted by a higher level in 1033 * the stack. 1034 */ 1035 dev_vdbg(hsotg->dev, 1036 "*** %s: Channel %d, chan->halt_pending already set ***\n", 1037 __func__, chan->hc_num); 1038 return; 1039 } 1040 1041 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1042 1043 /* No need to set the bit in DDMA for disabling the channel */ 1044 /* TODO check it everywhere channel is disabled */ 1045 if (hsotg->core_params->dma_desc_enable <= 0) { 1046 if (dbg_hc(chan)) 1047 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 1048 hcchar |= HCCHAR_CHENA; 1049 } else { 1050 if (dbg_hc(chan)) 1051 dev_dbg(hsotg->dev, "desc DMA enabled\n"); 1052 } 1053 hcchar |= HCCHAR_CHDIS; 1054 1055 if (hsotg->core_params->dma_enable <= 0) { 1056 if (dbg_hc(chan)) 1057 dev_vdbg(hsotg->dev, "DMA not enabled\n"); 1058 hcchar |= HCCHAR_CHENA; 1059 1060 /* Check for space in the request queue to issue the halt */ 1061 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1062 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 1063 dev_vdbg(hsotg->dev, "control/bulk\n"); 1064 nptxsts = DWC2_READ_4(hsotg, GNPTXSTS); 1065 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 1066 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1067 hcchar &= ~HCCHAR_CHENA; 1068 } 1069 } else { 1070 if (dbg_perio()) 1071 dev_vdbg(hsotg->dev, "isoc/intr\n"); 1072 hptxsts = DWC2_READ_4(hsotg, HPTXSTS); 1073 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 1074 hsotg->queuing_high_bandwidth) { 1075 if (dbg_perio()) 1076 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1077 hcchar &= ~HCCHAR_CHENA; 1078 } 1079 } 1080 } else { 1081 if (dbg_hc(chan)) 1082 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1083 } 1084 1085 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 1086 chan->halt_status = halt_status; 1087 1088 if (hcchar & HCCHAR_CHENA) { 1089 if (dbg_hc(chan)) 1090 dev_vdbg(hsotg->dev, "Channel enabled\n"); 1091 chan->halt_pending = 1; 1092 chan->halt_on_queue = 0; 1093 } else { 1094 if (dbg_hc(chan)) 1095 dev_vdbg(hsotg->dev, "Channel disabled\n"); 1096 chan->halt_on_queue = 1; 1097 } 1098 1099 if (dbg_hc(chan)) { 1100 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1101 chan->hc_num); 1102 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", 1103 hcchar); 1104 dev_vdbg(hsotg->dev, " halt_pending: %d\n", 1105 chan->halt_pending); 1106 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", 1107 chan->halt_on_queue); 1108 dev_vdbg(hsotg->dev, " halt_status: %d\n", 1109 chan->halt_status); 1110 } 1111 } 1112 1113 /** 1114 * dwc2_hc_cleanup() - Clears the transfer state for a host channel 1115 * 1116 * @hsotg: Programming view of DWC_otg controller 1117 * @chan: Identifies the host channel to clean up 1118 * 1119 * This function is normally called after a transfer is done and the host 1120 * channel is being released 1121 */ 1122 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1123 { 1124 u32 hcintmsk; 1125 1126 chan->xfer_started = 0; 1127 1128 /* 1129 * Clear channel interrupt enables and any unhandled channel interrupt 1130 * conditions 1131 */ 1132 DWC2_WRITE_4(hsotg, HCINTMSK(chan->hc_num), 0); 1133 hcintmsk = 0xffffffff; 1134 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1135 DWC2_WRITE_4(hsotg, HCINT(chan->hc_num), hcintmsk); 1136 } 1137 1138 /** 1139 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in 1140 * which frame a periodic transfer should occur 1141 * 1142 * @hsotg: Programming view of DWC_otg controller 1143 * @chan: Identifies the host channel to set up and its properties 1144 * @hcchar: Current value of the HCCHAR register for the specified host channel 1145 * 1146 * This function has no effect on non-periodic transfers 1147 */ 1148 STATIC void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 1149 struct dwc2_host_chan *chan, u32 *hcchar) 1150 { 1151 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1152 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1153 /* 1 if _next_ frame is odd, 0 if it's even */ 1154 if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1)) 1155 *hcchar |= HCCHAR_ODDFRM; 1156 } 1157 } 1158 1159 STATIC void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) 1160 { 1161 /* Set up the initial PID for the transfer */ 1162 if (chan->speed == USB_SPEED_HIGH) { 1163 if (chan->ep_is_in) { 1164 if (chan->multi_count == 1) 1165 chan->data_pid_start = DWC2_HC_PID_DATA0; 1166 else if (chan->multi_count == 2) 1167 chan->data_pid_start = DWC2_HC_PID_DATA1; 1168 else 1169 chan->data_pid_start = DWC2_HC_PID_DATA2; 1170 } else { 1171 if (chan->multi_count == 1) 1172 chan->data_pid_start = DWC2_HC_PID_DATA0; 1173 else 1174 chan->data_pid_start = DWC2_HC_PID_MDATA; 1175 } 1176 } else { 1177 chan->data_pid_start = DWC2_HC_PID_DATA0; 1178 } 1179 } 1180 1181 /** 1182 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with 1183 * the Host Channel 1184 * 1185 * @hsotg: Programming view of DWC_otg controller 1186 * @chan: Information needed to initialize the host channel 1187 * 1188 * This function should only be called in Slave mode. For a channel associated 1189 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel 1190 * associated with a periodic EP, the periodic Tx FIFO is written. 1191 * 1192 * Upon return the xfer_buf and xfer_count fields in chan are incremented by 1193 * the number of bytes written to the Tx FIFO. 1194 */ 1195 STATIC void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 1196 struct dwc2_host_chan *chan) 1197 { 1198 u32 i; 1199 u32 remaining_count; 1200 u32 byte_count; 1201 u32 dword_count; 1202 u32 *data_buf = (u32 *)chan->xfer_buf; 1203 u32 data_fifo; 1204 1205 if (dbg_hc(chan)) 1206 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1207 1208 data_fifo = HCFIFO(chan->hc_num); 1209 1210 remaining_count = chan->xfer_len - chan->xfer_count; 1211 if (remaining_count > chan->max_packet) 1212 byte_count = chan->max_packet; 1213 else 1214 byte_count = remaining_count; 1215 1216 dword_count = (byte_count + 3) / 4; 1217 1218 if (((unsigned long)data_buf & 0x3) == 0) { 1219 /* xfer_buf is DWORD aligned */ 1220 for (i = 0; i < dword_count; i++, data_buf++) 1221 DWC2_WRITE_4(hsotg, data_fifo, *data_buf); 1222 } else { 1223 /* xfer_buf is not DWORD aligned */ 1224 for (i = 0; i < dword_count; i++, data_buf++) { 1225 u32 data = data_buf[0] | data_buf[1] << 8 | 1226 data_buf[2] << 16 | data_buf[3] << 24; 1227 DWC2_WRITE_4(hsotg, data_fifo, data); 1228 } 1229 } 1230 1231 chan->xfer_count += byte_count; 1232 chan->xfer_buf += byte_count; 1233 } 1234 1235 /** 1236 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host 1237 * channel and starts the transfer 1238 * 1239 * @hsotg: Programming view of DWC_otg controller 1240 * @chan: Information needed to initialize the host channel. The xfer_len value 1241 * may be reduced to accommodate the max widths of the XferSize and 1242 * PktCnt fields in the HCTSIZn register. The multi_count value may be 1243 * changed to reflect the final xfer_len value. 1244 * 1245 * This function may be called in either Slave mode or DMA mode. In Slave mode, 1246 * the caller must ensure that there is sufficient space in the request queue 1247 * and Tx Data FIFO. 1248 * 1249 * For an OUT transfer in Slave mode, it loads a data packet into the 1250 * appropriate FIFO. If necessary, additional data packets are loaded in the 1251 * Host ISR. 1252 * 1253 * For an IN transfer in Slave mode, a data packet is requested. The data 1254 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, 1255 * additional data packets are requested in the Host ISR. 1256 * 1257 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ 1258 * register along with a packet count of 1 and the channel is enabled. This 1259 * causes a single PING transaction to occur. Other fields in HCTSIZ are 1260 * simply set to 0 since no data transfer occurs in this case. 1261 * 1262 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with 1263 * all the information required to perform the subsequent data transfer. In 1264 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the 1265 * controller performs the entire PING protocol, then starts the data 1266 * transfer. 1267 */ 1268 void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 1269 struct dwc2_host_chan *chan) 1270 { 1271 u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size; 1272 u16 max_hc_pkt_count = hsotg->core_params->max_packet_count; 1273 u32 hcchar; 1274 u32 hctsiz = 0; 1275 u16 num_packets; 1276 1277 if (dbg_hc(chan)) 1278 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1279 1280 if (chan->do_ping) { 1281 if (hsotg->core_params->dma_enable <= 0) { 1282 if (dbg_hc(chan)) 1283 dev_vdbg(hsotg->dev, "ping, no DMA\n"); 1284 dwc2_hc_do_ping(hsotg, chan); 1285 chan->xfer_started = 1; 1286 return; 1287 } else { 1288 if (dbg_hc(chan)) 1289 dev_vdbg(hsotg->dev, "ping, DMA\n"); 1290 hctsiz |= TSIZ_DOPNG; 1291 } 1292 } 1293 1294 if (chan->do_split) { 1295 if (dbg_hc(chan)) 1296 dev_vdbg(hsotg->dev, "split\n"); 1297 num_packets = 1; 1298 1299 if (chan->complete_split && !chan->ep_is_in) 1300 /* 1301 * For CSPLIT OUT Transfer, set the size to 0 so the 1302 * core doesn't expect any data written to the FIFO 1303 */ 1304 chan->xfer_len = 0; 1305 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) 1306 chan->xfer_len = chan->max_packet; 1307 else if (!chan->ep_is_in && chan->xfer_len > 188) 1308 chan->xfer_len = 188; 1309 1310 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1311 TSIZ_XFERSIZE_MASK; 1312 } else { 1313 if (dbg_hc(chan)) 1314 dev_vdbg(hsotg->dev, "no split\n"); 1315 /* 1316 * Ensure that the transfer length and packet count will fit 1317 * in the widths allocated for them in the HCTSIZn register 1318 */ 1319 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1320 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1321 /* 1322 * Make sure the transfer size is no larger than one 1323 * (micro)frame's worth of data. (A check was done 1324 * when the periodic transfer was accepted to ensure 1325 * that a (micro)frame's worth of data can be 1326 * programmed into a channel.) 1327 */ 1328 u32 max_periodic_len = 1329 chan->multi_count * chan->max_packet; 1330 1331 if (chan->xfer_len > max_periodic_len) 1332 chan->xfer_len = max_periodic_len; 1333 } else if (chan->xfer_len > max_hc_xfer_size) { 1334 /* 1335 * Make sure that xfer_len is a multiple of max packet 1336 * size 1337 */ 1338 chan->xfer_len = 1339 max_hc_xfer_size - chan->max_packet + 1; 1340 } 1341 1342 if (chan->xfer_len > 0) { 1343 num_packets = (chan->xfer_len + chan->max_packet - 1) / 1344 chan->max_packet; 1345 if (num_packets > max_hc_pkt_count) { 1346 num_packets = max_hc_pkt_count; 1347 chan->xfer_len = num_packets * chan->max_packet; 1348 } 1349 } else { 1350 /* Need 1 packet for transfer length of 0 */ 1351 num_packets = 1; 1352 } 1353 1354 if (chan->ep_is_in) 1355 /* 1356 * Always program an integral # of max packets for IN 1357 * transfers 1358 */ 1359 chan->xfer_len = num_packets * chan->max_packet; 1360 1361 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1362 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1363 /* 1364 * Make sure that the multi_count field matches the 1365 * actual transfer length 1366 */ 1367 chan->multi_count = num_packets; 1368 1369 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1370 dwc2_set_pid_isoc(chan); 1371 1372 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1373 TSIZ_XFERSIZE_MASK; 1374 } 1375 1376 chan->start_pkt_count = num_packets; 1377 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1378 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1379 TSIZ_SC_MC_PID_MASK; 1380 DWC2_WRITE_4(hsotg, HCTSIZ(chan->hc_num), hctsiz); 1381 if (dbg_hc(chan)) { 1382 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1383 hctsiz, chan->hc_num); 1384 1385 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1386 chan->hc_num); 1387 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", 1388 (hctsiz & TSIZ_XFERSIZE_MASK) >> 1389 TSIZ_XFERSIZE_SHIFT); 1390 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", 1391 (hctsiz & TSIZ_PKTCNT_MASK) >> 1392 TSIZ_PKTCNT_SHIFT); 1393 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1394 (hctsiz & TSIZ_SC_MC_PID_MASK) >> 1395 TSIZ_SC_MC_PID_SHIFT); 1396 } 1397 1398 if (hsotg->core_params->dma_enable > 0) { 1399 dma_addr_t dma_addr; 1400 1401 if (chan->align_buf) { 1402 if (dbg_hc(chan)) 1403 dev_vdbg(hsotg->dev, "align_buf\n"); 1404 dma_addr = chan->align_buf; 1405 } else { 1406 dma_addr = chan->xfer_dma; 1407 } 1408 struct dwc2_core_dma_config *dma_config = 1409 hsotg->core_dma_config; 1410 if (dma_config == NULL) { 1411 DWC2_WRITE_4(hsotg, HCDMA(chan->hc_num), 1412 (u32)dma_addr); 1413 if (dbg_hc(chan)) 1414 dev_vdbg(hsotg->dev, 1415 "Wrote %08lx to HCDMA(%d)\n", 1416 (unsigned long)dma_addr, 1417 chan->hc_num); 1418 } else { 1419 (void)(*dma_config->set_dma_addr)( 1420 dma_config->set_dma_addr_data, dma_addr, 1421 chan->hc_num); 1422 } 1423 } 1424 1425 /* Start the split */ 1426 if (chan->do_split) { 1427 u32 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chan->hc_num)); 1428 1429 hcsplt |= HCSPLT_SPLTENA; 1430 DWC2_WRITE_4(hsotg, HCSPLT(chan->hc_num), hcsplt); 1431 } 1432 1433 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1434 hcchar &= ~HCCHAR_MULTICNT_MASK; 1435 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1436 HCCHAR_MULTICNT_MASK; 1437 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1438 1439 if (hcchar & HCCHAR_CHDIS) 1440 dev_warn(hsotg->dev, 1441 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1442 __func__, chan->hc_num, hcchar); 1443 1444 /* Set host channel enable after all other setup is complete */ 1445 hcchar |= HCCHAR_CHENA; 1446 hcchar &= ~HCCHAR_CHDIS; 1447 1448 if (dbg_hc(chan)) 1449 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1450 (hcchar & HCCHAR_MULTICNT_MASK) >> 1451 HCCHAR_MULTICNT_SHIFT); 1452 1453 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 1454 if (dbg_hc(chan)) 1455 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1456 chan->hc_num); 1457 1458 chan->xfer_started = 1; 1459 chan->requests++; 1460 1461 if (hsotg->core_params->dma_enable <= 0 && 1462 !chan->ep_is_in && chan->xfer_len > 0) 1463 /* Load OUT packet into the appropriate Tx FIFO */ 1464 dwc2_hc_write_packet(hsotg, chan); 1465 } 1466 1467 /** 1468 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a 1469 * host channel and starts the transfer in Descriptor DMA mode 1470 * 1471 * @hsotg: Programming view of DWC_otg controller 1472 * @chan: Information needed to initialize the host channel 1473 * 1474 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. 1475 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field 1476 * with micro-frame bitmap. 1477 * 1478 * Initializes HCDMA register with descriptor list address and CTD value then 1479 * starts the transfer via enabling the channel. 1480 */ 1481 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 1482 struct dwc2_host_chan *chan) 1483 { 1484 u32 hcchar; 1485 u32 hc_dma; 1486 u32 hctsiz = 0; 1487 1488 if (chan->do_ping) 1489 hctsiz |= TSIZ_DOPNG; 1490 1491 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1492 dwc2_set_pid_isoc(chan); 1493 1494 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ 1495 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1496 TSIZ_SC_MC_PID_MASK; 1497 1498 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ 1499 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; 1500 1501 /* Non-zero only for high-speed interrupt endpoints */ 1502 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; 1503 1504 if (dbg_hc(chan)) { 1505 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1506 chan->hc_num); 1507 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1508 chan->data_pid_start); 1509 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 1510 } 1511 1512 DWC2_WRITE_4(hsotg, HCTSIZ(chan->hc_num), hctsiz); 1513 1514 hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK; 1515 1516 /* Always start from first descriptor */ 1517 hc_dma &= ~HCDMA_CTD_MASK; 1518 DWC2_WRITE_4(hsotg, HCDMA(chan->hc_num), hc_dma); 1519 if (dbg_hc(chan)) 1520 dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n", 1521 hc_dma, chan->hc_num); 1522 1523 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1524 hcchar &= ~HCCHAR_MULTICNT_MASK; 1525 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1526 HCCHAR_MULTICNT_MASK; 1527 1528 if (hcchar & HCCHAR_CHDIS) 1529 dev_warn(hsotg->dev, 1530 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1531 __func__, chan->hc_num, hcchar); 1532 1533 /* Set host channel enable after all other setup is complete */ 1534 hcchar |= HCCHAR_CHENA; 1535 hcchar &= ~HCCHAR_CHDIS; 1536 1537 if (dbg_hc(chan)) 1538 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1539 (hcchar & HCCHAR_MULTICNT_MASK) >> 1540 HCCHAR_MULTICNT_SHIFT); 1541 1542 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 1543 if (dbg_hc(chan)) 1544 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1545 chan->hc_num); 1546 1547 chan->xfer_started = 1; 1548 chan->requests++; 1549 } 1550 1551 /** 1552 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by 1553 * a previous call to dwc2_hc_start_transfer() 1554 * 1555 * @hsotg: Programming view of DWC_otg controller 1556 * @chan: Information needed to initialize the host channel 1557 * 1558 * The caller must ensure there is sufficient space in the request queue and Tx 1559 * Data FIFO. This function should only be called in Slave mode. In DMA mode, 1560 * the controller acts autonomously to complete transfers programmed to a host 1561 * channel. 1562 * 1563 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO 1564 * if there is any data remaining to be queued. For an IN transfer, another 1565 * data packet is always requested. For the SETUP phase of a control transfer, 1566 * this function does nothing. 1567 * 1568 * Return: 1 if a new request is queued, 0 if no more requests are required 1569 * for this transfer 1570 */ 1571 int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 1572 struct dwc2_host_chan *chan) 1573 { 1574 if (dbg_hc(chan)) 1575 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1576 chan->hc_num); 1577 1578 if (chan->do_split) 1579 /* SPLITs always queue just once per channel */ 1580 return 0; 1581 1582 if (chan->data_pid_start == DWC2_HC_PID_SETUP) 1583 /* SETUPs are queued only once since they can't be NAK'd */ 1584 return 0; 1585 1586 if (chan->ep_is_in) { 1587 /* 1588 * Always queue another request for other IN transfers. If 1589 * back-to-back INs are issued and NAKs are received for both, 1590 * the driver may still be processing the first NAK when the 1591 * second NAK is received. When the interrupt handler clears 1592 * the NAK interrupt for the first NAK, the second NAK will 1593 * not be seen. So we can't depend on the NAK interrupt 1594 * handler to requeue a NAK'd request. Instead, IN requests 1595 * are issued each time this function is called. When the 1596 * transfer completes, the extra requests for the channel will 1597 * be flushed. 1598 */ 1599 u32 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1600 1601 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1602 hcchar |= HCCHAR_CHENA; 1603 hcchar &= ~HCCHAR_CHDIS; 1604 if (dbg_hc(chan)) 1605 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 1606 hcchar); 1607 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 1608 chan->requests++; 1609 return 1; 1610 } 1611 1612 /* OUT transfers */ 1613 1614 if (chan->xfer_count < chan->xfer_len) { 1615 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1616 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1617 u32 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1618 1619 dwc2_hc_set_even_odd_frame(hsotg, chan, 1620 &hcchar); 1621 } 1622 1623 /* Load OUT packet into the appropriate Tx FIFO */ 1624 dwc2_hc_write_packet(hsotg, chan); 1625 chan->requests++; 1626 return 1; 1627 } 1628 1629 return 0; 1630 } 1631 1632 /** 1633 * dwc2_hc_do_ping() - Starts a PING transfer 1634 * 1635 * @hsotg: Programming view of DWC_otg controller 1636 * @chan: Information needed to initialize the host channel 1637 * 1638 * This function should only be called in Slave mode. The Do Ping bit is set in 1639 * the HCTSIZ register, then the channel is enabled. 1640 */ 1641 void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1642 { 1643 u32 hcchar; 1644 u32 hctsiz; 1645 1646 if (dbg_hc(chan)) 1647 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1648 chan->hc_num); 1649 1650 1651 hctsiz = TSIZ_DOPNG; 1652 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 1653 DWC2_WRITE_4(hsotg, HCTSIZ(chan->hc_num), hctsiz); 1654 1655 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1656 hcchar |= HCCHAR_CHENA; 1657 hcchar &= ~HCCHAR_CHDIS; 1658 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 1659 } 1660 1661 /** 1662 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for 1663 * the HFIR register according to PHY type and speed 1664 * 1665 * @hsotg: Programming view of DWC_otg controller 1666 * 1667 * NOTE: The caller can modify the value of the HFIR register only after the 1668 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) 1669 * has been set 1670 */ 1671 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 1672 { 1673 u32 usbcfg; 1674 u32 hprt0; 1675 int clock = 60; /* default value */ 1676 1677 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 1678 hprt0 = DWC2_READ_4(hsotg, HPRT0); 1679 1680 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 1681 !(usbcfg & GUSBCFG_PHYIF16)) 1682 clock = 60; 1683 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == 1684 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) 1685 clock = 48; 1686 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 1687 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 1688 clock = 30; 1689 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 1690 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) 1691 clock = 60; 1692 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 1693 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 1694 clock = 48; 1695 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && 1696 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) 1697 clock = 48; 1698 if ((usbcfg & GUSBCFG_PHYSEL) && 1699 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 1700 clock = 48; 1701 1702 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) 1703 /* High speed case */ 1704 return 125 * clock; 1705 else 1706 /* FS/LS case */ 1707 return 1000 * clock; 1708 } 1709 1710 /** 1711 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination 1712 * buffer 1713 * 1714 * @core_if: Programming view of DWC_otg controller 1715 * @dest: Destination buffer for the packet 1716 * @bytes: Number of bytes to copy to the destination 1717 */ 1718 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 1719 { 1720 bus_size_t fifo = HCFIFO(0); 1721 u32 *data_buf = (u32 *)dest; 1722 int word_count = (bytes + 3) / 4; 1723 int i; 1724 1725 /* 1726 * Todo: Account for the case where dest is not dword aligned. This 1727 * requires reading data from the FIFO into a u32 temp buffer, then 1728 * moving it into the data buffer. 1729 */ 1730 1731 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 1732 1733 for (i = 0; i < word_count; i++, data_buf++) 1734 *data_buf = DWC2_READ_4(hsotg, fifo); 1735 } 1736 1737 /** 1738 * dwc2_dump_host_registers() - Prints the host registers 1739 * 1740 * @hsotg: Programming view of DWC_otg controller 1741 * 1742 * NOTE: This function will be removed once the peripheral controller code 1743 * is integrated and the driver is stable 1744 */ 1745 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) 1746 { 1747 #ifdef DWC2_DEBUG 1748 bus_size_t addr; 1749 int i; 1750 1751 dev_dbg(hsotg->dev, "Host Global Registers\n"); 1752 addr = HCFG; 1753 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", 1754 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1755 addr = HFIR; 1756 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", 1757 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1758 addr = HFNUM; 1759 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", 1760 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1761 addr = HPTXSTS; 1762 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", 1763 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1764 addr = HAINT; 1765 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", 1766 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1767 addr = HAINTMSK; 1768 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", 1769 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1770 if (hsotg->core_params->dma_desc_enable > 0) { 1771 addr = HFLBADDR; 1772 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", 1773 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1774 } 1775 1776 addr = HPRT0; 1777 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", 1778 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1779 1780 for (i = 0; i < hsotg->core_params->host_channels; i++) { 1781 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); 1782 addr = HCCHAR(i); 1783 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", 1784 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1785 addr = HCSPLT(i); 1786 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", 1787 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1788 addr = HCINT(i); 1789 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", 1790 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1791 addr = HCINTMSK(i); 1792 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", 1793 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1794 addr = HCTSIZ(i); 1795 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", 1796 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1797 addr = HCDMA(i); 1798 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", 1799 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1800 if (hsotg->core_params->dma_desc_enable > 0) { 1801 addr = HCDMAB(i); 1802 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", 1803 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1804 } 1805 } 1806 #endif 1807 } 1808 1809 /** 1810 * dwc2_dump_global_registers() - Prints the core global registers 1811 * 1812 * @hsotg: Programming view of DWC_otg controller 1813 * 1814 * NOTE: This function will be removed once the peripheral controller code 1815 * is integrated and the driver is stable 1816 */ 1817 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) 1818 { 1819 #ifdef DWC2_DEBUG 1820 bus_size_t addr; 1821 1822 dev_dbg(hsotg->dev, "Core Global Registers\n"); 1823 addr = GOTGCTL; 1824 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", 1825 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1826 addr = GOTGINT; 1827 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", 1828 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1829 addr = GAHBCFG; 1830 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", 1831 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1832 addr = GUSBCFG; 1833 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", 1834 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1835 addr = GRSTCTL; 1836 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", 1837 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1838 addr = GINTSTS; 1839 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", 1840 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1841 addr = GINTMSK; 1842 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", 1843 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1844 addr = GRXSTSR; 1845 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", 1846 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1847 addr = GRXFSIZ; 1848 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", 1849 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1850 addr = GNPTXFSIZ; 1851 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", 1852 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1853 addr = GNPTXSTS; 1854 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", 1855 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1856 addr = GI2CCTL; 1857 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", 1858 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1859 addr = GPVNDCTL; 1860 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", 1861 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1862 addr = GGPIO; 1863 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", 1864 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1865 addr = GUID; 1866 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", 1867 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1868 addr = GSNPSID; 1869 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", 1870 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1871 addr = GHWCFG1; 1872 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", 1873 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1874 addr = GHWCFG2; 1875 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", 1876 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1877 addr = GHWCFG3; 1878 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", 1879 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1880 addr = GHWCFG4; 1881 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", 1882 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1883 addr = GLPMCFG; 1884 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", 1885 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1886 addr = GPWRDN; 1887 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", 1888 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1889 addr = GDFIFOCFG; 1890 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", 1891 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1892 addr = HPTXFSIZ; 1893 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", 1894 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1895 1896 addr = PCGCTL; 1897 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", 1898 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 1899 #endif 1900 } 1901 1902 /** 1903 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO 1904 * 1905 * @hsotg: Programming view of DWC_otg controller 1906 * @num: Tx FIFO to flush 1907 */ 1908 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) 1909 { 1910 u32 greset; 1911 int count = 0; 1912 1913 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); 1914 1915 greset = GRSTCTL_TXFFLSH; 1916 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; 1917 DWC2_WRITE_4(hsotg, GRSTCTL, greset); 1918 1919 do { 1920 greset = DWC2_READ_4(hsotg, GRSTCTL); 1921 if (++count > 10000) { 1922 dev_warn(hsotg->dev, 1923 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", 1924 __func__, greset, 1925 DWC2_READ_4(hsotg, GNPTXSTS)); 1926 break; 1927 } 1928 udelay(1); 1929 } while (greset & GRSTCTL_TXFFLSH); 1930 1931 /* Wait for at least 3 PHY Clocks */ 1932 udelay(1); 1933 } 1934 1935 /** 1936 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO 1937 * 1938 * @hsotg: Programming view of DWC_otg controller 1939 */ 1940 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) 1941 { 1942 u32 greset; 1943 int count = 0; 1944 1945 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1946 1947 greset = GRSTCTL_RXFFLSH; 1948 DWC2_WRITE_4(hsotg, GRSTCTL, greset); 1949 1950 do { 1951 greset = DWC2_READ_4(hsotg, GRSTCTL); 1952 if (++count > 10000) { 1953 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", 1954 __func__, greset); 1955 break; 1956 } 1957 udelay(1); 1958 } while (greset & GRSTCTL_RXFFLSH); 1959 1960 /* Wait for at least 3 PHY Clocks */ 1961 udelay(1); 1962 } 1963 1964 #define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c)) 1965 1966 /* Parameter access functions */ 1967 void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val) 1968 { 1969 int valid = 1; 1970 1971 switch (val) { 1972 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 1973 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 1974 valid = 0; 1975 break; 1976 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 1977 switch (hsotg->hw_params.op_mode) { 1978 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 1979 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 1980 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 1981 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 1982 break; 1983 default: 1984 valid = 0; 1985 break; 1986 } 1987 break; 1988 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 1989 /* always valid */ 1990 break; 1991 default: 1992 valid = 0; 1993 break; 1994 } 1995 1996 if (!valid) { 1997 if (val >= 0) 1998 dev_err(hsotg->dev, 1999 "%d invalid for otg_cap parameter. Check HW configuration.\n", 2000 val); 2001 switch (hsotg->hw_params.op_mode) { 2002 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 2003 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 2004 break; 2005 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 2006 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 2007 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 2008 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 2009 break; 2010 default: 2011 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 2012 break; 2013 } 2014 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val); 2015 } 2016 2017 hsotg->core_params->otg_cap = val; 2018 } 2019 2020 void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val) 2021 { 2022 int valid = 1; 2023 2024 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH) 2025 valid = 0; 2026 if (val < 0) 2027 valid = 0; 2028 2029 if (!valid) { 2030 if (val >= 0) 2031 dev_err(hsotg->dev, 2032 "%d invalid for dma_enable parameter. Check HW configuration.\n", 2033 val); 2034 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH; 2035 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val); 2036 } 2037 2038 hsotg->core_params->dma_enable = val; 2039 } 2040 2041 void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val) 2042 { 2043 int valid = 1; 2044 2045 if (val > 0 && (hsotg->core_params->dma_enable <= 0 || 2046 !hsotg->hw_params.dma_desc_enable)) 2047 valid = 0; 2048 if (val < 0) 2049 valid = 0; 2050 2051 if (!valid) { 2052 if (val >= 0) 2053 dev_err(hsotg->dev, 2054 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n", 2055 val); 2056 val = (hsotg->core_params->dma_enable > 0 && 2057 hsotg->hw_params.dma_desc_enable); 2058 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val); 2059 } 2060 2061 hsotg->core_params->dma_desc_enable = val; 2062 } 2063 2064 void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, 2065 int val) 2066 { 2067 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2068 if (val >= 0) { 2069 dev_err(hsotg->dev, 2070 "Wrong value for host_support_fs_low_power\n"); 2071 dev_err(hsotg->dev, 2072 "host_support_fs_low_power must be 0 or 1\n"); 2073 } 2074 val = 0; 2075 dev_dbg(hsotg->dev, 2076 "Setting host_support_fs_low_power to %d\n", val); 2077 } 2078 2079 hsotg->core_params->host_support_fs_ls_low_power = val; 2080 } 2081 2082 void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val) 2083 { 2084 int valid = 1; 2085 2086 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo) 2087 valid = 0; 2088 if (val < 0) 2089 valid = 0; 2090 2091 if (!valid) { 2092 if (val >= 0) 2093 dev_err(hsotg->dev, 2094 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n", 2095 val); 2096 val = hsotg->hw_params.enable_dynamic_fifo; 2097 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val); 2098 } 2099 2100 hsotg->core_params->enable_dynamic_fifo = val; 2101 } 2102 2103 void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val) 2104 { 2105 int valid = 1; 2106 2107 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size) 2108 valid = 0; 2109 2110 if (!valid) { 2111 if (val >= 0) 2112 dev_err(hsotg->dev, 2113 "%d invalid for host_rx_fifo_size. Check HW configuration.\n", 2114 val); 2115 val = hsotg->hw_params.host_rx_fifo_size; 2116 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val); 2117 } 2118 2119 hsotg->core_params->host_rx_fifo_size = val; 2120 } 2121 2122 void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) 2123 { 2124 int valid = 1; 2125 2126 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size) 2127 valid = 0; 2128 2129 if (!valid) { 2130 if (val >= 0) 2131 dev_err(hsotg->dev, 2132 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n", 2133 val); 2134 val = hsotg->hw_params.host_nperio_tx_fifo_size; 2135 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n", 2136 val); 2137 } 2138 2139 hsotg->core_params->host_nperio_tx_fifo_size = val; 2140 } 2141 2142 void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) 2143 { 2144 int valid = 1; 2145 2146 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size) 2147 valid = 0; 2148 2149 if (!valid) { 2150 if (val >= 0) 2151 dev_err(hsotg->dev, 2152 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", 2153 val); 2154 val = hsotg->hw_params.host_perio_tx_fifo_size; 2155 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", 2156 val); 2157 } 2158 2159 hsotg->core_params->host_perio_tx_fifo_size = val; 2160 } 2161 2162 void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val) 2163 { 2164 int valid = 1; 2165 2166 if (val < 2047 || val > hsotg->hw_params.max_transfer_size) 2167 valid = 0; 2168 2169 if (!valid) { 2170 if (val >= 0) 2171 dev_err(hsotg->dev, 2172 "%d invalid for max_transfer_size. Check HW configuration.\n", 2173 val); 2174 val = hsotg->hw_params.max_transfer_size; 2175 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); 2176 } 2177 2178 hsotg->core_params->max_transfer_size = val; 2179 } 2180 2181 void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val) 2182 { 2183 int valid = 1; 2184 2185 if (val < 15 || val > hsotg->hw_params.max_packet_count) 2186 valid = 0; 2187 2188 if (!valid) { 2189 if (val >= 0) 2190 dev_err(hsotg->dev, 2191 "%d invalid for max_packet_count. Check HW configuration.\n", 2192 val); 2193 val = hsotg->hw_params.max_packet_count; 2194 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); 2195 } 2196 2197 hsotg->core_params->max_packet_count = val; 2198 } 2199 2200 void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val) 2201 { 2202 int valid = 1; 2203 2204 if (val < 1 || val > hsotg->hw_params.host_channels) 2205 valid = 0; 2206 2207 if (!valid) { 2208 if (val >= 0) 2209 dev_err(hsotg->dev, 2210 "%d invalid for host_channels. Check HW configuration.\n", 2211 val); 2212 val = hsotg->hw_params.host_channels; 2213 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val); 2214 } 2215 2216 hsotg->core_params->host_channels = val; 2217 } 2218 2219 void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) 2220 { 2221 int valid = 0; 2222 u32 hs_phy_type, fs_phy_type; 2223 2224 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS, 2225 DWC2_PHY_TYPE_PARAM_ULPI)) { 2226 if (val >= 0) { 2227 dev_err(hsotg->dev, "Wrong value for phy_type\n"); 2228 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n"); 2229 } 2230 2231 valid = 0; 2232 } 2233 2234 hs_phy_type = hsotg->hw_params.hs_phy_type; 2235 fs_phy_type = hsotg->hw_params.fs_phy_type; 2236 if (val == DWC2_PHY_TYPE_PARAM_UTMI && 2237 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 2238 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 2239 valid = 1; 2240 else if (val == DWC2_PHY_TYPE_PARAM_ULPI && 2241 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI || 2242 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 2243 valid = 1; 2244 else if (val == DWC2_PHY_TYPE_PARAM_FS && 2245 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 2246 valid = 1; 2247 2248 if (!valid) { 2249 if (val >= 0) 2250 dev_err(hsotg->dev, 2251 "%d invalid for phy_type. Check HW configuration.\n", 2252 val); 2253 val = DWC2_PHY_TYPE_PARAM_FS; 2254 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 2255 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 2256 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 2257 val = DWC2_PHY_TYPE_PARAM_UTMI; 2258 else 2259 val = DWC2_PHY_TYPE_PARAM_ULPI; 2260 } 2261 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); 2262 } 2263 2264 hsotg->core_params->phy_type = val; 2265 } 2266 2267 STATIC int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg) 2268 { 2269 return hsotg->core_params->phy_type; 2270 } 2271 2272 void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val) 2273 { 2274 int valid = 1; 2275 2276 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2277 if (val >= 0) { 2278 dev_err(hsotg->dev, "Wrong value for speed parameter\n"); 2279 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n"); 2280 } 2281 valid = 0; 2282 } 2283 2284 if (val == DWC2_SPEED_PARAM_HIGH && 2285 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) 2286 valid = 0; 2287 2288 if (!valid) { 2289 if (val >= 0) 2290 dev_err(hsotg->dev, 2291 "%d invalid for speed parameter. Check HW configuration.\n", 2292 val); 2293 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ? 2294 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 2295 dev_dbg(hsotg->dev, "Setting speed to %d\n", val); 2296 } 2297 2298 hsotg->core_params->speed = val; 2299 } 2300 2301 void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val) 2302 { 2303 int valid = 1; 2304 2305 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ, 2306 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) { 2307 if (val >= 0) { 2308 dev_err(hsotg->dev, 2309 "Wrong value for host_ls_low_power_phy_clk parameter\n"); 2310 dev_err(hsotg->dev, 2311 "host_ls_low_power_phy_clk must be 0 or 1\n"); 2312 } 2313 valid = 0; 2314 } 2315 2316 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ && 2317 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) 2318 valid = 0; 2319 2320 if (!valid) { 2321 if (val >= 0) 2322 dev_err(hsotg->dev, 2323 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", 2324 val); 2325 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS 2326 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 2327 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ; 2328 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n", 2329 val); 2330 } 2331 2332 hsotg->core_params->host_ls_low_power_phy_clk = val; 2333 } 2334 2335 void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val) 2336 { 2337 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2338 if (val >= 0) { 2339 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n"); 2340 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n"); 2341 } 2342 val = 0; 2343 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val); 2344 } 2345 2346 hsotg->core_params->phy_ulpi_ddr = val; 2347 } 2348 2349 void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val) 2350 { 2351 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2352 if (val >= 0) { 2353 dev_err(hsotg->dev, 2354 "Wrong value for phy_ulpi_ext_vbus\n"); 2355 dev_err(hsotg->dev, 2356 "phy_ulpi_ext_vbus must be 0 or 1\n"); 2357 } 2358 val = 0; 2359 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val); 2360 } 2361 2362 hsotg->core_params->phy_ulpi_ext_vbus = val; 2363 } 2364 2365 void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) 2366 { 2367 int valid = 0; 2368 2369 switch (hsotg->hw_params.utmi_phy_data_width) { 2370 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 2371 valid = (val == 8); 2372 break; 2373 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 2374 valid = (val == 16); 2375 break; 2376 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 2377 valid = (val == 8 || val == 16); 2378 break; 2379 } 2380 2381 if (!valid) { 2382 if (val >= 0) { 2383 dev_err(hsotg->dev, 2384 "%d invalid for phy_utmi_width. Check HW configuration.\n", 2385 val); 2386 } 2387 val = (hsotg->hw_params.utmi_phy_data_width == 2388 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 2389 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); 2390 } 2391 2392 hsotg->core_params->phy_utmi_width = val; 2393 } 2394 2395 void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val) 2396 { 2397 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2398 if (val >= 0) { 2399 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n"); 2400 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n"); 2401 } 2402 val = 0; 2403 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val); 2404 } 2405 2406 hsotg->core_params->ulpi_fs_ls = val; 2407 } 2408 2409 void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val) 2410 { 2411 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2412 if (val >= 0) { 2413 dev_err(hsotg->dev, "Wrong value for ts_dline\n"); 2414 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n"); 2415 } 2416 val = 0; 2417 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val); 2418 } 2419 2420 hsotg->core_params->ts_dline = val; 2421 } 2422 2423 void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val) 2424 { 2425 int valid = 1; 2426 2427 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2428 if (val >= 0) { 2429 dev_err(hsotg->dev, "Wrong value for i2c_enable\n"); 2430 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n"); 2431 } 2432 2433 valid = 0; 2434 } 2435 2436 if (val == 1 && !(hsotg->hw_params.i2c_enable)) 2437 valid = 0; 2438 2439 if (!valid) { 2440 if (val >= 0) 2441 dev_err(hsotg->dev, 2442 "%d invalid for i2c_enable. Check HW configuration.\n", 2443 val); 2444 val = hsotg->hw_params.i2c_enable; 2445 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); 2446 } 2447 2448 hsotg->core_params->i2c_enable = val; 2449 } 2450 2451 void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val) 2452 { 2453 int valid = 1; 2454 2455 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2456 if (val >= 0) { 2457 dev_err(hsotg->dev, 2458 "Wrong value for en_multiple_tx_fifo,\n"); 2459 dev_err(hsotg->dev, 2460 "en_multiple_tx_fifo must be 0 or 1\n"); 2461 } 2462 valid = 0; 2463 } 2464 2465 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo) 2466 valid = 0; 2467 2468 if (!valid) { 2469 if (val >= 0) 2470 dev_err(hsotg->dev, 2471 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", 2472 val); 2473 val = hsotg->hw_params.en_multiple_tx_fifo; 2474 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val); 2475 } 2476 2477 hsotg->core_params->en_multiple_tx_fifo = val; 2478 } 2479 2480 void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val) 2481 { 2482 int valid = 1; 2483 2484 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2485 if (val >= 0) { 2486 dev_err(hsotg->dev, 2487 "'%d' invalid for parameter reload_ctl\n", val); 2488 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n"); 2489 } 2490 valid = 0; 2491 } 2492 2493 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a) 2494 valid = 0; 2495 2496 if (!valid) { 2497 if (val >= 0) 2498 dev_err(hsotg->dev, 2499 "%d invalid for parameter reload_ctl. Check HW configuration.\n", 2500 val); 2501 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a; 2502 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val); 2503 } 2504 2505 hsotg->core_params->reload_ctl = val; 2506 } 2507 2508 void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) 2509 { 2510 if (val != -1) 2511 hsotg->core_params->ahbcfg = val; 2512 else 2513 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << 2514 GAHBCFG_HBSTLEN_SHIFT; 2515 } 2516 2517 void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) 2518 { 2519 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2520 if (val >= 0) { 2521 dev_err(hsotg->dev, 2522 "'%d' invalid for parameter otg_ver\n", val); 2523 dev_err(hsotg->dev, 2524 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n"); 2525 } 2526 val = 0; 2527 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val); 2528 } 2529 2530 hsotg->core_params->otg_ver = val; 2531 } 2532 2533 STATIC void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val) 2534 { 2535 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2536 if (val >= 0) { 2537 dev_err(hsotg->dev, 2538 "'%d' invalid for parameter uframe_sched\n", 2539 val); 2540 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n"); 2541 } 2542 val = 1; 2543 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); 2544 } 2545 2546 hsotg->core_params->uframe_sched = val; 2547 } 2548 2549 /* 2550 * This function is called during module intialization to pass module parameters 2551 * for the DWC_otg core. 2552 */ 2553 void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 2554 const struct dwc2_core_params *params) 2555 { 2556 dev_dbg(hsotg->dev, "%s()\n", __func__); 2557 2558 dwc2_set_param_otg_cap(hsotg, params->otg_cap); 2559 dwc2_set_param_dma_enable(hsotg, params->dma_enable); 2560 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable); 2561 dwc2_set_param_host_support_fs_ls_low_power(hsotg, 2562 params->host_support_fs_ls_low_power); 2563 dwc2_set_param_enable_dynamic_fifo(hsotg, 2564 params->enable_dynamic_fifo); 2565 dwc2_set_param_host_rx_fifo_size(hsotg, 2566 params->host_rx_fifo_size); 2567 dwc2_set_param_host_nperio_tx_fifo_size(hsotg, 2568 params->host_nperio_tx_fifo_size); 2569 dwc2_set_param_host_perio_tx_fifo_size(hsotg, 2570 params->host_perio_tx_fifo_size); 2571 dwc2_set_param_max_transfer_size(hsotg, 2572 params->max_transfer_size); 2573 dwc2_set_param_max_packet_count(hsotg, 2574 params->max_packet_count); 2575 dwc2_set_param_host_channels(hsotg, params->host_channels); 2576 dwc2_set_param_phy_type(hsotg, params->phy_type); 2577 dwc2_set_param_speed(hsotg, params->speed); 2578 dwc2_set_param_host_ls_low_power_phy_clk(hsotg, 2579 params->host_ls_low_power_phy_clk); 2580 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); 2581 dwc2_set_param_phy_ulpi_ext_vbus(hsotg, 2582 params->phy_ulpi_ext_vbus); 2583 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); 2584 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); 2585 dwc2_set_param_ts_dline(hsotg, params->ts_dline); 2586 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); 2587 dwc2_set_param_en_multiple_tx_fifo(hsotg, 2588 params->en_multiple_tx_fifo); 2589 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); 2590 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); 2591 dwc2_set_param_otg_ver(hsotg, params->otg_ver); 2592 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched); 2593 } 2594 2595 /** 2596 * During device initialization, read various hardware configuration 2597 * registers and interpret the contents. 2598 */ 2599 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 2600 { 2601 struct dwc2_hw_params *hw = &hsotg->hw_params; 2602 unsigned width; 2603 u32 hwcfg2, hwcfg3, hwcfg4; 2604 u32 hptxfsiz, grxfsiz, gnptxfsiz; 2605 u32 gusbcfg; 2606 2607 /* 2608 * Attempt to ensure this device is really a DWC_otg Controller. 2609 * Read and verify the GSNPSID register contents. The value should be 2610 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", 2611 * as in "OTG version 2.xx" or "OTG version 3.xx". 2612 */ 2613 hw->snpsid = DWC2_READ_4(hsotg, GSNPSID); 2614 if ((hw->snpsid & 0xfffff000) != 0x4f542000 && 2615 (hw->snpsid & 0xfffff000) != 0x4f543000) { 2616 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 2617 hw->snpsid); 2618 return -ENODEV; 2619 } 2620 2621 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 2622 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 2623 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 2624 2625 hwcfg2 = DWC2_READ_4(hsotg, GHWCFG2); 2626 hwcfg3 = DWC2_READ_4(hsotg, GHWCFG3); 2627 hwcfg4 = DWC2_READ_4(hsotg, GHWCFG4); 2628 gnptxfsiz = DWC2_READ_4(hsotg, GNPTXFSIZ); 2629 grxfsiz = DWC2_READ_4(hsotg, GRXFSIZ); 2630 2631 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", DWC2_READ_4(hsotg, GHWCFG1)); 2632 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); 2633 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3); 2634 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4); 2635 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); 2636 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); 2637 2638 /* Force host mode to get HPTXFSIZ exact power on value */ 2639 gusbcfg = DWC2_READ_4(hsotg, GUSBCFG); 2640 gusbcfg |= GUSBCFG_FORCEHOSTMODE; 2641 DWC2_WRITE_4(hsotg, GUSBCFG, gusbcfg); 2642 usleep_range(100000, 150000); 2643 2644 hptxfsiz = DWC2_READ_4(hsotg, HPTXFSIZ); 2645 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); 2646 gusbcfg = DWC2_READ_4(hsotg, GUSBCFG); 2647 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; 2648 DWC2_WRITE_4(hsotg, GUSBCFG, gusbcfg); 2649 usleep_range(100000, 150000); 2650 2651 /* hwcfg2 */ 2652 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 2653 GHWCFG2_OP_MODE_SHIFT; 2654 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 2655 GHWCFG2_ARCHITECTURE_SHIFT; 2656 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 2657 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 2658 GHWCFG2_NUM_HOST_CHAN_SHIFT); 2659 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 2660 GHWCFG2_HS_PHY_TYPE_SHIFT; 2661 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 2662 GHWCFG2_FS_PHY_TYPE_SHIFT; 2663 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 2664 GHWCFG2_NUM_DEV_EP_SHIFT; 2665 hw->nperio_tx_q_depth = 2666 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 2667 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 2668 hw->host_perio_tx_q_depth = 2669 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 2670 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 2671 hw->dev_token_q_depth = 2672 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 2673 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 2674 2675 /* hwcfg3 */ 2676 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 2677 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 2678 hw->max_transfer_size = (1 << (width + 11)) - 1; 2679 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 2680 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 2681 hw->max_packet_count = (1 << (width + 4)) - 1; 2682 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 2683 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 2684 GHWCFG3_DFIFO_DEPTH_SHIFT; 2685 2686 /* hwcfg4 */ 2687 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 2688 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 2689 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 2690 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 2691 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 2692 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 2693 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 2694 2695 /* fifo sizes */ 2696 hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 2697 GRXFSIZ_DEPTH_SHIFT; 2698 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 2699 FIFOSIZE_DEPTH_SHIFT; 2700 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 2701 FIFOSIZE_DEPTH_SHIFT; 2702 2703 dev_dbg(hsotg->dev, "Detected values from hardware:\n"); 2704 dev_dbg(hsotg->dev, " op_mode=%d\n", 2705 hw->op_mode); 2706 dev_dbg(hsotg->dev, " arch=%d\n", 2707 hw->arch); 2708 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n", 2709 hw->dma_desc_enable); 2710 dev_dbg(hsotg->dev, " power_optimized=%d\n", 2711 hw->power_optimized); 2712 dev_dbg(hsotg->dev, " i2c_enable=%d\n", 2713 hw->i2c_enable); 2714 dev_dbg(hsotg->dev, " hs_phy_type=%d\n", 2715 hw->hs_phy_type); 2716 dev_dbg(hsotg->dev, " fs_phy_type=%d\n", 2717 hw->fs_phy_type); 2718 dev_dbg(hsotg->dev, " utmi_phy_data_wdith=%d\n", 2719 hw->utmi_phy_data_width); 2720 dev_dbg(hsotg->dev, " num_dev_ep=%d\n", 2721 hw->num_dev_ep); 2722 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", 2723 hw->num_dev_perio_in_ep); 2724 dev_dbg(hsotg->dev, " host_channels=%d\n", 2725 hw->host_channels); 2726 dev_dbg(hsotg->dev, " max_transfer_size=%d\n", 2727 hw->max_transfer_size); 2728 dev_dbg(hsotg->dev, " max_packet_count=%d\n", 2729 hw->max_packet_count); 2730 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n", 2731 hw->nperio_tx_q_depth); 2732 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n", 2733 hw->host_perio_tx_q_depth); 2734 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n", 2735 hw->dev_token_q_depth); 2736 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n", 2737 hw->enable_dynamic_fifo); 2738 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n", 2739 hw->en_multiple_tx_fifo); 2740 dev_dbg(hsotg->dev, " total_fifo_size=%d\n", 2741 hw->total_fifo_size); 2742 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n", 2743 hw->host_rx_fifo_size); 2744 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n", 2745 hw->host_nperio_tx_fifo_size); 2746 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n", 2747 hw->host_perio_tx_fifo_size); 2748 dev_dbg(hsotg->dev, "\n"); 2749 2750 return 0; 2751 } 2752 2753 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg) 2754 { 2755 return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103; 2756 } 2757 2758 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) 2759 { 2760 if (DWC2_READ_4(hsotg, GSNPSID) == 0xffffffff) 2761 return false; 2762 else 2763 return true; 2764 } 2765 2766 /** 2767 * dwc2_enable_global_interrupts() - Enables the controller's Global 2768 * Interrupt in the AHB Config register 2769 * 2770 * @hsotg: Programming view of DWC_otg controller 2771 */ 2772 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) 2773 { 2774 u32 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 2775 2776 ahbcfg |= GAHBCFG_GLBL_INTR_EN; 2777 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 2778 } 2779 2780 /** 2781 * dwc2_disable_global_interrupts() - Disables the controller's Global 2782 * Interrupt in the AHB Config register 2783 * 2784 * @hsotg: Programming view of DWC_otg controller 2785 */ 2786 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) 2787 { 2788 u32 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 2789 2790 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2791 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 2792 } 2793