1 /* $OpenBSD: dwc2_core.c,v 1.13 2022/09/08 19:02:04 mglocker Exp $ */ 2 /* $NetBSD: dwc2_core.c,v 1.6 2014/04/03 06:34:58 skrll Exp $ */ 3 4 /* 5 * core.c - DesignWare HS OTG Controller common routines 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * The Core code provides basic services for accessing and managing the 42 * DWC_otg hardware. These services are used by both the Host Controller 43 * Driver and the Peripheral Controller Driver. 44 */ 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/signal.h> 48 #include <sys/proc.h> 49 #include <sys/timeout.h> 50 #include <sys/mutex.h> 51 #include <sys/pool.h> 52 #include <sys/task.h> 53 54 #include <machine/bus.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdivar.h> 59 #include <dev/usb/usb_mem.h> 60 61 #include <dev/usb/dwc2/dwc2.h> 62 #include <dev/usb/dwc2/dwc2var.h> 63 64 #include <dev/usb/dwc2/dwc2_core.h> 65 #include <dev/usb/dwc2/dwc2_hcd.h> 66 67 /** 68 * dwc2_backup_global_registers() - Backup global controller registers. 69 * When suspending usb bus, registers needs to be backuped 70 * if controller power is disabled once suspended. 71 * 72 * @hsotg: Programming view of the DWC_otg controller 73 */ 74 STATIC int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg) 75 { 76 struct dwc2_gregs_backup *gr; 77 78 dev_dbg(hsotg->dev, "%s\n", __func__); 79 80 /* Backup global regs */ 81 gr = &hsotg->gr_backup; 82 83 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL); 84 gr->gintmsk = dwc2_readl(hsotg, GINTMSK); 85 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG); 86 gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG); 87 gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 88 gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 89 gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG); 90 gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1); 91 gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG); 92 gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL); 93 gr->pcgcctl = dwc2_readl(hsotg, PCGCTL); 94 95 gr->valid = true; 96 return 0; 97 } 98 99 /** 100 * dwc2_restore_global_registers() - Restore controller global registers. 101 * When resuming usb bus, device registers needs to be restored 102 * if controller power were disabled. 103 * 104 * @hsotg: Programming view of the DWC_otg controller 105 */ 106 STATIC int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) 107 { 108 struct dwc2_gregs_backup *gr; 109 110 dev_dbg(hsotg->dev, "%s\n", __func__); 111 112 /* Restore global regs */ 113 gr = &hsotg->gr_backup; 114 if (!gr->valid) { 115 dev_err(hsotg->dev, "%s: no global registers to restore\n", 116 __func__); 117 return -EINVAL; 118 } 119 gr->valid = false; 120 121 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 122 dwc2_writel(hsotg, gr->gotgctl, GOTGCTL); 123 dwc2_writel(hsotg, gr->gintmsk, GINTMSK); 124 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); 125 dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG); 126 dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ); 127 dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ); 128 dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG); 129 dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1); 130 dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG); 131 dwc2_writel(hsotg, gr->pcgcctl, PCGCTL); 132 dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL); 133 134 return 0; 135 } 136 137 /** 138 * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down. 139 * 140 * @hsotg: Programming view of the DWC_otg controller 141 * @rem_wakeup: indicates whether resume is initiated by Reset. 142 * @restore: Controller registers need to be restored 143 */ 144 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup, 145 bool restore) 146 { 147 struct dwc2_gregs_backup *gr; 148 149 gr = &hsotg->gr_backup; 150 151 /* 152 * Restore host or device regisers with the same mode core enterted 153 * to partial power down by checking "GOTGCTL_CURMODE_HOST" backup 154 * value of the "gotgctl" register. 155 */ 156 if (gr->gotgctl & GOTGCTL_CURMODE_HOST) 157 return dwc2_host_exit_partial_power_down(hsotg, rem_wakeup, 158 restore); 159 else 160 return dwc2_gadget_exit_partial_power_down(hsotg, restore); 161 } 162 163 /** 164 * dwc2_enter_partial_power_down() - Put controller in Partial Power Down. 165 * 166 * @hsotg: Programming view of the DWC_otg controller 167 */ 168 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg) 169 { 170 if (dwc2_is_host_mode(hsotg)) 171 return dwc2_host_enter_partial_power_down(hsotg); 172 else 173 return dwc2_gadget_enter_partial_power_down(hsotg); 174 } 175 176 /** 177 * dwc2_restore_essential_regs() - Restore essiential regs of core. 178 * 179 * @hsotg: Programming view of the DWC_otg controller 180 * @rmode: Restore mode, enabled in case of remote-wakeup. 181 * @is_host: Host or device mode. 182 */ 183 static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode, 184 int is_host) 185 { 186 u32 pcgcctl; 187 struct dwc2_gregs_backup *gr; 188 struct dwc2_dregs_backup *dr; 189 struct dwc2_hregs_backup *hr; 190 191 gr = &hsotg->gr_backup; 192 dr = &hsotg->dr_backup; 193 hr = &hsotg->hr_backup; 194 195 dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__); 196 197 /* Load restore values for [31:14] bits */ 198 pcgcctl = (gr->pcgcctl & 0xffffc000); 199 /* If High Speed */ 200 if (is_host) { 201 if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK)) 202 pcgcctl |= (1 << 17); 203 } else { 204 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK)) 205 pcgcctl |= (1 << 17); 206 } 207 dwc2_writel(hsotg, pcgcctl, PCGCTL); 208 209 /* Umnask global Interrupt in GAHBCFG and restore it */ 210 dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG); 211 212 /* Clear all pending interupts */ 213 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 214 215 /* Unmask restore done interrupt */ 216 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK); 217 218 /* Restore GUSBCFG and HCFG/DCFG */ 219 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); 220 221 if (is_host) { 222 dwc2_writel(hsotg, hr->hcfg, HCFG); 223 if (rmode) 224 pcgcctl |= PCGCTL_RESTOREMODE; 225 dwc2_writel(hsotg, pcgcctl, PCGCTL); 226 udelay(10); 227 228 pcgcctl |= PCGCTL_ESS_REG_RESTORED; 229 dwc2_writel(hsotg, pcgcctl, PCGCTL); 230 udelay(10); 231 } else { 232 dwc2_writel(hsotg, dr->dcfg, DCFG); 233 if (!rmode) 234 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE; 235 dwc2_writel(hsotg, pcgcctl, PCGCTL); 236 udelay(10); 237 238 pcgcctl |= PCGCTL_ESS_REG_RESTORED; 239 dwc2_writel(hsotg, pcgcctl, PCGCTL); 240 udelay(10); 241 } 242 } 243 244 /** 245 * dwc2_hib_restore_common() - Common part of restore routine. 246 * 247 * @hsotg: Programming view of the DWC_otg controller 248 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup. 249 * @is_host: Host or device mode. 250 */ 251 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 252 int is_host) 253 { 254 u32 gpwrdn; 255 256 /* Switch-on voltage to the core */ 257 gpwrdn = dwc2_readl(hsotg, GPWRDN); 258 gpwrdn &= ~GPWRDN_PWRDNSWTCH; 259 dwc2_writel(hsotg, gpwrdn, GPWRDN); 260 udelay(10); 261 262 /* Reset core */ 263 gpwrdn = dwc2_readl(hsotg, GPWRDN); 264 gpwrdn &= ~GPWRDN_PWRDNRSTN; 265 dwc2_writel(hsotg, gpwrdn, GPWRDN); 266 udelay(10); 267 268 /* Enable restore from PMU */ 269 gpwrdn = dwc2_readl(hsotg, GPWRDN); 270 gpwrdn |= GPWRDN_RESTORE; 271 dwc2_writel(hsotg, gpwrdn, GPWRDN); 272 udelay(10); 273 274 /* Disable Power Down Clamp */ 275 gpwrdn = dwc2_readl(hsotg, GPWRDN); 276 gpwrdn &= ~GPWRDN_PWRDNCLMP; 277 dwc2_writel(hsotg, gpwrdn, GPWRDN); 278 udelay(50); 279 280 if (!is_host && rem_wakeup) 281 udelay(70); 282 283 /* Deassert reset core */ 284 gpwrdn = dwc2_readl(hsotg, GPWRDN); 285 gpwrdn |= GPWRDN_PWRDNRSTN; 286 dwc2_writel(hsotg, gpwrdn, GPWRDN); 287 udelay(10); 288 289 /* Disable PMU interrupt */ 290 gpwrdn = dwc2_readl(hsotg, GPWRDN); 291 gpwrdn &= ~GPWRDN_PMUINTSEL; 292 dwc2_writel(hsotg, gpwrdn, GPWRDN); 293 udelay(10); 294 295 /* Set Restore Essential Regs bit in PCGCCTL register */ 296 dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host); 297 298 /* 299 * Wait For Restore_done Interrupt. This mechanism of polling the 300 * interrupt is introduced to avoid any possible race conditions 301 */ 302 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE, 303 20000)) { 304 dev_dbg(hsotg->dev, 305 "%s: Restore Done wasn't generated here\n", 306 __func__); 307 } else { 308 dev_dbg(hsotg->dev, "restore done generated here\n"); 309 310 /* 311 * To avoid restore done interrupt storm after restore is 312 * generated clear GINTSTS_RESTOREDONE bit. 313 */ 314 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTSTS); 315 } 316 } 317 318 /** 319 * dwc2_wait_for_mode() - Waits for the controller mode. 320 * @hsotg: Programming view of the DWC_otg controller. 321 * @host_mode: If true, waits for host mode, otherwise device mode. 322 */ 323 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg, 324 bool host_mode) 325 { 326 struct timeval start; 327 struct timeval end; 328 unsigned int timeout = 110; 329 330 dev_vdbg(hsotg->dev, "Waiting for %s mode\n", 331 host_mode ? "host" : "device"); 332 333 getmicrotime(&start); 334 335 while (1) { 336 unsigned int ms; 337 338 if (dwc2_is_host_mode(hsotg) == host_mode) { 339 dev_vdbg(hsotg->dev, "%s mode set\n", 340 host_mode ? "Host" : "Device"); 341 break; 342 } 343 344 getmicrotime(&end); 345 ms = (end.tv_usec - start.tv_usec) / 1000; 346 347 if (ms >= timeout) { 348 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n", 349 __func__, host_mode ? "host" : "device"); 350 break; 351 } 352 353 usleep_range(1000, 2000); 354 } 355 } 356 357 /** 358 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce 359 * filter is enabled. 360 * 361 * @hsotg: Programming view of DWC_otg controller 362 */ 363 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg) 364 { 365 u32 gsnpsid; 366 u32 ghwcfg4; 367 368 if (!dwc2_hw_is_otg(hsotg)) 369 return false; 370 371 /* Check if core configuration includes the IDDIG filter. */ 372 ghwcfg4 = dwc2_readl(hsotg, GHWCFG4); 373 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN)) 374 return false; 375 376 /* 377 * Check if the IDDIG debounce filter is bypassed. Available 378 * in core version >= 3.10a. 379 */ 380 gsnpsid = dwc2_readl(hsotg, GSNPSID); 381 if (gsnpsid >= DWC2_CORE_REV_3_10a) { 382 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL); 383 384 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS) 385 return false; 386 } 387 388 return true; 389 } 390 391 /* 392 * dwc2_enter_hibernation() - Common function to enter hibernation. 393 * 394 * @hsotg: Programming view of the DWC_otg controller 395 * @is_host: True if core is in host mode. 396 * 397 * Return: 0 if successful, negative error code otherwise 398 */ 399 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host) 400 { 401 if (is_host) 402 return dwc2_host_enter_hibernation(hsotg); 403 else 404 return dwc2_gadget_enter_hibernation(hsotg); 405 } 406 407 /* 408 * dwc2_exit_hibernation() - Common function to exit from hibernation. 409 * 410 * @hsotg: Programming view of the DWC_otg controller 411 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup. 412 * @reset: Enabled in case of restore with reset. 413 * @is_host: True if core is in host mode. 414 * 415 * Return: 0 if successful, negative error code otherwise 416 */ 417 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 418 int reset, int is_host) 419 { 420 if (is_host) 421 return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset); 422 else 423 return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset); 424 } 425 426 /* 427 * Do core a soft reset of the core. Be careful with this because it 428 * resets all the internal state machines of the core. 429 */ 430 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait) 431 { 432 u32 greset; 433 bool wait_for_host_mode = false; 434 435 dev_vdbg(hsotg->dev, "%s()\n", __func__); 436 437 /* 438 * If the current mode is host, either due to the force mode 439 * bit being set (which persists after core reset) or the 440 * connector id pin, a core soft reset will temporarily reset 441 * the mode to device. A delay from the IDDIG debounce filter 442 * will occur before going back to host mode. 443 * 444 * Determine whether we will go back into host mode after a 445 * reset and account for this delay after the reset. 446 */ 447 if (dwc2_iddig_filter_enabled(hsotg)) { 448 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL); 449 u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG); 450 451 if (!(gotgctl & GOTGCTL_CONID_B) || 452 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) { 453 wait_for_host_mode = true; 454 } 455 } 456 457 /* Core Soft Reset */ 458 greset = dwc2_readl(hsotg, GRSTCTL); 459 greset |= GRSTCTL_CSFTRST; 460 dwc2_writel(hsotg, greset, GRSTCTL); 461 462 if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) < 463 (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) { 464 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, 465 GRSTCTL_CSFTRST, 10000)) { 466 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n", 467 __func__); 468 return -EBUSY; 469 } 470 } else { 471 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, 472 GRSTCTL_CSFTRST_DONE, 10000)) { 473 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n", 474 __func__); 475 return -EBUSY; 476 } 477 greset = dwc2_readl(hsotg, GRSTCTL); 478 greset &= ~GRSTCTL_CSFTRST; 479 greset |= GRSTCTL_CSFTRST_DONE; 480 dwc2_writel(hsotg, greset, GRSTCTL); 481 } 482 483 /* 484 * Switching from device mode to host mode by disconnecting 485 * device cable core enters and exits form hibernation. 486 * However, the fifo map remains not cleared. It results 487 * to a WARNING (WARNING: CPU: 5 PID: 0 at drivers/usb/dwc2/ 488 * gadget.c:307 dwc2_hsotg_init_fifo+0x12/0x152 [dwc2]) 489 * if in host mode we disconnect the micro a to b host 490 * cable. Because core reset occurs. 491 * To avoid the WARNING, fifo_map should be cleared 492 * in dwc2_core_reset() function by taking into account configs. 493 * fifo_map must be cleared only if driver is configured in 494 * "CONFIG_USB_DWC2_PERIPHERAL" or "CONFIG_USB_DWC2_DUAL_ROLE" 495 * mode. 496 */ 497 dwc2_clear_fifo_map(hsotg); 498 499 /* Wait for AHB master IDLE state */ 500 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) { 501 dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n", 502 __func__); 503 return -EBUSY; 504 } 505 506 if (wait_for_host_mode && !skip_wait) 507 dwc2_wait_for_mode(hsotg, true); 508 509 return 0; 510 } 511 512 /** 513 * dwc2_force_mode() - Force the mode of the controller. 514 * 515 * Forcing the mode is needed for two cases: 516 * 517 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the 518 * controller to stay in a particular mode regardless of ID pin 519 * changes. We do this once during probe. 520 * 521 * 2) During probe we want to read reset values of the hw 522 * configuration registers that are only available in either host or 523 * device mode. We may need to force the mode if the current mode does 524 * not allow us to access the register in the mode that we want. 525 * 526 * In either case it only makes sense to force the mode if the 527 * controller hardware is OTG capable. 528 * 529 * Checks are done in this function to determine whether doing a force 530 * would be valid or not. 531 * 532 * If a force is done, it requires a IDDIG debounce filter delay if 533 * the filter is configured and enabled. We poll the current mode of 534 * the controller to account for this delay. 535 * 536 * @hsotg: Programming view of DWC_otg controller 537 * @host: Host mode flag 538 */ 539 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) 540 { 541 u32 gusbcfg; 542 u32 set; 543 u32 clear; 544 545 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device"); 546 547 /* 548 * Force mode has no effect if the hardware is not OTG. 549 */ 550 if (!dwc2_hw_is_otg(hsotg)) 551 return; 552 553 /* 554 * If dr_mode is either peripheral or host only, there is no 555 * need to ever force the mode to the opposite mode. 556 */ 557 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)) 558 return; 559 560 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST)) 561 return; 562 563 gusbcfg = dwc2_readl(hsotg, GUSBCFG); 564 565 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE; 566 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE; 567 568 gusbcfg &= ~clear; 569 gusbcfg |= set; 570 dwc2_writel(hsotg, gusbcfg, GUSBCFG); 571 572 dwc2_wait_for_mode(hsotg, host); 573 return; 574 } 575 576 /** 577 * dwc2_clear_force_mode() - Clears the force mode bits. 578 * 579 * After clearing the bits, wait up to 100 ms to account for any 580 * potential IDDIG filter delay. We can't know if we expect this delay 581 * or not because the value of the connector ID status is affected by 582 * the force mode. We only need to call this once during probe if 583 * dr_mode == OTG. 584 * 585 * @hsotg: Programming view of DWC_otg controller 586 */ 587 STATIC void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) 588 { 589 u32 gusbcfg; 590 591 if (!dwc2_hw_is_otg(hsotg)) 592 return; 593 594 dev_dbg(hsotg->dev, "Clearing force mode bits\n"); 595 596 gusbcfg = dwc2_readl(hsotg, GUSBCFG); 597 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; 598 gusbcfg &= ~GUSBCFG_FORCEDEVMODE; 599 dwc2_writel(hsotg, gusbcfg, GUSBCFG); 600 601 if (dwc2_iddig_filter_enabled(hsotg)) 602 dwc2_msleep(100); 603 } 604 605 /* 606 * Sets or clears force mode based on the dr_mode parameter. 607 */ 608 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) 609 { 610 switch (hsotg->dr_mode) { 611 case USB_DR_MODE_HOST: 612 /* 613 * NOTE: This is required for some rockchip soc based 614 * platforms on their host-only dwc2. 615 */ 616 if (!dwc2_hw_is_otg(hsotg)) 617 dwc2_msleep(50); 618 619 break; 620 case USB_DR_MODE_PERIPHERAL: 621 dwc2_force_mode(hsotg, false); 622 break; 623 case USB_DR_MODE_OTG: 624 dwc2_clear_force_mode(hsotg); 625 break; 626 default: 627 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n", 628 __func__, hsotg->dr_mode); 629 break; 630 } 631 } 632 633 /* 634 * dwc2_enable_acg - enable active clock gating feature 635 */ 636 void dwc2_enable_acg(struct dwc2_hsotg *hsotg) 637 { 638 if (hsotg->params.acg_enable) { 639 u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1); 640 641 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n"); 642 pcgcctl1 |= PCGCCTL1_GATEEN; 643 dwc2_writel(hsotg, pcgcctl1, PCGCCTL1); 644 } 645 } 646 647 /** 648 * dwc2_dump_host_registers() - Prints the host registers 649 * 650 * @hsotg: Programming view of DWC_otg controller 651 * 652 * NOTE: This function will be removed once the peripheral controller code 653 * is integrated and the driver is stable 654 */ 655 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) 656 { 657 #ifdef DWC2_DEBUG 658 bus_size_t addr; 659 int i; 660 661 dev_dbg(hsotg->dev, "Host Global Registers\n"); 662 addr = HCFG; 663 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", 664 (unsigned long)addr, dwc2_readl(hsotg, HCFG)); 665 addr = HFIR; 666 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", 667 (unsigned long)addr, dwc2_readl(hsotg, HFIR)); 668 addr = HFNUM; 669 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", 670 (unsigned long)addr, dwc2_readl(hsotg, HFNUM)); 671 addr = HPTXSTS; 672 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", 673 (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS)); 674 addr = HAINT; 675 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", 676 (unsigned long)addr, dwc2_readl(hsotg, HAINT)); 677 addr = HAINTMSK; 678 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", 679 (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK)); 680 if (hsotg->params.dma_desc_enable) { 681 addr = HFLBADDR; 682 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", 683 (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR)); 684 } 685 686 addr = HPRT0; 687 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", 688 (unsigned long)addr, dwc2_readl(hsotg, HPRT0)); 689 690 for (i = 0; i < hsotg->params.host_channels; i++) { 691 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); 692 addr = HCCHAR(i); 693 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", 694 (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i))); 695 addr = HCSPLT(i); 696 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", 697 (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i))); 698 addr = HCINT(i); 699 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", 700 (unsigned long)addr, dwc2_readl(hsotg, HCINT(i))); 701 addr = HCINTMSK(i); 702 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", 703 (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i))); 704 addr = HCTSIZ(i); 705 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", 706 (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i))); 707 addr = HCDMA(i); 708 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", 709 (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i))); 710 if (hsotg->params.dma_desc_enable) { 711 addr = HCDMAB(i); 712 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", 713 (unsigned long)addr, dwc2_readl(hsotg, 714 HCDMAB(i))); 715 } 716 } 717 #endif 718 } 719 720 /** 721 * dwc2_dump_global_registers() - Prints the core global registers 722 * 723 * @hsotg: Programming view of DWC_otg controller 724 * 725 * NOTE: This function will be removed once the peripheral controller code 726 * is integrated and the driver is stable 727 */ 728 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) 729 { 730 #ifdef DWC2_DEBUG 731 bus_size_t addr; 732 733 dev_dbg(hsotg->dev, "Core Global Registers\n"); 734 addr = GOTGCTL; 735 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", 736 (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL)); 737 addr = GOTGINT; 738 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", 739 (unsigned long)addr, dwc2_readl(hsotg, GOTGINT)); 740 addr = GAHBCFG; 741 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", 742 (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG)); 743 addr = GUSBCFG; 744 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", 745 (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG)); 746 addr = GRSTCTL; 747 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", 748 (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL)); 749 addr = GINTSTS; 750 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", 751 (unsigned long)addr, dwc2_readl(hsotg, GINTSTS)); 752 addr = GINTMSK; 753 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", 754 (unsigned long)addr, dwc2_readl(hsotg, GINTMSK)); 755 addr = GRXSTSR; 756 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", 757 (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR)); 758 addr = GRXFSIZ; 759 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", 760 (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ)); 761 addr = GNPTXFSIZ; 762 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", 763 (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ)); 764 addr = GNPTXSTS; 765 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", 766 (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS)); 767 addr = GI2CCTL; 768 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", 769 (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL)); 770 addr = GPVNDCTL; 771 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", 772 (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL)); 773 addr = GGPIO; 774 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", 775 (unsigned long)addr, dwc2_readl(hsotg, GGPIO)); 776 addr = GUID; 777 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", 778 (unsigned long)addr, dwc2_readl(hsotg, GUID)); 779 addr = GSNPSID; 780 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", 781 (unsigned long)addr, dwc2_readl(hsotg, GSNPSID)); 782 addr = GHWCFG1; 783 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", 784 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1)); 785 addr = GHWCFG2; 786 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", 787 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2)); 788 addr = GHWCFG3; 789 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", 790 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3)); 791 addr = GHWCFG4; 792 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", 793 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4)); 794 addr = GLPMCFG; 795 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", 796 (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG)); 797 addr = GPWRDN; 798 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", 799 (unsigned long)addr, dwc2_readl(hsotg, GPWRDN)); 800 addr = GDFIFOCFG; 801 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", 802 (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG)); 803 addr = HPTXFSIZ; 804 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", 805 (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ)); 806 807 addr = PCGCTL; 808 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", 809 (unsigned long)addr, dwc2_readl(hsotg, PCGCTL)); 810 #endif 811 } 812 813 /** 814 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO 815 * 816 * @hsotg: Programming view of DWC_otg controller 817 * @num: Tx FIFO to flush 818 */ 819 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) 820 { 821 u32 greset; 822 823 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); 824 825 /* Wait for AHB master IDLE state */ 826 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) 827 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n", 828 __func__); 829 830 greset = GRSTCTL_TXFFLSH; 831 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; 832 dwc2_writel(hsotg, greset, GRSTCTL); 833 834 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000)) 835 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n", 836 __func__); 837 838 /* Wait for at least 3 PHY Clocks */ 839 udelay(1); 840 } 841 842 /** 843 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO 844 * 845 * @hsotg: Programming view of DWC_otg controller 846 */ 847 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) 848 { 849 u32 greset; 850 851 dev_vdbg(hsotg->dev, "%s()\n", __func__); 852 853 /* Wait for AHB master IDLE state */ 854 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) 855 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n", 856 __func__); 857 858 greset = GRSTCTL_RXFFLSH; 859 dwc2_writel(hsotg, greset, GRSTCTL); 860 861 /* Wait for RxFIFO flush done */ 862 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000)) 863 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n", 864 __func__); 865 866 /* Wait for at least 3 PHY Clocks */ 867 udelay(1); 868 } 869 870 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) 871 { 872 if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff) 873 return false; 874 else 875 return true; 876 } 877 878 /** 879 * dwc2_enable_global_interrupts() - Enables the controller's Global 880 * Interrupt in the AHB Config register 881 * 882 * @hsotg: Programming view of DWC_otg controller 883 */ 884 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) 885 { 886 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG); 887 888 ahbcfg |= GAHBCFG_GLBL_INTR_EN; 889 dwc2_writel(hsotg, ahbcfg, GAHBCFG); 890 } 891 892 /** 893 * dwc2_disable_global_interrupts() - Disables the controller's Global 894 * Interrupt in the AHB Config register 895 * 896 * @hsotg: Programming view of DWC_otg controller 897 */ 898 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) 899 { 900 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG); 901 902 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 903 dwc2_writel(hsotg, ahbcfg, GAHBCFG); 904 } 905 906 /* Returns the controller's GHWCFG2.OTG_MODE. */ 907 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg) 908 { 909 u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2); 910 911 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >> 912 GHWCFG2_OP_MODE_SHIFT; 913 } 914 915 /* Returns true if the controller is capable of DRD. */ 916 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg) 917 { 918 unsigned int op_mode = dwc2_op_mode(hsotg); 919 920 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) || 921 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) || 922 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE); 923 } 924 925 /* Returns true if the controller is host-only. */ 926 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg) 927 { 928 unsigned int op_mode = dwc2_op_mode(hsotg); 929 930 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) || 931 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST); 932 } 933 934 /* Returns true if the controller is device-only. */ 935 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg) 936 { 937 unsigned int op_mode = dwc2_op_mode(hsotg); 938 939 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || 940 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE); 941 } 942 943 /** 944 * dwc2_hsotg_wait_bit_set - Waits for bit to be set. 945 * @hsotg: Programming view of DWC_otg controller. 946 * @offset: Register's offset where bit/bits must be set. 947 * @mask: Mask of the bit/bits which must be set. 948 * @timeout: Timeout to wait. 949 * 950 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout. 951 */ 952 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, 953 u32 timeout) 954 { 955 u32 i; 956 957 for (i = 0; i < timeout; i++) { 958 if (dwc2_readl(hsotg, offset) & mask) 959 return 0; 960 udelay(1); 961 } 962 963 return -ETIMEDOUT; 964 } 965 966 /** 967 * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear. 968 * @hsotg: Programming view of DWC_otg controller. 969 * @offset: Register's offset where bit/bits must be set. 970 * @mask: Mask of the bit/bits which must be set. 971 * @timeout: Timeout to wait. 972 * 973 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout. 974 */ 975 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, 976 u32 timeout) 977 { 978 u32 i; 979 980 for (i = 0; i < timeout; i++) { 981 if (!(dwc2_readl(hsotg, offset) & mask)) 982 return 0; 983 udelay(1); 984 } 985 986 return -ETIMEDOUT; 987 } 988 989 /* 990 * Initializes the FSLSPClkSel field of the HCFG register depending on the 991 * PHY type 992 */ 993 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 994 { 995 u32 hcfg, val; 996 997 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 998 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 999 hsotg->params.ulpi_fs_ls) || 1000 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 1001 /* Full speed PHY */ 1002 val = HCFG_FSLSPCLKSEL_48_MHZ; 1003 } else { 1004 /* High speed PHY running at full speed or high speed */ 1005 val = HCFG_FSLSPCLKSEL_30_60_MHZ; 1006 } 1007 1008 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 1009 hcfg = dwc2_readl(hsotg, HCFG); 1010 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 1011 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 1012 dwc2_writel(hsotg, hcfg, HCFG); 1013 } 1014 1015 STATIC int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 1016 { 1017 u32 usbcfg, ggpio, i2cctl; 1018 int retval = 0; 1019 1020 /* 1021 * core_init() is now called on every switch so only call the 1022 * following for the first time through 1023 */ 1024 if (select_phy) { 1025 dev_dbg(hsotg->dev, "FS PHY selected\n"); 1026 1027 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1028 if (!(usbcfg & GUSBCFG_PHYSEL)) { 1029 usbcfg |= GUSBCFG_PHYSEL; 1030 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1031 1032 /* Reset after a PHY select */ 1033 retval = dwc2_core_reset(hsotg, false); 1034 1035 if (retval) { 1036 dev_err(hsotg->dev, 1037 "%s: Reset failed, aborting", __func__); 1038 return retval; 1039 } 1040 } 1041 1042 if (hsotg->params.activate_stm_fs_transceiver) { 1043 ggpio = dwc2_readl(hsotg, GGPIO); 1044 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) { 1045 dev_dbg(hsotg->dev, "Activating transceiver\n"); 1046 /* 1047 * STM32F4x9 uses the GGPIO register as general 1048 * core configuration register. 1049 */ 1050 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN; 1051 dwc2_writel(hsotg, ggpio, GGPIO); 1052 } 1053 } 1054 } 1055 1056 /* 1057 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 1058 * do this on HNP Dev/Host mode switches (done in dev_init and 1059 * host_init). 1060 */ 1061 if (dwc2_is_host_mode(hsotg)) 1062 dwc2_init_fs_ls_pclk_sel(hsotg); 1063 1064 if (hsotg->params.i2c_enable) { 1065 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 1066 1067 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 1068 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1069 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 1070 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1071 1072 /* Program GI2CCTL.I2CEn */ 1073 i2cctl = dwc2_readl(hsotg, GI2CCTL); 1074 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 1075 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 1076 i2cctl &= ~GI2CCTL_I2CEN; 1077 dwc2_writel(hsotg, i2cctl, GI2CCTL); 1078 i2cctl |= GI2CCTL_I2CEN; 1079 dwc2_writel(hsotg, i2cctl, GI2CCTL); 1080 } 1081 1082 return retval; 1083 } 1084 1085 STATIC int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 1086 { 1087 u32 usbcfg, usbcfg_old; 1088 int retval = 0; 1089 1090 if (!select_phy) 1091 return 0; 1092 1093 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1094 usbcfg_old = usbcfg; 1095 1096 /* 1097 * HS PHY parameters. These parameters are preserved during soft reset 1098 * so only program the first time. Do a soft reset immediately after 1099 * setting phyif. 1100 */ 1101 switch (hsotg->params.phy_type) { 1102 case DWC2_PHY_TYPE_PARAM_ULPI: 1103 /* ULPI interface */ 1104 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 1105 usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 1106 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 1107 if (hsotg->params.phy_ulpi_ddr) 1108 usbcfg |= GUSBCFG_DDRSEL; 1109 1110 /* Set external VBUS indicator as needed. */ 1111 if (hsotg->params.oc_disable) 1112 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND | 1113 GUSBCFG_INDICATORPASSTHROUGH); 1114 break; 1115 case DWC2_PHY_TYPE_PARAM_UTMI: 1116 /* UTMI+ interface */ 1117 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 1118 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 1119 if (hsotg->params.phy_utmi_width == 16) 1120 usbcfg |= GUSBCFG_PHYIF16; 1121 break; 1122 default: 1123 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 1124 break; 1125 } 1126 1127 if (usbcfg != usbcfg_old) { 1128 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1129 1130 /* Reset after setting the PHY parameters */ 1131 retval = dwc2_core_reset(hsotg, false); 1132 if (retval) { 1133 dev_err(hsotg->dev, 1134 "%s: Reset failed, aborting", __func__); 1135 return retval; 1136 } 1137 } 1138 1139 return retval; 1140 } 1141 1142 static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg) 1143 { 1144 u32 usbcfg; 1145 1146 if (hsotg->params.phy_type != DWC2_PHY_TYPE_PARAM_UTMI) 1147 return; 1148 1149 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1150 1151 usbcfg &= ~GUSBCFG_USBTRDTIM_MASK; 1152 if (hsotg->params.phy_utmi_width == 16) 1153 usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT; 1154 else 1155 usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT; 1156 1157 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1158 } 1159 1160 STATIC int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 1161 { 1162 u32 usbcfg; 1163 u32 otgctl; 1164 int retval = 0; 1165 1166 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 1167 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && 1168 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 1169 /* If FS/LS mode with FS/LS PHY */ 1170 retval = dwc2_fs_phy_init(hsotg, select_phy); 1171 if (retval) 1172 return retval; 1173 } else { 1174 /* High speed PHY */ 1175 retval = dwc2_hs_phy_init(hsotg, select_phy); 1176 if (retval) 1177 return retval; 1178 1179 if (dwc2_is_device_mode(hsotg)) 1180 dwc2_set_turnaround_time(hsotg); 1181 } 1182 1183 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 1184 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 1185 hsotg->params.ulpi_fs_ls) { 1186 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 1187 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1188 usbcfg |= GUSBCFG_ULPI_FS_LS; 1189 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 1190 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1191 } else { 1192 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1193 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 1194 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 1195 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1196 } 1197 1198 if (!hsotg->params.activate_ingenic_overcurrent_detection) { 1199 if (dwc2_is_host_mode(hsotg)) { 1200 otgctl = dwc2_readl(hsotg, GOTGCTL); 1201 otgctl |= GOTGCTL_VBVALOEN | GOTGCTL_VBVALOVAL; 1202 dwc2_writel(hsotg, otgctl, GOTGCTL); 1203 } 1204 } 1205 1206 return retval; 1207 } 1208