1 /* $OpenBSD: dwc2.c,v 1.62 2022/07/02 08:50:42 visa Exp $ */ 2 /* $NetBSD: dwc2.c,v 1.32 2014/09/02 23:26:20 macallan Exp $ */ 3 4 /*- 5 * Copyright (c) 2013 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Nick Hudson 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/device.h> 38 #include <sys/proc.h> 39 #include <sys/queue.h> 40 #include <sys/endian.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/usb/usb.h> 45 #include <dev/usb/usbdi.h> 46 #include <dev/usb/usbdivar.h> 47 #include <dev/usb/usb_mem.h> 48 49 #include <dev/usb/dwc2/dwc2.h> 50 #include <dev/usb/dwc2/dwc2var.h> 51 52 #include <dev/usb/dwc2/dwc2_core.h> 53 #include <dev/usb/dwc2/dwc2_hcd.h> 54 55 #ifdef DWC2_COUNTERS 56 #define DWC2_EVCNT_ADD(a,b) ((void)((a).ev_count += (b))) 57 #else 58 #define DWC2_EVCNT_ADD(a,b) do { } while (/*CONSTCOND*/0) 59 #endif 60 #define DWC2_EVCNT_INCR(a) DWC2_EVCNT_ADD((a), 1) 61 62 #ifdef DWC2_DEBUG 63 #define DPRINTFN(n,fmt,...) do { \ 64 if (dwc2debug >= (n)) { \ 65 printf("%s: " fmt, \ 66 __FUNCTION__,## __VA_ARGS__); \ 67 } \ 68 } while (0) 69 #define DPRINTF(...) DPRINTFN(1, __VA_ARGS__) 70 int dwc2debug = 0; 71 #else 72 #define DPRINTF(...) do { } while (0) 73 #define DPRINTFN(...) do { } while (0) 74 #endif 75 76 STATIC usbd_status dwc2_open(struct usbd_pipe *); 77 STATIC int dwc2_setaddr(struct usbd_device *, int); 78 STATIC void dwc2_poll(struct usbd_bus *); 79 STATIC void dwc2_softintr(void *); 80 81 STATIC struct usbd_xfer *dwc2_allocx(struct usbd_bus *); 82 STATIC void dwc2_freex(struct usbd_bus *, struct usbd_xfer *); 83 84 STATIC usbd_status dwc2_root_ctrl_transfer(struct usbd_xfer *); 85 STATIC usbd_status dwc2_root_ctrl_start(struct usbd_xfer *); 86 STATIC void dwc2_root_ctrl_abort(struct usbd_xfer *); 87 STATIC void dwc2_root_ctrl_close(struct usbd_pipe *); 88 STATIC void dwc2_root_ctrl_done(struct usbd_xfer *); 89 90 STATIC usbd_status dwc2_root_intr_transfer(struct usbd_xfer *); 91 STATIC usbd_status dwc2_root_intr_start(struct usbd_xfer *); 92 STATIC void dwc2_root_intr_abort(struct usbd_xfer *); 93 STATIC void dwc2_root_intr_close(struct usbd_pipe *); 94 STATIC void dwc2_root_intr_done(struct usbd_xfer *); 95 96 STATIC usbd_status dwc2_device_ctrl_transfer(struct usbd_xfer *); 97 STATIC usbd_status dwc2_device_ctrl_start(struct usbd_xfer *); 98 STATIC void dwc2_device_ctrl_abort(struct usbd_xfer *); 99 STATIC void dwc2_device_ctrl_close(struct usbd_pipe *); 100 STATIC void dwc2_device_ctrl_done(struct usbd_xfer *); 101 102 STATIC usbd_status dwc2_device_bulk_transfer(struct usbd_xfer *); 103 STATIC usbd_status dwc2_device_bulk_start(struct usbd_xfer *); 104 STATIC void dwc2_device_bulk_abort(struct usbd_xfer *); 105 STATIC void dwc2_device_bulk_close(struct usbd_pipe *); 106 STATIC void dwc2_device_bulk_done(struct usbd_xfer *); 107 108 STATIC usbd_status dwc2_device_intr_transfer(struct usbd_xfer *); 109 STATIC usbd_status dwc2_device_intr_start(struct usbd_xfer *); 110 STATIC void dwc2_device_intr_abort(struct usbd_xfer *); 111 STATIC void dwc2_device_intr_close(struct usbd_pipe *); 112 STATIC void dwc2_device_intr_done(struct usbd_xfer *); 113 114 STATIC usbd_status dwc2_device_isoc_transfer(struct usbd_xfer *); 115 STATIC usbd_status dwc2_device_isoc_start(struct usbd_xfer *); 116 STATIC void dwc2_device_isoc_abort(struct usbd_xfer *); 117 STATIC void dwc2_device_isoc_close(struct usbd_pipe *); 118 STATIC void dwc2_device_isoc_done(struct usbd_xfer *); 119 120 STATIC usbd_status dwc2_device_start(struct usbd_xfer *); 121 122 STATIC void dwc2_close_pipe(struct usbd_pipe *); 123 STATIC void dwc2_abort_xfer(struct usbd_xfer *, usbd_status); 124 125 STATIC void dwc2_device_clear_toggle(struct usbd_pipe *); 126 STATIC void dwc2_noop(struct usbd_pipe *pipe); 127 128 STATIC int dwc2_interrupt(struct dwc2_softc *); 129 STATIC void dwc2_rhc(void *); 130 131 STATIC void dwc2_timeout(void *); 132 STATIC void dwc2_timeout_task(void *); 133 134 static inline void 135 dwc2_allocate_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw, 136 struct usbd_xfer *xfer) 137 { 138 } 139 140 static inline void 141 dwc2_free_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw, 142 struct usbd_xfer *xfer) 143 { 144 } 145 146 #define DWC2_INTR_ENDPT 1 147 148 STATIC const struct usbd_bus_methods dwc2_bus_methods = { 149 .open_pipe = dwc2_open, 150 .dev_setaddr = dwc2_setaddr, 151 .soft_intr = dwc2_softintr, 152 .do_poll = dwc2_poll, 153 .allocx = dwc2_allocx, 154 .freex = dwc2_freex, 155 }; 156 157 STATIC const struct usbd_pipe_methods dwc2_root_ctrl_methods = { 158 .transfer = dwc2_root_ctrl_transfer, 159 .start = dwc2_root_ctrl_start, 160 .abort = dwc2_root_ctrl_abort, 161 .close = dwc2_root_ctrl_close, 162 .cleartoggle = dwc2_noop, 163 .done = dwc2_root_ctrl_done, 164 }; 165 166 STATIC const struct usbd_pipe_methods dwc2_root_intr_methods = { 167 .transfer = dwc2_root_intr_transfer, 168 .start = dwc2_root_intr_start, 169 .abort = dwc2_root_intr_abort, 170 .close = dwc2_root_intr_close, 171 .cleartoggle = dwc2_noop, 172 .done = dwc2_root_intr_done, 173 }; 174 175 STATIC const struct usbd_pipe_methods dwc2_device_ctrl_methods = { 176 .transfer = dwc2_device_ctrl_transfer, 177 .start = dwc2_device_ctrl_start, 178 .abort = dwc2_device_ctrl_abort, 179 .close = dwc2_device_ctrl_close, 180 .cleartoggle = dwc2_noop, 181 .done = dwc2_device_ctrl_done, 182 }; 183 184 STATIC const struct usbd_pipe_methods dwc2_device_intr_methods = { 185 .transfer = dwc2_device_intr_transfer, 186 .start = dwc2_device_intr_start, 187 .abort = dwc2_device_intr_abort, 188 .close = dwc2_device_intr_close, 189 .cleartoggle = dwc2_device_clear_toggle, 190 .done = dwc2_device_intr_done, 191 }; 192 193 STATIC const struct usbd_pipe_methods dwc2_device_bulk_methods = { 194 .transfer = dwc2_device_bulk_transfer, 195 .start = dwc2_device_bulk_start, 196 .abort = dwc2_device_bulk_abort, 197 .close = dwc2_device_bulk_close, 198 .cleartoggle = dwc2_device_clear_toggle, 199 .done = dwc2_device_bulk_done, 200 }; 201 202 STATIC const struct usbd_pipe_methods dwc2_device_isoc_methods = { 203 .transfer = dwc2_device_isoc_transfer, 204 .start = dwc2_device_isoc_start, 205 .abort = dwc2_device_isoc_abort, 206 .close = dwc2_device_isoc_close, 207 .cleartoggle = dwc2_noop, 208 .done = dwc2_device_isoc_done, 209 }; 210 211 /* 212 * Work around the half configured control (default) pipe when setting 213 * the address of a device. 214 */ 215 STATIC int 216 dwc2_setaddr(struct usbd_device *dev, int addr) 217 { 218 if (usbd_set_address(dev, addr)) 219 return (1); 220 221 dev->address = addr; 222 223 /* 224 * Re-establish the default pipe with the new address and the 225 * new max packet size. 226 */ 227 dwc2_close_pipe(dev->default_pipe); 228 if (dwc2_open(dev->default_pipe)) 229 return (EINVAL); 230 231 return (0); 232 } 233 234 struct usbd_xfer * 235 dwc2_allocx(struct usbd_bus *bus) 236 { 237 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 238 struct dwc2_xfer *dxfer; 239 240 DPRINTFN(10, "\n"); 241 242 DWC2_EVCNT_INCR(sc->sc_ev_xferpoolget); 243 dxfer = pool_get(&sc->sc_xferpool, PR_WAITOK); 244 if (dxfer != NULL) { 245 memset(dxfer, 0, sizeof(*dxfer)); 246 dxfer->urb = dwc2_hcd_urb_alloc(sc->sc_hsotg, 247 DWC2_MAXISOCPACKETS, M_NOWAIT); 248 #ifdef DIAGNOSTIC 249 dxfer->xfer.busy_free = XFER_ONQU; 250 #endif 251 } 252 return (struct usbd_xfer *)dxfer; 253 } 254 255 void 256 dwc2_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 257 { 258 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 259 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 260 261 DPRINTFN(10, "\n"); 262 263 #ifdef DIAGNOSTIC 264 if (xfer->busy_free != XFER_ONQU && 265 xfer->status != USBD_NOT_STARTED) { 266 DPRINTF("xfer=%p not busy, 0x%08x\n", xfer, xfer->busy_free); 267 } 268 xfer->busy_free = XFER_FREE; 269 #endif 270 DWC2_EVCNT_INCR(sc->sc_ev_xferpoolput); 271 dwc2_hcd_urb_free(sc->sc_hsotg, dxfer->urb, DWC2_MAXISOCPACKETS); 272 pool_put(&sc->sc_xferpool, xfer); 273 } 274 275 STATIC void 276 dwc2_rhc(void *addr) 277 { 278 struct dwc2_softc *sc = addr; 279 struct usbd_xfer *xfer; 280 u_char *p; 281 282 DPRINTF("\n"); 283 mtx_enter(&sc->sc_lock); 284 xfer = sc->sc_intrxfer; 285 286 if (xfer == NULL) { 287 /* Just ignore the change. */ 288 mtx_leave(&sc->sc_lock); 289 return; 290 291 } 292 293 /* set port bit */ 294 p = KERNADDR(&xfer->dmabuf, 0); 295 296 p[0] = 0x02; /* we only have one port (1 << 1) */ 297 298 xfer->actlen = xfer->length; 299 xfer->status = USBD_NORMAL_COMPLETION; 300 301 usb_transfer_complete(xfer); 302 mtx_leave(&sc->sc_lock); 303 } 304 305 STATIC void 306 dwc2_softintr(void *v) 307 { 308 struct usbd_bus *bus = v; 309 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 310 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 311 struct dwc2_xfer *dxfer, *next; 312 TAILQ_HEAD(, dwc2_xfer) claimed = TAILQ_HEAD_INITIALIZER(claimed); 313 314 /* 315 * Grab all the xfers that have not been aborted or timed out. 316 * Do so under a single lock -- without dropping it to run 317 * usb_transfer_complete as we go -- so that dwc2_abortx won't 318 * remove next out from under us during iteration when we've 319 * dropped the lock. 320 */ 321 mtx_enter(&hsotg->lock); 322 TAILQ_FOREACH_SAFE(dxfer, &sc->sc_complete, xnext, next) { 323 KASSERT(dxfer->xfer.status == USBD_IN_PROGRESS); 324 KASSERT(dxfer->intr_status != USBD_CANCELLED); 325 KASSERT(dxfer->intr_status != USBD_TIMEOUT); 326 TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext); 327 TAILQ_INSERT_TAIL(&claimed, dxfer, xnext); 328 } 329 mtx_leave(&hsotg->lock); 330 331 /* Now complete them. */ 332 while (!TAILQ_EMPTY(&claimed)) { 333 dxfer = TAILQ_FIRST(&claimed); 334 KASSERT(dxfer->xfer.status == USBD_IN_PROGRESS); 335 KASSERT(dxfer->intr_status != USBD_CANCELLED); 336 KASSERT(dxfer->intr_status != USBD_TIMEOUT); 337 TAILQ_REMOVE(&claimed, dxfer, xnext); 338 339 dxfer->xfer.status = dxfer->intr_status; 340 usb_transfer_complete(&dxfer->xfer); 341 } 342 } 343 344 STATIC void 345 dwc2_timeout(void *addr) 346 { 347 struct usbd_xfer *xfer = addr; 348 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 349 350 DPRINTF("xfer=%p\n", xfer); 351 352 if (sc->sc_bus.dying) { 353 dwc2_timeout_task(addr); 354 return; 355 } 356 357 /* Execute the abort in a process context. */ 358 usb_init_task(&xfer->abort_task, dwc2_timeout_task, addr, 359 USB_TASK_TYPE_ABORT); 360 usb_add_task(xfer->device, &xfer->abort_task); 361 } 362 363 STATIC void 364 dwc2_timeout_task(void *addr) 365 { 366 struct usbd_xfer *xfer = addr; 367 int s; 368 369 DPRINTF("xfer=%p\n", xfer); 370 371 s = splusb(); 372 dwc2_abort_xfer(xfer, USBD_TIMEOUT); 373 splx(s); 374 } 375 376 usbd_status 377 dwc2_open(struct usbd_pipe *pipe) 378 { 379 struct usbd_device *dev = pipe->device; 380 struct dwc2_softc *sc = DWC2_PIPE2SC(pipe); 381 struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe); 382 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 383 uint8_t addr = dev->address; 384 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 385 usbd_status err; 386 387 DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype, 388 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? "in" : "out"); 389 390 if (sc->sc_bus.dying) { 391 return USBD_IOERROR; 392 } 393 394 if (addr == sc->sc_addr) { 395 switch (ed->bEndpointAddress) { 396 case USB_CONTROL_ENDPOINT: 397 pipe->methods = &dwc2_root_ctrl_methods; 398 break; 399 case UE_DIR_IN | DWC2_INTR_ENDPT: 400 pipe->methods = &dwc2_root_intr_methods; 401 break; 402 default: 403 DPRINTF("bad bEndpointAddress 0x%02x\n", 404 ed->bEndpointAddress); 405 return USBD_INVAL; 406 } 407 DPRINTF("root hub pipe open\n"); 408 return USBD_NORMAL_COMPLETION; 409 } 410 411 switch (xfertype) { 412 case UE_CONTROL: 413 pipe->methods = &dwc2_device_ctrl_methods; 414 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 415 0, USB_DMA_COHERENT, &dpipe->req_dma); 416 if (err) 417 return USBD_NOMEM; 418 break; 419 case UE_INTERRUPT: 420 pipe->methods = &dwc2_device_intr_methods; 421 break; 422 case UE_ISOCHRONOUS: 423 pipe->methods = &dwc2_device_isoc_methods; 424 break; 425 case UE_BULK: 426 pipe->methods = &dwc2_device_bulk_methods; 427 break; 428 default: 429 DPRINTF("bad xfer type %d\n", xfertype); 430 return USBD_INVAL; 431 } 432 433 /* QH */ 434 dpipe->priv = NULL; 435 436 return USBD_NORMAL_COMPLETION; 437 } 438 439 STATIC void 440 dwc2_poll(struct usbd_bus *bus) 441 { 442 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 443 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 444 445 mtx_enter(&hsotg->lock); 446 dwc2_interrupt(sc); 447 mtx_leave(&hsotg->lock); 448 } 449 450 /* 451 * Close a reqular pipe. 452 * Assumes that there are no pending transactions. 453 */ 454 STATIC void 455 dwc2_close_pipe(struct usbd_pipe *pipe) 456 { 457 /* nothing */ 458 } 459 460 /* 461 * Abort a device request. 462 */ 463 STATIC void 464 dwc2_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 465 { 466 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 467 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 468 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 469 struct dwc2_xfer *d; 470 int err; 471 472 splsoftassert(IPL_SOFTUSB); 473 474 DPRINTF("xfer %p pipe %p status 0x%08x\n", xfer, xfer->pipe, 475 xfer->status); 476 477 /* XXX The stack should not call abort() in this case. */ 478 if (sc->sc_bus.dying || xfer->status == USBD_NOT_STARTED) { 479 xfer->status = status; 480 timeout_del(&xfer->timeout_handle); 481 usb_rem_task(xfer->device, &xfer->abort_task); 482 usb_transfer_complete(xfer); 483 return; 484 } 485 486 KASSERT(xfer->status != USBD_CANCELLED); 487 /* Transfer is already done. */ 488 if (xfer->status != USBD_IN_PROGRESS) { 489 DPRINTF("%s: already done \n", __func__); 490 return; 491 } 492 493 /* Prevent any timeout to kick in. */ 494 timeout_del(&xfer->timeout_handle); 495 usb_rem_task(xfer->device, &xfer->abort_task); 496 497 /* Claim the transfer status as cancelled. */ 498 xfer->status = USBD_CANCELLED; 499 500 KASSERTMSG((xfer->status == USBD_CANCELLED || 501 xfer->status == USBD_TIMEOUT), 502 "bad abort status: %d", xfer->status); 503 504 mtx_enter(&hsotg->lock); 505 506 /* 507 * Check whether we aborted or timed out after the hardware 508 * completion interrupt determined that it's done but before 509 * the soft interrupt could actually complete it. If so, it's 510 * too late for the soft interrupt -- at this point we've 511 * already committed to abort it or time it out, so we need to 512 * take it off the softint's list of work in case the caller, 513 * say, frees the xfer before the softint runs. 514 * 515 * This logic is unusual among host controller drivers, and 516 * happens because dwc2 decides to complete xfers in the hard 517 * interrupt handler rather than in the soft interrupt handler, 518 * but usb_transfer_complete must be deferred to softint -- and 519 * we happened to swoop in between the hard interrupt and the 520 * soft interrupt. Other host controller drivers do almost all 521 * processing in the softint so there's no intermediate stage. 522 * 523 * Fortunately, this linear search to discern the intermediate 524 * stage is not likely to be a serious performance impact 525 * because it happens only on abort or timeout. 526 */ 527 TAILQ_FOREACH(d, &sc->sc_complete, xnext) { 528 if (d == dxfer) { 529 TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext); 530 break; 531 } 532 } 533 534 /* 535 * HC Step 1: Handle the hardware. 536 */ 537 err = dwc2_hcd_urb_dequeue(hsotg, dxfer->urb); 538 if (err) { 539 DPRINTF("dwc2_hcd_urb_dequeue failed\n"); 540 } 541 542 mtx_leave(&hsotg->lock); 543 544 /* 545 * Final Step: Notify completion to waiting xfers. 546 */ 547 usb_transfer_complete(xfer); 548 } 549 550 STATIC void 551 dwc2_noop(struct usbd_pipe *pipe) 552 { 553 554 } 555 556 STATIC void 557 dwc2_device_clear_toggle(struct usbd_pipe *pipe) 558 { 559 560 DPRINTF("toggle %d -> 0", pipe->endpoint->savedtoggle); 561 } 562 563 /***********************************************************************/ 564 565 /* 566 * Data structures and routines to emulate the root hub. 567 */ 568 569 STATIC const usb_device_descriptor_t dwc2_devd = { 570 .bLength = sizeof(usb_device_descriptor_t), 571 .bDescriptorType = UDESC_DEVICE, 572 .bcdUSB = {0x00, 0x02}, 573 .bDeviceClass = UDCLASS_HUB, 574 .bDeviceSubClass = UDSUBCLASS_HUB, 575 .bDeviceProtocol = UDPROTO_HSHUBSTT, 576 .bMaxPacketSize = 64, 577 .bcdDevice = {0x00, 0x01}, 578 .iManufacturer = 1, 579 .iProduct = 2, 580 .bNumConfigurations = 1, 581 }; 582 583 struct dwc2_config_desc { 584 usb_config_descriptor_t confd; 585 usb_interface_descriptor_t ifcd; 586 usb_endpoint_descriptor_t endpd; 587 } __packed; 588 589 STATIC const struct dwc2_config_desc dwc2_confd = { 590 .confd = { 591 .bLength = USB_CONFIG_DESCRIPTOR_SIZE, 592 .bDescriptorType = UDESC_CONFIG, 593 .wTotalLength[0] = sizeof(dwc2_confd), 594 .bNumInterfaces = 1, 595 .bConfigurationValue = 1, 596 .iConfiguration = 0, 597 .bmAttributes = UC_BUS_POWERED | UC_SELF_POWERED, 598 .bMaxPower = 0, 599 }, 600 .ifcd = { 601 .bLength = USB_INTERFACE_DESCRIPTOR_SIZE, 602 .bDescriptorType = UDESC_INTERFACE, 603 .bInterfaceNumber = 0, 604 .bAlternateSetting = 0, 605 .bNumEndpoints = 1, 606 .bInterfaceClass = UICLASS_HUB, 607 .bInterfaceSubClass = UISUBCLASS_HUB, 608 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 609 .iInterface = 0 610 }, 611 .endpd = { 612 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 613 .bDescriptorType = UDESC_ENDPOINT, 614 .bEndpointAddress = UE_DIR_IN | DWC2_INTR_ENDPT, 615 .bmAttributes = UE_INTERRUPT, 616 .wMaxPacketSize = {8, 0}, /* max packet */ 617 .bInterval = 255, 618 }, 619 }; 620 621 STATIC usbd_status 622 dwc2_root_ctrl_transfer(struct usbd_xfer *xfer) 623 { 624 usbd_status err; 625 626 err = usb_insert_transfer(xfer); 627 if (err) 628 return err; 629 630 return dwc2_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 631 } 632 633 STATIC usbd_status 634 dwc2_root_ctrl_start(struct usbd_xfer *xfer) 635 { 636 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 637 usb_device_request_t *req; 638 uint8_t *buf; 639 uint16_t len; 640 int value, index, l, s, totlen; 641 usbd_status err = USBD_IOERROR; 642 643 if (sc->sc_bus.dying) 644 return USBD_IOERROR; 645 646 req = &xfer->request; 647 648 DPRINTFN(4, "type=0x%02x request=%02x\n", 649 req->bmRequestType, req->bRequest); 650 651 len = UGETW(req->wLength); 652 value = UGETW(req->wValue); 653 index = UGETW(req->wIndex); 654 655 buf = len ? KERNADDR(&xfer->dmabuf, 0) : NULL; 656 657 totlen = 0; 658 659 #define C(x,y) ((x) | ((y) << 8)) 660 switch (C(req->bRequest, req->bmRequestType)) { 661 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 662 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 663 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 664 /* 665 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 666 * for the integrated root hub. 667 */ 668 break; 669 case C(UR_GET_CONFIG, UT_READ_DEVICE): 670 if (len > 0) { 671 *buf = sc->sc_conf; 672 totlen = 1; 673 } 674 break; 675 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 676 DPRINTFN(8, "wValue=0x%04x\n", value); 677 678 if (len == 0) 679 break; 680 switch (value) { 681 case C(0, UDESC_DEVICE): 682 l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 683 memcpy(buf, &dwc2_devd, l); 684 buf += l; 685 len -= l; 686 totlen += l; 687 688 break; 689 case C(0, UDESC_CONFIG): 690 l = min(len, sizeof(dwc2_confd)); 691 memcpy(buf, &dwc2_confd, l); 692 buf += l; 693 len -= l; 694 totlen += l; 695 696 break; 697 #define sd ((usb_string_descriptor_t *)buf) 698 case C(0, UDESC_STRING): 699 totlen = usbd_str(sd, len, "\001"); 700 break; 701 case C(1, UDESC_STRING): 702 totlen = usbd_str(sd, len, sc->sc_vendor); 703 break; 704 case C(2, UDESC_STRING): 705 totlen = usbd_str(sd, len, "DWC2 root hub"); 706 break; 707 #undef sd 708 default: 709 goto fail; 710 } 711 break; 712 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 713 if (len > 0) { 714 *buf = 0; 715 totlen = 1; 716 } 717 break; 718 case C(UR_GET_STATUS, UT_READ_DEVICE): 719 if (len > 1) { 720 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 721 totlen = 2; 722 } 723 break; 724 case C(UR_GET_STATUS, UT_READ_INTERFACE): 725 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 726 if (len > 1) { 727 USETW(((usb_status_t *)buf)->wStatus, 0); 728 totlen = 2; 729 } 730 break; 731 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 732 DPRINTF("UR_SET_ADDRESS, UT_WRITE_DEVICE: addr %d\n", 733 value); 734 if (value >= USB_MAX_DEVICES) 735 goto fail; 736 737 sc->sc_addr = value; 738 break; 739 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 740 if (value != 0 && value != 1) 741 goto fail; 742 743 sc->sc_conf = value; 744 break; 745 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 746 break; 747 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 748 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 749 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 750 err = USBD_IOERROR; 751 goto fail; 752 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 753 break; 754 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 755 break; 756 default: 757 /* Hub requests - XXXNH len check? */ 758 err = dwc2_hcd_hub_control(sc->sc_hsotg, 759 C(req->bRequest, req->bmRequestType), value, index, 760 buf, len); 761 if (err) { 762 err = USBD_IOERROR; 763 goto fail; 764 } 765 totlen = len; 766 } 767 xfer->actlen = totlen; 768 err = USBD_NORMAL_COMPLETION; 769 770 fail: 771 s = splusb(); 772 xfer->status = err; 773 usb_transfer_complete(xfer); 774 splx(s); 775 776 return err; 777 } 778 779 STATIC void 780 dwc2_root_ctrl_abort(struct usbd_xfer *xfer) 781 { 782 DPRINTFN(10, "\n"); 783 784 /* Nothing to do, all transfers are synchronous. */ 785 } 786 787 STATIC void 788 dwc2_root_ctrl_close(struct usbd_pipe *pipe) 789 { 790 DPRINTFN(10, "\n"); 791 792 /* Nothing to do. */ 793 } 794 795 STATIC void 796 dwc2_root_ctrl_done(struct usbd_xfer *xfer) 797 { 798 DPRINTFN(10, "\n"); 799 800 /* Nothing to do. */ 801 } 802 803 STATIC usbd_status 804 dwc2_root_intr_transfer(struct usbd_xfer *xfer) 805 { 806 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 807 usbd_status err; 808 809 DPRINTF("\n"); 810 811 /* Insert last in queue. */ 812 mtx_enter(&sc->sc_lock); 813 err = usb_insert_transfer(xfer); 814 mtx_leave(&sc->sc_lock); 815 if (err) 816 return err; 817 818 /* Pipe isn't running, start first */ 819 return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 820 } 821 822 STATIC usbd_status 823 dwc2_root_intr_start(struct usbd_xfer *xfer) 824 { 825 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 826 const bool polling = sc->sc_bus.use_polling; 827 828 DPRINTF("\n"); 829 830 if (sc->sc_bus.dying) 831 return USBD_IOERROR; 832 833 if (!polling) 834 mtx_enter(&sc->sc_lock); 835 KASSERT(sc->sc_intrxfer == NULL); 836 sc->sc_intrxfer = xfer; 837 xfer->status = USBD_IN_PROGRESS; 838 if (!polling) 839 mtx_leave(&sc->sc_lock); 840 841 return USBD_IN_PROGRESS; 842 } 843 844 /* Abort a root interrupt request. */ 845 STATIC void 846 dwc2_root_intr_abort(struct usbd_xfer *xfer) 847 { 848 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 849 850 DPRINTF("xfer=%p\n", xfer); 851 852 /* If xfer has already completed, nothing to do here. */ 853 if (sc->sc_intrxfer == NULL) 854 return; 855 856 /* 857 * Otherwise, sc->sc_intrxfer had better be this transfer. 858 * Cancel it. 859 */ 860 KASSERT(sc->sc_intrxfer == xfer); 861 KASSERT(xfer->status == USBD_IN_PROGRESS); 862 xfer->status = USBD_CANCELLED; 863 usb_transfer_complete(xfer); 864 } 865 866 STATIC void 867 dwc2_root_intr_close(struct usbd_pipe *pipe) 868 { 869 struct dwc2_softc *sc = DWC2_PIPE2SC(pipe); 870 871 DPRINTF("\n"); 872 873 /* 874 * Caller must guarantee the xfer has completed first, by 875 * closing the pipe only after normal completion or an abort. 876 */ 877 if (sc->sc_intrxfer == NULL) 878 panic("%s: sc->sc_intrxfer == NULL", __func__); 879 } 880 881 STATIC void 882 dwc2_root_intr_done(struct usbd_xfer *xfer) 883 { 884 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 885 886 DPRINTF("\n"); 887 888 /* Claim the xfer so it doesn't get completed again. */ 889 KASSERT(sc->sc_intrxfer == xfer); 890 KASSERT(xfer->status != USBD_IN_PROGRESS); 891 sc->sc_intrxfer = NULL; 892 } 893 894 /***********************************************************************/ 895 896 STATIC usbd_status 897 dwc2_device_ctrl_transfer(struct usbd_xfer *xfer) 898 { 899 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 900 usbd_status err; 901 902 DPRINTF("\n"); 903 904 /* Insert last in queue. */ 905 mtx_enter(&sc->sc_lock); 906 err = usb_insert_transfer(xfer); 907 mtx_leave(&sc->sc_lock); 908 if (err) 909 return err; 910 911 /* Pipe isn't running, start first */ 912 return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 913 } 914 915 STATIC usbd_status 916 dwc2_device_ctrl_start(struct usbd_xfer *xfer) 917 { 918 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 919 usbd_status err; 920 const bool polling = sc->sc_bus.use_polling; 921 922 DPRINTF("\n"); 923 924 if (!polling) 925 mtx_enter(&sc->sc_lock); 926 xfer->status = USBD_IN_PROGRESS; 927 err = dwc2_device_start(xfer); 928 if (!polling) 929 mtx_leave(&sc->sc_lock); 930 931 if (err) 932 return err; 933 934 return USBD_IN_PROGRESS; 935 } 936 937 STATIC void 938 dwc2_device_ctrl_abort(struct usbd_xfer *xfer) 939 { 940 DPRINTF("xfer=%p\n", xfer); 941 dwc2_abort_xfer(xfer, USBD_CANCELLED); 942 } 943 944 STATIC void 945 dwc2_device_ctrl_close(struct usbd_pipe *pipe) 946 { 947 struct dwc2_softc * const sc = DWC2_PIPE2SC(pipe); 948 struct dwc2_pipe * const dpipe = DWC2_PIPE2DPIPE(pipe); 949 950 DPRINTF("pipe=%p\n", pipe); 951 dwc2_close_pipe(pipe); 952 953 usb_freemem(&sc->sc_bus, &dpipe->req_dma); 954 } 955 956 STATIC void 957 dwc2_device_ctrl_done(struct usbd_xfer *xfer) 958 { 959 960 DPRINTF("xfer=%p\n", xfer); 961 } 962 963 /***********************************************************************/ 964 965 STATIC usbd_status 966 dwc2_device_bulk_transfer(struct usbd_xfer *xfer) 967 { 968 usbd_status err; 969 970 DPRINTF("xfer=%p\n", xfer); 971 972 /* Insert last in queue. */ 973 err = usb_insert_transfer(xfer); 974 if (err) 975 return err; 976 977 /* Pipe isn't running, start first */ 978 return dwc2_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 979 } 980 981 STATIC usbd_status 982 dwc2_device_bulk_start(struct usbd_xfer *xfer) 983 { 984 usbd_status err; 985 986 DPRINTF("xfer=%p\n", xfer); 987 988 xfer->status = USBD_IN_PROGRESS; 989 err = dwc2_device_start(xfer); 990 991 return err; 992 } 993 994 STATIC void 995 dwc2_device_bulk_abort(struct usbd_xfer *xfer) 996 { 997 DPRINTF("xfer=%p\n", xfer); 998 999 dwc2_abort_xfer(xfer, USBD_CANCELLED); 1000 } 1001 1002 STATIC void 1003 dwc2_device_bulk_close(struct usbd_pipe *pipe) 1004 { 1005 1006 DPRINTF("pipe=%p\n", pipe); 1007 1008 dwc2_close_pipe(pipe); 1009 } 1010 1011 STATIC void 1012 dwc2_device_bulk_done(struct usbd_xfer *xfer) 1013 { 1014 1015 DPRINTF("xfer=%p\n", xfer); 1016 } 1017 1018 /***********************************************************************/ 1019 1020 STATIC usbd_status 1021 dwc2_device_intr_transfer(struct usbd_xfer *xfer) 1022 { 1023 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1024 usbd_status err; 1025 1026 DPRINTF("xfer=%p\n", xfer); 1027 1028 /* Insert last in queue. */ 1029 mtx_enter(&sc->sc_lock); 1030 err = usb_insert_transfer(xfer); 1031 mtx_leave(&sc->sc_lock); 1032 if (err) 1033 return err; 1034 1035 /* Pipe isn't running, start first */ 1036 return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 1037 } 1038 1039 STATIC usbd_status 1040 dwc2_device_intr_start(struct usbd_xfer *xfer) 1041 { 1042 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1043 usbd_status err; 1044 const bool polling = sc->sc_bus.use_polling; 1045 1046 if (!polling) 1047 mtx_enter(&sc->sc_lock); 1048 xfer->status = USBD_IN_PROGRESS; 1049 err = dwc2_device_start(xfer); 1050 if (!polling) 1051 mtx_leave(&sc->sc_lock); 1052 1053 if (err) 1054 return err; 1055 1056 return USBD_IN_PROGRESS; 1057 } 1058 1059 /* Abort a device interrupt request. */ 1060 STATIC void 1061 dwc2_device_intr_abort(struct usbd_xfer *xfer) 1062 { 1063 KASSERT(xfer->pipe->intrxfer == xfer); 1064 1065 DPRINTF("xfer=%p\n", xfer); 1066 1067 dwc2_abort_xfer(xfer, USBD_CANCELLED); 1068 } 1069 1070 STATIC void 1071 dwc2_device_intr_close(struct usbd_pipe *pipe) 1072 { 1073 1074 DPRINTF("pipe=%p\n", pipe); 1075 1076 dwc2_close_pipe(pipe); 1077 } 1078 1079 STATIC void 1080 dwc2_device_intr_done(struct usbd_xfer *xfer) 1081 { 1082 1083 DPRINTF("\n"); 1084 1085 if (xfer->pipe->repeat) { 1086 xfer->status = USBD_IN_PROGRESS; 1087 dwc2_device_start(xfer); 1088 } 1089 } 1090 1091 /***********************************************************************/ 1092 1093 usbd_status 1094 dwc2_device_isoc_transfer(struct usbd_xfer *xfer) 1095 { 1096 usbd_status err; 1097 1098 DPRINTF("xfer=%p\n", xfer); 1099 1100 /* Insert last in queue. */ 1101 err = usb_insert_transfer(xfer); 1102 if (err) 1103 return err; 1104 1105 /* Pipe isn't running, start first */ 1106 return dwc2_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 1107 } 1108 1109 usbd_status 1110 dwc2_device_isoc_start(struct usbd_xfer *xfer) 1111 { 1112 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1113 struct dwc2_softc *sc = DWC2_DPIPE2SC(dpipe); 1114 usbd_status err; 1115 1116 /* Why would you do that anyway? */ 1117 if (sc->sc_bus.use_polling) 1118 return (USBD_INVAL); 1119 1120 xfer->status = USBD_IN_PROGRESS; 1121 err = dwc2_device_start(xfer); 1122 1123 return err; 1124 } 1125 1126 void 1127 dwc2_device_isoc_abort(struct usbd_xfer *xfer) 1128 { 1129 DPRINTF("xfer=%p\n", xfer); 1130 1131 dwc2_abort_xfer(xfer, USBD_CANCELLED); 1132 } 1133 1134 void 1135 dwc2_device_isoc_close(struct usbd_pipe *pipe) 1136 { 1137 DPRINTF("\n"); 1138 1139 dwc2_close_pipe(pipe); 1140 } 1141 1142 void 1143 dwc2_device_isoc_done(struct usbd_xfer *xfer) 1144 { 1145 1146 DPRINTF("\n"); 1147 } 1148 1149 1150 usbd_status 1151 dwc2_device_start(struct usbd_xfer *xfer) 1152 { 1153 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 1154 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1155 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1156 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 1157 struct dwc2_hcd_urb *dwc2_urb; 1158 1159 struct usbd_device *dev = xfer->pipe->device; 1160 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 1161 uint8_t addr = dev->address; 1162 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1163 uint8_t epnum = UE_GET_ADDR(ed->bEndpointAddress); 1164 uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 1165 uint16_t mps = UE_GET_SIZE(UGETW(ed->wMaxPacketSize)); 1166 uint32_t len; 1167 1168 uint32_t flags = 0; 1169 uint32_t off = 0; 1170 int retval, err; 1171 int alloc_bandwidth = 0; 1172 1173 DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->pipe); 1174 1175 if (xfertype == UE_ISOCHRONOUS || 1176 xfertype == UE_INTERRUPT) { 1177 mtx_enter(&hsotg->lock); 1178 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, xfer)) 1179 alloc_bandwidth = 1; 1180 mtx_leave(&hsotg->lock); 1181 } 1182 1183 /* 1184 * For Control pipe the direction is from the request, all other 1185 * transfers have been set correctly at pipe open time. 1186 */ 1187 if (xfertype == UE_CONTROL) { 1188 usb_device_request_t *req = &xfer->request; 1189 1190 DPRINTFN(3, "xfer=%p type=0x%02x request=0x%02x wValue=0x%04x " 1191 "wIndex=0x%04x len=%d addr=%d endpt=%d dir=%s speed=%d " 1192 "mps=%d\n", 1193 xfer, req->bmRequestType, req->bRequest, UGETW(req->wValue), 1194 UGETW(req->wIndex), UGETW(req->wLength), dev->address, 1195 epnum, dir == UT_READ ? "in" :"out", dev->speed, mps); 1196 1197 /* Copy request packet to our DMA buffer */ 1198 memcpy(KERNADDR(&dpipe->req_dma, 0), req, sizeof(*req)); 1199 usb_syncmem(&dpipe->req_dma, 0, sizeof(*req), 1200 BUS_DMASYNC_PREWRITE); 1201 len = UGETW(req->wLength); 1202 if ((req->bmRequestType & UT_READ) == UT_READ) { 1203 dir = UE_DIR_IN; 1204 } else { 1205 dir = UE_DIR_OUT; 1206 } 1207 1208 DPRINTFN(3, "req = %p dma = %llx len %d dir %s\n", 1209 KERNADDR(&dpipe->req_dma, 0), 1210 (long long)DMAADDR(&dpipe->req_dma, 0), 1211 len, dir == UE_DIR_IN ? "in" : "out"); 1212 } else if (xfertype == UE_ISOCHRONOUS) { 1213 DPRINTFN(3, "xfer=%p nframes=%d flags=%d addr=%d endpt=%d," 1214 " mps=%d dir %s\n", xfer, xfer->nframes, xfer->flags, addr, 1215 epnum, mps, dir == UT_READ ? "in" :"out"); 1216 1217 #ifdef DIAGNOSTIC 1218 len = 0; 1219 for (size_t i = 0; i < xfer->nframes; i++) 1220 len += xfer->frlengths[i]; 1221 if (len != xfer->length) 1222 panic("len (%d) != xfer->length (%d)", len, 1223 xfer->length); 1224 #endif 1225 len = xfer->length; 1226 } else { 1227 DPRINTFN(3, "xfer=%p len=%d flags=%d addr=%d endpt=%d," 1228 " mps=%d dir %s\n", xfer, xfer->length, xfer->flags, addr, 1229 epnum, mps, dir == UT_READ ? "in" :"out"); 1230 1231 len = xfer->length; 1232 } 1233 1234 dwc2_urb = dxfer->urb; 1235 if (!dwc2_urb) 1236 return USBD_NOMEM; 1237 1238 // KASSERT(dwc2_urb->packet_count == xfer->nframes); 1239 memset(dwc2_urb, 0, sizeof(*dwc2_urb) + 1240 sizeof(dwc2_urb->iso_descs[0]) * DWC2_MAXISOCPACKETS); 1241 1242 dwc2_urb->priv = xfer; 1243 dwc2_urb->packet_count = xfer->nframes; 1244 1245 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, addr, epnum, xfertype, dir, 1246 mps); 1247 1248 if (xfertype == UE_CONTROL) { 1249 dwc2_urb->setup_usbdma = &dpipe->req_dma; 1250 dwc2_urb->setup_packet = KERNADDR(&dpipe->req_dma, 0); 1251 dwc2_urb->setup_dma = DMAADDR(&dpipe->req_dma, 0); 1252 } else { 1253 /* XXXNH - % mps required? */ 1254 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && (len % mps) == 0) 1255 flags |= URB_SEND_ZERO_PACKET; 1256 } 1257 flags |= URB_GIVEBACK_ASAP; 1258 1259 /* 1260 * control transfers with no data phase don't touch usbdma, but 1261 * everything else does. 1262 */ 1263 if (!(xfertype == UE_CONTROL && len == 0)) { 1264 dwc2_urb->usbdma = &xfer->dmabuf; 1265 dwc2_urb->buf = KERNADDR(dwc2_urb->usbdma, 0); 1266 dwc2_urb->dma = DMAADDR(dwc2_urb->usbdma, 0); 1267 1268 usb_syncmem(&xfer->dmabuf, 0, len, 1269 dir == UE_DIR_IN ? 1270 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1271 } 1272 dwc2_urb->length = len; 1273 dwc2_urb->flags = flags; 1274 dwc2_urb->status = -EINPROGRESS; 1275 1276 if (xfertype == UE_INTERRUPT || 1277 xfertype == UE_ISOCHRONOUS) { 1278 uint16_t ival; 1279 1280 if (xfertype == UE_INTERRUPT && 1281 dpipe->pipe.interval != USBD_DEFAULT_INTERVAL) { 1282 ival = dpipe->pipe.interval; 1283 } else { 1284 ival = ed->bInterval; 1285 } 1286 1287 if (ival < 1) { 1288 retval = -ENODEV; 1289 goto fail; 1290 } 1291 if (dev->speed == USB_SPEED_HIGH || 1292 (dev->speed == USB_SPEED_FULL && xfertype == UE_ISOCHRONOUS)) { 1293 if (ival > 16) { 1294 /* 1295 * illegal with HS/FS, but there were 1296 * documentation bugs in the spec 1297 */ 1298 ival = 256; 1299 } else { 1300 ival = (1 << (ival - 1)); 1301 } 1302 } else { 1303 if (xfertype == UE_INTERRUPT && ival < 10) 1304 ival = 10; 1305 } 1306 dwc2_urb->interval = ival; 1307 } 1308 1309 /* XXXNH bring down from callers?? */ 1310 // mtx_enter(&sc->sc_lock); 1311 1312 xfer->actlen = 0; 1313 1314 KASSERT(xfertype != UE_ISOCHRONOUS || 1315 xfer->nframes <= DWC2_MAXISOCPACKETS); 1316 KASSERTMSG(xfer->nframes == 0 || xfertype == UE_ISOCHRONOUS, 1317 "nframes %d xfertype %d\n", xfer->nframes, xfertype); 1318 1319 off = 0; 1320 for (size_t i = 0; i < xfer->nframes; ++i) { 1321 DPRINTFN(3, "xfer=%p frame=%zu offset=%d length=%d\n", xfer, i, 1322 off, xfer->frlengths[i]); 1323 1324 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, off, 1325 xfer->frlengths[i]); 1326 off += xfer->frlengths[i]; 1327 } 1328 1329 struct dwc2_qh *qh = dpipe->priv; 1330 struct dwc2_qtd *qtd; 1331 bool qh_allocated = false; 1332 1333 /* Create QH for the endpoint if it doesn't exist */ 1334 if (!qh) { 1335 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, M_NOWAIT); 1336 if (!qh) { 1337 retval = -ENOMEM; 1338 goto fail; 1339 } 1340 dpipe->priv = qh; 1341 qh_allocated = true; 1342 } 1343 1344 qtd = pool_get(&sc->sc_qtdpool, PR_NOWAIT); 1345 if (!qtd) { 1346 retval = -ENOMEM; 1347 goto fail1; 1348 } 1349 memset(qtd, 0, sizeof(*qtd)); 1350 1351 /* might need to check cpu_intr_p */ 1352 mtx_enter(&hsotg->lock); 1353 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 1354 if (retval) 1355 goto fail2; 1356 if (xfer->timeout && !sc->sc_bus.use_polling) { 1357 timeout_set(&xfer->timeout_handle, dwc2_timeout, xfer); 1358 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 1359 } 1360 xfer->status = USBD_IN_PROGRESS; 1361 1362 if (alloc_bandwidth) { 1363 dwc2_allocate_bus_bandwidth(hsotg, 1364 dwc2_hcd_get_ep_bandwidth(hsotg, dpipe), 1365 xfer); 1366 } 1367 mtx_leave(&hsotg->lock); 1368 1369 return USBD_IN_PROGRESS; 1370 1371 fail2: 1372 dwc2_urb->priv = NULL; 1373 mtx_leave(&hsotg->lock); 1374 pool_put(&sc->sc_qtdpool, qtd); 1375 1376 fail1: 1377 if (qh_allocated) { 1378 dpipe->priv = NULL; 1379 dwc2_hcd_qh_free(hsotg, qh); 1380 } 1381 fail: 1382 1383 switch (retval) { 1384 case -EINVAL: 1385 case -ENODEV: 1386 err = USBD_INVAL; 1387 break; 1388 case -ENOMEM: 1389 err = USBD_NOMEM; 1390 break; 1391 default: 1392 err = USBD_IOERROR; 1393 } 1394 1395 return err; 1396 1397 } 1398 1399 int dwc2_intr(void *p) 1400 { 1401 struct dwc2_softc *sc = p; 1402 struct dwc2_hsotg *hsotg; 1403 int ret = 0; 1404 1405 if (sc == NULL) 1406 return 0; 1407 1408 hsotg = sc->sc_hsotg; 1409 mtx_enter(&hsotg->lock); 1410 1411 if (sc->sc_bus.dying) 1412 goto done; 1413 1414 if (sc->sc_bus.use_polling) { 1415 uint32_t intrs; 1416 1417 intrs = dwc2_read_core_intr(hsotg); 1418 DWC2_WRITE_4(hsotg, GINTSTS, intrs); 1419 } else { 1420 ret = dwc2_interrupt(sc); 1421 } 1422 1423 done: 1424 mtx_leave(&hsotg->lock); 1425 1426 return ret; 1427 } 1428 1429 int 1430 dwc2_interrupt(struct dwc2_softc *sc) 1431 { 1432 int ret = 0; 1433 1434 if (sc->sc_hcdenabled) { 1435 ret |= dwc2_handle_hcd_intr(sc->sc_hsotg); 1436 } 1437 1438 ret |= dwc2_handle_common_intr(sc->sc_hsotg); 1439 1440 return ret; 1441 } 1442 1443 /***********************************************************************/ 1444 1445 int 1446 dwc2_detach(struct dwc2_softc *sc, int flags) 1447 { 1448 int rv = 0; 1449 1450 if (sc->sc_child != NULL) 1451 rv = config_detach(sc->sc_child, flags); 1452 1453 return rv; 1454 } 1455 1456 /***********************************************************************/ 1457 int 1458 dwc2_init(struct dwc2_softc *sc) 1459 { 1460 int err = 0; 1461 1462 sc->sc_bus.usbrev = USBREV_2_0; 1463 sc->sc_bus.methods = &dwc2_bus_methods; 1464 sc->sc_bus.pipe_size = sizeof(struct dwc2_pipe); 1465 sc->sc_hcdenabled = false; 1466 1467 mtx_init(&sc->sc_lock, IPL_SOFTUSB); 1468 1469 TAILQ_INIT(&sc->sc_complete); 1470 1471 sc->sc_rhc_si = softintr_establish(IPL_SOFTUSB, dwc2_rhc, sc); 1472 1473 pool_init(&sc->sc_xferpool, sizeof(struct dwc2_xfer), 0, IPL_USB, 0, 1474 "dwc2xfer", NULL); 1475 pool_init(&sc->sc_qhpool, sizeof(struct dwc2_qh), 0, IPL_USB, 0, 1476 "dwc2qh", NULL); 1477 pool_init(&sc->sc_qtdpool, sizeof(struct dwc2_qtd), 0, IPL_USB, 0, 1478 "dwc2qtd", NULL); 1479 1480 sc->sc_hsotg = malloc(sizeof(struct dwc2_hsotg), M_USBHC, 1481 M_ZERO | M_WAITOK); 1482 sc->sc_hsotg->hsotg_sc = sc; 1483 sc->sc_hsotg->dev = &sc->sc_bus.bdev; 1484 sc->sc_hcdenabled = true; 1485 1486 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 1487 struct dwc2_core_params defparams; 1488 int retval; 1489 1490 if (sc->sc_params == NULL) { 1491 /* Default all params to autodetect */ 1492 dwc2_set_all_params(&defparams, -1); 1493 sc->sc_params = &defparams; 1494 1495 /* 1496 * Disable descriptor dma mode by default as the HW can support 1497 * it, but does not support it for SPLIT transactions. 1498 */ 1499 defparams.dma_desc_enable = 0; 1500 } 1501 hsotg->dr_mode = USB_DR_MODE_HOST; 1502 1503 /* 1504 * Reset before dwc2_get_hwparams() then it could get power-on real 1505 * reset value form registers. 1506 */ 1507 dwc2_core_reset(hsotg); 1508 usb_delay_ms(&sc->sc_bus, 500); 1509 1510 /* Detect config values from hardware */ 1511 retval = dwc2_get_hwparams(hsotg); 1512 if (retval) { 1513 goto fail2; 1514 } 1515 1516 hsotg->core_params = malloc(sizeof(*hsotg->core_params), M_USBHC, 1517 M_ZERO | M_WAITOK); 1518 dwc2_set_all_params(hsotg->core_params, -1); 1519 1520 /* Validate parameter values */ 1521 dwc2_set_parameters(hsotg, sc->sc_params); 1522 1523 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1524 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1525 if (hsotg->dr_mode != USB_DR_MODE_HOST) { 1526 retval = dwc2_gadget_init(hsotg); 1527 if (retval) 1528 goto fail2; 1529 hsotg->gadget_enabled = 1; 1530 } 1531 #endif 1532 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \ 1533 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1534 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { 1535 retval = dwc2_hcd_init(hsotg); 1536 if (retval) { 1537 if (hsotg->gadget_enabled) 1538 dwc2_hsotg_remove(hsotg); 1539 goto fail2; 1540 } 1541 hsotg->hcd_enabled = 1; 1542 } 1543 #endif 1544 1545 #ifdef DWC2_DEBUG 1546 uint32_t snpsid = hsotg->hw_params.snpsid; 1547 dev_dbg(hsotg->dev, "Core Release: %x.%x%x%x (snpsid=%x)\n", 1548 snpsid >> 12 & 0xf, snpsid >> 8 & 0xf, 1549 snpsid >> 4 & 0xf, snpsid & 0xf, snpsid); 1550 #endif 1551 1552 return 0; 1553 1554 fail2: 1555 err = -retval; 1556 free(sc->sc_hsotg, M_USBHC, sizeof(struct dwc2_hsotg)); 1557 softintr_disestablish(sc->sc_rhc_si); 1558 1559 return err; 1560 } 1561 1562 #if 0 1563 /* 1564 * curmode is a mode indication bit 0 = device, 1 = host 1565 */ 1566 STATIC const char * const intnames[32] = { 1567 "curmode", "modemis", "otgint", "sof", 1568 "rxflvl", "nptxfemp", "ginnakeff", "goutnakeff", 1569 "ulpickint", "i2cint", "erlysusp", "usbsusp", 1570 "usbrst", "enumdone", "isooutdrop", "eopf", 1571 "restore_done", "epmis", "iepint", "oepint", 1572 "incompisoin", "incomplp", "fetsusp", "resetdet", 1573 "prtint", "hchint", "ptxfemp", "lpm", 1574 "conidstschng", "disconnint", "sessreqint", "wkupint" 1575 }; 1576 1577 1578 /***********************************************************************/ 1579 1580 #endif 1581 1582 1583 void 1584 dw_timeout(void *arg) 1585 { 1586 struct delayed_work *dw = arg; 1587 1588 task_set(&dw->work, dw->dw_fn, dw->dw_arg); 1589 task_add(dw->dw_wq, &dw->work); 1590 } 1591 1592 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 1593 int *hub_port) 1594 { 1595 struct usbd_xfer *xfer = context; 1596 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1597 struct usbd_device *dev = dpipe->pipe.device; 1598 1599 *hub_addr = dev->myhsport->parent->address; 1600 *hub_port = dev->myhsport->portno; 1601 } 1602 1603 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 1604 { 1605 struct usbd_xfer *xfer = context; 1606 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1607 struct usbd_device *dev = dpipe->pipe.device; 1608 1609 return dev->speed; 1610 } 1611 1612 /* 1613 * Sets the final status of an URB and returns it to the upper layer. Any 1614 * required cleanup of the URB is performed. 1615 * 1616 * Must be called with interrupt disabled and spinlock held 1617 */ 1618 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 1619 int status) 1620 { 1621 struct usbd_xfer *xfer; 1622 struct dwc2_xfer *dxfer; 1623 struct dwc2_softc *sc; 1624 usb_endpoint_descriptor_t *ed; 1625 uint8_t xfertype; 1626 1627 if (!qtd) { 1628 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 1629 return; 1630 } 1631 1632 if (!qtd->urb) { 1633 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 1634 return; 1635 } 1636 1637 xfer = qtd->urb->priv; 1638 if (!xfer) { 1639 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 1640 return; 1641 } 1642 1643 dxfer = DWC2_XFER2DXFER(xfer); 1644 sc = DWC2_XFER2SC(xfer); 1645 ed = xfer->pipe->endpoint->edesc; 1646 xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1647 1648 struct dwc2_hcd_urb *urb = qtd->urb; 1649 xfer->actlen = dwc2_hcd_urb_get_actual_length(urb); 1650 1651 DPRINTFN(3, "xfer=%p actlen=%d\n", xfer, xfer->actlen); 1652 1653 if (xfertype == UE_ISOCHRONOUS) { 1654 xfer->actlen = 0; 1655 for (size_t i = 0; i < xfer->nframes; ++i) { 1656 xfer->frlengths[i] = 1657 dwc2_hcd_urb_get_iso_desc_actual_length( 1658 urb, i); 1659 DPRINTFN(1, "xfer=%p frame=%zu length=%d\n", xfer, i, 1660 xfer->frlengths[i]); 1661 xfer->actlen += xfer->frlengths[i]; 1662 } 1663 DPRINTFN(1, "xfer=%p actlen=%d (isoc)\n", xfer, xfer->actlen); 1664 } 1665 1666 if (xfertype == UE_ISOCHRONOUS && dbg_perio()) { 1667 for (size_t i = 0; i < xfer->nframes; i++) 1668 dev_vdbg(hsotg->dev, " ISO Desc %zu status %d\n", 1669 i, urb->iso_descs[i].status); 1670 } 1671 1672 if (!status) { 1673 if (!(xfer->flags & USBD_SHORT_XFER_OK) && 1674 xfer->actlen < xfer->length) 1675 status = -EIO; 1676 } 1677 1678 switch (status) { 1679 case 0: 1680 dxfer->intr_status = USBD_NORMAL_COMPLETION; 1681 break; 1682 case -EPIPE: 1683 dxfer->intr_status = USBD_STALLED; 1684 break; 1685 case -EPROTO: 1686 dxfer->intr_status = USBD_INVAL; 1687 break; 1688 case -EIO: 1689 dxfer->intr_status = USBD_IOERROR; 1690 break; 1691 case -EOVERFLOW: 1692 dxfer->intr_status = USBD_IOERROR; 1693 break; 1694 default: 1695 dxfer->intr_status = USBD_IOERROR; 1696 printf("%s: unknown error status %d\n", __func__, status); 1697 } 1698 1699 if (dxfer->intr_status == USBD_NORMAL_COMPLETION) { 1700 /* 1701 * control transfers with no data phase don't touch dmabuf, but 1702 * everything else does. 1703 */ 1704 if (!(xfertype == UE_CONTROL && 1705 UGETW(xfer->request.wLength) == 0) && 1706 xfer->actlen > 0 /* XXX PR/53503 */ 1707 ) { 1708 int rd = usbd_xfer_isread(xfer); 1709 1710 usb_syncmem(&xfer->dmabuf, 0, xfer->actlen, 1711 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1712 } 1713 } 1714 1715 if (xfertype == UE_ISOCHRONOUS || 1716 xfertype == UE_INTERRUPT) { 1717 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1718 1719 dwc2_free_bus_bandwidth(hsotg, 1720 dwc2_hcd_get_ep_bandwidth(hsotg, dpipe), 1721 xfer); 1722 } 1723 1724 qtd->urb = NULL; 1725 timeout_del(&xfer->timeout_handle); 1726 usb_rem_task(xfer->device, &xfer->abort_task); 1727 MUTEX_ASSERT_LOCKED(&hsotg->lock); 1728 1729 TAILQ_INSERT_TAIL(&sc->sc_complete, dxfer, xnext); 1730 1731 mtx_leave(&hsotg->lock); 1732 usb_schedsoftintr(&sc->sc_bus); 1733 mtx_enter(&hsotg->lock); 1734 } 1735 1736 1737 int 1738 _dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1739 { 1740 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 1741 1742 mtx_enter(&hsotg->lock); 1743 1744 hsotg->lx_state = DWC2_L0; 1745 1746 if (dwc2_is_device_mode(hsotg)) { 1747 mtx_leave(&hsotg->lock); 1748 return 0; /* why 0 ?? */ 1749 } 1750 1751 dwc2_hcd_reinit(hsotg); 1752 1753 mtx_leave(&hsotg->lock); 1754 return 0; 1755 } 1756 1757 int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 1758 { 1759 1760 return false; 1761 } 1762