1 /* $OpenBSD: dwc2.c,v 1.56 2021/07/23 21:47:22 mglocker Exp $ */ 2 /* $NetBSD: dwc2.c,v 1.32 2014/09/02 23:26:20 macallan Exp $ */ 3 4 /*- 5 * Copyright (c) 2013 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Nick Hudson 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/device.h> 38 #include <sys/select.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 #include <sys/endian.h> 42 43 #include <machine/bus.h> 44 45 #include <dev/usb/usb.h> 46 #include <dev/usb/usbdi.h> 47 #include <dev/usb/usbdivar.h> 48 #include <dev/usb/usb_mem.h> 49 50 #include <dev/usb/dwc2/dwc2.h> 51 #include <dev/usb/dwc2/dwc2var.h> 52 53 #include <dev/usb/dwc2/dwc2_core.h> 54 #include <dev/usb/dwc2/dwc2_hcd.h> 55 56 #ifdef DWC2_COUNTERS 57 #define DWC2_EVCNT_ADD(a,b) ((void)((a).ev_count += (b))) 58 #else 59 #define DWC2_EVCNT_ADD(a,b) do { } while (/*CONSTCOND*/0) 60 #endif 61 #define DWC2_EVCNT_INCR(a) DWC2_EVCNT_ADD((a), 1) 62 63 #ifdef DWC2_DEBUG 64 #define DPRINTFN(n,fmt,...) do { \ 65 if (dwc2debug >= (n)) { \ 66 printf("%s: " fmt, \ 67 __FUNCTION__,## __VA_ARGS__); \ 68 } \ 69 } while (0) 70 #define DPRINTF(...) DPRINTFN(1, __VA_ARGS__) 71 int dwc2debug = 0; 72 #else 73 #define DPRINTF(...) do { } while (0) 74 #define DPRINTFN(...) do { } while (0) 75 #endif 76 77 STATIC usbd_status dwc2_open(struct usbd_pipe *); 78 STATIC int dwc2_setaddr(struct usbd_device *, int); 79 STATIC void dwc2_poll(struct usbd_bus *); 80 STATIC void dwc2_softintr(void *); 81 82 STATIC struct usbd_xfer *dwc2_allocx(struct usbd_bus *); 83 STATIC void dwc2_freex(struct usbd_bus *, struct usbd_xfer *); 84 85 STATIC usbd_status dwc2_root_ctrl_transfer(struct usbd_xfer *); 86 STATIC usbd_status dwc2_root_ctrl_start(struct usbd_xfer *); 87 STATIC void dwc2_root_ctrl_abort(struct usbd_xfer *); 88 STATIC void dwc2_root_ctrl_close(struct usbd_pipe *); 89 STATIC void dwc2_root_ctrl_done(struct usbd_xfer *); 90 91 STATIC usbd_status dwc2_root_intr_transfer(struct usbd_xfer *); 92 STATIC usbd_status dwc2_root_intr_start(struct usbd_xfer *); 93 STATIC void dwc2_root_intr_abort(struct usbd_xfer *); 94 STATIC void dwc2_root_intr_close(struct usbd_pipe *); 95 STATIC void dwc2_root_intr_done(struct usbd_xfer *); 96 97 STATIC usbd_status dwc2_device_ctrl_transfer(struct usbd_xfer *); 98 STATIC usbd_status dwc2_device_ctrl_start(struct usbd_xfer *); 99 STATIC void dwc2_device_ctrl_abort(struct usbd_xfer *); 100 STATIC void dwc2_device_ctrl_close(struct usbd_pipe *); 101 STATIC void dwc2_device_ctrl_done(struct usbd_xfer *); 102 103 STATIC usbd_status dwc2_device_bulk_transfer(struct usbd_xfer *); 104 STATIC usbd_status dwc2_device_bulk_start(struct usbd_xfer *); 105 STATIC void dwc2_device_bulk_abort(struct usbd_xfer *); 106 STATIC void dwc2_device_bulk_close(struct usbd_pipe *); 107 STATIC void dwc2_device_bulk_done(struct usbd_xfer *); 108 109 STATIC usbd_status dwc2_device_intr_transfer(struct usbd_xfer *); 110 STATIC usbd_status dwc2_device_intr_start(struct usbd_xfer *); 111 STATIC void dwc2_device_intr_abort(struct usbd_xfer *); 112 STATIC void dwc2_device_intr_close(struct usbd_pipe *); 113 STATIC void dwc2_device_intr_done(struct usbd_xfer *); 114 115 STATIC usbd_status dwc2_device_isoc_transfer(struct usbd_xfer *); 116 STATIC usbd_status dwc2_device_isoc_start(struct usbd_xfer *); 117 STATIC void dwc2_device_isoc_abort(struct usbd_xfer *); 118 STATIC void dwc2_device_isoc_close(struct usbd_pipe *); 119 STATIC void dwc2_device_isoc_done(struct usbd_xfer *); 120 121 STATIC usbd_status dwc2_device_start(struct usbd_xfer *); 122 123 STATIC void dwc2_close_pipe(struct usbd_pipe *); 124 STATIC void dwc2_abort_xfer(struct usbd_xfer *, usbd_status); 125 126 STATIC void dwc2_device_clear_toggle(struct usbd_pipe *); 127 STATIC void dwc2_noop(struct usbd_pipe *pipe); 128 129 STATIC int dwc2_interrupt(struct dwc2_softc *); 130 STATIC void dwc2_rhc(void *); 131 132 STATIC void dwc2_timeout(void *); 133 STATIC void dwc2_timeout_task(void *); 134 135 static inline void 136 dwc2_allocate_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw, 137 struct usbd_xfer *xfer) 138 { 139 } 140 141 static inline void 142 dwc2_free_bus_bandwidth(struct dwc2_hsotg *hsotg, u16 bw, 143 struct usbd_xfer *xfer) 144 { 145 } 146 147 #define DWC2_INTR_ENDPT 1 148 149 STATIC struct usbd_bus_methods dwc2_bus_methods = { 150 .open_pipe = dwc2_open, 151 .dev_setaddr = dwc2_setaddr, 152 .soft_intr = dwc2_softintr, 153 .do_poll = dwc2_poll, 154 .allocx = dwc2_allocx, 155 .freex = dwc2_freex, 156 }; 157 158 STATIC struct usbd_pipe_methods dwc2_root_ctrl_methods = { 159 .transfer = dwc2_root_ctrl_transfer, 160 .start = dwc2_root_ctrl_start, 161 .abort = dwc2_root_ctrl_abort, 162 .close = dwc2_root_ctrl_close, 163 .cleartoggle = dwc2_noop, 164 .done = dwc2_root_ctrl_done, 165 }; 166 167 STATIC struct usbd_pipe_methods dwc2_root_intr_methods = { 168 .transfer = dwc2_root_intr_transfer, 169 .start = dwc2_root_intr_start, 170 .abort = dwc2_root_intr_abort, 171 .close = dwc2_root_intr_close, 172 .cleartoggle = dwc2_noop, 173 .done = dwc2_root_intr_done, 174 }; 175 176 STATIC struct usbd_pipe_methods dwc2_device_ctrl_methods = { 177 .transfer = dwc2_device_ctrl_transfer, 178 .start = dwc2_device_ctrl_start, 179 .abort = dwc2_device_ctrl_abort, 180 .close = dwc2_device_ctrl_close, 181 .cleartoggle = dwc2_noop, 182 .done = dwc2_device_ctrl_done, 183 }; 184 185 STATIC struct usbd_pipe_methods dwc2_device_intr_methods = { 186 .transfer = dwc2_device_intr_transfer, 187 .start = dwc2_device_intr_start, 188 .abort = dwc2_device_intr_abort, 189 .close = dwc2_device_intr_close, 190 .cleartoggle = dwc2_device_clear_toggle, 191 .done = dwc2_device_intr_done, 192 }; 193 194 STATIC struct usbd_pipe_methods dwc2_device_bulk_methods = { 195 .transfer = dwc2_device_bulk_transfer, 196 .start = dwc2_device_bulk_start, 197 .abort = dwc2_device_bulk_abort, 198 .close = dwc2_device_bulk_close, 199 .cleartoggle = dwc2_device_clear_toggle, 200 .done = dwc2_device_bulk_done, 201 }; 202 203 STATIC struct usbd_pipe_methods dwc2_device_isoc_methods = { 204 .transfer = dwc2_device_isoc_transfer, 205 .start = dwc2_device_isoc_start, 206 .abort = dwc2_device_isoc_abort, 207 .close = dwc2_device_isoc_close, 208 .cleartoggle = dwc2_noop, 209 .done = dwc2_device_isoc_done, 210 }; 211 212 /* 213 * Work around the half configured control (default) pipe when setting 214 * the address of a device. 215 */ 216 STATIC int 217 dwc2_setaddr(struct usbd_device *dev, int addr) 218 { 219 if (usbd_set_address(dev, addr)) 220 return (1); 221 222 dev->address = addr; 223 224 /* 225 * Re-establish the default pipe with the new address and the 226 * new max packet size. 227 */ 228 dwc2_close_pipe(dev->default_pipe); 229 if (dwc2_open(dev->default_pipe)) 230 return (EINVAL); 231 232 return (0); 233 } 234 235 struct usbd_xfer * 236 dwc2_allocx(struct usbd_bus *bus) 237 { 238 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 239 struct dwc2_xfer *dxfer; 240 241 DPRINTFN(10, "\n"); 242 243 DWC2_EVCNT_INCR(sc->sc_ev_xferpoolget); 244 dxfer = pool_get(&sc->sc_xferpool, PR_WAITOK); 245 if (dxfer != NULL) { 246 memset(dxfer, 0, sizeof(*dxfer)); 247 dxfer->urb = dwc2_hcd_urb_alloc(sc->sc_hsotg, 248 DWC2_MAXISOCPACKETS, M_NOWAIT); 249 #ifdef DIAGNOSTIC 250 dxfer->xfer.busy_free = XFER_ONQU; 251 #endif 252 } 253 return (struct usbd_xfer *)dxfer; 254 } 255 256 void 257 dwc2_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 258 { 259 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 260 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 261 262 DPRINTFN(10, "\n"); 263 264 #ifdef DIAGNOSTIC 265 if (xfer->busy_free != XFER_ONQU && 266 xfer->status != USBD_NOT_STARTED) { 267 DPRINTF("xfer=%p not busy, 0x%08x\n", xfer, xfer->busy_free); 268 } 269 xfer->busy_free = XFER_FREE; 270 #endif 271 DWC2_EVCNT_INCR(sc->sc_ev_xferpoolput); 272 dwc2_hcd_urb_free(sc->sc_hsotg, dxfer->urb, DWC2_MAXISOCPACKETS); 273 pool_put(&sc->sc_xferpool, xfer); 274 } 275 276 STATIC void 277 dwc2_rhc(void *addr) 278 { 279 struct dwc2_softc *sc = addr; 280 struct usbd_xfer *xfer; 281 u_char *p; 282 283 DPRINTF("\n"); 284 mtx_enter(&sc->sc_lock); 285 xfer = sc->sc_intrxfer; 286 287 if (xfer == NULL) { 288 /* Just ignore the change. */ 289 mtx_leave(&sc->sc_lock); 290 return; 291 292 } 293 294 /* set port bit */ 295 p = KERNADDR(&xfer->dmabuf, 0); 296 297 p[0] = 0x02; /* we only have one port (1 << 1) */ 298 299 xfer->actlen = xfer->length; 300 xfer->status = USBD_NORMAL_COMPLETION; 301 302 usb_transfer_complete(xfer); 303 mtx_leave(&sc->sc_lock); 304 } 305 306 STATIC void 307 dwc2_softintr(void *v) 308 { 309 struct usbd_bus *bus = v; 310 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 311 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 312 struct dwc2_xfer *dxfer, *next; 313 TAILQ_HEAD(, dwc2_xfer) claimed = TAILQ_HEAD_INITIALIZER(claimed); 314 315 /* 316 * Grab all the xfers that have not been aborted or timed out. 317 * Do so under a single lock -- without dropping it to run 318 * usb_transfer_complete as we go -- so that dwc2_abortx won't 319 * remove next out from under us during iteration when we've 320 * dropped the lock. 321 */ 322 mtx_enter(&hsotg->lock); 323 TAILQ_FOREACH_SAFE(dxfer, &sc->sc_complete, xnext, next) { 324 KASSERT(dxfer->xfer.status == USBD_IN_PROGRESS); 325 KASSERT(dxfer->intr_status != USBD_CANCELLED); 326 KASSERT(dxfer->intr_status != USBD_TIMEOUT); 327 TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext); 328 TAILQ_INSERT_TAIL(&claimed, dxfer, xnext); 329 } 330 mtx_leave(&hsotg->lock); 331 332 /* Now complete them. */ 333 while (!TAILQ_EMPTY(&claimed)) { 334 dxfer = TAILQ_FIRST(&claimed); 335 KASSERT(dxfer->xfer.status == USBD_IN_PROGRESS); 336 KASSERT(dxfer->intr_status != USBD_CANCELLED); 337 KASSERT(dxfer->intr_status != USBD_TIMEOUT); 338 TAILQ_REMOVE(&claimed, dxfer, xnext); 339 340 dxfer->xfer.status = dxfer->intr_status; 341 usb_transfer_complete(&dxfer->xfer); 342 } 343 } 344 345 STATIC void 346 dwc2_timeout(void *addr) 347 { 348 struct usbd_xfer *xfer = addr; 349 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 350 351 DPRINTF("xfer=%p\n", xfer); 352 353 if (sc->sc_bus.dying) { 354 dwc2_timeout_task(addr); 355 return; 356 } 357 358 /* Execute the abort in a process context. */ 359 usb_init_task(&xfer->abort_task, dwc2_timeout_task, addr, 360 USB_TASK_TYPE_ABORT); 361 usb_add_task(xfer->device, &xfer->abort_task); 362 } 363 364 STATIC void 365 dwc2_timeout_task(void *addr) 366 { 367 struct usbd_xfer *xfer = addr; 368 int s; 369 370 DPRINTF("xfer=%p\n", xfer); 371 372 s = splusb(); 373 dwc2_abort_xfer(xfer, USBD_TIMEOUT); 374 splx(s); 375 } 376 377 usbd_status 378 dwc2_open(struct usbd_pipe *pipe) 379 { 380 struct usbd_device *dev = pipe->device; 381 struct dwc2_softc *sc = DWC2_PIPE2SC(pipe); 382 struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe); 383 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 384 uint8_t addr = dev->address; 385 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 386 usbd_status err; 387 388 DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype, 389 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? "in" : "out"); 390 391 if (sc->sc_bus.dying) { 392 return USBD_IOERROR; 393 } 394 395 if (addr == sc->sc_addr) { 396 switch (ed->bEndpointAddress) { 397 case USB_CONTROL_ENDPOINT: 398 pipe->methods = &dwc2_root_ctrl_methods; 399 break; 400 case UE_DIR_IN | DWC2_INTR_ENDPT: 401 pipe->methods = &dwc2_root_intr_methods; 402 break; 403 default: 404 DPRINTF("bad bEndpointAddress 0x%02x\n", 405 ed->bEndpointAddress); 406 return USBD_INVAL; 407 } 408 DPRINTF("root hub pipe open\n"); 409 return USBD_NORMAL_COMPLETION; 410 } 411 412 switch (xfertype) { 413 case UE_CONTROL: 414 pipe->methods = &dwc2_device_ctrl_methods; 415 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 416 0, USB_DMA_COHERENT, &dpipe->req_dma); 417 if (err) 418 return USBD_NOMEM; 419 break; 420 case UE_INTERRUPT: 421 pipe->methods = &dwc2_device_intr_methods; 422 break; 423 case UE_ISOCHRONOUS: 424 pipe->methods = &dwc2_device_isoc_methods; 425 break; 426 case UE_BULK: 427 pipe->methods = &dwc2_device_bulk_methods; 428 break; 429 default: 430 DPRINTF("bad xfer type %d\n", xfertype); 431 return USBD_INVAL; 432 } 433 434 /* QH */ 435 dpipe->priv = NULL; 436 437 return USBD_NORMAL_COMPLETION; 438 } 439 440 STATIC void 441 dwc2_poll(struct usbd_bus *bus) 442 { 443 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 444 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 445 446 mtx_enter(&hsotg->lock); 447 dwc2_interrupt(sc); 448 mtx_leave(&hsotg->lock); 449 } 450 451 /* 452 * Close a reqular pipe. 453 * Assumes that there are no pending transactions. 454 */ 455 STATIC void 456 dwc2_close_pipe(struct usbd_pipe *pipe) 457 { 458 /* nothing */ 459 } 460 461 /* 462 * Abort a device request. 463 */ 464 STATIC void 465 dwc2_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 466 { 467 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 468 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 469 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 470 struct dwc2_xfer *d, *tmp; 471 bool wake; 472 int err; 473 474 splsoftassert(IPL_SOFTUSB); 475 476 DPRINTF("xfer=%p\n", xfer); 477 478 if (sc->sc_bus.dying) { 479 xfer->status = status; 480 timeout_del(&xfer->timeout_handle); 481 usb_rem_task(xfer->device, &xfer->abort_task); 482 usb_transfer_complete(xfer); 483 return; 484 } 485 486 /* 487 * If an abort is already in progress then just wait for it to 488 * complete and return. 489 */ 490 if (dxfer->flags & DWC2_XFER_ABORTING) { 491 xfer->status = status; 492 dxfer->flags |= DWC2_XFER_ABORTWAIT; 493 while (dxfer->flags & DWC2_XFER_ABORTING) 494 tsleep_nsec(&dxfer->flags, PZERO, "dwc2xfer", INFSLP); 495 return; 496 } 497 498 mtx_enter(&hsotg->lock); 499 500 /* The transfer might have been completed already. */ 501 if (xfer->status != USBD_IN_PROGRESS) { 502 DPRINTF("xfer=%p already completed\n", xfer); 503 mtx_leave(&hsotg->lock); 504 return; 505 } 506 507 /* 508 * Step 1: Make the stack ignore it and stop the timeout. 509 */ 510 dxfer->flags |= DWC2_XFER_ABORTING; 511 512 xfer->status = status; /* make software ignore it */ 513 timeout_del(&xfer->timeout_handle); 514 usb_rem_task(xfer->device, &xfer->abort_task); 515 516 /* XXXNH suboptimal */ 517 TAILQ_FOREACH_SAFE(d, &sc->sc_complete, xnext, tmp) { 518 if (d == dxfer) { 519 TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext); 520 } 521 } 522 523 err = dwc2_hcd_urb_dequeue(hsotg, dxfer->urb); 524 if (err) { 525 DPRINTF("dwc2_hcd_urb_dequeue failed\n"); 526 } 527 528 mtx_leave(&hsotg->lock); 529 530 /* 531 * Step 2: Execute callback. 532 */ 533 wake = dxfer->flags & DWC2_XFER_ABORTWAIT; 534 dxfer->flags &= ~(DWC2_XFER_ABORTING | DWC2_XFER_ABORTWAIT); 535 536 usb_transfer_complete(xfer); 537 if (wake) { 538 wakeup(&dxfer->flags); 539 } 540 } 541 542 STATIC void 543 dwc2_noop(struct usbd_pipe *pipe) 544 { 545 546 } 547 548 STATIC void 549 dwc2_device_clear_toggle(struct usbd_pipe *pipe) 550 { 551 552 DPRINTF("toggle %d -> 0", pipe->endpoint->savedtoggle); 553 } 554 555 /***********************************************************************/ 556 557 /* 558 * Data structures and routines to emulate the root hub. 559 */ 560 561 STATIC const usb_device_descriptor_t dwc2_devd = { 562 .bLength = sizeof(usb_device_descriptor_t), 563 .bDescriptorType = UDESC_DEVICE, 564 .bcdUSB = {0x00, 0x02}, 565 .bDeviceClass = UDCLASS_HUB, 566 .bDeviceSubClass = UDSUBCLASS_HUB, 567 .bDeviceProtocol = UDPROTO_HSHUBSTT, 568 .bMaxPacketSize = 64, 569 .bcdDevice = {0x00, 0x01}, 570 .iManufacturer = 1, 571 .iProduct = 2, 572 .bNumConfigurations = 1, 573 }; 574 575 struct dwc2_config_desc { 576 usb_config_descriptor_t confd; 577 usb_interface_descriptor_t ifcd; 578 usb_endpoint_descriptor_t endpd; 579 } __packed; 580 581 STATIC const struct dwc2_config_desc dwc2_confd = { 582 .confd = { 583 .bLength = USB_CONFIG_DESCRIPTOR_SIZE, 584 .bDescriptorType = UDESC_CONFIG, 585 .wTotalLength[0] = sizeof(dwc2_confd), 586 .bNumInterfaces = 1, 587 .bConfigurationValue = 1, 588 .iConfiguration = 0, 589 .bmAttributes = UC_BUS_POWERED | UC_SELF_POWERED, 590 .bMaxPower = 0, 591 }, 592 .ifcd = { 593 .bLength = USB_INTERFACE_DESCRIPTOR_SIZE, 594 .bDescriptorType = UDESC_INTERFACE, 595 .bInterfaceNumber = 0, 596 .bAlternateSetting = 0, 597 .bNumEndpoints = 1, 598 .bInterfaceClass = UICLASS_HUB, 599 .bInterfaceSubClass = UISUBCLASS_HUB, 600 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 601 .iInterface = 0 602 }, 603 .endpd = { 604 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 605 .bDescriptorType = UDESC_ENDPOINT, 606 .bEndpointAddress = UE_DIR_IN | DWC2_INTR_ENDPT, 607 .bmAttributes = UE_INTERRUPT, 608 .wMaxPacketSize = {8, 0}, /* max packet */ 609 .bInterval = 255, 610 }, 611 }; 612 613 STATIC usbd_status 614 dwc2_root_ctrl_transfer(struct usbd_xfer *xfer) 615 { 616 usbd_status err; 617 618 err = usb_insert_transfer(xfer); 619 if (err) 620 return err; 621 622 return dwc2_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 623 } 624 625 STATIC usbd_status 626 dwc2_root_ctrl_start(struct usbd_xfer *xfer) 627 { 628 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 629 usb_device_request_t *req; 630 uint8_t *buf; 631 uint16_t len; 632 int value, index, l, s, totlen; 633 usbd_status err = USBD_IOERROR; 634 635 if (sc->sc_bus.dying) 636 return USBD_IOERROR; 637 638 req = &xfer->request; 639 640 DPRINTFN(4, "type=0x%02x request=%02x\n", 641 req->bmRequestType, req->bRequest); 642 643 len = UGETW(req->wLength); 644 value = UGETW(req->wValue); 645 index = UGETW(req->wIndex); 646 647 buf = len ? KERNADDR(&xfer->dmabuf, 0) : NULL; 648 649 totlen = 0; 650 651 #define C(x,y) ((x) | ((y) << 8)) 652 switch (C(req->bRequest, req->bmRequestType)) { 653 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 654 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 655 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 656 /* 657 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 658 * for the integrated root hub. 659 */ 660 break; 661 case C(UR_GET_CONFIG, UT_READ_DEVICE): 662 if (len > 0) { 663 *buf = sc->sc_conf; 664 totlen = 1; 665 } 666 break; 667 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 668 DPRINTFN(8, "wValue=0x%04x\n", value); 669 670 if (len == 0) 671 break; 672 switch (value) { 673 case C(0, UDESC_DEVICE): 674 l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 675 // USETW(dwc2_devd.idVendor, sc->sc_id_vendor); 676 memcpy(buf, &dwc2_devd, l); 677 buf += l; 678 len -= l; 679 totlen += l; 680 681 break; 682 case C(0, UDESC_CONFIG): 683 l = min(len, sizeof(dwc2_confd)); 684 memcpy(buf, &dwc2_confd, l); 685 buf += l; 686 len -= l; 687 totlen += l; 688 689 break; 690 #define sd ((usb_string_descriptor_t *)buf) 691 case C(0, UDESC_STRING): 692 totlen = usbd_str(sd, len, "\001"); 693 break; 694 case C(1, UDESC_STRING): 695 totlen = usbd_str(sd, len, sc->sc_vendor); 696 break; 697 case C(2, UDESC_STRING): 698 totlen = usbd_str(sd, len, "DWC2 root hub"); 699 break; 700 #undef sd 701 default: 702 goto fail; 703 } 704 break; 705 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 706 if (len > 0) { 707 *buf = 0; 708 totlen = 1; 709 } 710 break; 711 case C(UR_GET_STATUS, UT_READ_DEVICE): 712 if (len > 1) { 713 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 714 totlen = 2; 715 } 716 break; 717 case C(UR_GET_STATUS, UT_READ_INTERFACE): 718 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 719 if (len > 1) { 720 USETW(((usb_status_t *)buf)->wStatus, 0); 721 totlen = 2; 722 } 723 break; 724 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 725 DPRINTF("UR_SET_ADDRESS, UT_WRITE_DEVICE: addr %d\n", 726 value); 727 if (value >= USB_MAX_DEVICES) 728 goto fail; 729 730 sc->sc_addr = value; 731 break; 732 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 733 if (value != 0 && value != 1) 734 goto fail; 735 736 sc->sc_conf = value; 737 break; 738 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 739 break; 740 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 741 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 742 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 743 err = USBD_IOERROR; 744 goto fail; 745 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 746 break; 747 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 748 break; 749 default: 750 /* Hub requests - XXXNH len check? */ 751 err = dwc2_hcd_hub_control(sc->sc_hsotg, 752 C(req->bRequest, req->bmRequestType), value, index, 753 buf, len); 754 if (err) { 755 err = USBD_IOERROR; 756 goto fail; 757 } 758 totlen = len; 759 } 760 xfer->actlen = totlen; 761 err = USBD_NORMAL_COMPLETION; 762 763 fail: 764 s = splusb(); 765 xfer->status = err; 766 usb_transfer_complete(xfer); 767 splx(s); 768 769 return err; 770 } 771 772 STATIC void 773 dwc2_root_ctrl_abort(struct usbd_xfer *xfer) 774 { 775 DPRINTFN(10, "\n"); 776 777 /* Nothing to do, all transfers are synchronous. */ 778 } 779 780 STATIC void 781 dwc2_root_ctrl_close(struct usbd_pipe *pipe) 782 { 783 DPRINTFN(10, "\n"); 784 785 /* Nothing to do. */ 786 } 787 788 STATIC void 789 dwc2_root_ctrl_done(struct usbd_xfer *xfer) 790 { 791 DPRINTFN(10, "\n"); 792 793 /* Nothing to do. */ 794 } 795 796 STATIC usbd_status 797 dwc2_root_intr_transfer(struct usbd_xfer *xfer) 798 { 799 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 800 usbd_status err; 801 802 DPRINTF("\n"); 803 804 /* Insert last in queue. */ 805 mtx_enter(&sc->sc_lock); 806 err = usb_insert_transfer(xfer); 807 mtx_leave(&sc->sc_lock); 808 if (err) 809 return err; 810 811 /* Pipe isn't running, start first */ 812 return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 813 } 814 815 STATIC usbd_status 816 dwc2_root_intr_start(struct usbd_xfer *xfer) 817 { 818 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 819 const bool polling = sc->sc_bus.use_polling; 820 821 DPRINTF("\n"); 822 823 if (sc->sc_bus.dying) 824 return USBD_IOERROR; 825 826 if (!polling) 827 mtx_enter(&sc->sc_lock); 828 KASSERT(sc->sc_intrxfer == NULL); 829 sc->sc_intrxfer = xfer; 830 xfer->status = USBD_IN_PROGRESS; 831 if (!polling) 832 mtx_leave(&sc->sc_lock); 833 834 return USBD_IN_PROGRESS; 835 } 836 837 /* Abort a root interrupt request. */ 838 STATIC void 839 dwc2_root_intr_abort(struct usbd_xfer *xfer) 840 { 841 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 842 843 DPRINTF("xfer=%p\n", xfer); 844 845 /* If xfer has already completed, nothing to do here. */ 846 if (sc->sc_intrxfer == NULL) 847 return; 848 849 /* 850 * Otherwise, sc->sc_intrxfer had better be this transfer. 851 * Cancel it. 852 */ 853 KASSERT(sc->sc_intrxfer == xfer); 854 KASSERT(xfer->status == USBD_IN_PROGRESS); 855 xfer->status = USBD_CANCELLED; 856 usb_transfer_complete(xfer); 857 } 858 859 STATIC void 860 dwc2_root_intr_close(struct usbd_pipe *pipe) 861 { 862 struct dwc2_softc *sc = DWC2_PIPE2SC(pipe); 863 864 DPRINTF("\n"); 865 866 /* 867 * Caller must guarantee the xfer has completed first, by 868 * closing the pipe only after normal completion or an abort. 869 */ 870 if (sc->sc_intrxfer == NULL) 871 panic("%s: sc->sc_intrxfer == NULL", __func__); 872 } 873 874 STATIC void 875 dwc2_root_intr_done(struct usbd_xfer *xfer) 876 { 877 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 878 879 DPRINTF("\n"); 880 881 /* Claim the xfer so it doesn't get completed again. */ 882 KASSERT(sc->sc_intrxfer == xfer); 883 KASSERT(xfer->status != USBD_IN_PROGRESS); 884 sc->sc_intrxfer = NULL; 885 } 886 887 /***********************************************************************/ 888 889 STATIC usbd_status 890 dwc2_device_ctrl_transfer(struct usbd_xfer *xfer) 891 { 892 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 893 usbd_status err; 894 895 DPRINTF("\n"); 896 897 /* Insert last in queue. */ 898 mtx_enter(&sc->sc_lock); 899 err = usb_insert_transfer(xfer); 900 mtx_leave(&sc->sc_lock); 901 if (err) 902 return err; 903 904 /* Pipe isn't running, start first */ 905 return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 906 } 907 908 STATIC usbd_status 909 dwc2_device_ctrl_start(struct usbd_xfer *xfer) 910 { 911 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 912 usbd_status err; 913 const bool polling = sc->sc_bus.use_polling; 914 915 DPRINTF("\n"); 916 917 if (!polling) 918 mtx_enter(&sc->sc_lock); 919 xfer->status = USBD_IN_PROGRESS; 920 err = dwc2_device_start(xfer); 921 if (!polling) 922 mtx_leave(&sc->sc_lock); 923 924 if (err) 925 return err; 926 927 return USBD_IN_PROGRESS; 928 } 929 930 STATIC void 931 dwc2_device_ctrl_abort(struct usbd_xfer *xfer) 932 { 933 DPRINTF("xfer=%p\n", xfer); 934 dwc2_abort_xfer(xfer, USBD_CANCELLED); 935 } 936 937 STATIC void 938 dwc2_device_ctrl_close(struct usbd_pipe *pipe) 939 { 940 struct dwc2_softc * const sc = DWC2_PIPE2SC(pipe); 941 struct dwc2_pipe * const dpipe = DWC2_PIPE2DPIPE(pipe); 942 943 DPRINTF("pipe=%p\n", pipe); 944 dwc2_close_pipe(pipe); 945 946 usb_freemem(&sc->sc_bus, &dpipe->req_dma); 947 } 948 949 STATIC void 950 dwc2_device_ctrl_done(struct usbd_xfer *xfer) 951 { 952 953 DPRINTF("xfer=%p\n", xfer); 954 } 955 956 /***********************************************************************/ 957 958 STATIC usbd_status 959 dwc2_device_bulk_transfer(struct usbd_xfer *xfer) 960 { 961 usbd_status err; 962 963 DPRINTF("xfer=%p\n", xfer); 964 965 /* Insert last in queue. */ 966 err = usb_insert_transfer(xfer); 967 if (err) 968 return err; 969 970 /* Pipe isn't running, start first */ 971 return dwc2_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 972 } 973 974 STATIC usbd_status 975 dwc2_device_bulk_start(struct usbd_xfer *xfer) 976 { 977 usbd_status err; 978 979 DPRINTF("xfer=%p\n", xfer); 980 981 xfer->status = USBD_IN_PROGRESS; 982 err = dwc2_device_start(xfer); 983 984 return err; 985 } 986 987 STATIC void 988 dwc2_device_bulk_abort(struct usbd_xfer *xfer) 989 { 990 DPRINTF("xfer=%p\n", xfer); 991 992 dwc2_abort_xfer(xfer, USBD_CANCELLED); 993 } 994 995 STATIC void 996 dwc2_device_bulk_close(struct usbd_pipe *pipe) 997 { 998 999 DPRINTF("pipe=%p\n", pipe); 1000 1001 dwc2_close_pipe(pipe); 1002 } 1003 1004 STATIC void 1005 dwc2_device_bulk_done(struct usbd_xfer *xfer) 1006 { 1007 1008 DPRINTF("xfer=%p\n", xfer); 1009 } 1010 1011 /***********************************************************************/ 1012 1013 STATIC usbd_status 1014 dwc2_device_intr_transfer(struct usbd_xfer *xfer) 1015 { 1016 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1017 usbd_status err; 1018 1019 DPRINTF("xfer=%p\n", xfer); 1020 1021 /* Insert last in queue. */ 1022 mtx_enter(&sc->sc_lock); 1023 err = usb_insert_transfer(xfer); 1024 mtx_leave(&sc->sc_lock); 1025 if (err) 1026 return err; 1027 1028 /* Pipe isn't running, start first */ 1029 return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 1030 } 1031 1032 STATIC usbd_status 1033 dwc2_device_intr_start(struct usbd_xfer *xfer) 1034 { 1035 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1036 usbd_status err; 1037 const bool polling = sc->sc_bus.use_polling; 1038 1039 if (!polling) 1040 mtx_enter(&sc->sc_lock); 1041 xfer->status = USBD_IN_PROGRESS; 1042 err = dwc2_device_start(xfer); 1043 if (!polling) 1044 mtx_leave(&sc->sc_lock); 1045 1046 if (err) 1047 return err; 1048 1049 return USBD_IN_PROGRESS; 1050 } 1051 1052 /* Abort a device interrupt request. */ 1053 STATIC void 1054 dwc2_device_intr_abort(struct usbd_xfer *xfer) 1055 { 1056 KASSERT(xfer->pipe->intrxfer == xfer); 1057 1058 DPRINTF("xfer=%p\n", xfer); 1059 1060 dwc2_abort_xfer(xfer, USBD_CANCELLED); 1061 } 1062 1063 STATIC void 1064 dwc2_device_intr_close(struct usbd_pipe *pipe) 1065 { 1066 1067 DPRINTF("pipe=%p\n", pipe); 1068 1069 dwc2_close_pipe(pipe); 1070 } 1071 1072 STATIC void 1073 dwc2_device_intr_done(struct usbd_xfer *xfer) 1074 { 1075 1076 DPRINTF("\n"); 1077 1078 if (xfer->pipe->repeat) { 1079 xfer->status = USBD_IN_PROGRESS; 1080 dwc2_device_start(xfer); 1081 } 1082 } 1083 1084 /***********************************************************************/ 1085 1086 usbd_status 1087 dwc2_device_isoc_transfer(struct usbd_xfer *xfer) 1088 { 1089 usbd_status err; 1090 1091 DPRINTF("xfer=%p\n", xfer); 1092 1093 /* Insert last in queue. */ 1094 err = usb_insert_transfer(xfer); 1095 if (err) 1096 return err; 1097 1098 /* Pipe isn't running, start first */ 1099 return dwc2_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 1100 } 1101 1102 usbd_status 1103 dwc2_device_isoc_start(struct usbd_xfer *xfer) 1104 { 1105 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1106 struct dwc2_softc *sc = DWC2_DPIPE2SC(dpipe); 1107 usbd_status err; 1108 1109 /* Why would you do that anyway? */ 1110 if (sc->sc_bus.use_polling) 1111 return (USBD_INVAL); 1112 1113 xfer->status = USBD_IN_PROGRESS; 1114 err = dwc2_device_start(xfer); 1115 1116 return err; 1117 } 1118 1119 void 1120 dwc2_device_isoc_abort(struct usbd_xfer *xfer) 1121 { 1122 DPRINTF("xfer=%p\n", xfer); 1123 1124 dwc2_abort_xfer(xfer, USBD_CANCELLED); 1125 } 1126 1127 void 1128 dwc2_device_isoc_close(struct usbd_pipe *pipe) 1129 { 1130 DPRINTF("\n"); 1131 1132 dwc2_close_pipe(pipe); 1133 } 1134 1135 void 1136 dwc2_device_isoc_done(struct usbd_xfer *xfer) 1137 { 1138 1139 DPRINTF("\n"); 1140 } 1141 1142 1143 usbd_status 1144 dwc2_device_start(struct usbd_xfer *xfer) 1145 { 1146 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 1147 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1148 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1149 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 1150 struct dwc2_hcd_urb *dwc2_urb; 1151 1152 struct usbd_device *dev = xfer->pipe->device; 1153 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 1154 uint8_t addr = dev->address; 1155 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1156 uint8_t epnum = UE_GET_ADDR(ed->bEndpointAddress); 1157 uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 1158 uint16_t mps = UE_GET_SIZE(UGETW(ed->wMaxPacketSize)); 1159 uint32_t len; 1160 1161 uint32_t flags = 0; 1162 uint32_t off = 0; 1163 int retval, err; 1164 int alloc_bandwidth = 0; 1165 1166 DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->pipe); 1167 1168 if (xfertype == UE_ISOCHRONOUS || 1169 xfertype == UE_INTERRUPT) { 1170 mtx_enter(&hsotg->lock); 1171 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, xfer)) 1172 alloc_bandwidth = 1; 1173 mtx_leave(&hsotg->lock); 1174 } 1175 1176 /* 1177 * For Control pipe the direction is from the request, all other 1178 * transfers have been set correctly at pipe open time. 1179 */ 1180 if (xfertype == UE_CONTROL) { 1181 usb_device_request_t *req = &xfer->request; 1182 1183 DPRINTFN(3, "xfer=%p type=0x%02x request=0x%02x wValue=0x%04x " 1184 "wIndex=0x%04x len=%d addr=%d endpt=%d dir=%s speed=%d " 1185 "mps=%d\n", 1186 xfer, req->bmRequestType, req->bRequest, UGETW(req->wValue), 1187 UGETW(req->wIndex), UGETW(req->wLength), dev->address, 1188 epnum, dir == UT_READ ? "in" :"out", dev->speed, mps); 1189 1190 /* Copy request packet to our DMA buffer */ 1191 memcpy(KERNADDR(&dpipe->req_dma, 0), req, sizeof(*req)); 1192 usb_syncmem(&dpipe->req_dma, 0, sizeof(*req), 1193 BUS_DMASYNC_PREWRITE); 1194 len = UGETW(req->wLength); 1195 if ((req->bmRequestType & UT_READ) == UT_READ) { 1196 dir = UE_DIR_IN; 1197 } else { 1198 dir = UE_DIR_OUT; 1199 } 1200 1201 DPRINTFN(3, "req = %p dma = %llx len %d dir %s\n", 1202 KERNADDR(&dpipe->req_dma, 0), 1203 (long long)DMAADDR(&dpipe->req_dma, 0), 1204 len, dir == UE_DIR_IN ? "in" : "out"); 1205 } else if (xfertype == UE_ISOCHRONOUS) { 1206 DPRINTFN(3, "xfer=%p nframes=%d flags=%d addr=%d endpt=%d," 1207 " mps=%d dir %s\n", xfer, xfer->nframes, xfer->flags, addr, 1208 epnum, mps, dir == UT_READ ? "in" :"out"); 1209 1210 #ifdef DIAGNOSTIC 1211 len = 0; 1212 for (size_t i = 0; i < xfer->nframes; i++) 1213 len += xfer->frlengths[i]; 1214 if (len != xfer->length) 1215 panic("len (%d) != xfer->length (%d)", len, 1216 xfer->length); 1217 #endif 1218 len = xfer->length; 1219 } else { 1220 DPRINTFN(3, "xfer=%p len=%d flags=%d addr=%d endpt=%d," 1221 " mps=%d dir %s\n", xfer, xfer->length, xfer->flags, addr, 1222 epnum, mps, dir == UT_READ ? "in" :"out"); 1223 1224 len = xfer->length; 1225 } 1226 1227 dwc2_urb = dxfer->urb; 1228 if (!dwc2_urb) 1229 return USBD_NOMEM; 1230 1231 // KASSERT(dwc2_urb->packet_count == xfer->nframes); 1232 memset(dwc2_urb, 0, sizeof(*dwc2_urb) + 1233 sizeof(dwc2_urb->iso_descs[0]) * DWC2_MAXISOCPACKETS); 1234 1235 dwc2_urb->priv = xfer; 1236 dwc2_urb->packet_count = xfer->nframes; 1237 1238 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, addr, epnum, xfertype, dir, 1239 mps); 1240 1241 if (xfertype == UE_CONTROL) { 1242 dwc2_urb->setup_usbdma = &dpipe->req_dma; 1243 dwc2_urb->setup_packet = KERNADDR(&dpipe->req_dma, 0); 1244 dwc2_urb->setup_dma = DMAADDR(&dpipe->req_dma, 0); 1245 } else { 1246 /* XXXNH - % mps required? */ 1247 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && (len % mps) == 0) 1248 flags |= URB_SEND_ZERO_PACKET; 1249 } 1250 flags |= URB_GIVEBACK_ASAP; 1251 1252 /* 1253 * control transfers with no data phase don't touch usbdma, but 1254 * everything else does. 1255 */ 1256 if (!(xfertype == UE_CONTROL && len == 0)) { 1257 dwc2_urb->usbdma = &xfer->dmabuf; 1258 dwc2_urb->buf = KERNADDR(dwc2_urb->usbdma, 0); 1259 dwc2_urb->dma = DMAADDR(dwc2_urb->usbdma, 0); 1260 1261 usb_syncmem(&xfer->dmabuf, 0, len, 1262 dir == UE_DIR_IN ? 1263 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1264 } 1265 dwc2_urb->length = len; 1266 dwc2_urb->flags = flags; 1267 dwc2_urb->status = -EINPROGRESS; 1268 1269 if (xfertype == UE_INTERRUPT || 1270 xfertype == UE_ISOCHRONOUS) { 1271 uint16_t ival; 1272 1273 if (xfertype == UE_INTERRUPT && 1274 dpipe->pipe.interval != USBD_DEFAULT_INTERVAL) { 1275 ival = dpipe->pipe.interval; 1276 } else { 1277 ival = ed->bInterval; 1278 } 1279 1280 if (ival < 1) { 1281 retval = -ENODEV; 1282 goto fail; 1283 } 1284 if (dev->speed == USB_SPEED_HIGH || 1285 (dev->speed == USB_SPEED_FULL && xfertype == UE_ISOCHRONOUS)) { 1286 if (ival > 16) { 1287 /* 1288 * illegal with HS/FS, but there were 1289 * documentation bugs in the spec 1290 */ 1291 ival = 256; 1292 } else { 1293 ival = (1 << (ival - 1)); 1294 } 1295 } else { 1296 if (xfertype == UE_INTERRUPT && ival < 10) 1297 ival = 10; 1298 } 1299 dwc2_urb->interval = ival; 1300 } 1301 1302 /* XXXNH bring down from callers?? */ 1303 // mtx_enter(&sc->sc_lock); 1304 1305 xfer->actlen = 0; 1306 1307 KASSERT(xfertype != UE_ISOCHRONOUS || 1308 xfer->nframes <= DWC2_MAXISOCPACKETS); 1309 KASSERTMSG(xfer->nframes == 0 || xfertype == UE_ISOCHRONOUS, 1310 "nframes %d xfertype %d\n", xfer->nframes, xfertype); 1311 1312 off = 0; 1313 for (size_t i = 0; i < xfer->nframes; ++i) { 1314 DPRINTFN(3, "xfer=%p frame=%zu offset=%d length=%d\n", xfer, i, 1315 off, xfer->frlengths[i]); 1316 1317 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, off, 1318 xfer->frlengths[i]); 1319 off += xfer->frlengths[i]; 1320 } 1321 1322 struct dwc2_qh *qh = dpipe->priv; 1323 struct dwc2_qtd *qtd; 1324 bool qh_allocated = false; 1325 1326 /* Create QH for the endpoint if it doesn't exist */ 1327 if (!qh) { 1328 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, M_NOWAIT); 1329 if (!qh) { 1330 retval = -ENOMEM; 1331 goto fail; 1332 } 1333 dpipe->priv = qh; 1334 qh_allocated = true; 1335 } 1336 1337 qtd = pool_get(&sc->sc_qtdpool, PR_NOWAIT); 1338 if (!qtd) { 1339 retval = -ENOMEM; 1340 goto fail1; 1341 } 1342 memset(qtd, 0, sizeof(*qtd)); 1343 1344 /* might need to check cpu_intr_p */ 1345 mtx_enter(&hsotg->lock); 1346 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 1347 if (retval) 1348 goto fail2; 1349 if (xfer->timeout && !sc->sc_bus.use_polling) { 1350 timeout_set(&xfer->timeout_handle, dwc2_timeout, xfer); 1351 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 1352 } 1353 xfer->status = USBD_IN_PROGRESS; 1354 1355 if (alloc_bandwidth) { 1356 dwc2_allocate_bus_bandwidth(hsotg, 1357 dwc2_hcd_get_ep_bandwidth(hsotg, dpipe), 1358 xfer); 1359 } 1360 1361 mtx_leave(&hsotg->lock); 1362 // mtx_exit(&sc->sc_lock); 1363 1364 return USBD_IN_PROGRESS; 1365 1366 fail2: 1367 dwc2_urb->priv = NULL; 1368 mtx_leave(&hsotg->lock); 1369 pool_put(&sc->sc_qtdpool, qtd); 1370 1371 fail1: 1372 if (qh_allocated) { 1373 dpipe->priv = NULL; 1374 dwc2_hcd_qh_free(hsotg, qh); 1375 } 1376 fail: 1377 1378 switch (retval) { 1379 case -EINVAL: 1380 case -ENODEV: 1381 err = USBD_INVAL; 1382 break; 1383 case -ENOMEM: 1384 err = USBD_NOMEM; 1385 break; 1386 default: 1387 err = USBD_IOERROR; 1388 } 1389 1390 return err; 1391 1392 } 1393 1394 int dwc2_intr(void *p) 1395 { 1396 struct dwc2_softc *sc = p; 1397 struct dwc2_hsotg *hsotg; 1398 int ret = 0; 1399 1400 if (sc == NULL) 1401 return 0; 1402 1403 hsotg = sc->sc_hsotg; 1404 mtx_enter(&hsotg->lock); 1405 1406 if (sc->sc_bus.dying) 1407 goto done; 1408 1409 if (sc->sc_bus.use_polling) { 1410 uint32_t intrs; 1411 1412 intrs = dwc2_read_core_intr(hsotg); 1413 DWC2_WRITE_4(hsotg, GINTSTS, intrs); 1414 } else { 1415 ret = dwc2_interrupt(sc); 1416 } 1417 1418 done: 1419 mtx_leave(&hsotg->lock); 1420 1421 return ret; 1422 } 1423 1424 int 1425 dwc2_interrupt(struct dwc2_softc *sc) 1426 { 1427 int ret = 0; 1428 1429 if (sc->sc_hcdenabled) { 1430 ret |= dwc2_handle_hcd_intr(sc->sc_hsotg); 1431 } 1432 1433 ret |= dwc2_handle_common_intr(sc->sc_hsotg); 1434 1435 return ret; 1436 } 1437 1438 /***********************************************************************/ 1439 1440 int 1441 dwc2_detach(struct dwc2_softc *sc, int flags) 1442 { 1443 int rv = 0; 1444 1445 if (sc->sc_child != NULL) 1446 rv = config_detach(sc->sc_child, flags); 1447 1448 return rv; 1449 } 1450 1451 /***********************************************************************/ 1452 int 1453 dwc2_init(struct dwc2_softc *sc) 1454 { 1455 int err = 0; 1456 1457 sc->sc_bus.usbrev = USBREV_2_0; 1458 sc->sc_bus.methods = &dwc2_bus_methods; 1459 sc->sc_bus.pipe_size = sizeof(struct dwc2_pipe); 1460 sc->sc_hcdenabled = false; 1461 1462 mtx_init(&sc->sc_lock, IPL_SOFTUSB); 1463 1464 TAILQ_INIT(&sc->sc_complete); 1465 1466 sc->sc_rhc_si = softintr_establish(IPL_SOFTUSB, dwc2_rhc, sc); 1467 1468 pool_init(&sc->sc_xferpool, sizeof(struct dwc2_xfer), 0, IPL_USB, 0, 1469 "dwc2xfer", NULL); 1470 pool_init(&sc->sc_qhpool, sizeof(struct dwc2_qh), 0, IPL_USB, 0, 1471 "dwc2qh", NULL); 1472 pool_init(&sc->sc_qtdpool, sizeof(struct dwc2_qtd), 0, IPL_USB, 0, 1473 "dwc2qtd", NULL); 1474 1475 sc->sc_hsotg = malloc(sizeof(struct dwc2_hsotg), M_DEVBUF, 1476 M_ZERO | M_WAITOK); 1477 sc->sc_hsotg->hsotg_sc = sc; 1478 sc->sc_hsotg->dev = &sc->sc_bus.bdev; 1479 sc->sc_hcdenabled = true; 1480 1481 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 1482 struct dwc2_core_params defparams; 1483 int retval; 1484 1485 if (sc->sc_params == NULL) { 1486 /* Default all params to autodetect */ 1487 dwc2_set_all_params(&defparams, -1); 1488 sc->sc_params = &defparams; 1489 1490 /* 1491 * Disable descriptor dma mode by default as the HW can support 1492 * it, but does not support it for SPLIT transactions. 1493 */ 1494 defparams.dma_desc_enable = 0; 1495 } 1496 hsotg->dr_mode = USB_DR_MODE_HOST; 1497 1498 /* 1499 * Reset before dwc2_get_hwparams() then it could get power-on real 1500 * reset value form registers. 1501 */ 1502 dwc2_core_reset(hsotg); 1503 usb_delay_ms(&sc->sc_bus, 500); 1504 1505 /* Detect config values from hardware */ 1506 retval = dwc2_get_hwparams(hsotg); 1507 if (retval) { 1508 goto fail2; 1509 } 1510 1511 hsotg->core_params = malloc(sizeof(*hsotg->core_params), M_DEVBUF, 1512 M_ZERO | M_WAITOK); 1513 dwc2_set_all_params(hsotg->core_params, -1); 1514 1515 /* Validate parameter values */ 1516 dwc2_set_parameters(hsotg, sc->sc_params); 1517 1518 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1519 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1520 if (hsotg->dr_mode != USB_DR_MODE_HOST) { 1521 retval = dwc2_gadget_init(hsotg); 1522 if (retval) 1523 goto fail2; 1524 hsotg->gadget_enabled = 1; 1525 } 1526 #endif 1527 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \ 1528 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1529 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { 1530 retval = dwc2_hcd_init(hsotg); 1531 if (retval) { 1532 if (hsotg->gadget_enabled) 1533 dwc2_hsotg_remove(hsotg); 1534 goto fail2; 1535 } 1536 hsotg->hcd_enabled = 1; 1537 } 1538 #endif 1539 1540 #ifdef DWC2_DEBUG 1541 uint32_t snpsid = hsotg->hw_params.snpsid; 1542 dev_dbg(hsotg->dev, "Core Release: %x.%x%x%x (snpsid=%x)\n", 1543 snpsid >> 12 & 0xf, snpsid >> 8 & 0xf, 1544 snpsid >> 4 & 0xf, snpsid & 0xf, snpsid); 1545 #endif 1546 1547 return 0; 1548 1549 fail2: 1550 err = -retval; 1551 free(sc->sc_hsotg, M_DEVBUF, sizeof(struct dwc2_hsotg)); 1552 softintr_disestablish(sc->sc_rhc_si); 1553 1554 return err; 1555 } 1556 1557 #if 0 1558 /* 1559 * curmode is a mode indication bit 0 = device, 1 = host 1560 */ 1561 STATIC const char * const intnames[32] = { 1562 "curmode", "modemis", "otgint", "sof", 1563 "rxflvl", "nptxfemp", "ginnakeff", "goutnakeff", 1564 "ulpickint", "i2cint", "erlysusp", "usbsusp", 1565 "usbrst", "enumdone", "isooutdrop", "eopf", 1566 "restore_done", "epmis", "iepint", "oepint", 1567 "incompisoin", "incomplp", "fetsusp", "resetdet", 1568 "prtint", "hchint", "ptxfemp", "lpm", 1569 "conidstschng", "disconnint", "sessreqint", "wkupint" 1570 }; 1571 1572 1573 /***********************************************************************/ 1574 1575 #endif 1576 1577 1578 void 1579 dw_timeout(void *arg) 1580 { 1581 struct delayed_work *dw = arg; 1582 1583 task_set(&dw->work, dw->dw_fn, dw->dw_arg); 1584 task_add(dw->dw_wq, &dw->work); 1585 } 1586 1587 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 1588 int *hub_port) 1589 { 1590 struct usbd_xfer *xfer = context; 1591 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1592 struct usbd_device *dev = dpipe->pipe.device; 1593 1594 *hub_addr = dev->myhsport->parent->address; 1595 *hub_port = dev->myhsport->portno; 1596 } 1597 1598 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 1599 { 1600 struct usbd_xfer *xfer = context; 1601 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1602 struct usbd_device *dev = dpipe->pipe.device; 1603 1604 return dev->speed; 1605 } 1606 1607 /* 1608 * Sets the final status of an URB and returns it to the upper layer. Any 1609 * required cleanup of the URB is performed. 1610 * 1611 * Must be called with interrupt disabled and spinlock held 1612 */ 1613 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 1614 int status) 1615 { 1616 struct usbd_xfer *xfer; 1617 struct dwc2_xfer *dxfer; 1618 struct dwc2_softc *sc; 1619 usb_endpoint_descriptor_t *ed; 1620 uint8_t xfertype; 1621 1622 if (!qtd) { 1623 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 1624 return; 1625 } 1626 1627 if (!qtd->urb) { 1628 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 1629 return; 1630 } 1631 1632 xfer = qtd->urb->priv; 1633 if (!xfer) { 1634 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 1635 return; 1636 } 1637 1638 dxfer = DWC2_XFER2DXFER(xfer); 1639 sc = DWC2_XFER2SC(xfer); 1640 ed = xfer->pipe->endpoint->edesc; 1641 xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1642 1643 struct dwc2_hcd_urb *urb = qtd->urb; 1644 xfer->actlen = dwc2_hcd_urb_get_actual_length(urb); 1645 1646 DPRINTFN(3, "xfer=%p actlen=%d\n", xfer, xfer->actlen); 1647 1648 if (xfertype == UE_ISOCHRONOUS) { 1649 xfer->actlen = 0; 1650 for (size_t i = 0; i < xfer->nframes; ++i) { 1651 xfer->frlengths[i] = 1652 dwc2_hcd_urb_get_iso_desc_actual_length( 1653 urb, i); 1654 DPRINTFN(1, "xfer=%p frame=%zu length=%d\n", xfer, i, 1655 xfer->frlengths[i]); 1656 xfer->actlen += xfer->frlengths[i]; 1657 } 1658 DPRINTFN(1, "xfer=%p actlen=%d (isoc)\n", xfer, xfer->actlen); 1659 } 1660 1661 if (xfertype == UE_ISOCHRONOUS && dbg_perio()) { 1662 for (size_t i = 0; i < xfer->nframes; i++) 1663 dev_vdbg(hsotg->dev, " ISO Desc %zu status %d\n", 1664 i, urb->iso_descs[i].status); 1665 } 1666 1667 if (!status) { 1668 if (!(xfer->flags & USBD_SHORT_XFER_OK) && 1669 xfer->actlen < xfer->length) 1670 status = -EIO; 1671 } 1672 1673 switch (status) { 1674 case 0: 1675 dxfer->intr_status = USBD_NORMAL_COMPLETION; 1676 break; 1677 case -EPIPE: 1678 dxfer->intr_status = USBD_STALLED; 1679 break; 1680 case -EPROTO: 1681 dxfer->intr_status = USBD_INVAL; 1682 break; 1683 case -EIO: 1684 dxfer->intr_status = USBD_IOERROR; 1685 break; 1686 case -EOVERFLOW: 1687 dxfer->intr_status = USBD_IOERROR; 1688 break; 1689 default: 1690 dxfer->intr_status = USBD_IOERROR; 1691 printf("%s: unknown error status %d\n", __func__, status); 1692 } 1693 1694 if (dxfer->intr_status == USBD_NORMAL_COMPLETION) { 1695 /* 1696 * control transfers with no data phase don't touch dmabuf, but 1697 * everything else does. 1698 */ 1699 if (!(xfertype == UE_CONTROL && 1700 xfer->length == 0) && 1701 xfer->actlen > 0 /* XXX PR/53503 */ 1702 ) { 1703 int rd = usbd_xfer_isread(xfer); 1704 1705 usb_syncmem(&xfer->dmabuf, 0, xfer->actlen, 1706 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1707 } 1708 } 1709 1710 if (xfertype == UE_ISOCHRONOUS || 1711 xfertype == UE_INTERRUPT) { 1712 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1713 1714 dwc2_free_bus_bandwidth(hsotg, 1715 dwc2_hcd_get_ep_bandwidth(hsotg, dpipe), 1716 xfer); 1717 } 1718 1719 qtd->urb = NULL; 1720 timeout_del(&xfer->timeout_handle); 1721 usb_rem_task(xfer->device, &xfer->abort_task); 1722 MUTEX_ASSERT_LOCKED(&hsotg->lock); 1723 1724 TAILQ_INSERT_TAIL(&sc->sc_complete, dxfer, xnext); 1725 1726 mtx_leave(&hsotg->lock); 1727 usb_schedsoftintr(&sc->sc_bus); 1728 mtx_enter(&hsotg->lock); 1729 } 1730 1731 1732 int 1733 _dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1734 { 1735 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 1736 1737 mtx_enter(&hsotg->lock); 1738 1739 hsotg->lx_state = DWC2_L0; 1740 1741 if (dwc2_is_device_mode(hsotg)) { 1742 mtx_leave(&hsotg->lock); 1743 return 0; /* why 0 ?? */ 1744 } 1745 1746 dwc2_hcd_reinit(hsotg); 1747 1748 mtx_leave(&hsotg->lock); 1749 return 0; 1750 } 1751 1752 int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 1753 { 1754 1755 return false; 1756 } 1757