1 /* $OpenBSD: asc_tcds.c,v 1.6 2008/08/09 16:42:30 miod Exp $ */ 2 /* $NetBSD: asc_tcds.c,v 1.5 2001/11/15 09:48:19 lukem Exp $ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 */ 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/device.h> 61 #include <sys/buf.h> 62 63 #include <scsi/scsi_all.h> 64 #include <scsi/scsiconf.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 #include <dev/tc/ascvar.h> 69 70 #include <machine/bus.h> 71 72 #include <dev/tc/tcvar.h> 73 #include <dev/tc/tcdsreg.h> 74 #include <dev/tc/tcdsvar.h> 75 76 struct asc_tcds_softc { 77 struct asc_softc asc; 78 79 struct tcds_slotconfig *sc_tcds; 80 }; 81 82 int asc_tcds_match (struct device *, void *, void *); 83 void asc_tcds_attach(struct device *, struct device *, void *); 84 85 /* Linkup to the rest of the kernel */ 86 struct cfattach asc_tcds_ca = { 87 sizeof(struct asc_tcds_softc), asc_tcds_match, asc_tcds_attach 88 }; 89 90 /* 91 * Functions and the switch for the MI code. 92 */ 93 int tcds_dma_isintr(struct ncr53c9x_softc *); 94 void tcds_dma_reset(struct ncr53c9x_softc *); 95 int tcds_dma_intr(struct ncr53c9x_softc *); 96 int tcds_dma_setup(struct ncr53c9x_softc *, caddr_t *, 97 size_t *, int, size_t *); 98 void tcds_dma_go(struct ncr53c9x_softc *); 99 void tcds_dma_stop(struct ncr53c9x_softc *); 100 int tcds_dma_isactive(struct ncr53c9x_softc *); 101 void tcds_clear_latched_intr(struct ncr53c9x_softc *); 102 103 struct ncr53c9x_glue asc_tcds_glue = { 104 asc_read_reg, 105 asc_write_reg, 106 tcds_dma_isintr, 107 tcds_dma_reset, 108 tcds_dma_intr, 109 tcds_dma_setup, 110 tcds_dma_go, 111 tcds_dma_stop, 112 tcds_dma_isactive, 113 tcds_clear_latched_intr, 114 }; 115 116 extern struct scsi_adapter asc_switch; 117 extern struct scsi_device asc_dev; 118 119 int 120 asc_tcds_match(parent, cf, aux) 121 struct device *parent; 122 void *cf, *aux; 123 { 124 125 /* We always exist. */ 126 return 1; 127 } 128 129 #define DMAMAX(a) (NBPG - ((a) & (NBPG - 1))) 130 131 /* 132 * Attach this instance, and then all the sub-devices 133 */ 134 void 135 asc_tcds_attach(parent, self, aux) 136 struct device *parent, *self; 137 void *aux; 138 { 139 struct tcdsdev_attach_args *tcdsdev = aux; 140 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)self; 141 struct ncr53c9x_softc *sc = &asc->asc.sc_ncr53c9x; 142 int error; 143 144 /* 145 * Set up glue for MI code early; we use some of it here. 146 */ 147 sc->sc_glue = &asc_tcds_glue; 148 149 asc->asc.sc_bst = tcdsdev->tcdsda_bst; 150 asc->asc.sc_bsh = tcdsdev->tcdsda_bsh; 151 asc->sc_tcds = tcdsdev->tcdsda_sc; 152 153 /* 154 * The TCDS ASIC cannot DMA across 8k boundaries, and this 155 * driver is written such that each DMA segment gets a new 156 * call to tcds_dma_setup(). Thus, the DMA map only needs 157 * to support 8k transfers. 158 */ 159 asc->asc.sc_dmat = tcdsdev->tcdsda_dmat; 160 if ((error = bus_dmamap_create(asc->asc.sc_dmat, NBPG, 1, NBPG, 161 NBPG, BUS_DMA_NOWAIT, &asc->asc.sc_dmamap)) < 0) { 162 printf("failed to create dma map, error = %d\n", error); 163 } 164 165 sc->sc_id = tcdsdev->tcdsda_id; 166 sc->sc_freq = tcdsdev->tcdsda_freq; 167 168 /* gimme MHz */ 169 sc->sc_freq /= 1000000; 170 171 tcds_intr_establish(parent, tcdsdev->tcdsda_chip, ncr53c9x_intr, sc, 172 self->dv_xname); 173 174 /* 175 * XXX More of this should be in ncr53c9x_attach(), but 176 * XXX should we really poke around the chip that much in 177 * XXX the MI code? Think about this more... 178 */ 179 180 /* 181 * Set up static configuration info. 182 */ 183 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 184 sc->sc_cfg2 = NCRCFG2_SCSI2; 185 sc->sc_cfg3 = NCRCFG3_CDB; 186 if (sc->sc_freq > 25) 187 sc->sc_cfg3 |= NCRF9XCFG3_FCLK; 188 sc->sc_rev = tcdsdev->tcdsda_variant; 189 if (tcdsdev->tcdsda_fast) { 190 sc->sc_features |= NCR_F_FASTSCSI; 191 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 192 } 193 194 /* 195 * XXX minsync and maxxfer _should_ be set up in MI code, 196 * XXX but it appears to have some dependency on what sort 197 * XXX of DMA we're hooked up to, etc. 198 */ 199 200 /* 201 * This is the value used to start sync negotiations 202 * Note that the NCR register "SYNCTP" is programmed 203 * in "clocks per byte", and has a minimum value of 4. 204 * The SCSI period used in negotiation is one-fourth 205 * of the time (in nanoseconds) needed to transfer one byte. 206 * Since the chip's clock is given in MHz, we have the following 207 * formula: 4 * period = (1000 / freq) * 4 208 */ 209 sc->sc_minsync = (1000 / sc->sc_freq) * tcdsdev->tcdsda_period / 4; 210 211 sc->sc_maxxfer = 64 * 1024; 212 213 /* Do the common parts of attachment. */ 214 ncr53c9x_attach(sc, &asc_switch, &asc_dev); 215 } 216 217 void 218 tcds_dma_reset(sc) 219 struct ncr53c9x_softc *sc; 220 { 221 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 222 223 /* TCDS SCSI disable/reset/enable. */ 224 tcds_scsi_reset(asc->sc_tcds); /* XXX */ 225 226 if (asc->asc.sc_flags & ASC_MAPLOADED) 227 bus_dmamap_unload(asc->asc.sc_dmat, asc->asc.sc_dmamap); 228 asc->asc.sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 229 } 230 231 /* 232 * start a dma transfer or keep it going 233 */ 234 int 235 tcds_dma_setup(sc, addr, len, ispullup, dmasize) 236 struct ncr53c9x_softc *sc; 237 caddr_t *addr; 238 size_t *len, *dmasize; 239 int ispullup; /* DMA into main memory */ 240 { 241 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 242 struct tcds_slotconfig *tcds = asc->sc_tcds; 243 size_t size; 244 u_int32_t dic; 245 246 NCR_DMA(("tcds_dma %d: start %d@%p,%s\n", tcds->sc_slot, 247 (int)*asc->asc.sc_dmalen, *asc->asc.sc_dmaaddr, 248 (ispullup) ? "IN" : "OUT")); 249 250 /* 251 * the rules say we cannot transfer more than the limit 252 * of this DMA chip (64k) and we cannot cross a 8k boundary. 253 */ 254 size = min(*dmasize, DMAMAX((size_t)*addr)); 255 asc->asc.sc_dmaaddr = addr; 256 asc->asc.sc_dmalen = len; 257 asc->asc.sc_flags = (ispullup) ? ASC_ISPULLUP : 0; 258 *dmasize = asc->asc.sc_dmasize = size; 259 260 NCR_DMA(("dma_start: dmasize = %d\n", (int)size)); 261 262 if (size == 0) 263 return 0; 264 265 if (bus_dmamap_load(asc->asc.sc_dmat, asc->asc.sc_dmamap, *addr, size, 266 NULL, BUS_DMA_NOWAIT | (ispullup ? BUS_DMA_READ : BUS_DMA_WRITE))) { 267 /* 268 * XXX Should return an error, here, but the upper-layer 269 * XXX doesn't check the return value! 270 */ 271 panic("tcds_dma_setup: dmamap load failed"); 272 } 273 274 /* synchronize dmamap contents with memory image */ 275 bus_dmamap_sync(asc->asc.sc_dmat, asc->asc.sc_dmamap, 0, size, 276 (ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 277 278 /* load address, set/clear unaligned transfer and read/write bits. */ 279 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_sda, 280 asc->asc.sc_dmamap->dm_segs[0].ds_addr >> 2); 281 dic = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic); 282 dic &= ~TCDS_DIC_ADDRMASK; 283 dic |= asc->asc.sc_dmamap->dm_segs[0].ds_addr & TCDS_DIC_ADDRMASK; 284 if (ispullup) 285 dic |= TCDS_DIC_WRITE; 286 else 287 dic &= ~TCDS_DIC_WRITE; 288 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic, dic); 289 290 asc->asc.sc_flags |= ASC_MAPLOADED; 291 return 0; 292 } 293 294 void 295 tcds_dma_go(sc) 296 struct ncr53c9x_softc *sc; 297 { 298 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 299 300 /* mark unit as DMA-active */ 301 asc->asc.sc_flags |= ASC_DMAACTIVE; 302 303 /* start DMA */ 304 tcds_dma_enable(asc->sc_tcds, 1); 305 } 306 307 void 308 tcds_dma_stop(sc) 309 struct ncr53c9x_softc *sc; 310 { 311 #if 0 312 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 313 #endif 314 315 /* 316 * XXX STOP DMA HERE! 317 */ 318 } 319 320 /* 321 * Pseudo (chained) interrupt from the asc driver to kick the 322 * current running DMA transfer. Called from ncr53c9x_intr() 323 * for now. 324 * 325 * return 1 if it was a DMA continue. 326 */ 327 int 328 tcds_dma_intr(sc) 329 struct ncr53c9x_softc *sc; 330 { 331 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 332 struct tcds_slotconfig *tcds = asc->sc_tcds; 333 int trans, resid; 334 u_int32_t tcl, tcm; 335 u_int32_t dud, dudmask, *addr; 336 bus_addr_t pa; 337 338 NCR_DMA(("tcds_dma %d: intr", tcds->sc_slot)); 339 340 if (tcds_scsi_iserr(tcds)) 341 return 0; 342 343 /* This is an "assertion" :) */ 344 if ((asc->asc.sc_flags & ASC_DMAACTIVE) == 0) 345 panic("tcds_dma_intr: DMA wasn't active"); 346 347 /* DMA has stopped */ 348 tcds_dma_enable(tcds, 0); 349 asc->asc.sc_flags &= ~ASC_DMAACTIVE; 350 351 if (asc->asc.sc_dmasize == 0) { 352 /* A "Transfer Pad" operation completed */ 353 tcl = NCR_READ_REG(sc, NCR_TCL); 354 tcm = NCR_READ_REG(sc, NCR_TCM); 355 NCR_DMA(("dma_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 356 tcl | (tcm << 8), tcl, tcm)); 357 return 0; 358 } 359 360 resid = 0; 361 if ((asc->asc.sc_flags & ASC_ISPULLUP) == 0 && 362 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 363 NCR_DMA(("dma_intr: empty esp FIFO of %d ", resid)); 364 DELAY(1); 365 } 366 367 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 368 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 369 370 trans = asc->asc.sc_dmasize - resid; 371 if (trans < 0) { /* transferred < 0 ? */ 372 printf("tcds_dma %d: xfer (%d) > req (%d)\n", 373 tcds->sc_slot, trans, (int)asc->asc.sc_dmasize); 374 trans = asc->asc.sc_dmasize; 375 } 376 377 NCR_DMA(("dma_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 378 tcl, tcm, trans, resid)); 379 380 *asc->asc.sc_dmalen -= trans; 381 *asc->asc.sc_dmaaddr += trans; 382 383 bus_dmamap_sync(asc->asc.sc_dmat, asc->asc.sc_dmamap, 384 0, asc->asc.sc_dmamap->dm_mapsize, 385 (asc->asc.sc_flags & ASC_ISPULLUP) 386 ? BUS_DMASYNC_POSTREAD 387 : BUS_DMASYNC_POSTWRITE); 388 389 /* 390 * Clean up unaligned DMAs into main memory. 391 */ 392 if (asc->asc.sc_flags & ASC_ISPULLUP) { 393 /* Handle unaligned starting address, length. */ 394 dud = bus_space_read_4(tcds->sc_bst, 395 tcds->sc_bsh, tcds->sc_dud0); 396 if ((dud & TCDS_DUD0_VALIDBITS) != 0) { 397 addr = (u_int32_t *) 398 ((paddr_t)*asc->asc.sc_dmaaddr & ~0x3); 399 dudmask = 0; 400 if (dud & TCDS_DUD0_VALID00) 401 panic("tcds_dma: dud0 byte 0 valid"); 402 if (dud & TCDS_DUD0_VALID01) 403 dudmask |= TCDS_DUD_BYTE01; 404 if (dud & TCDS_DUD0_VALID10) 405 dudmask |= TCDS_DUD_BYTE10; 406 #ifdef DIAGNOSTIC 407 if (dud & TCDS_DUD0_VALID11) 408 dudmask |= TCDS_DUD_BYTE11; 409 #endif 410 NCR_DMA(("dud0 at %p dudmask 0x%x\n", 411 addr, dudmask)); 412 *addr = (*addr & ~dudmask) | (dud & dudmask); 413 } 414 dud = bus_space_read_4(tcds->sc_bst, 415 tcds->sc_bsh, tcds->sc_dud1); 416 if ((dud & TCDS_DUD1_VALIDBITS) != 0) { 417 pa = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, 418 tcds->sc_sda) << 2; 419 dudmask = 0; 420 if (dud & TCDS_DUD1_VALID00) 421 dudmask |= TCDS_DUD_BYTE00; 422 if (dud & TCDS_DUD1_VALID01) 423 dudmask |= TCDS_DUD_BYTE01; 424 if (dud & TCDS_DUD1_VALID10) 425 dudmask |= TCDS_DUD_BYTE10; 426 #ifdef DIAGNOSTIC 427 if (dud & TCDS_DUD1_VALID11) 428 panic("tcds_dma: dud1 byte 3 valid"); 429 #endif 430 NCR_DMA(("dud1 at 0x%lx dudmask 0x%x\n", 431 pa, dudmask)); 432 /* XXX Fix TC_PHYS_TO_UNCACHED() */ 433 #if defined(__alpha__) 434 addr = (u_int32_t *)ALPHA_PHYS_TO_K0SEG(pa); 435 #elif defined(__mips__) 436 addr = (u_int32_t *)MIPS_PHYS_TO_KSEG1(pa); 437 #else 438 #error TURBOchannel only exists on DECs, folks... 439 #endif 440 *addr = (*addr & ~dudmask) | (dud & dudmask); 441 } 442 /* XXX deal with saved residual byte? */ 443 } 444 445 bus_dmamap_unload(asc->asc.sc_dmat, asc->asc.sc_dmamap); 446 asc->asc.sc_flags &= ~ASC_MAPLOADED; 447 448 return 0; 449 } 450 451 /* 452 * Glue functions. 453 */ 454 int 455 tcds_dma_isintr(sc) 456 struct ncr53c9x_softc *sc; 457 { 458 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 459 int x; 460 461 x = tcds_scsi_isintr(asc->sc_tcds, 1); 462 463 /* XXX */ 464 return x; 465 } 466 467 int 468 tcds_dma_isactive(sc) 469 struct ncr53c9x_softc *sc; 470 { 471 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 472 473 return !!(asc->asc.sc_flags & ASC_DMAACTIVE); 474 } 475 476 void 477 tcds_clear_latched_intr(sc) 478 struct ncr53c9x_softc *sc; 479 { 480 struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; 481 482 /* Clear the TCDS interrupt bit. */ 483 (void)tcds_scsi_isintr(asc->sc_tcds, 1); 484 } 485