1 /* $OpenBSD: asc_tc.c,v 1.11 2010/11/11 17:54:54 miod Exp $ */ 2 /* $NetBSD: asc_tc.c,v 1.19 2001/11/15 09:48:19 lukem Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Tohru Nishimura. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/buf.h> 37 38 #include <scsi/scsi_all.h> 39 #include <scsi/scsiconf.h> 40 #include <scsi/scsi_message.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/ic/ncr53c9xreg.h> 45 #include <dev/ic/ncr53c9xvar.h> 46 #include <dev/tc/ascvar.h> 47 48 #include <dev/tc/tcvar.h> 49 50 struct asc_tc_softc { 51 struct asc_softc asc; 52 53 /* XXX XXX XXX */ 54 caddr_t sc_base, sc_bounce, sc_target; 55 }; 56 57 int asc_tc_match(struct device *, void *, void *); 58 void asc_tc_attach(struct device *, struct device *, void *); 59 60 struct cfattach asc_tc_ca = { 61 sizeof(struct asc_tc_softc), asc_tc_match, asc_tc_attach 62 }; 63 64 extern struct scsi_adapter asc_switch; 65 66 int asc_dma_isintr(struct ncr53c9x_softc *); 67 void asc_tc_reset(struct ncr53c9x_softc *); 68 int asc_tc_intr(struct ncr53c9x_softc *); 69 int asc_tc_setup(struct ncr53c9x_softc *, caddr_t *, 70 size_t *, int, size_t *); 71 void asc_tc_go(struct ncr53c9x_softc *); 72 void asc_tc_stop(struct ncr53c9x_softc *); 73 int asc_dma_isactive(struct ncr53c9x_softc *); 74 void asc_clear_latched_intr(struct ncr53c9x_softc *); 75 76 struct ncr53c9x_glue asc_tc_glue = { 77 asc_read_reg, 78 asc_write_reg, 79 asc_dma_isintr, 80 asc_tc_reset, 81 asc_tc_intr, 82 asc_tc_setup, 83 asc_tc_go, 84 asc_tc_stop, 85 asc_dma_isactive, 86 asc_clear_latched_intr, 87 }; 88 89 /* 90 * Parameters specific to PMAZ-A TC option card. 91 */ 92 #define PMAZ_OFFSET_53C94 0x0 /* from module base */ 93 #define PMAZ_OFFSET_DMAR 0x40000 /* DMA Address Register */ 94 #define PMAZ_OFFSET_RAM 0x80000 /* 128KB SRAM buffer */ 95 #define PMAZ_OFFSET_ROM 0xc0000 /* diagnostic ROM */ 96 97 #define PMAZ_RAM_SIZE 0x20000 /* 128k (32k*32) */ 98 #define PER_TGT_DMA_SIZE ((PMAZ_RAM_SIZE/7) & ~(sizeof(int)-1)) 99 100 #define PMAZ_DMAR_WRITE 0x80000000 /* DMA direction bit */ 101 #define PMAZ_DMAR_MASK 0x1ffff /* 17 bits, 128k */ 102 #define PMAZ_DMA_ADDR(x) ((unsigned long)(x) & PMAZ_DMAR_MASK) 103 104 int 105 asc_tc_match(parent, cfdata, aux) 106 struct device *parent; 107 void *cfdata, *aux; 108 { 109 struct tc_attach_args *d = aux; 110 111 if (strncmp("PMAZ-AA ", d->ta_modname, TC_ROM_LLEN)) 112 return (0); 113 114 return (1); 115 } 116 117 void 118 asc_tc_attach(parent, self, aux) 119 struct device *parent, *self; 120 void *aux; 121 { 122 struct tc_attach_args *ta = aux; 123 struct asc_tc_softc *asc = (struct asc_tc_softc *)self; 124 struct ncr53c9x_softc *sc = &asc->asc.sc_ncr53c9x; 125 126 /* 127 * Set up glue for MI code early; we use some of it here. 128 */ 129 sc->sc_glue = &asc_tc_glue; 130 asc->asc.sc_bst = ta->ta_memt; 131 asc->asc.sc_dmat = ta->ta_dmat; 132 if (bus_space_map(asc->asc.sc_bst, ta->ta_addr, 133 PMAZ_OFFSET_RAM + PMAZ_RAM_SIZE, 0, &asc->asc.sc_bsh)) { 134 printf("%s: unable to map device\n", sc->sc_dev.dv_xname); 135 return; 136 } 137 asc->sc_base = (caddr_t)ta->ta_addr; /* XXX XXX XXX */ 138 139 tc_intr_establish(parent, ta->ta_cookie, IPL_BIO, ncr53c9x_intr, sc, 140 self->dv_xname); 141 142 sc->sc_id = 7; 143 sc->sc_freq = TC_SPEED_TO_KHZ(ta->ta_busspeed); /* in kHz so far */ 144 145 /* 146 * XXX More of this should be in ncr53c9x_attach(), but 147 * XXX should we really poke around the chip that much in 148 * XXX the MI code? Think about this more... 149 */ 150 151 /* 152 * Set up static configuration info. 153 */ 154 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 155 sc->sc_cfg2 = NCRCFG2_SCSI2; 156 sc->sc_cfg3 = 0; 157 sc->sc_rev = NCR_VARIANT_NCR53C94; 158 159 /* 160 * XXX minsync and maxxfer _should_ be set up in MI code, 161 * XXX but it appears to have some dependency on what sort 162 * XXX of DMA we're hooked up to, etc. 163 */ 164 165 /* 166 * This is the value used to start sync negotiations 167 * Note that the NCR register "SYNCTP" is programmed 168 * in "clocks per byte", and has a minimum value of 4. 169 * The SCSI period used in negotiation is one-fourth 170 * of the time (in nanoseconds) needed to transfer one byte. 171 * Since the chip's clock is given in kHz, we have the following 172 * formula: 4 * period = (1000000 / freq) * 4 173 */ 174 sc->sc_minsync = (1000000 / sc->sc_freq) * 5 / 4; 175 176 sc->sc_maxxfer = 64 * 1024; 177 178 /* convert sc_freq to MHz */ 179 sc->sc_freq /= 1000; 180 181 /* Do the common parts of attachment. */ 182 ncr53c9x_attach(sc, &asc_switch); 183 } 184 185 void 186 asc_tc_reset(sc) 187 struct ncr53c9x_softc *sc; 188 { 189 struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; 190 191 asc->asc.sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 192 } 193 194 int 195 asc_tc_intr(sc) 196 struct ncr53c9x_softc *sc; 197 { 198 struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; 199 int trans, resid; 200 201 resid = 0; 202 if ((asc->asc.sc_flags & ASC_ISPULLUP) == 0 && 203 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 204 NCR_DMA(("asc_tc_intr: empty FIFO of %d ", resid)); 205 DELAY(1); 206 } 207 208 resid += NCR_READ_REG(sc, NCR_TCL); 209 resid += NCR_READ_REG(sc, NCR_TCM) << 8; 210 211 trans = asc->asc.sc_dmasize - resid; 212 213 if (asc->asc.sc_flags & ASC_ISPULLUP) 214 memcpy(asc->sc_target, asc->sc_bounce, trans); 215 *asc->asc.sc_dmalen -= trans; 216 *asc->asc.sc_dmaaddr += trans; 217 asc->asc.sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 218 219 return (0); 220 } 221 222 int 223 asc_tc_setup(sc, addr, len, datain, dmasize) 224 struct ncr53c9x_softc *sc; 225 caddr_t *addr; 226 size_t *len; 227 int datain; 228 size_t *dmasize; 229 { 230 struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; 231 u_int32_t tc_dmar; 232 size_t size; 233 234 asc->asc.sc_dmaaddr = addr; 235 asc->asc.sc_dmalen = len; 236 asc->asc.sc_flags = (datain) ? ASC_ISPULLUP : 0; 237 238 NCR_DMA(("asc_tc_setup: start %ld@%p, %s\n", (long)*asc->asc.sc_dmalen, 239 *asc->asc.sc_dmaaddr, datain ? "IN" : "OUT")); 240 241 size = *dmasize; 242 if (size > PER_TGT_DMA_SIZE) 243 size = PER_TGT_DMA_SIZE; 244 *dmasize = asc->asc.sc_dmasize = size; 245 246 NCR_DMA(("asc_tc_setup: dmasize = %ld\n", (long)asc->asc.sc_dmasize)); 247 248 asc->sc_bounce = asc->sc_base + PMAZ_OFFSET_RAM; 249 asc->sc_bounce += PER_TGT_DMA_SIZE * 250 sc->sc_nexus->xs->sc_link->target; 251 asc->sc_target = *addr; 252 253 if ((asc->asc.sc_flags & ASC_ISPULLUP) == 0) 254 memcpy(asc->sc_bounce, asc->sc_target, size); 255 256 #if 1 257 if (asc->asc.sc_flags & ASC_ISPULLUP) 258 tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce); 259 else 260 tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce); 261 bus_space_write_4(asc->asc.sc_bst, asc->asc.sc_bsh, PMAZ_OFFSET_DMAR, 262 tc_dmar); 263 asc->asc.sc_flags |= ASC_MAPLOADED|ASC_DMAACTIVE; 264 #endif 265 return (0); 266 } 267 268 void 269 asc_tc_go(sc) 270 struct ncr53c9x_softc *sc; 271 { 272 #if 0 273 struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; 274 u_int32_t tc_dmar; 275 276 if (asc->asc.sc_flags & ASC_ISPULLUP) 277 tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce); 278 else 279 tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce); 280 bus_space_write_4(asc->asc.sc_bst, asc->asc.sc_bsh, PMAZ_OFFSET_DMAR, 281 tc_dmar); 282 asc->asc.sc_flags |= ASC_DMAACTIVE; 283 #endif 284 } 285 286 /* NEVER CALLED BY MI 53C9x ENGINE INDEED */ 287 void 288 asc_tc_stop(sc) 289 struct ncr53c9x_softc *sc; 290 { 291 #if 0 292 struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; 293 294 if (asc->asc.sc_flags & ASC_ISPULLUP) 295 memcpy(asc->sc_target, asc->sc_bounce, asc->sc_dmasize); 296 asc->asc.sc_flags &= ~ASC_DMAACTIVE; 297 #endif 298 } 299 300 /* 301 * Glue functions. 302 */ 303 int 304 asc_dma_isintr(sc) 305 struct ncr53c9x_softc *sc; 306 { 307 return !!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT); 308 } 309 310 int 311 asc_dma_isactive(sc) 312 struct ncr53c9x_softc *sc; 313 { 314 struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; 315 316 return !!(asc->asc.sc_flags & ASC_DMAACTIVE); 317 } 318 319 void 320 asc_clear_latched_intr(sc) 321 struct ncr53c9x_softc *sc; 322 { 323 } 324