1 /* $OpenBSD: asc_tc.c,v 1.9 2008/08/09 16:42:30 miod Exp $ */ 2 /* $NetBSD: asc_tc.c,v 1.19 2001/11/15 09:48:19 lukem Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Tohru Nishimura. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/buf.h> 37 38 #include <scsi/scsi_all.h> 39 #include <scsi/scsiconf.h> 40 #include <scsi/scsi_message.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/ic/ncr53c9xreg.h> 45 #include <dev/ic/ncr53c9xvar.h> 46 #include <dev/tc/ascvar.h> 47 48 #include <dev/tc/tcvar.h> 49 50 struct asc_tc_softc { 51 struct asc_softc asc; 52 53 /* XXX XXX XXX */ 54 caddr_t sc_base, sc_bounce, sc_target; 55 }; 56 57 int asc_tc_match(struct device *, void *, void *); 58 void asc_tc_attach(struct device *, struct device *, void *); 59 60 struct cfattach asc_tc_ca = { 61 sizeof(struct asc_tc_softc), asc_tc_match, asc_tc_attach 62 }; 63 64 extern struct scsi_adapter asc_switch; 65 extern struct scsi_device asc_dev; 66 67 int asc_dma_isintr(struct ncr53c9x_softc *); 68 void asc_tc_reset(struct ncr53c9x_softc *); 69 int asc_tc_intr(struct ncr53c9x_softc *); 70 int asc_tc_setup(struct ncr53c9x_softc *, caddr_t *, 71 size_t *, int, size_t *); 72 void asc_tc_go(struct ncr53c9x_softc *); 73 void asc_tc_stop(struct ncr53c9x_softc *); 74 int asc_dma_isactive(struct ncr53c9x_softc *); 75 void asc_clear_latched_intr(struct ncr53c9x_softc *); 76 77 struct ncr53c9x_glue asc_tc_glue = { 78 asc_read_reg, 79 asc_write_reg, 80 asc_dma_isintr, 81 asc_tc_reset, 82 asc_tc_intr, 83 asc_tc_setup, 84 asc_tc_go, 85 asc_tc_stop, 86 asc_dma_isactive, 87 asc_clear_latched_intr, 88 }; 89 90 /* 91 * Parameters specific to PMAZ-A TC option card. 92 */ 93 #define PMAZ_OFFSET_53C94 0x0 /* from module base */ 94 #define PMAZ_OFFSET_DMAR 0x40000 /* DMA Address Register */ 95 #define PMAZ_OFFSET_RAM 0x80000 /* 128KB SRAM buffer */ 96 #define PMAZ_OFFSET_ROM 0xc0000 /* diagnostic ROM */ 97 98 #define PMAZ_RAM_SIZE 0x20000 /* 128k (32k*32) */ 99 #define PER_TGT_DMA_SIZE ((PMAZ_RAM_SIZE/7) & ~(sizeof(int)-1)) 100 101 #define PMAZ_DMAR_WRITE 0x80000000 /* DMA direction bit */ 102 #define PMAZ_DMAR_MASK 0x1ffff /* 17 bits, 128k */ 103 #define PMAZ_DMA_ADDR(x) ((unsigned long)(x) & PMAZ_DMAR_MASK) 104 105 int 106 asc_tc_match(parent, cfdata, aux) 107 struct device *parent; 108 void *cfdata, *aux; 109 { 110 struct tc_attach_args *d = aux; 111 112 if (strncmp("PMAZ-AA ", d->ta_modname, TC_ROM_LLEN)) 113 return (0); 114 115 return (1); 116 } 117 118 void 119 asc_tc_attach(parent, self, aux) 120 struct device *parent, *self; 121 void *aux; 122 { 123 struct tc_attach_args *ta = aux; 124 struct asc_tc_softc *asc = (struct asc_tc_softc *)self; 125 struct ncr53c9x_softc *sc = &asc->asc.sc_ncr53c9x; 126 127 /* 128 * Set up glue for MI code early; we use some of it here. 129 */ 130 sc->sc_glue = &asc_tc_glue; 131 asc->asc.sc_bst = ta->ta_memt; 132 asc->asc.sc_dmat = ta->ta_dmat; 133 if (bus_space_map(asc->asc.sc_bst, ta->ta_addr, 134 PMAZ_OFFSET_RAM + PMAZ_RAM_SIZE, 0, &asc->asc.sc_bsh)) { 135 printf("%s: unable to map device\n", sc->sc_dev.dv_xname); 136 return; 137 } 138 asc->sc_base = (caddr_t)ta->ta_addr; /* XXX XXX XXX */ 139 140 tc_intr_establish(parent, ta->ta_cookie, IPL_BIO, ncr53c9x_intr, sc, 141 self->dv_xname); 142 143 sc->sc_id = 7; 144 sc->sc_freq = (ta->ta_busspeed) ? 25000000 : 12500000; 145 146 /* gimme MHz */ 147 sc->sc_freq /= 1000000; 148 149 /* 150 * XXX More of this should be in ncr53c9x_attach(), but 151 * XXX should we really poke around the chip that much in 152 * XXX the MI code? Think about this more... 153 */ 154 155 /* 156 * Set up static configuration info. 157 */ 158 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 159 sc->sc_cfg2 = NCRCFG2_SCSI2; 160 sc->sc_cfg3 = 0; 161 sc->sc_rev = NCR_VARIANT_NCR53C94; 162 163 /* 164 * XXX minsync and maxxfer _should_ be set up in MI code, 165 * XXX but it appears to have some dependency on what sort 166 * XXX of DMA we're hooked up to, etc. 167 */ 168 169 /* 170 * This is the value used to start sync negotiations 171 * Note that the NCR register "SYNCTP" is programmed 172 * in "clocks per byte", and has a minimum value of 4. 173 * The SCSI period used in negotiation is one-fourth 174 * of the time (in nanoseconds) needed to transfer one byte. 175 * Since the chip's clock is given in MHz, we have the following 176 * formula: 4 * period = (1000 / freq) * 4 177 */ 178 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; 179 180 sc->sc_maxxfer = 64 * 1024; 181 182 /* Do the common parts of attachment. */ 183 ncr53c9x_attach(sc, &asc_switch, &asc_dev); 184 } 185 186 void 187 asc_tc_reset(sc) 188 struct ncr53c9x_softc *sc; 189 { 190 struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; 191 192 asc->asc.sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 193 } 194 195 int 196 asc_tc_intr(sc) 197 struct ncr53c9x_softc *sc; 198 { 199 struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; 200 int trans, resid; 201 202 resid = 0; 203 if ((asc->asc.sc_flags & ASC_ISPULLUP) == 0 && 204 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 205 NCR_DMA(("asc_tc_intr: empty FIFO of %d ", resid)); 206 DELAY(1); 207 } 208 209 resid += NCR_READ_REG(sc, NCR_TCL); 210 resid += NCR_READ_REG(sc, NCR_TCM) << 8; 211 212 trans = asc->asc.sc_dmasize - resid; 213 214 if (asc->asc.sc_flags & ASC_ISPULLUP) 215 memcpy(asc->sc_target, asc->sc_bounce, trans); 216 *asc->asc.sc_dmalen -= trans; 217 *asc->asc.sc_dmaaddr += trans; 218 asc->asc.sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 219 220 return (0); 221 } 222 223 int 224 asc_tc_setup(sc, addr, len, datain, dmasize) 225 struct ncr53c9x_softc *sc; 226 caddr_t *addr; 227 size_t *len; 228 int datain; 229 size_t *dmasize; 230 { 231 struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; 232 u_int32_t tc_dmar; 233 size_t size; 234 235 asc->asc.sc_dmaaddr = addr; 236 asc->asc.sc_dmalen = len; 237 asc->asc.sc_flags = (datain) ? ASC_ISPULLUP : 0; 238 239 NCR_DMA(("asc_tc_setup: start %ld@%p, %s\n", (long)*asc->asc.sc_dmalen, 240 *asc->asc.sc_dmaaddr, datain ? "IN" : "OUT")); 241 242 size = *dmasize; 243 if (size > PER_TGT_DMA_SIZE) 244 size = PER_TGT_DMA_SIZE; 245 *dmasize = asc->asc.sc_dmasize = size; 246 247 NCR_DMA(("asc_tc_setup: dmasize = %ld\n", (long)asc->asc.sc_dmasize)); 248 249 asc->sc_bounce = asc->sc_base + PMAZ_OFFSET_RAM; 250 asc->sc_bounce += PER_TGT_DMA_SIZE * 251 sc->sc_nexus->xs->sc_link->target; 252 asc->sc_target = *addr; 253 254 if ((asc->asc.sc_flags & ASC_ISPULLUP) == 0) 255 memcpy(asc->sc_bounce, asc->sc_target, size); 256 257 #if 1 258 if (asc->asc.sc_flags & ASC_ISPULLUP) 259 tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce); 260 else 261 tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce); 262 bus_space_write_4(asc->asc.sc_bst, asc->asc.sc_bsh, PMAZ_OFFSET_DMAR, 263 tc_dmar); 264 asc->asc.sc_flags |= ASC_MAPLOADED|ASC_DMAACTIVE; 265 #endif 266 return (0); 267 } 268 269 void 270 asc_tc_go(sc) 271 struct ncr53c9x_softc *sc; 272 { 273 #if 0 274 struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; 275 u_int32_t tc_dmar; 276 277 if (asc->asc.sc_flags & ASC_ISPULLUP) 278 tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce); 279 else 280 tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce); 281 bus_space_write_4(asc->asc.sc_bst, asc->asc.sc_bsh, PMAZ_OFFSET_DMAR, 282 tc_dmar); 283 asc->asc.sc_flags |= ASC_DMAACTIVE; 284 #endif 285 } 286 287 /* NEVER CALLED BY MI 53C9x ENGINE INDEED */ 288 void 289 asc_tc_stop(sc) 290 struct ncr53c9x_softc *sc; 291 { 292 #if 0 293 struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; 294 295 if (asc->asc.sc_flags & ASC_ISPULLUP) 296 memcpy(asc->sc_target, asc->sc_bounce, asc->sc_dmasize); 297 asc->asc.sc_flags &= ~ASC_DMAACTIVE; 298 #endif 299 } 300 301 /* 302 * Glue functions. 303 */ 304 int 305 asc_dma_isintr(sc) 306 struct ncr53c9x_softc *sc; 307 { 308 return !!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT); 309 } 310 311 int 312 asc_dma_isactive(sc) 313 struct ncr53c9x_softc *sc; 314 { 315 struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; 316 317 return !!(asc->asc.sc_flags & ASC_DMAACTIVE); 318 } 319 320 void 321 asc_clear_latched_intr(sc) 322 struct ncr53c9x_softc *sc; 323 { 324 } 325