1 /* $OpenBSD: sdmmcvar.h,v 1.26 2016/05/05 11:01:08 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _SDMMCVAR_H_ 20 #define _SDMMCVAR_H_ 21 22 #include <sys/queue.h> 23 #include <sys/rwlock.h> 24 25 #include <machine/bus.h> 26 27 #include <scsi/scsi_all.h> 28 #include <scsi/scsiconf.h> 29 30 #include <dev/sdmmc/sdmmcchip.h> 31 #include <dev/sdmmc/sdmmcreg.h> 32 33 struct sdmmc_csd { 34 int csdver; /* CSD structure format */ 35 int mmcver; /* MMC version (for CID format) */ 36 int capacity; /* total number of sectors */ 37 int sector_size; /* sector size in bytes */ 38 int read_bl_len; /* block length for reads */ 39 int ccc; /* Card Command Class for SD */ 40 /* ... */ 41 }; 42 43 struct sdmmc_cid { 44 int mid; /* manufacturer identification number */ 45 int oid; /* OEM/product identification number */ 46 char pnm[8]; /* product name (MMC v1 has the longest) */ 47 int rev; /* product revision */ 48 int psn; /* product serial number */ 49 int mdt; /* manufacturing date */ 50 }; 51 52 struct sdmmc_scr { 53 int sd_spec; 54 int bus_width; 55 }; 56 57 typedef u_int32_t sdmmc_response[4]; 58 59 struct sdmmc_softc; 60 61 struct sdmmc_task { 62 void (*func)(void *arg); 63 void *arg; 64 int onqueue; 65 struct sdmmc_softc *sc; 66 TAILQ_ENTRY(sdmmc_task) next; 67 }; 68 69 #define sdmmc_init_task(xtask, xfunc, xarg) do { \ 70 (xtask)->func = (xfunc); \ 71 (xtask)->arg = (xarg); \ 72 (xtask)->onqueue = 0; \ 73 (xtask)->sc = NULL; \ 74 } while (0) 75 76 #define sdmmc_task_pending(xtask) ((xtask)->onqueue) 77 78 struct sdmmc_command { 79 struct sdmmc_task c_task; /* task queue entry */ 80 u_int16_t c_opcode; /* SD or MMC command index */ 81 u_int32_t c_arg; /* SD/MMC command argument */ 82 sdmmc_response c_resp; /* response buffer */ 83 bus_dmamap_t c_dmamap; 84 void *c_data; /* buffer to send or read into */ 85 int c_datalen; /* length of data buffer */ 86 int c_blklen; /* block length */ 87 int c_flags; /* see below */ 88 #define SCF_ITSDONE 0x0001 /* command is complete */ 89 #define SCF_CMD(flags) ((flags) & 0x00f0) 90 #define SCF_CMD_AC 0x0000 91 #define SCF_CMD_ADTC 0x0010 92 #define SCF_CMD_BC 0x0020 93 #define SCF_CMD_BCR 0x0030 94 #define SCF_CMD_READ 0x0040 /* read command (data expected) */ 95 #define SCF_RSP_BSY 0x0100 96 #define SCF_RSP_136 0x0200 97 #define SCF_RSP_CRC 0x0400 98 #define SCF_RSP_IDX 0x0800 99 #define SCF_RSP_PRESENT 0x1000 100 /* response types */ 101 #define SCF_RSP_R0 0 /* none */ 102 #define SCF_RSP_R1 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 103 #define SCF_RSP_R1B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY) 104 #define SCF_RSP_R2 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_136) 105 #define SCF_RSP_R3 (SCF_RSP_PRESENT) 106 #define SCF_RSP_R4 (SCF_RSP_PRESENT) 107 #define SCF_RSP_R5 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 108 #define SCF_RSP_R5B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY) 109 #define SCF_RSP_R6 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 110 #define SCF_RSP_R7 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 111 int c_error; /* errno value on completion */ 112 113 /* Host controller owned fields for data xfer in progress */ 114 int c_resid; /* remaining I/O */ 115 u_char *c_buf; /* remaining data */ 116 }; 117 118 /* 119 * Decoded PC Card 16 based Card Information Structure (CIS), 120 * per card (function 0) and per function (1 and greater). 121 */ 122 struct sdmmc_cis { 123 u_int16_t manufacturer; 124 #define SDMMC_VENDOR_INVALID 0xffff 125 u_int16_t product; 126 #define SDMMC_PRODUCT_INVALID 0xffff 127 u_int8_t function; 128 #define SDMMC_FUNCTION_INVALID 0xff 129 u_char cis1_major; 130 u_char cis1_minor; 131 char cis1_info_buf[256]; 132 char *cis1_info[4]; 133 }; 134 135 /* 136 * Structure describing either an SD card I/O function or a SD/MMC 137 * memory card from a "stack of cards" that responded to CMD2. For a 138 * combo card with one I/O function and one memory card, there will be 139 * two of these structures allocated. Each card slot has such a list 140 * of sdmmc_function structures. 141 */ 142 struct sdmmc_function { 143 /* common members */ 144 struct sdmmc_softc *sc; /* card slot softc */ 145 u_int16_t rca; /* relative card address */ 146 int flags; 147 #define SFF_ERROR 0x0001 /* function is poo; ignore it */ 148 #define SFF_SDHC 0x0002 /* SD High Capacity card */ 149 SIMPLEQ_ENTRY(sdmmc_function) sf_list; 150 /* SD card I/O function members */ 151 int number; /* I/O function number or -1 */ 152 struct device *child; /* function driver */ 153 struct sdmmc_cis cis; /* decoded CIS */ 154 /* SD/MMC memory card members */ 155 struct sdmmc_csd csd; /* decoded CSD value */ 156 struct sdmmc_cid cid; /* decoded CID value */ 157 sdmmc_response raw_cid; /* temp. storage for decoding */ 158 struct sdmmc_scr scr; /* decoded SCR value */ 159 }; 160 161 /* 162 * Structure describing a single SD/MMC/SDIO card slot. 163 */ 164 struct sdmmc_softc { 165 struct device sc_dev; /* base device */ 166 #define DEVNAME(sc) ((sc)->sc_dev.dv_xname) 167 sdmmc_chipset_tag_t sct; /* host controller chipset tag */ 168 sdmmc_chipset_handle_t sch; /* host controller chipset handle */ 169 170 bus_dma_tag_t sc_dmat; 171 bus_dmamap_t sc_dmap; 172 #define SDMMC_MAXNSEGS ((MAXPHYS / PAGE_SIZE) + 1) 173 174 int sc_flags; 175 #define SMF_SD_MODE 0x0001 /* host in SD mode (MMC otherwise) */ 176 #define SMF_IO_MODE 0x0002 /* host in I/O mode (SD mode only) */ 177 #define SMF_MEM_MODE 0x0004 /* host in memory mode (SD or MMC) */ 178 #define SMF_CARD_PRESENT 0x0010 /* card presence noticed */ 179 #define SMF_CARD_ATTACHED 0x0020 /* card driver(s) attached */ 180 #define SMF_STOP_AFTER_MULTIPLE 0x0040 /* send a stop after a multiple cmd */ 181 #define SMF_CONFIG_PENDING 0x0080 /* config_pending_incr() called */ 182 183 uint32_t sc_caps; /* host capability */ 184 #define SMC_CAPS_AUTO_STOP 0x0001 /* send CMD12 automagically by host */ 185 #define SMC_CAPS_4BIT_MODE 0x0002 /* 4-bits data bus width */ 186 #define SMC_CAPS_DMA 0x0004 /* DMA transfer */ 187 #define SMC_CAPS_SPI_MODE 0x0008 /* SPI mode */ 188 #define SMC_CAPS_POLL_CARD_DET 0x0010 /* Polling card detect */ 189 #define SMC_CAPS_SINGLE_ONLY 0x0020 /* only single read/write */ 190 #define SMC_CAPS_8BIT_MODE 0x0040 /* 8-bits data bus width */ 191 #define SMC_CAPS_MULTI_SEG_DMA 0x0080 /* multiple segment DMA transfer */ 192 #define SMC_CAPS_SD_HIGHSPEED 0x0100 /* SD high-speed timing */ 193 #define SMC_CAPS_MMC_HIGHSPEED 0x0200 /* MMC high-speed timing */ 194 #define SMC_CAPS_UHS_SDR50 0x0400 /* UHS SDR50 timing */ 195 #define SMC_CAPS_UHS_SDR104 0x0800 /* UHS SDR104 timing */ 196 #define SMC_CAPS_UHS_DDR50 0x1000 /* UHS DDR50 timing */ 197 #define SMC_CAPS_UHS_MASK 0x1c00 198 #define SMC_CAPS_MMC_DDR52 0x2000 /* eMMC DDR52 timing */ 199 #define SMC_CAPS_MMC_HS200 0x4000 /* eMMC HS200 timing */ 200 #define SMC_CAPS_MMC_HS400 0x8000 /* eMMC HS400 timing */ 201 202 int sc_function_count; /* number of I/O functions (SDIO) */ 203 struct sdmmc_function *sc_card; /* selected card */ 204 struct sdmmc_function *sc_fn0; /* function 0, the card itself */ 205 SIMPLEQ_HEAD(, sdmmc_function) sf_head; /* list of card functions */ 206 int sc_dying; /* bus driver is shutting down */ 207 struct proc *sc_task_thread; /* asynchronous tasks */ 208 TAILQ_HEAD(, sdmmc_task) sc_tskq; /* task thread work queue */ 209 struct sdmmc_task sc_discover_task; /* card attach/detach task */ 210 struct sdmmc_task sc_intr_task; /* card interrupt task */ 211 struct rwlock sc_lock; /* lock around host controller */ 212 void *sc_scsibus; /* SCSI bus emulation softc */ 213 TAILQ_HEAD(, sdmmc_intr_handler) sc_intrq; /* interrupt handlers */ 214 long sc_max_xfer; /* maximum transfer size */ 215 }; 216 217 /* 218 * Attach devices at the sdmmc bus. 219 */ 220 struct sdmmc_attach_args { 221 struct scsi_link *scsi_link; /* XXX */ 222 struct sdmmc_function *sf; 223 }; 224 225 #define IPL_SDMMC IPL_BIO 226 #define splsdmmc() splbio() 227 228 #define SDMMC_ASSERT_LOCKED(sc) \ 229 rw_assert_wrlock(&(sc)->sc_lock) 230 231 void sdmmc_add_task(struct sdmmc_softc *, struct sdmmc_task *); 232 void sdmmc_del_task(struct sdmmc_task *); 233 234 struct sdmmc_function *sdmmc_function_alloc(struct sdmmc_softc *); 235 void sdmmc_function_free(struct sdmmc_function *); 236 int sdmmc_set_bus_power(struct sdmmc_softc *, u_int32_t, u_int32_t); 237 int sdmmc_mmc_command(struct sdmmc_softc *, struct sdmmc_command *); 238 int sdmmc_app_command(struct sdmmc_softc *, struct sdmmc_command *); 239 void sdmmc_go_idle_state(struct sdmmc_softc *); 240 int sdmmc_select_card(struct sdmmc_softc *, struct sdmmc_function *); 241 int sdmmc_set_relative_addr(struct sdmmc_softc *, 242 struct sdmmc_function *); 243 int sdmmc_send_if_cond(struct sdmmc_softc *, uint32_t); 244 245 void sdmmc_intr_enable(struct sdmmc_function *); 246 void sdmmc_intr_disable(struct sdmmc_function *); 247 void *sdmmc_intr_establish(struct device *, int (*)(void *), 248 void *, const char *); 249 void sdmmc_intr_disestablish(void *); 250 void sdmmc_intr_task(void *); 251 252 int sdmmc_io_enable(struct sdmmc_softc *); 253 void sdmmc_io_scan(struct sdmmc_softc *); 254 int sdmmc_io_init(struct sdmmc_softc *, struct sdmmc_function *); 255 void sdmmc_io_attach(struct sdmmc_softc *); 256 void sdmmc_io_detach(struct sdmmc_softc *); 257 u_int8_t sdmmc_io_read_1(struct sdmmc_function *, int); 258 u_int16_t sdmmc_io_read_2(struct sdmmc_function *, int); 259 u_int32_t sdmmc_io_read_4(struct sdmmc_function *, int); 260 int sdmmc_io_read_multi_1(struct sdmmc_function *, int, u_char *, int); 261 void sdmmc_io_write_1(struct sdmmc_function *, int, u_int8_t); 262 void sdmmc_io_write_2(struct sdmmc_function *, int, u_int16_t); 263 void sdmmc_io_write_4(struct sdmmc_function *, int, u_int32_t); 264 int sdmmc_io_write_multi_1(struct sdmmc_function *, int, u_char *, int); 265 int sdmmc_io_function_ready(struct sdmmc_function *); 266 int sdmmc_io_function_enable(struct sdmmc_function *); 267 void sdmmc_io_function_disable(struct sdmmc_function *); 268 269 int sdmmc_read_cis(struct sdmmc_function *, struct sdmmc_cis *); 270 void sdmmc_print_cis(struct sdmmc_function *); 271 void sdmmc_check_cis_quirks(struct sdmmc_function *); 272 273 int sdmmc_mem_enable(struct sdmmc_softc *); 274 void sdmmc_mem_scan(struct sdmmc_softc *); 275 int sdmmc_mem_init(struct sdmmc_softc *, struct sdmmc_function *); 276 int sdmmc_mem_read_block(struct sdmmc_function *, int, u_char *, size_t); 277 int sdmmc_mem_write_block(struct sdmmc_function *, int, u_char *, size_t); 278 279 /* ioctls */ 280 281 #include <sys/ioccom.h> 282 283 struct bio_sdmmc_command { 284 void *cookie; 285 struct sdmmc_command cmd; 286 }; 287 288 struct bio_sdmmc_debug { 289 void *cookie; 290 int debug; 291 }; 292 293 #define SDIOCEXECMMC _IOWR('S',0, struct bio_sdmmc_command) 294 #define SDIOCEXECAPP _IOWR('S',1, struct bio_sdmmc_command) 295 #define SDIOCSETDEBUG _IOWR('S',2, struct bio_sdmmc_debug) 296 297 #endif 298