1 /* $OpenBSD: sdmmcreg.h,v 1.11 2016/05/05 11:01:08 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _SDMMCREG_H_ 20 #define _SDMMCREG_H_ 21 22 /* MMC commands */ /* response type */ 23 #define MMC_GO_IDLE_STATE 0 /* R0 */ 24 #define MMC_SEND_OP_COND 1 /* R3 */ 25 #define MMC_ALL_SEND_CID 2 /* R2 */ 26 #define MMC_SET_RELATIVE_ADDR 3 /* R1 */ 27 #define MMC_SWITCH 6 /* R1B */ 28 #define MMC_SELECT_CARD 7 /* R1 */ 29 #define MMC_SEND_EXT_CSD 8 /* R1 */ 30 #define MMC_SEND_CSD 9 /* R2 */ 31 #define MMC_STOP_TRANSMISSION 12 /* R1B */ 32 #define MMC_SEND_STATUS 13 /* R1 */ 33 #define MMC_SET_BLOCKLEN 16 /* R1 */ 34 #define MMC_READ_BLOCK_SINGLE 17 /* R1 */ 35 #define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */ 36 #define MMC_SET_BLOCK_COUNT 23 /* R1 */ 37 #define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */ 38 #define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */ 39 #define MMC_APP_CMD 55 /* R1 */ 40 41 /* SD commands */ /* response type */ 42 #define SD_SEND_RELATIVE_ADDR 3 /* R6 */ 43 #define SD_SEND_SWITCH_FUNC 6 /* R1 */ 44 #define SD_SEND_IF_COND 8 /* R7 */ 45 46 /* SD application commands */ /* response type */ 47 #define SD_APP_SET_BUS_WIDTH 6 /* R1 */ 48 #define SD_APP_OP_COND 41 /* R3 */ 49 #define SD_APP_SEND_SCR 51 /* R1 */ 50 51 /* OCR bits */ 52 #define MMC_OCR_MEM_READY (1<<31) /* memory power-up status bit */ 53 #define MMC_OCR_ACCESS_MODE_MASK 0x60000000 /* bits 30:29 */ 54 #define MMC_OCR_SECTOR_MODE (1<<30) 55 #define MMC_OCR_BYTE_MODE (1<<29) 56 #define MMC_OCR_3_5V_3_6V (1<<23) 57 #define MMC_OCR_3_4V_3_5V (1<<22) 58 #define MMC_OCR_3_3V_3_4V (1<<21) 59 #define MMC_OCR_3_2V_3_3V (1<<20) 60 #define MMC_OCR_3_1V_3_2V (1<<19) 61 #define MMC_OCR_3_0V_3_1V (1<<18) 62 #define MMC_OCR_2_9V_3_0V (1<<17) 63 #define MMC_OCR_2_8V_2_9V (1<<16) 64 #define MMC_OCR_2_7V_2_8V (1<<15) 65 #define MMC_OCR_2_6V_2_7V (1<<14) 66 #define MMC_OCR_2_5V_2_6V (1<<13) 67 #define MMC_OCR_2_4V_2_5V (1<<12) 68 #define MMC_OCR_2_3V_2_4V (1<<11) 69 #define MMC_OCR_2_2V_2_3V (1<<10) 70 #define MMC_OCR_2_1V_2_2V (1<<9) 71 #define MMC_OCR_2_0V_2_1V (1<<8) 72 #define MMC_OCR_1_65V_1_95V (1<<7) 73 74 #define SD_OCR_SDHC_CAP (1<<30) 75 #define SD_OCR_VOL_MASK 0xFF8000 /* bits 23:15 */ 76 77 /* R1 response type bits */ 78 #define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */ 79 #define MMC_R1_APP_CMD (1<<5) /* app. commands supported */ 80 81 /* 48-bit response decoding (32 bits w/o CRC) */ 82 #define MMC_R1(resp) ((resp)[0]) 83 #define MMC_R3(resp) ((resp)[0]) 84 #define SD_R6(resp) ((resp)[0]) 85 86 /* RCA argument and response */ 87 #define MMC_ARG_RCA(rca) ((rca) << 16) 88 #define SD_R6_RCA(resp) (SD_R6((resp)) >> 16) 89 90 /* bus width argument */ 91 #define SD_ARG_BUS_WIDTH_1 0 92 #define SD_ARG_BUS_WIDTH_4 2 93 94 /* EXT_CSD fields */ 95 #define EXT_CSD_BUS_WIDTH 183 /* WO */ 96 #define EXT_CSD_HS_TIMING 185 /* R/W */ 97 #define EXT_CSD_REV 192 /* RO */ 98 #define EXT_CSD_STRUCTURE 194 /* RO */ 99 #define EXT_CSD_CARD_TYPE 196 /* RO */ 100 #define EXT_CSD_SEC_COUNT 212 /* RO */ 101 102 /* EXT_CSD field definitions */ 103 #define EXT_CSD_CMD_SET_NORMAL (1U << 0) 104 #define EXT_CSD_CMD_SET_SECURE (1U << 1) 105 #define EXT_CSD_CMD_SET_CPSECURE (1U << 2) 106 107 /* EXT_CSD_HS_TIMING */ 108 #define EXT_CSD_HS_TIMING_BC 0 109 #define EXT_CSD_HS_TIMING_HS 1 110 #define EXT_CSD_HS_TIMING_HS200 2 111 #define EXT_CSD_HS_TIMING_HS400 3 112 113 /* EXT_CSD_BUS_WIDTH */ 114 #define EXT_CSD_BUS_WIDTH_1 0 115 #define EXT_CSD_BUS_WIDTH_4 1 116 #define EXT_CSD_BUS_WIDTH_8 2 117 #define EXT_CSD_BUS_WIDTH_4_DDR 5 118 #define EXT_CSD_BUS_WIDTH_8_DDR 6 119 120 /* EXT_CSD_CARD_TYPE */ 121 /* The only currently valid values for this field are 0x01, 0x03, 0x07, 122 * 0x0B and 0x0F. */ 123 #define EXT_CSD_CARD_TYPE_F_26M (1 << 0) 124 #define EXT_CSD_CARD_TYPE_F_52M (1 << 1) 125 #define EXT_CSD_CARD_TYPE_F_52M_1_8V (1 << 2) 126 #define EXT_CSD_CARD_TYPE_F_52M_1_2V (1 << 3) 127 #define EXT_CSD_CARD_TYPE_26M 0x01 128 #define EXT_CSD_CARD_TYPE_52M 0x03 129 #define EXT_CSD_CARD_TYPE_52M_V18 0x07 130 #define EXT_CSD_CARD_TYPE_52M_V12 0x0b 131 #define EXT_CSD_CARD_TYPE_52M_V12_18 0x0f 132 133 /* MMC_SWITCH access mode */ 134 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 135 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in value */ 136 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in value */ 137 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ 138 139 /* MMC R2 response (CSD) */ 140 #define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2) 141 #define MMC_CSD_CSDVER_1_0 1 142 #define MMC_CSD_CSDVER_2_0 2 143 #define MMC_CSD_CSDVER_EXT_CSD 3 144 #define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4) 145 #define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */ 146 #define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */ 147 #define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */ 148 #define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */ 149 #define MMC_CSD_MMCVER_4_0 4 /* MMC 4 */ 150 #define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4) 151 #define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12) 152 #define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \ 153 (MMC_CSD_C_SIZE_MULT((resp))+2)) 154 #define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3) 155 156 /* MMC v1 R2 response (CID) */ 157 #define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24) 158 #define MMC_CID_PNM_V1_CPY(resp, pnm) \ 159 do { \ 160 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 161 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 162 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 163 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 164 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 165 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \ 166 (pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \ 167 (pnm)[7] = '\0'; \ 168 } while (0) 169 #define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8) 170 #define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24) 171 #define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8) 172 173 /* MMC v2 R2 response (CID) */ 174 #define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8) 175 #define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16) 176 #define MMC_CID_PNM_V2_CPY(resp, pnm) \ 177 do { \ 178 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 179 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 180 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 181 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 182 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 183 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \ 184 (pnm)[6] = '\0'; \ 185 } while (0) 186 #define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32) 187 188 /* SD R2 response (CSD) */ 189 #define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2) 190 #define SD_CSD_CSDVER_1_0 0 191 #define SD_CSD_CSDVER_2_0 1 192 #define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8) 193 #define SD_CSD_TAAC_1_5_MSEC 0x26 194 #define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8) 195 #define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8) 196 #define SD_CSD_SPEED_25_MHZ 0x32 197 #define SD_CSD_SPEED_50_MHZ 0x5a 198 #define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12) 199 #define SD_CSD_CCC_BASIC (1 << 0) /* basic */ 200 #define SD_CSD_CCC_BR (1 << 2) /* block read */ 201 #define SD_CSD_CCC_BW (1 << 4) /* block write */ 202 #define SD_CSD_CCC_ERACE (1 << 5) /* erase */ 203 #define SD_CSD_CCC_WP (1 << 6) /* write protection */ 204 #define SD_CSD_CCC_LC (1 << 7) /* lock card */ 205 #define SD_CSD_CCC_AS (1 << 8) /*application specific*/ 206 #define SD_CSD_CCC_IOM (1 << 9) /* I/O mode */ 207 #define SD_CSD_CCC_SWITCH (1 << 10) /* switch */ 208 #define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4) 209 #define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1) 210 #define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1) 211 #define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1) 212 #define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1) 213 #define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12) 214 #define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \ 215 (SD_CSD_C_SIZE_MULT((resp))+2)) 216 #define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22) 217 #define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10) 218 #define SD_CSD_V2_BL_LEN 0x9 /* 512 */ 219 #define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3) 220 #define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3) 221 #define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3) 222 #define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3) 223 #define SD_CSD_VDD_RW_CURR_100mA 0x7 224 #define SD_CSD_VDD_RW_CURR_80mA 0x6 225 #define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3) 226 #define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1) 227 #define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */ 228 #define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */ 229 #define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1) 230 #define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3) 231 #define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4) 232 #define SD_CSD_RW_BL_LEN_2G 0xa 233 #define SD_CSD_RW_BL_LEN_1G 0x9 234 #define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1) 235 #define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1) 236 #define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1) 237 #define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1) 238 #define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1) 239 #define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2) 240 241 /* SD R2 response (CID) */ 242 #define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8) 243 #define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16) 244 #define SD_CID_PNM_CPY(resp, pnm) \ 245 do { \ 246 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 247 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 248 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 249 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 250 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 251 (pnm)[5] = '\0'; \ 252 } while (0) 253 #define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8) 254 #define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32) 255 #define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12) 256 257 /* SCR (SD Configuration Register) */ 258 #define SCR_STRUCTURE(scr) MMC_RSP_BITS((scr), 60, 4) 259 #define SCR_STRUCTURE_VER_1_0 0 /* Version 1.0 */ 260 #define SCR_SD_SPEC(scr) MMC_RSP_BITS((scr), 56, 4) 261 #define SCR_SD_SPEC_VER_1_0 0 /* Version 1.0 and 1.01 */ 262 #define SCR_SD_SPEC_VER_1_10 1 /* Version 1.10 */ 263 #define SCR_SD_SPEC_VER_2 2 /* Version 2.00 or Version 3.0X */ 264 #define SCR_DATA_STAT_AFTER_ERASE(scr) MMC_RSP_BITS((scr), 55, 1) 265 #define SCR_SD_SECURITY(scr) MMC_RSP_BITS((scr), 52, 3) 266 #define SCR_SD_SECURITY_NONE 0 /* no security */ 267 #define SCR_SD_SECURITY_1_0 1 /* security protocol 1.0 */ 268 #define SCR_SD_SECURITY_1_0_2 2 /* security protocol 1.0 */ 269 #define SCR_SD_BUS_WIDTHS(scr) MMC_RSP_BITS((scr), 48, 4) 270 #define SCR_SD_BUS_WIDTHS_1BIT (1 << 0) /* 1bit (DAT0) */ 271 #define SCR_SD_BUS_WIDTHS_4BIT (1 << 2) /* 4bit (DAT0-3) */ 272 #define SCR_SD_SPEC3(scr) MMC_RSP_BITS((scr), 47, 1) 273 #define SCR_EX_SECURITY(scr) MMC_RSP_BITS((scr), 43, 4) 274 #define SCR_SD_SPEC4(scr) MMC_RSP_BITS((scr), 42, 1) 275 #define SCR_RESERVED(scr) MMC_RSP_BITS((scr), 34, 8) 276 #define SCR_CMD_SUPPORT_CMD23(scr) MMC_RSP_BITS((scr), 33, 1) 277 #define SCR_CMD_SUPPORT_CMD20(scr) MMC_RSP_BITS((scr), 32, 1) 278 #define SCR_RESERVED2(scr) MMC_RSP_BITS((scr), 0, 32) 279 280 /* Status of Switch Function */ 281 #define SFUNC_STATUS_GROUP(status, group) \ 282 (__bitfield((uint32_t *)(status), 400 + (group - 1) * 16, 16)) 283 284 #define SD_ACCESS_MODE_SDR12 0 285 #define SD_ACCESS_MODE_SDR25 1 286 #define SD_ACCESS_MODE_SDR50 2 287 #define SD_ACCESS_MODE_SDR104 3 288 #define SD_ACCESS_MODE_DDR50 4 289 290 /* Might be slow, but it should work on big and little endian systems. */ 291 #define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start)-8, (len)) 292 static __inline int 293 __bitfield(u_int32_t *src, int start, int len) 294 { 295 u_int8_t *sp; 296 u_int32_t dst, mask; 297 int shift, bs, bc; 298 299 if (start < 0 || len < 0 || len > 32) 300 return 0; 301 302 dst = 0; 303 mask = len % 32 ? UINT_MAX >> (32 - (len % 32)) : UINT_MAX; 304 shift = 0; 305 306 while (len > 0) { 307 sp = (u_int8_t *)src + start / 8; 308 bs = start % 8; 309 bc = 8 - bs; 310 if (bc > len) 311 bc = len; 312 dst |= (*sp++ >> bs) << shift; 313 shift += bc; 314 start += bc; 315 len -= bc; 316 } 317 318 dst &= mask; 319 return (int)dst; 320 } 321 322 #endif 323