xref: /openbsd-src/sys/dev/sdmmc/sdmmcchip.h (revision 834ff46cdc127050471ec5871d62421e559b5881)
1*834ff46cSdlg /*	$OpenBSD: sdmmcchip.h,v 1.15 2023/04/19 02:01:02 dlg Exp $	*/
2aae4fe77Suwe 
3aae4fe77Suwe /*
4aae4fe77Suwe  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
5aae4fe77Suwe  *
6aae4fe77Suwe  * Permission to use, copy, modify, and distribute this software for any
7aae4fe77Suwe  * purpose with or without fee is hereby granted, provided that the above
8aae4fe77Suwe  * copyright notice and this permission notice appear in all copies.
9aae4fe77Suwe  *
10aae4fe77Suwe  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11aae4fe77Suwe  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12aae4fe77Suwe  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13aae4fe77Suwe  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14aae4fe77Suwe  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15aae4fe77Suwe  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16aae4fe77Suwe  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17aae4fe77Suwe  */
18aae4fe77Suwe 
19aae4fe77Suwe #ifndef _SDMMC_CHIP_H_
20aae4fe77Suwe #define _SDMMC_CHIP_H_
21aae4fe77Suwe 
22c6293583Skettenis #include <machine/bus.h>
23c6293583Skettenis 
24aae4fe77Suwe struct sdmmc_command;
25aae4fe77Suwe 
26aae4fe77Suwe typedef struct sdmmc_chip_functions *sdmmc_chipset_tag_t;
27aae4fe77Suwe typedef void *sdmmc_chipset_handle_t;
28aae4fe77Suwe 
29aae4fe77Suwe struct sdmmc_chip_functions {
30aae4fe77Suwe 	/* host controller reset */
31aae4fe77Suwe 	int	(*host_reset)(sdmmc_chipset_handle_t);
32aae4fe77Suwe 	/* host capabilities */
33aae4fe77Suwe 	u_int32_t (*host_ocr)(sdmmc_chipset_handle_t);
34aae4fe77Suwe 	int	(*host_maxblklen)(sdmmc_chipset_handle_t);
35aae4fe77Suwe 	/* card detection */
36aae4fe77Suwe 	int	(*card_detect)(sdmmc_chipset_handle_t);
37aae4fe77Suwe 	/* bus power and clock frequency */
38aae4fe77Suwe 	int	(*bus_power)(sdmmc_chipset_handle_t, u_int32_t);
39820e06f1Skettenis 	int	(*bus_clock)(sdmmc_chipset_handle_t, int, int);
40b140af5cSkettenis 	int	(*bus_width)(sdmmc_chipset_handle_t, int);
41aae4fe77Suwe 	/* command execution */
42a6fd99a7Suwe 	void	(*exec_command)(sdmmc_chipset_handle_t,
43aae4fe77Suwe 		    struct sdmmc_command *);
44b979651fSuwe 	/* card interrupt */
45b979651fSuwe 	void	(*card_intr_mask)(sdmmc_chipset_handle_t, int);
46b979651fSuwe 	void	(*card_intr_ack)(sdmmc_chipset_handle_t);
47820e06f1Skettenis 	/* UHS functions */
48820e06f1Skettenis 	int	(*signal_voltage)(sdmmc_chipset_handle_t, int);
49a62fc20aSkettenis 	int	(*execute_tuning)(sdmmc_chipset_handle_t, int);
50f3036462Sjmatthew 	/* hibernate */
51f3036462Sjmatthew 	int	(*hibernate_init)(sdmmc_chipset_handle_t, void *);
52aae4fe77Suwe };
53aae4fe77Suwe 
54aae4fe77Suwe /* host controller reset */
55aae4fe77Suwe #define sdmmc_chip_host_reset(tag, handle)				\
56aae4fe77Suwe 	((tag)->host_reset((handle)))
57aae4fe77Suwe /* host capabilities */
58aae4fe77Suwe #define sdmmc_chip_host_ocr(tag, handle)				\
59aae4fe77Suwe 	((tag)->host_ocr((handle)))
60aae4fe77Suwe #define sdmmc_chip_host_maxblklen(tag, handle)				\
61aae4fe77Suwe 	((tag)->host_maxblklen((handle)))
62aae4fe77Suwe /* card detection */
63aae4fe77Suwe #define sdmmc_chip_card_detect(tag, handle)				\
64aae4fe77Suwe 	((tag)->card_detect((handle)))
65aae4fe77Suwe /* bus power and clock frequency */
66aae4fe77Suwe #define sdmmc_chip_bus_power(tag, handle, ocr)				\
67aae4fe77Suwe 	((tag)->bus_power((handle), (ocr)))
68820e06f1Skettenis #define sdmmc_chip_bus_clock(tag, handle, freq, timing)			\
69820e06f1Skettenis 	((tag)->bus_clock((handle), (freq), (timing)))
70b140af5cSkettenis #define sdmmc_chip_bus_width(tag, handle, width)			\
71b140af5cSkettenis 	((tag)->bus_width((handle), (width)))
72aae4fe77Suwe /* command execution */
73aae4fe77Suwe #define sdmmc_chip_exec_command(tag, handle, cmdp)			\
74aae4fe77Suwe 	((tag)->exec_command((handle), (cmdp)))
75b979651fSuwe /* card interrupt */
76b979651fSuwe #define sdmmc_chip_card_intr_mask(tag, handle, enable)			\
77b979651fSuwe 	((tag)->card_intr_mask((handle), (enable)))
78b979651fSuwe #define sdmmc_chip_card_intr_ack(tag, handle)				\
79b979651fSuwe 	((tag)->card_intr_ack((handle)))
80820e06f1Skettenis /* UHS functions */
81820e06f1Skettenis #define sdmmc_chip_signal_voltage(tag, handle, voltage)			\
82820e06f1Skettenis 	((tag)->signal_voltage((handle), (voltage)))
83a62fc20aSkettenis #define sdmmc_chip_execute_tuning(tag, handle, timing)			\
84a62fc20aSkettenis 	((tag)->execute_tuning((handle), (timing)))
85aae4fe77Suwe 
86aae4fe77Suwe /* clock frequencies for sdmmc_chip_bus_clock() */
87aae4fe77Suwe #define SDMMC_SDCLK_OFF		0
88aae4fe77Suwe #define SDMMC_SDCLK_400KHZ	400
89aae4fe77Suwe #define SDMMC_SDCLK_25MHZ	25000
906ca10361Skettenis #define SDMMC_SDCLK_50MHZ	50000
91aae4fe77Suwe 
92820e06f1Skettenis /* voltage levels for sdmmc_chip_signal_voltage() */
93820e06f1Skettenis #define SDMMC_SIGNAL_VOLTAGE_330	0
94820e06f1Skettenis #define SDMMC_SIGNAL_VOLTAGE_180	1
95820e06f1Skettenis 
96820e06f1Skettenis #define SDMMC_TIMING_LEGACY	0
97820e06f1Skettenis #define SDMMC_TIMING_HIGHSPEED	1
98a62fc20aSkettenis #define SDMMC_TIMING_UHS_SDR50	2
99a62fc20aSkettenis #define SDMMC_TIMING_UHS_SDR104	3
100a62fc20aSkettenis #define SDMMC_TIMING_MMC_DDR52	4
101a62fc20aSkettenis #define SDMMC_TIMING_MMC_HS200	5
102820e06f1Skettenis 
10368a1c7f6Spatrick #define SDMMC_MAX_FUNCTIONS	8
10468a1c7f6Spatrick 
105aae4fe77Suwe struct sdmmcbus_attach_args {
106aae4fe77Suwe 	const char *saa_busname;
107aae4fe77Suwe 	sdmmc_chipset_tag_t sct;
108aae4fe77Suwe 	sdmmc_chipset_handle_t sch;
109c6293583Skettenis 	bus_dma_tag_t dmat;
110b58329e9Skettenis 	bus_dmamap_t dmap;
11146a44037Smiod 	int	flags;
11224518680Srapha 	int	caps;
1132afcf50dSpatrick 	long	max_seg;
11446a44037Smiod 	long	max_xfer;
115*834ff46cSdlg 	bus_size_t dma_boundary;
11668a1c7f6Spatrick 	void	*cookies[SDMMC_MAX_FUNCTIONS];
117aae4fe77Suwe };
118aae4fe77Suwe 
119a6fd99a7Suwe void	sdmmc_needs_discover(struct device *);
120b979651fSuwe void	sdmmc_card_intr(struct device *);
121a6fd99a7Suwe void	sdmmc_delay(u_int);
122aae4fe77Suwe 
123aae4fe77Suwe #endif
124