1 /* $OpenBSD: sdmmc_mem.c,v 1.35 2020/08/24 15:06:10 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* Routines for SD/MMC memory cards. */ 20 21 #include <sys/param.h> 22 #include <sys/device.h> 23 #include <sys/kernel.h> 24 #include <sys/malloc.h> 25 #include <sys/systm.h> 26 27 #include <dev/sdmmc/sdmmcchip.h> 28 #include <dev/sdmmc/sdmmcreg.h> 29 #include <dev/sdmmc/sdmmcvar.h> 30 31 #ifdef HIBERNATE 32 #include <uvm/uvm_extern.h> 33 #endif 34 35 typedef struct { uint32_t _bits[512/32]; } __packed __aligned(4) sdmmc_bitfield512_t; 36 37 void sdmmc_be512_to_bitfield512(sdmmc_bitfield512_t *); 38 39 int sdmmc_decode_csd(struct sdmmc_softc *, sdmmc_response, 40 struct sdmmc_function *); 41 int sdmmc_decode_cid(struct sdmmc_softc *, sdmmc_response, 42 struct sdmmc_function *); 43 void sdmmc_print_cid(struct sdmmc_cid *); 44 45 int sdmmc_mem_send_op_cond(struct sdmmc_softc *, u_int32_t, u_int32_t *); 46 int sdmmc_mem_set_blocklen(struct sdmmc_softc *, struct sdmmc_function *); 47 48 int sdmmc_mem_send_scr(struct sdmmc_softc *, uint32_t *); 49 int sdmmc_mem_decode_scr(struct sdmmc_softc *, uint32_t *, 50 struct sdmmc_function *); 51 52 int sdmmc_mem_send_cxd_data(struct sdmmc_softc *, int, void *, size_t); 53 int sdmmc_mem_set_bus_width(struct sdmmc_function *, int); 54 int sdmmc_mem_mmc_switch(struct sdmmc_function *, uint8_t, uint8_t, uint8_t); 55 int sdmmc_mem_signal_voltage(struct sdmmc_softc *, int); 56 57 int sdmmc_mem_sd_init(struct sdmmc_softc *, struct sdmmc_function *); 58 int sdmmc_mem_mmc_init(struct sdmmc_softc *, struct sdmmc_function *); 59 int sdmmc_mem_single_read_block(struct sdmmc_function *, int, u_char *, 60 size_t); 61 int sdmmc_mem_read_block_subr(struct sdmmc_function *, bus_dmamap_t, 62 int, u_char *, size_t); 63 int sdmmc_mem_single_write_block(struct sdmmc_function *, int, u_char *, 64 size_t); 65 int sdmmc_mem_write_block_subr(struct sdmmc_function *, bus_dmamap_t, 66 int, u_char *, size_t); 67 68 #ifdef SDMMC_DEBUG 69 #define DPRINTF(s) printf s 70 #else 71 #define DPRINTF(s) /**/ 72 #endif 73 74 const struct { 75 const char *name; 76 int v; 77 int freq; 78 } switch_group0_functions[] = { 79 /* Default/SDR12 */ 80 { "Default/SDR12", 0, 25000 }, 81 82 /* High-Speed/SDR25 */ 83 { "High-Speed/SDR25", SMC_CAPS_SD_HIGHSPEED, 50000 }, 84 85 /* SDR50 */ 86 { "SDR50", SMC_CAPS_UHS_SDR50, 100000 }, 87 88 /* SDR104 */ 89 { "SDR104", SMC_CAPS_UHS_SDR104, 208000 }, 90 91 /* DDR50 */ 92 { "DDR50", SMC_CAPS_UHS_DDR50, 50000 }, 93 }; 94 95 const int sdmmc_mmc_timings[] = { 96 [SDMMC_TIMING_LEGACY] = 26000, 97 [SDMMC_TIMING_HIGHSPEED] = 52000, 98 [SDMMC_TIMING_MMC_DDR52] = 52000, 99 [SDMMC_TIMING_MMC_HS200] = 200000 100 }; 101 102 /* 103 * Initialize SD/MMC memory cards and memory in SDIO "combo" cards. 104 */ 105 int 106 sdmmc_mem_enable(struct sdmmc_softc *sc) 107 { 108 uint32_t host_ocr; 109 uint32_t card_ocr; 110 uint32_t new_ocr; 111 uint32_t ocr = 0; 112 int error; 113 114 rw_assert_wrlock(&sc->sc_lock); 115 116 /* Set host mode to SD "combo" card or SD memory-only. */ 117 CLR(sc->sc_flags, SMF_UHS_MODE); 118 SET(sc->sc_flags, SMF_SD_MODE|SMF_MEM_MODE); 119 120 /* Reset memory (*must* do that before CMD55 or CMD1). */ 121 sdmmc_go_idle_state(sc); 122 123 /* 124 * Read the SD/MMC memory OCR value by issuing CMD55 followed 125 * by ACMD41 to read the OCR value from memory-only SD cards. 126 * MMC cards will not respond to CMD55 or ACMD41 and this is 127 * how we distinguish them from SD cards. 128 */ 129 mmc_mode: 130 if (sdmmc_mem_send_op_cond(sc, 0, &card_ocr) != 0) { 131 if (ISSET(sc->sc_flags, SMF_SD_MODE) && 132 !ISSET(sc->sc_flags, SMF_IO_MODE)) { 133 /* Not a SD card, switch to MMC mode. */ 134 CLR(sc->sc_flags, SMF_SD_MODE); 135 goto mmc_mode; 136 } 137 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 138 DPRINTF(("%s: can't read memory OCR\n", 139 DEVNAME(sc))); 140 return 1; 141 } else { 142 /* Not a "combo" card. */ 143 CLR(sc->sc_flags, SMF_MEM_MODE); 144 return 0; 145 } 146 } 147 148 /* Set the lowest voltage supported by the card and host. */ 149 host_ocr = sdmmc_chip_host_ocr(sc->sct, sc->sch); 150 if (sdmmc_set_bus_power(sc, host_ocr, card_ocr) != 0) { 151 DPRINTF(("%s: can't supply voltage requested by card\n", 152 DEVNAME(sc))); 153 return 1; 154 } 155 156 /* Tell the card(s) to enter the idle state (again). */ 157 sdmmc_go_idle_state(sc); 158 159 host_ocr &= card_ocr; /* only allow the common voltages */ 160 161 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 162 if (sdmmc_send_if_cond(sc, card_ocr) == 0) 163 SET(ocr, MMC_OCR_HCS); 164 165 if (sdmmc_chip_host_ocr(sc->sct, sc->sch) & MMC_OCR_S18A) 166 SET(ocr, MMC_OCR_S18A); 167 } 168 host_ocr |= ocr; 169 170 /* Send the new OCR value until all cards are ready. */ 171 if (sdmmc_mem_send_op_cond(sc, host_ocr, &new_ocr) != 0) { 172 DPRINTF(("%s: can't send memory OCR\n", DEVNAME(sc))); 173 return 1; 174 } 175 176 if (ISSET(sc->sc_flags, SMF_SD_MODE) && ISSET(new_ocr, MMC_OCR_S18A)) { 177 /* 178 * Card and host support low voltage mode, begin switch 179 * sequence. 180 */ 181 struct sdmmc_command cmd; 182 183 memset(&cmd, 0, sizeof(cmd)); 184 cmd.c_arg = 0; 185 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 186 cmd.c_opcode = SD_VOLTAGE_SWITCH; 187 DPRINTF(("%s: switching card to 1.8V\n", DEVNAME(sc))); 188 error = sdmmc_mmc_command(sc, &cmd); 189 if (error) { 190 DPRINTF(("%s: voltage switch command failed\n", 191 SDMMCDEVNAME(sc))); 192 return error; 193 } 194 195 error = sdmmc_mem_signal_voltage(sc, SDMMC_SIGNAL_VOLTAGE_180); 196 if (error) 197 return error; 198 199 SET(sc->sc_flags, SMF_UHS_MODE); 200 } 201 202 return 0; 203 } 204 205 int 206 sdmmc_mem_signal_voltage(struct sdmmc_softc *sc, int signal_voltage) 207 { 208 int error; 209 210 /* 211 * Stop the clock 212 */ 213 error = sdmmc_chip_bus_clock(sc->sct, sc->sch, 0, SDMMC_TIMING_LEGACY); 214 if (error) 215 return error; 216 217 delay(1000); 218 219 /* 220 * Card switch command was successful, update host controller 221 * signal voltage setting. 222 */ 223 DPRINTF(("%s: switching host to %s\n", SDMMCDEVNAME(sc), 224 signal_voltage == SDMMC_SIGNAL_VOLTAGE_180 ? "1.8V" : "3.3V")); 225 error = sdmmc_chip_signal_voltage(sc->sct, sc->sch, signal_voltage); 226 if (error) 227 return error; 228 229 delay(5000); 230 231 /* 232 * Switch to SDR12 timing 233 */ 234 error = sdmmc_chip_bus_clock(sc->sct, sc->sch, SDMMC_SDCLK_25MHZ, 235 SDMMC_TIMING_LEGACY); 236 if (error) 237 return error; 238 239 delay(1000); 240 241 return 0; 242 } 243 244 /* 245 * Read the CSD and CID from all cards and assign each card a unique 246 * relative card address (RCA). CMD2 is ignored by SDIO-only cards. 247 */ 248 void 249 sdmmc_mem_scan(struct sdmmc_softc *sc) 250 { 251 struct sdmmc_command cmd; 252 struct sdmmc_function *sf; 253 u_int16_t next_rca; 254 int error; 255 int i; 256 257 rw_assert_wrlock(&sc->sc_lock); 258 259 /* 260 * CMD2 is a broadcast command understood by SD cards and MMC 261 * cards. All cards begin to respond to the command, but back 262 * off if another card drives the CMD line to a different level. 263 * Only one card will get its entire response through. That 264 * card remains silent once it has been assigned a RCA. 265 */ 266 for (i = 0; i < 100; i++) { 267 bzero(&cmd, sizeof cmd); 268 cmd.c_opcode = MMC_ALL_SEND_CID; 269 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R2; 270 271 error = sdmmc_mmc_command(sc, &cmd); 272 if (error == ETIMEDOUT) { 273 /* No more cards there. */ 274 break; 275 } else if (error != 0) { 276 DPRINTF(("%s: can't read CID\n", DEVNAME(sc))); 277 break; 278 } 279 280 /* In MMC mode, find the next available RCA. */ 281 next_rca = 1; 282 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) 283 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) 284 next_rca++; 285 286 /* Allocate a sdmmc_function structure. */ 287 sf = sdmmc_function_alloc(sc); 288 sf->rca = next_rca; 289 290 /* 291 * Remember the CID returned in the CMD2 response for 292 * later decoding. 293 */ 294 bcopy(cmd.c_resp, sf->raw_cid, sizeof sf->raw_cid); 295 296 /* 297 * Silence the card by assigning it a unique RCA, or 298 * querying it for its RCA in the case of SD. 299 */ 300 if (sdmmc_set_relative_addr(sc, sf) != 0) { 301 printf("%s: can't set mem RCA\n", DEVNAME(sc)); 302 sdmmc_function_free(sf); 303 break; 304 } 305 306 #if 0 307 /* Verify that the RCA has been set by selecting the card. */ 308 if (sdmmc_select_card(sc, sf) != 0) { 309 printf("%s: can't select mem RCA %d\n", 310 DEVNAME(sc), sf->rca); 311 sdmmc_function_free(sf); 312 break; 313 } 314 315 /* Deselect. */ 316 (void)sdmmc_select_card(sc, NULL); 317 #endif 318 319 /* 320 * If this is a memory-only card, the card responding 321 * first becomes an alias for SDIO function 0. 322 */ 323 if (sc->sc_fn0 == NULL) 324 sc->sc_fn0 = sf; 325 326 SIMPLEQ_INSERT_TAIL(&sc->sf_head, sf, sf_list); 327 } 328 329 /* 330 * All cards are either inactive or awaiting further commands. 331 * Read the CSDs and decode the raw CID for each card. 332 */ 333 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) { 334 bzero(&cmd, sizeof cmd); 335 cmd.c_opcode = MMC_SEND_CSD; 336 cmd.c_arg = MMC_ARG_RCA(sf->rca); 337 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R2; 338 339 if (sdmmc_mmc_command(sc, &cmd) != 0) { 340 SET(sf->flags, SFF_ERROR); 341 continue; 342 } 343 344 if (sdmmc_decode_csd(sc, cmd.c_resp, sf) != 0 || 345 sdmmc_decode_cid(sc, sf->raw_cid, sf) != 0) { 346 SET(sf->flags, SFF_ERROR); 347 continue; 348 } 349 350 #ifdef SDMMC_DEBUG 351 printf("%s: CID: ", DEVNAME(sc)); 352 sdmmc_print_cid(&sf->cid); 353 #endif 354 } 355 } 356 357 int 358 sdmmc_decode_csd(struct sdmmc_softc *sc, sdmmc_response resp, 359 struct sdmmc_function *sf) 360 { 361 struct sdmmc_csd *csd = &sf->csd; 362 363 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 364 /* 365 * CSD version 1.0 corresponds to SD system 366 * specification version 1.0 - 1.10. (SanDisk, 3.5.3) 367 */ 368 csd->csdver = SD_CSD_CSDVER(resp); 369 switch (csd->csdver) { 370 case SD_CSD_CSDVER_2_0: 371 sf->flags |= SFF_SDHC; 372 csd->capacity = SD_CSD_V2_CAPACITY(resp); 373 csd->read_bl_len = SD_CSD_V2_BL_LEN; 374 break; 375 case SD_CSD_CSDVER_1_0: 376 csd->capacity = SD_CSD_CAPACITY(resp); 377 csd->read_bl_len = SD_CSD_READ_BL_LEN(resp); 378 break; 379 default: 380 printf("%s: unknown SD CSD structure version 0x%x\n", 381 DEVNAME(sc), csd->csdver); 382 return 1; 383 break; 384 } 385 csd->ccc = SD_CSD_CCC(resp); 386 } else { 387 csd->csdver = MMC_CSD_CSDVER(resp); 388 if (csd->csdver == MMC_CSD_CSDVER_1_0 || 389 csd->csdver == MMC_CSD_CSDVER_2_0 || 390 csd->csdver == MMC_CSD_CSDVER_EXT_CSD) { 391 csd->mmcver = MMC_CSD_MMCVER(resp); 392 csd->capacity = MMC_CSD_CAPACITY(resp); 393 csd->read_bl_len = MMC_CSD_READ_BL_LEN(resp); 394 } else { 395 printf("%s: unknown MMC CSD structure version 0x%x\n", 396 DEVNAME(sc), csd->csdver); 397 return 1; 398 } 399 } 400 csd->sector_size = MIN(1 << csd->read_bl_len, 401 sdmmc_chip_host_maxblklen(sc->sct, sc->sch)); 402 if (csd->sector_size < (1<<csd->read_bl_len)) 403 csd->capacity *= (1<<csd->read_bl_len) / 404 csd->sector_size; 405 406 return 0; 407 } 408 409 int 410 sdmmc_decode_cid(struct sdmmc_softc *sc, sdmmc_response resp, 411 struct sdmmc_function *sf) 412 { 413 struct sdmmc_cid *cid = &sf->cid; 414 415 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 416 cid->mid = SD_CID_MID(resp); 417 cid->oid = SD_CID_OID(resp); 418 SD_CID_PNM_CPY(resp, cid->pnm); 419 cid->rev = SD_CID_REV(resp); 420 cid->psn = SD_CID_PSN(resp); 421 cid->mdt = SD_CID_MDT(resp); 422 } else { 423 switch(sf->csd.mmcver) { 424 case MMC_CSD_MMCVER_1_0: 425 case MMC_CSD_MMCVER_1_4: 426 cid->mid = MMC_CID_MID_V1(resp); 427 MMC_CID_PNM_V1_CPY(resp, cid->pnm); 428 cid->rev = MMC_CID_REV_V1(resp); 429 cid->psn = MMC_CID_PSN_V1(resp); 430 cid->mdt = MMC_CID_MDT_V1(resp); 431 break; 432 case MMC_CSD_MMCVER_2_0: 433 case MMC_CSD_MMCVER_3_1: 434 case MMC_CSD_MMCVER_4_0: 435 cid->mid = MMC_CID_MID_V2(resp); 436 cid->oid = MMC_CID_OID_V2(resp); 437 MMC_CID_PNM_V2_CPY(resp, cid->pnm); 438 cid->psn = MMC_CID_PSN_V2(resp); 439 break; 440 default: 441 printf("%s: unknown MMC version %d\n", 442 DEVNAME(sc), sf->csd.mmcver); 443 return 1; 444 } 445 } 446 return 0; 447 } 448 449 #ifdef SDMMC_DEBUG 450 void 451 sdmmc_print_cid(struct sdmmc_cid *cid) 452 { 453 printf("mid=0x%02x oid=0x%04x pnm=\"%s\" rev=0x%02x psn=0x%08x" 454 " mdt=%03x\n", cid->mid, cid->oid, cid->pnm, cid->rev, cid->psn, 455 cid->mdt); 456 } 457 #endif 458 459 int 460 sdmmc_mem_send_scr(struct sdmmc_softc *sc, uint32_t *scr) 461 { 462 struct sdmmc_command cmd; 463 void *ptr = NULL; 464 int datalen = 8; 465 int error = 0; 466 467 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 468 if (ptr == NULL) 469 goto out; 470 471 memset(&cmd, 0, sizeof(cmd)); 472 cmd.c_data = ptr; 473 cmd.c_datalen = datalen; 474 cmd.c_blklen = datalen; 475 cmd.c_arg = 0; 476 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1; 477 cmd.c_opcode = SD_APP_SEND_SCR; 478 479 error = sdmmc_app_command(sc, &cmd); 480 if (error == 0) 481 memcpy(scr, ptr, datalen); 482 483 out: 484 if (ptr != NULL) 485 free(ptr, M_DEVBUF, datalen); 486 487 return error; 488 } 489 490 int 491 sdmmc_mem_decode_scr(struct sdmmc_softc *sc, uint32_t *raw_scr, 492 struct sdmmc_function *sf) 493 { 494 sdmmc_response resp; 495 int ver; 496 497 memset(resp, 0, sizeof(resp)); 498 /* 499 * Change the raw SCR to a response. 500 */ 501 resp[0] = be32toh(raw_scr[1]) >> 8; // LSW 502 resp[1] = be32toh(raw_scr[0]); // MSW 503 resp[0] |= (resp[1] & 0xff) << 24; 504 resp[1] >>= 8; 505 506 ver = SCR_STRUCTURE(resp); 507 sf->scr.sd_spec = SCR_SD_SPEC(resp); 508 sf->scr.bus_width = SCR_SD_BUS_WIDTHS(resp); 509 510 DPRINTF(("%s: %s: %08x%08x ver=%d, spec=%d, bus width=%d\n", 511 DEVNAME(sc), __func__, resp[1], resp[0], 512 ver, sf->scr.sd_spec, sf->scr.bus_width)); 513 514 if (ver != 0) { 515 DPRINTF(("%s: unknown SCR structure version: %d\n", 516 DEVNAME(sc), ver)); 517 return EINVAL; 518 } 519 return 0; 520 } 521 522 int 523 sdmmc_mem_send_cxd_data(struct sdmmc_softc *sc, int opcode, void *data, 524 size_t datalen) 525 { 526 struct sdmmc_command cmd; 527 void *ptr = NULL; 528 int error = 0; 529 530 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 531 if (ptr == NULL) { 532 error = ENOMEM; 533 goto out; 534 } 535 536 memset(&cmd, 0, sizeof(cmd)); 537 cmd.c_data = ptr; 538 cmd.c_datalen = datalen; 539 cmd.c_blklen = datalen; 540 cmd.c_opcode = opcode; 541 cmd.c_arg = 0; 542 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ; 543 if (opcode == MMC_SEND_EXT_CSD) 544 SET(cmd.c_flags, SCF_RSP_R1); 545 else 546 SET(cmd.c_flags, SCF_RSP_R2); 547 548 error = sdmmc_mmc_command(sc, &cmd); 549 if (error == 0) 550 memcpy(data, ptr, datalen); 551 552 out: 553 if (ptr != NULL) 554 free(ptr, M_DEVBUF, datalen); 555 556 return error; 557 } 558 559 int 560 sdmmc_mem_set_bus_width(struct sdmmc_function *sf, int width) 561 { 562 struct sdmmc_softc *sc = sf->sc; 563 struct sdmmc_command cmd; 564 int error; 565 566 memset(&cmd, 0, sizeof(cmd)); 567 cmd.c_opcode = SD_APP_SET_BUS_WIDTH; 568 cmd.c_flags = SCF_RSP_R1 | SCF_CMD_AC; 569 570 switch (width) { 571 case 1: 572 cmd.c_arg = SD_ARG_BUS_WIDTH_1; 573 break; 574 575 case 4: 576 cmd.c_arg = SD_ARG_BUS_WIDTH_4; 577 break; 578 579 default: 580 return EINVAL; 581 } 582 583 error = sdmmc_app_command(sc, &cmd); 584 if (error == 0) 585 error = sdmmc_chip_bus_width(sc->sct, sc->sch, width); 586 return error; 587 } 588 589 int 590 sdmmc_mem_sd_switch(struct sdmmc_function *sf, int mode, int group, 591 int function, sdmmc_bitfield512_t *status) 592 { 593 struct sdmmc_softc *sc = sf->sc; 594 struct sdmmc_command cmd; 595 void *ptr = NULL; 596 int gsft, error = 0; 597 const int statlen = 64; 598 599 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 600 !ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) 601 return EINVAL; 602 603 if (group <= 0 || group > 6 || 604 function < 0 || function > 15) 605 return EINVAL; 606 607 gsft = (group - 1) << 2; 608 609 ptr = malloc(statlen, M_DEVBUF, M_NOWAIT | M_ZERO); 610 if (ptr == NULL) 611 goto out; 612 613 memset(&cmd, 0, sizeof(cmd)); 614 cmd.c_data = ptr; 615 cmd.c_datalen = statlen; 616 cmd.c_blklen = statlen; 617 cmd.c_opcode = SD_SEND_SWITCH_FUNC; 618 cmd.c_arg = 619 (!!mode << 31) | (function << gsft) | (0x00ffffff & ~(0xf << gsft)); 620 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1; 621 622 error = sdmmc_mmc_command(sc, &cmd); 623 if (error == 0) 624 memcpy(status, ptr, statlen); 625 626 out: 627 if (ptr != NULL) 628 free(ptr, M_DEVBUF, statlen); 629 630 if (error == 0) 631 sdmmc_be512_to_bitfield512(status); 632 633 return error; 634 } 635 636 int 637 sdmmc_mem_mmc_switch(struct sdmmc_function *sf, uint8_t set, uint8_t index, 638 uint8_t value) 639 { 640 struct sdmmc_softc *sc = sf->sc; 641 struct sdmmc_command cmd; 642 643 memset(&cmd, 0, sizeof(cmd)); 644 cmd.c_opcode = MMC_SWITCH; 645 cmd.c_arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 646 (index << 16) | (value << 8) | set; 647 cmd.c_flags = SCF_RSP_R1B | SCF_CMD_AC; 648 649 return sdmmc_mmc_command(sc, &cmd); 650 } 651 652 /* 653 * Initialize a SD/MMC memory card. 654 */ 655 int 656 sdmmc_mem_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 657 { 658 int error = 0; 659 660 rw_assert_wrlock(&sc->sc_lock); 661 662 if (sdmmc_select_card(sc, sf) != 0 || 663 sdmmc_mem_set_blocklen(sc, sf) != 0) 664 error = 1; 665 666 if (ISSET(sc->sc_flags, SMF_SD_MODE)) 667 error = sdmmc_mem_sd_init(sc, sf); 668 else 669 error = sdmmc_mem_mmc_init(sc, sf); 670 671 return error; 672 } 673 674 /* make 512-bit BE quantity __bitfield()-compatible */ 675 void 676 sdmmc_be512_to_bitfield512(sdmmc_bitfield512_t *buf) { 677 size_t i; 678 uint32_t tmp0, tmp1; 679 const size_t bitswords = nitems(buf->_bits); 680 for (i = 0; i < bitswords/2; i++) { 681 tmp0 = buf->_bits[i]; 682 tmp1 = buf->_bits[bitswords - 1 - i]; 683 buf->_bits[i] = be32toh(tmp1); 684 buf->_bits[bitswords - 1 - i] = be32toh(tmp0); 685 } 686 } 687 688 int 689 sdmmc_mem_select_transfer_mode(struct sdmmc_softc *sc, int support_func) 690 { 691 if (ISSET(sc->sc_flags, SMF_UHS_MODE)) { 692 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR104) && 693 ISSET(support_func, 1 << SD_ACCESS_MODE_SDR104)) { 694 return SD_ACCESS_MODE_SDR104; 695 } 696 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_DDR50) && 697 ISSET(support_func, 1 << SD_ACCESS_MODE_DDR50)) { 698 return SD_ACCESS_MODE_DDR50; 699 } 700 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR50) && 701 ISSET(support_func, 1 << SD_ACCESS_MODE_SDR50)) { 702 return SD_ACCESS_MODE_SDR50; 703 } 704 } 705 if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) && 706 ISSET(support_func, 1 << SD_ACCESS_MODE_SDR25)) { 707 return SD_ACCESS_MODE_SDR25; 708 } 709 return SD_ACCESS_MODE_SDR12; 710 } 711 712 int 713 sdmmc_mem_execute_tuning(struct sdmmc_softc *sc, struct sdmmc_function *sf) 714 { 715 int timing = -1; 716 717 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 718 if (!ISSET(sc->sc_flags, SMF_UHS_MODE)) 719 return 0; 720 721 switch (sf->csd.tran_speed) { 722 case 100000: 723 timing = SDMMC_TIMING_UHS_SDR50; 724 break; 725 case 208000: 726 timing = SDMMC_TIMING_UHS_SDR104; 727 break; 728 default: 729 return 0; 730 } 731 } else { 732 switch (sf->csd.tran_speed) { 733 case 200000: 734 timing = SDMMC_TIMING_MMC_HS200; 735 break; 736 default: 737 return 0; 738 } 739 } 740 741 DPRINTF(("%s: execute tuning for timing %d\n", SDMMCDEVNAME(sc), 742 timing)); 743 744 return sdmmc_chip_execute_tuning(sc->sct, sc->sch, timing); 745 } 746 747 int 748 sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 749 { 750 int support_func, best_func, error, i; 751 sdmmc_bitfield512_t status; /* Switch Function Status */ 752 uint32_t raw_scr[2]; 753 754 /* 755 * All SD cards are supposed to support Default Speed mode 756 * with frequencies up to 25 MHz. Bump up the clock frequency 757 * now as data transfers don't seem to work on the Realtek 758 * RTS5229 host controller if it is running at a low clock 759 * frequency. Reading the SCR requires a data transfer. 760 */ 761 error = sdmmc_chip_bus_clock(sc->sct, sc->sch, SDMMC_SDCLK_25MHZ, 762 SDMMC_TIMING_LEGACY); 763 if (error) { 764 printf("%s: can't change bus clock\n", DEVNAME(sc)); 765 return error; 766 } 767 768 error = sdmmc_mem_send_scr(sc, raw_scr); 769 if (error) { 770 printf("%s: SD_SEND_SCR send failed\n", DEVNAME(sc)); 771 return error; 772 } 773 error = sdmmc_mem_decode_scr(sc, raw_scr, sf); 774 if (error) 775 return error; 776 777 if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) && 778 ISSET(sf->scr.bus_width, SCR_SD_BUS_WIDTHS_4BIT)) { 779 DPRINTF(("%s: change bus width\n", DEVNAME(sc))); 780 error = sdmmc_mem_set_bus_width(sf, 4); 781 if (error) { 782 printf("%s: can't change bus width\n", DEVNAME(sc)); 783 return error; 784 } 785 } 786 787 best_func = 0; 788 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 789 ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) { 790 DPRINTF(("%s: switch func mode 0\n", DEVNAME(sc))); 791 error = sdmmc_mem_sd_switch(sf, 0, 1, 0, &status); 792 if (error) { 793 printf("%s: switch func mode 0 failed\n", DEVNAME(sc)); 794 return error; 795 } 796 797 support_func = SFUNC_STATUS_GROUP(&status, 1); 798 799 if (!ISSET(sc->sc_flags, SMF_UHS_MODE) && 800 (ISSET(support_func, 1 << SD_ACCESS_MODE_SDR50) || 801 ISSET(support_func, 1 << SD_ACCESS_MODE_DDR50) || 802 ISSET(support_func, 1 << SD_ACCESS_MODE_SDR104))) { 803 /* XXX UHS-I card started in 1.8V mode, switch now */ 804 error = sdmmc_mem_signal_voltage(sc, 805 SDMMC_SIGNAL_VOLTAGE_180); 806 if (error) { 807 printf("%s: failed to recover UHS card\n", DEVNAME(sc)); 808 return error; 809 } 810 SET(sc->sc_flags, SMF_UHS_MODE); 811 } 812 813 for (i = 0; i < nitems(switch_group0_functions); i++) { 814 if (!(support_func & (1 << i))) 815 continue; 816 DPRINTF(("%s: card supports mode %s\n", 817 SDMMCDEVNAME(sc), 818 switch_group0_functions[i].name)); 819 } 820 821 best_func = sdmmc_mem_select_transfer_mode(sc, support_func); 822 823 DPRINTF(("%s: using mode %s\n", SDMMCDEVNAME(sc), 824 switch_group0_functions[best_func].name)); 825 } 826 827 if (best_func != 0) { 828 DPRINTF(("%s: switch func mode 1(func=%d)\n", 829 DEVNAME(sc), best_func)); 830 error = 831 sdmmc_mem_sd_switch(sf, 1, 1, best_func, &status); 832 if (error) { 833 printf("%s: switch func mode 1 failed:" 834 " group 1 function %d(0x%2x)\n", 835 DEVNAME(sc), best_func, support_func); 836 return error; 837 } 838 sf->csd.tran_speed = 839 switch_group0_functions[best_func].freq; 840 841 /* Wait 400KHz x 8 clock (2.5us * 8 + slop) */ 842 delay(25); 843 844 /* change bus clock */ 845 error = sdmmc_chip_bus_clock(sc->sct, sc->sch, 846 sf->csd.tran_speed, SDMMC_TIMING_HIGHSPEED); 847 if (error) { 848 printf("%s: can't change bus clock\n", DEVNAME(sc)); 849 return error; 850 } 851 852 /* execute tuning (UHS) */ 853 error = sdmmc_mem_execute_tuning(sc, sf); 854 if (error) { 855 printf("%s: can't execute SD tuning\n", DEVNAME(sc)); 856 return error; 857 } 858 } 859 860 return 0; 861 } 862 863 int 864 sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 865 { 866 int width, value; 867 int card_type; 868 int error = 0; 869 u_int8_t ext_csd[512]; 870 int speed = 20000; 871 int timing = SDMMC_TIMING_LEGACY; 872 u_int32_t sectors = 0; 873 874 error = sdmmc_chip_bus_clock(sc->sct, sc->sch, speed, timing); 875 if (error) { 876 printf("%s: can't change bus clock\n", DEVNAME(sc)); 877 return error; 878 } 879 880 if (sf->csd.mmcver >= MMC_CSD_MMCVER_4_0) { 881 /* read EXT_CSD */ 882 error = sdmmc_mem_send_cxd_data(sc, 883 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 884 if (error != 0) { 885 SET(sf->flags, SFF_ERROR); 886 printf("%s: can't read EXT_CSD\n", DEVNAME(sc)); 887 return error; 888 } 889 890 card_type = ext_csd[EXT_CSD_CARD_TYPE]; 891 892 if (card_type & EXT_CSD_CARD_TYPE_F_HS200_1_8V && 893 ISSET(sc->sc_caps, SMC_CAPS_MMC_HS200)) { 894 speed = 200000; 895 timing = SDMMC_TIMING_MMC_HS200; 896 } else if (card_type & EXT_CSD_CARD_TYPE_F_DDR52_1_8V && 897 ISSET(sc->sc_caps, SMC_CAPS_MMC_DDR52)) { 898 speed = 52000; 899 timing = SDMMC_TIMING_MMC_DDR52; 900 } else if (card_type & EXT_CSD_CARD_TYPE_F_52M && 901 ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) { 902 speed = 52000; 903 timing = SDMMC_TIMING_HIGHSPEED; 904 } else if (card_type & EXT_CSD_CARD_TYPE_F_26M) { 905 speed = 26000; 906 } else { 907 printf("%s: unknown CARD_TYPE 0x%x\n", DEVNAME(sc), 908 ext_csd[EXT_CSD_CARD_TYPE]); 909 } 910 911 if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) { 912 width = 8; 913 value = EXT_CSD_BUS_WIDTH_8; 914 } else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) { 915 width = 4; 916 value = EXT_CSD_BUS_WIDTH_4; 917 } else { 918 width = 1; 919 value = EXT_CSD_BUS_WIDTH_1; 920 } 921 922 if (width != 1) { 923 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 924 EXT_CSD_BUS_WIDTH, value); 925 if (error == 0) 926 error = sdmmc_chip_bus_width(sc->sct, 927 sc->sch, width); 928 else { 929 DPRINTF(("%s: can't change bus width" 930 " (%d bit)\n", DEVNAME(sc), width)); 931 return error; 932 } 933 934 /* XXXX: need bus test? (using by CMD14 & CMD19) */ 935 sdmmc_delay(10000); 936 } 937 938 if (timing != SDMMC_TIMING_LEGACY) { 939 switch (timing) { 940 case SDMMC_TIMING_MMC_HS200: 941 value = EXT_CSD_HS_TIMING_HS200; 942 break; 943 case SDMMC_TIMING_MMC_DDR52: 944 case SDMMC_TIMING_HIGHSPEED: 945 value = EXT_CSD_HS_TIMING_HS; 946 break; 947 } 948 949 /* switch to high speed timing */ 950 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 951 EXT_CSD_HS_TIMING, value); 952 if (error != 0) { 953 printf("%s: can't change timing\n", 954 DEVNAME(sc)); 955 return error; 956 } 957 958 sdmmc_delay(10000); 959 } 960 961 KASSERT(timing < nitems(sdmmc_mmc_timings)); 962 sf->csd.tran_speed = sdmmc_mmc_timings[timing]; 963 964 if (timing != SDMMC_TIMING_LEGACY) { 965 /* read EXT_CSD again */ 966 error = sdmmc_mem_send_cxd_data(sc, 967 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 968 if (error != 0) { 969 printf("%s: can't re-read EXT_CSD\n", DEVNAME(sc)); 970 return error; 971 } 972 if (ext_csd[EXT_CSD_HS_TIMING] != value) { 973 printf("%s, HS_TIMING set failed\n", DEVNAME(sc)); 974 return EINVAL; 975 } 976 } 977 978 error = sdmmc_chip_bus_clock(sc->sct, sc->sch, speed, SDMMC_TIMING_HIGHSPEED); 979 if (error != 0) { 980 printf("%s: can't change bus clock\n", DEVNAME(sc)); 981 return error; 982 } 983 984 if (timing == SDMMC_TIMING_MMC_DDR52) { 985 switch (width) { 986 case 4: 987 value = EXT_CSD_BUS_WIDTH_4_DDR; 988 break; 989 case 8: 990 value = EXT_CSD_BUS_WIDTH_8_DDR; 991 break; 992 } 993 994 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 995 EXT_CSD_BUS_WIDTH, value); 996 if (error) { 997 printf("%s: can't switch to DDR\n", 998 DEVNAME(sc)); 999 return error; 1000 } 1001 1002 sdmmc_delay(10000); 1003 1004 error = sdmmc_chip_signal_voltage(sc->sct, sc->sch, 1005 SDMMC_SIGNAL_VOLTAGE_180); 1006 if (error) { 1007 printf("%s: can't switch signalling voltage\n", 1008 DEVNAME(sc)); 1009 return error; 1010 } 1011 1012 error = sdmmc_chip_bus_clock(sc->sct, sc->sch, speed, timing); 1013 if (error != 0) { 1014 printf("%s: can't change bus clock\n", DEVNAME(sc)); 1015 return error; 1016 } 1017 1018 sdmmc_delay(10000); 1019 } 1020 1021 sectors = ext_csd[EXT_CSD_SEC_COUNT + 0] << 0 | 1022 ext_csd[EXT_CSD_SEC_COUNT + 1] << 8 | 1023 ext_csd[EXT_CSD_SEC_COUNT + 2] << 16 | 1024 ext_csd[EXT_CSD_SEC_COUNT + 3] << 24; 1025 1026 if (sectors > (2u * 1024 * 1024 * 1024) / 512) { 1027 sf->flags |= SFF_SDHC; 1028 sf->csd.capacity = sectors; 1029 } 1030 1031 if (timing == SDMMC_TIMING_MMC_HS200) { 1032 /* execute tuning (HS200) */ 1033 error = sdmmc_mem_execute_tuning(sc, sf); 1034 if (error) { 1035 printf("%s: can't execute MMC tuning\n", DEVNAME(sc)); 1036 return error; 1037 } 1038 } 1039 } 1040 1041 return error; 1042 } 1043 1044 /* 1045 * Get or set the card's memory OCR value (SD or MMC). 1046 */ 1047 int 1048 sdmmc_mem_send_op_cond(struct sdmmc_softc *sc, u_int32_t ocr, 1049 u_int32_t *ocrp) 1050 { 1051 struct sdmmc_command cmd; 1052 int error; 1053 int i; 1054 1055 rw_assert_wrlock(&sc->sc_lock); 1056 1057 /* 1058 * If we change the OCR value, retry the command until the OCR 1059 * we receive in response has the "CARD BUSY" bit set, meaning 1060 * that all cards are ready for identification. 1061 */ 1062 for (i = 0; i < 100; i++) { 1063 bzero(&cmd, sizeof cmd); 1064 cmd.c_arg = ocr; 1065 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R3; 1066 1067 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 1068 cmd.c_opcode = SD_APP_OP_COND; 1069 error = sdmmc_app_command(sc, &cmd); 1070 } else { 1071 cmd.c_arg &= ~MMC_OCR_ACCESS_MODE_MASK; 1072 cmd.c_arg |= MMC_OCR_ACCESS_MODE_SECTOR; 1073 cmd.c_opcode = MMC_SEND_OP_COND; 1074 error = sdmmc_mmc_command(sc, &cmd); 1075 } 1076 if (error != 0) 1077 break; 1078 if (ISSET(MMC_R3(cmd.c_resp), MMC_OCR_MEM_READY) || 1079 ocr == 0) 1080 break; 1081 error = ETIMEDOUT; 1082 sdmmc_delay(10000); 1083 } 1084 if (error == 0 && ocrp != NULL) 1085 *ocrp = MMC_R3(cmd.c_resp); 1086 1087 return error; 1088 } 1089 1090 /* 1091 * Set the read block length appropriately for this card, according to 1092 * the card CSD register value. 1093 */ 1094 int 1095 sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf) 1096 { 1097 struct sdmmc_command cmd; 1098 1099 rw_assert_wrlock(&sc->sc_lock); 1100 1101 bzero(&cmd, sizeof cmd); 1102 cmd.c_opcode = MMC_SET_BLOCKLEN; 1103 cmd.c_arg = sf->csd.sector_size; 1104 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 1105 DPRINTF(("%s: read_bl_len=%d sector_size=%d\n", DEVNAME(sc), 1106 1 << sf->csd.read_bl_len, sf->csd.sector_size)); 1107 1108 return sdmmc_mmc_command(sc, &cmd); 1109 } 1110 1111 int 1112 sdmmc_mem_read_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1113 int blkno, u_char *data, size_t datalen) 1114 { 1115 struct sdmmc_softc *sc = sf->sc; 1116 struct sdmmc_command cmd; 1117 int error; 1118 1119 1120 if ((error = sdmmc_select_card(sc, sf)) != 0) 1121 goto err; 1122 1123 bzero(&cmd, sizeof cmd); 1124 cmd.c_data = data; 1125 cmd.c_datalen = datalen; 1126 cmd.c_blklen = sf->csd.sector_size; 1127 cmd.c_opcode = (datalen / cmd.c_blklen) > 1 ? 1128 MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 1129 if (sf->flags & SFF_SDHC) 1130 cmd.c_arg = blkno; 1131 else 1132 cmd.c_arg = blkno << 9; 1133 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1; 1134 cmd.c_dmamap = dmap; 1135 1136 error = sdmmc_mmc_command(sc, &cmd); 1137 if (error != 0) 1138 goto err; 1139 1140 if (ISSET(sc->sc_flags, SMF_STOP_AFTER_MULTIPLE) && 1141 cmd.c_opcode == MMC_READ_BLOCK_MULTIPLE) { 1142 bzero(&cmd, sizeof cmd); 1143 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1144 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1145 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B; 1146 error = sdmmc_mmc_command(sc, &cmd); 1147 if (error != 0) 1148 goto err; 1149 } 1150 1151 do { 1152 bzero(&cmd, sizeof cmd); 1153 cmd.c_opcode = MMC_SEND_STATUS; 1154 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1155 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 1156 error = sdmmc_mmc_command(sc, &cmd); 1157 if (error != 0) 1158 break; 1159 /* XXX time out */ 1160 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1161 1162 err: 1163 return (error); 1164 } 1165 1166 int 1167 sdmmc_mem_single_read_block(struct sdmmc_function *sf, int blkno, u_char *data, 1168 size_t datalen) 1169 { 1170 int error = 0; 1171 int i; 1172 1173 for (i = 0; i < datalen / sf->csd.sector_size; i++) { 1174 error = sdmmc_mem_read_block_subr(sf, NULL, blkno + i, 1175 data + i * sf->csd.sector_size, sf->csd.sector_size); 1176 if (error) 1177 break; 1178 } 1179 1180 return (error); 1181 } 1182 1183 int 1184 sdmmc_mem_read_block(struct sdmmc_function *sf, int blkno, u_char *data, 1185 size_t datalen) 1186 { 1187 struct sdmmc_softc *sc = sf->sc; 1188 int error; 1189 1190 rw_enter_write(&sc->sc_lock); 1191 1192 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1193 error = sdmmc_mem_single_read_block(sf, blkno, data, datalen); 1194 goto out; 1195 } 1196 1197 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1198 error = sdmmc_mem_read_block_subr(sf, NULL, blkno, 1199 data, datalen); 1200 goto out; 1201 } 1202 1203 /* DMA transfer */ 1204 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, 1205 NULL, BUS_DMA_NOWAIT|BUS_DMA_READ); 1206 if (error) 1207 goto out; 1208 1209 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1210 BUS_DMASYNC_PREREAD); 1211 1212 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1213 datalen); 1214 if (error) 1215 goto unload; 1216 1217 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1218 BUS_DMASYNC_POSTREAD); 1219 unload: 1220 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1221 1222 out: 1223 rw_exit(&sc->sc_lock); 1224 return (error); 1225 } 1226 1227 int 1228 sdmmc_mem_write_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1229 int blkno, u_char *data, size_t datalen) 1230 { 1231 struct sdmmc_softc *sc = sf->sc; 1232 struct sdmmc_command cmd; 1233 int error; 1234 1235 if ((error = sdmmc_select_card(sc, sf)) != 0) 1236 goto err; 1237 1238 bzero(&cmd, sizeof cmd); 1239 cmd.c_data = data; 1240 cmd.c_datalen = datalen; 1241 cmd.c_blklen = sf->csd.sector_size; 1242 cmd.c_opcode = (datalen / cmd.c_blklen) > 1 ? 1243 MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 1244 if (sf->flags & SFF_SDHC) 1245 cmd.c_arg = blkno; 1246 else 1247 cmd.c_arg = blkno << 9; 1248 cmd.c_flags = SCF_CMD_ADTC | SCF_RSP_R1; 1249 cmd.c_dmamap = dmap; 1250 1251 error = sdmmc_mmc_command(sc, &cmd); 1252 if (error != 0) 1253 goto err; 1254 1255 if (ISSET(sc->sc_flags, SMF_STOP_AFTER_MULTIPLE) && 1256 cmd.c_opcode == MMC_WRITE_BLOCK_MULTIPLE) { 1257 bzero(&cmd, sizeof cmd); 1258 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1259 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B; 1260 error = sdmmc_mmc_command(sc, &cmd); 1261 if (error != 0) 1262 goto err; 1263 } 1264 1265 do { 1266 bzero(&cmd, sizeof cmd); 1267 cmd.c_opcode = MMC_SEND_STATUS; 1268 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1269 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 1270 error = sdmmc_mmc_command(sc, &cmd); 1271 if (error != 0) 1272 break; 1273 /* XXX time out */ 1274 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1275 1276 err: 1277 return (error); 1278 } 1279 1280 int 1281 sdmmc_mem_single_write_block(struct sdmmc_function *sf, int blkno, u_char *data, 1282 size_t datalen) 1283 { 1284 int error = 0; 1285 int i; 1286 1287 for (i = 0; i < datalen / sf->csd.sector_size; i++) { 1288 error = sdmmc_mem_write_block_subr(sf, NULL, blkno + i, 1289 data + i * sf->csd.sector_size, sf->csd.sector_size); 1290 if (error) 1291 break; 1292 } 1293 1294 return (error); 1295 } 1296 1297 int 1298 sdmmc_mem_write_block(struct sdmmc_function *sf, int blkno, u_char *data, 1299 size_t datalen) 1300 { 1301 struct sdmmc_softc *sc = sf->sc; 1302 int error; 1303 1304 rw_enter_write(&sc->sc_lock); 1305 1306 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1307 error = sdmmc_mem_single_write_block(sf, blkno, data, datalen); 1308 goto out; 1309 } 1310 1311 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1312 error = sdmmc_mem_write_block_subr(sf, NULL, blkno, 1313 data, datalen); 1314 goto out; 1315 } 1316 1317 /* DMA transfer */ 1318 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, 1319 NULL, BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1320 if (error) 1321 goto out; 1322 1323 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1324 BUS_DMASYNC_PREWRITE); 1325 1326 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1327 datalen); 1328 if (error) 1329 goto unload; 1330 1331 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1332 BUS_DMASYNC_POSTWRITE); 1333 unload: 1334 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1335 1336 out: 1337 rw_exit(&sc->sc_lock); 1338 return (error); 1339 } 1340 1341 #ifdef HIBERNATE 1342 int 1343 sdmmc_mem_hibernate_write(struct sdmmc_function *sf, daddr_t blkno, 1344 u_char *data, size_t datalen) 1345 { 1346 struct sdmmc_softc *sc = sf->sc; 1347 int i, error; 1348 struct bus_dmamap dmamap; 1349 paddr_t phys_addr; 1350 1351 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1352 for (i = 0; i < datalen / sf->csd.sector_size; i++) { 1353 error = sdmmc_mem_write_block_subr(sf, NULL, blkno + i, 1354 data + i * sf->csd.sector_size, 1355 sf->csd.sector_size); 1356 if (error) 1357 return (error); 1358 } 1359 } else if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1360 return (sdmmc_mem_write_block_subr(sf, NULL, blkno, data, 1361 datalen)); 1362 } 1363 1364 /* pretend we're bus_dmamap_load */ 1365 bzero(&dmamap, sizeof(dmamap)); 1366 pmap_extract(pmap_kernel(), (vaddr_t)data, &phys_addr); 1367 dmamap.dm_mapsize = datalen; 1368 dmamap.dm_nsegs = 1; 1369 dmamap.dm_segs[0].ds_addr = phys_addr; 1370 dmamap.dm_segs[0].ds_len = datalen; 1371 return (sdmmc_mem_write_block_subr(sf, &dmamap, blkno, data, datalen)); 1372 } 1373 #endif 1374