1 /* $OpenBSD: qe.c,v 1.25 2013/11/26 09:50:33 mpi Exp $ */ 2 /* $NetBSD: qe.c,v 1.16 2001/03/30 17:30:18 christos Exp $ */ 3 4 /*- 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1998 Jason L. Wright. 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 */ 57 58 /* 59 * Driver for the SBus qec+qe QuadEthernet board. 60 * 61 * This driver was written using the AMD MACE Am79C940 documentation, some 62 * ideas gleaned from the S/Linux driver for this card, Solaris header files, 63 * and a loan of a card from Paul Southworth of the Internet Engineering 64 * Group (www.ieng.com). 65 */ 66 67 #define QEDEBUG 68 69 #include "bpfilter.h" 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/kernel.h> 74 #include <sys/errno.h> 75 #include <sys/ioctl.h> 76 #include <sys/mbuf.h> 77 #include <sys/socket.h> 78 #include <sys/syslog.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 82 #include <net/if.h> 83 #include <net/if_dl.h> 84 #include <net/if_types.h> 85 #include <net/netisr.h> 86 #include <net/if_media.h> 87 88 #ifdef INET 89 #include <netinet/in.h> 90 #include <netinet/in_systm.h> 91 #include <netinet/ip.h> 92 #include <netinet/if_ether.h> 93 #endif 94 95 #if NBPFILTER > 0 96 #include <net/bpf.h> 97 #endif 98 99 #include <machine/bus.h> 100 #include <machine/intr.h> 101 #include <machine/autoconf.h> 102 103 #include <dev/sbus/sbusvar.h> 104 #include <dev/sbus/qecreg.h> 105 #include <dev/sbus/qecvar.h> 106 #include <dev/sbus/qereg.h> 107 108 struct qe_softc { 109 struct device sc_dev; /* base device */ 110 bus_space_tag_t sc_bustag; /* bus & dma tags */ 111 bus_dma_tag_t sc_dmatag; 112 bus_dmamap_t sc_dmamap; 113 struct arpcom sc_arpcom; 114 struct ifmedia sc_ifmedia; /* interface media */ 115 116 struct qec_softc *sc_qec; /* QEC parent */ 117 118 bus_space_handle_t sc_qr; /* QEC registers */ 119 bus_space_handle_t sc_mr; /* MACE registers */ 120 bus_space_handle_t sc_cr; /* channel registers */ 121 122 int sc_channel; /* channel number */ 123 u_int sc_rev; /* board revision */ 124 125 int sc_burst; 126 127 struct qec_ring sc_rb; /* Packet Ring Buffer */ 128 129 #ifdef QEDEBUG 130 int sc_debug; 131 #endif 132 }; 133 134 int qematch(struct device *, void *, void *); 135 void qeattach(struct device *, struct device *, void *); 136 137 void qeinit(struct qe_softc *); 138 void qestart(struct ifnet *); 139 void qestop(struct qe_softc *); 140 void qewatchdog(struct ifnet *); 141 int qeioctl(struct ifnet *, u_long, caddr_t); 142 void qereset(struct qe_softc *); 143 144 int qeintr(void *); 145 int qe_eint(struct qe_softc *, u_int32_t); 146 int qe_rint(struct qe_softc *); 147 int qe_tint(struct qe_softc *); 148 void qe_mcreset(struct qe_softc *); 149 150 int qe_put(struct qe_softc *, int, struct mbuf *); 151 void qe_read(struct qe_softc *, int, int); 152 struct mbuf *qe_get(struct qe_softc *, int, int); 153 154 /* ifmedia callbacks */ 155 void qe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 156 int qe_ifmedia_upd(struct ifnet *); 157 158 struct cfattach qe_ca = { 159 sizeof(struct qe_softc), qematch, qeattach 160 }; 161 162 struct cfdriver qe_cd = { 163 NULL, "qe", DV_IFNET 164 }; 165 166 int 167 qematch(parent, vcf, aux) 168 struct device *parent; 169 void *vcf; 170 void *aux; 171 { 172 struct cfdata *cf = vcf; 173 struct sbus_attach_args *sa = aux; 174 175 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 176 } 177 178 void 179 qeattach(parent, self, aux) 180 struct device *parent, *self; 181 void *aux; 182 { 183 struct sbus_attach_args *sa = aux; 184 struct qec_softc *qec = (struct qec_softc *)parent; 185 struct qe_softc *sc = (struct qe_softc *)self; 186 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 187 int node = sa->sa_node; 188 bus_dma_tag_t dmatag = sa->sa_dmatag; 189 bus_dma_segment_t seg; 190 bus_size_t size; 191 int rseg, error; 192 extern void myetheraddr(u_char *); 193 194 /* Pass on the bus tags */ 195 sc->sc_bustag = sa->sa_bustag; 196 sc->sc_dmatag = sa->sa_dmatag; 197 198 if (sa->sa_nreg < 2) { 199 printf("%s: only %d register sets\n", 200 self->dv_xname, sa->sa_nreg); 201 return; 202 } 203 204 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, 205 (bus_addr_t)sa->sa_reg[0].sbr_offset, 206 (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0, &sc->sc_cr) != 0) { 207 printf("%s: cannot map registers\n", self->dv_xname); 208 return; 209 } 210 211 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot, 212 (bus_addr_t)sa->sa_reg[1].sbr_offset, 213 (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0, &sc->sc_mr) != 0) { 214 printf("%s: cannot map registers\n", self->dv_xname); 215 return; 216 } 217 218 sc->sc_rev = getpropint(node, "mace-version", -1); 219 printf(" rev %x", sc->sc_rev); 220 221 sc->sc_qec = qec; 222 sc->sc_qr = qec->sc_regs; 223 224 sc->sc_channel = getpropint(node, "channel#", -1); 225 sc->sc_burst = qec->sc_burst; 226 227 qestop(sc); 228 229 /* Note: no interrupt level passed */ 230 if (bus_intr_establish(sa->sa_bustag, 0, IPL_NET, 0, qeintr, sc, 231 self->dv_xname) == NULL) { 232 printf(": no interrupt established\n"); 233 return; 234 } 235 236 myetheraddr(sc->sc_arpcom.ac_enaddr); 237 238 /* 239 * Allocate descriptor ring and buffers. 240 */ 241 242 /* for now, allocate as many bufs as there are ring descriptors */ 243 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 244 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 245 246 size = 247 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 248 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 249 sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ + 250 sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ; 251 252 /* Get a DMA handle */ 253 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 254 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 255 printf("%s: DMA map create error %d\n", self->dv_xname, error); 256 return; 257 } 258 259 /* Allocate DMA buffer */ 260 if ((error = bus_dmamem_alloc(dmatag, size, 0, 0, 261 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 262 printf("%s: DMA buffer alloc error %d\n", 263 self->dv_xname, error); 264 return; 265 } 266 267 /* Map DMA buffer in CPU addressable space */ 268 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 269 &sc->sc_rb.rb_membase, 270 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 271 printf("%s: DMA buffer map error %d\n", 272 self->dv_xname, error); 273 bus_dmamem_free(dmatag, &seg, rseg); 274 return; 275 } 276 277 /* Load the buffer */ 278 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 279 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 280 printf("%s: DMA buffer map load error %d\n", 281 self->dv_xname, error); 282 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 283 bus_dmamem_free(dmatag, &seg, rseg); 284 return; 285 } 286 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 287 288 /* Initialize media properties */ 289 ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts); 290 ifmedia_add(&sc->sc_ifmedia, 291 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 0, NULL); 292 ifmedia_add(&sc->sc_ifmedia, 293 IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), 0, NULL); 294 ifmedia_add(&sc->sc_ifmedia, 295 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 0, NULL); 296 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 297 298 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 299 ifp->if_softc = sc; 300 ifp->if_start = qestart; 301 ifp->if_ioctl = qeioctl; 302 ifp->if_watchdog = qewatchdog; 303 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 304 IFF_MULTICAST; 305 IFQ_SET_READY(&ifp->if_snd); 306 307 /* Attach the interface. */ 308 if_attach(ifp); 309 ether_ifattach(ifp); 310 311 printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 312 } 313 314 /* 315 * Pull data off an interface. 316 * Len is the length of data, with local net header stripped. 317 * We copy the data into mbufs. When full cluster sized units are present, 318 * we copy into clusters. 319 */ 320 struct mbuf * 321 qe_get(sc, idx, totlen) 322 struct qe_softc *sc; 323 int idx, totlen; 324 { 325 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 326 struct mbuf *m; 327 struct mbuf *top, **mp; 328 int len, pad, boff = 0; 329 caddr_t bp; 330 331 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ; 332 333 MGETHDR(m, M_DONTWAIT, MT_DATA); 334 if (m == NULL) 335 return (NULL); 336 m->m_pkthdr.rcvif = ifp; 337 m->m_pkthdr.len = totlen; 338 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 339 m->m_data += pad; 340 len = MHLEN - pad; 341 top = NULL; 342 mp = ⊤ 343 344 while (totlen > 0) { 345 if (top) { 346 MGET(m, M_DONTWAIT, MT_DATA); 347 if (m == NULL) { 348 m_freem(top); 349 return (NULL); 350 } 351 len = MLEN; 352 } 353 if (top && totlen >= MINCLSIZE) { 354 MCLGET(m, M_DONTWAIT); 355 if (m->m_flags & M_EXT) 356 len = MCLBYTES; 357 } 358 m->m_len = len = min(totlen, len); 359 bcopy(bp + boff, mtod(m, caddr_t), len); 360 boff += len; 361 totlen -= len; 362 *mp = m; 363 mp = &m->m_next; 364 } 365 366 return (top); 367 } 368 369 /* 370 * Routine to copy from mbuf chain to transmit buffer in 371 * network buffer memory. 372 */ 373 __inline__ int 374 qe_put(sc, idx, m) 375 struct qe_softc *sc; 376 int idx; 377 struct mbuf *m; 378 { 379 struct mbuf *n; 380 int len, tlen = 0, boff = 0; 381 caddr_t bp; 382 383 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ; 384 385 for (; m; m = n) { 386 len = m->m_len; 387 if (len == 0) { 388 MFREE(m, n); 389 continue; 390 } 391 bcopy(mtod(m, caddr_t), bp+boff, len); 392 boff += len; 393 tlen += len; 394 MFREE(m, n); 395 } 396 return (tlen); 397 } 398 399 /* 400 * Pass a packet to the higher levels. 401 */ 402 __inline__ void 403 qe_read(sc, idx, len) 404 struct qe_softc *sc; 405 int idx, len; 406 { 407 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 408 struct mbuf *m; 409 410 if (len <= sizeof(struct ether_header) || 411 len > ETHERMTU + sizeof(struct ether_header)) { 412 413 printf("%s: invalid packet size %d; dropping\n", 414 ifp->if_xname, len); 415 416 ifp->if_ierrors++; 417 return; 418 } 419 420 /* 421 * Pull packet off interface. 422 */ 423 m = qe_get(sc, idx, len); 424 if (m == NULL) { 425 ifp->if_ierrors++; 426 return; 427 } 428 ifp->if_ipackets++; 429 430 #if NBPFILTER > 0 431 /* 432 * Check if there's a BPF listener on this interface. 433 * If so, hand off the raw packet to BPF. 434 */ 435 if (ifp->if_bpf) 436 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 437 #endif 438 /* Pass the packet up. */ 439 ether_input_mbuf(ifp, m); 440 } 441 442 /* 443 * Start output on interface. 444 * We make two assumptions here: 445 * 1) that the current priority is set to splnet _before_ this code 446 * is called *and* is returned to the appropriate priority after 447 * return 448 * 2) that the IFF_OACTIVE flag is checked before this code is called 449 * (i.e. that the output part of the interface is idle) 450 */ 451 void 452 qestart(ifp) 453 struct ifnet *ifp; 454 { 455 struct qe_softc *sc = (struct qe_softc *)ifp->if_softc; 456 struct qec_xd *txd = sc->sc_rb.rb_txd; 457 struct mbuf *m; 458 unsigned int bix, len; 459 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 460 461 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 462 return; 463 464 bix = sc->sc_rb.rb_tdhead; 465 466 for (;;) { 467 IFQ_POLL(&ifp->if_snd, m); 468 if (m == NULL) 469 break; 470 471 IFQ_DEQUEUE(&ifp->if_snd, m); 472 473 #if NBPFILTER > 0 474 /* 475 * If BPF is listening on this interface, let it see the 476 * packet before we commit it to the wire. 477 */ 478 if (ifp->if_bpf) 479 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 480 #endif 481 482 /* 483 * Copy the mbuf chain into the transmit buffer. 484 */ 485 len = qe_put(sc, bix, m); 486 487 /* 488 * Initialize transmit registers and start transmission 489 */ 490 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 491 (len & QEC_XD_LENGTH); 492 bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL, 493 QE_CR_CTRL_TWAKEUP); 494 495 if (++bix == QEC_XD_RING_MAXSIZE) 496 bix = 0; 497 498 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 499 ifp->if_flags |= IFF_OACTIVE; 500 break; 501 } 502 } 503 504 sc->sc_rb.rb_tdhead = bix; 505 } 506 507 void 508 qestop(sc) 509 struct qe_softc *sc; 510 { 511 bus_space_tag_t t = sc->sc_bustag; 512 bus_space_handle_t mr = sc->sc_mr; 513 bus_space_handle_t cr = sc->sc_cr; 514 int n; 515 516 /* Stop the schwurst */ 517 bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST); 518 for (n = 200; n > 0; n--) { 519 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) & 520 QE_MR_BIUCC_SWRST) == 0) 521 break; 522 DELAY(20); 523 } 524 525 /* then reset */ 526 bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET); 527 for (n = 200; n > 0; n--) { 528 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) & 529 QE_CR_CTRL_RESET) == 0) 530 break; 531 DELAY(20); 532 } 533 } 534 535 /* 536 * Reset interface. 537 */ 538 void 539 qereset(sc) 540 struct qe_softc *sc; 541 { 542 int s; 543 544 s = splnet(); 545 qestop(sc); 546 qeinit(sc); 547 splx(s); 548 } 549 550 void 551 qewatchdog(ifp) 552 struct ifnet *ifp; 553 { 554 struct qe_softc *sc = ifp->if_softc; 555 556 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 557 ifp->if_oerrors++; 558 559 qereset(sc); 560 } 561 562 /* 563 * Interrupt dispatch. 564 */ 565 int 566 qeintr(arg) 567 void *arg; 568 { 569 struct qe_softc *sc = (struct qe_softc *)arg; 570 bus_space_tag_t t = sc->sc_bustag; 571 u_int32_t qecstat, qestat; 572 int r = 0; 573 574 /* Read QEC status and channel status */ 575 qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 576 #ifdef QEDEBUG 577 if (sc->sc_debug) { 578 printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat); 579 } 580 #endif 581 582 /* Filter out status for this channel */ 583 qecstat = qecstat >> (4 * sc->sc_channel); 584 if ((qecstat & 0xf) == 0) 585 return (r); 586 587 qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT); 588 589 #ifdef QEDEBUG 590 if (sc->sc_debug) { 591 int i; 592 bus_space_tag_t t = sc->sc_bustag; 593 bus_space_handle_t mr = sc->sc_mr; 594 595 printf("qe%d: intr: qestat=%b\n", sc->sc_channel, 596 qestat, QE_CR_STAT_BITS); 597 598 printf("MACE registers:\n"); 599 for (i = 0 ; i < 32; i++) { 600 printf(" m[%d]=%x,", i, bus_space_read_1(t, mr, i)); 601 if (((i+1) & 7) == 0) 602 printf("\n"); 603 } 604 } 605 #endif 606 607 if (qestat & QE_CR_STAT_ALLERRORS) { 608 #ifdef QEDEBUG 609 if (sc->sc_debug) 610 printf("qe%d: eint: qestat=%b\n", sc->sc_channel, 611 qestat, QE_CR_STAT_BITS); 612 #endif 613 r |= qe_eint(sc, qestat); 614 if (r == -1) 615 return (1); 616 } 617 618 if (qestat & QE_CR_STAT_TXIRQ) 619 r |= qe_tint(sc); 620 621 if (qestat & QE_CR_STAT_RXIRQ) 622 r |= qe_rint(sc); 623 624 return (1); 625 } 626 627 /* 628 * Transmit interrupt. 629 */ 630 int 631 qe_tint(sc) 632 struct qe_softc *sc; 633 { 634 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 635 unsigned int bix, txflags; 636 637 bix = sc->sc_rb.rb_tdtail; 638 639 for (;;) { 640 if (sc->sc_rb.rb_td_nbusy <= 0) 641 break; 642 643 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 644 645 if (txflags & QEC_XD_OWN) 646 break; 647 648 ifp->if_flags &= ~IFF_OACTIVE; 649 ifp->if_opackets++; 650 651 if (++bix == QEC_XD_RING_MAXSIZE) 652 bix = 0; 653 654 --sc->sc_rb.rb_td_nbusy; 655 } 656 657 if (sc->sc_rb.rb_td_nbusy == 0) 658 ifp->if_timer = 0; 659 660 if (sc->sc_rb.rb_tdtail != bix) { 661 sc->sc_rb.rb_tdtail = bix; 662 if (ifp->if_flags & IFF_OACTIVE) { 663 ifp->if_flags &= ~IFF_OACTIVE; 664 qestart(ifp); 665 } 666 } 667 668 return (1); 669 } 670 671 /* 672 * Receive interrupt. 673 */ 674 int 675 qe_rint(sc) 676 struct qe_softc *sc; 677 { 678 struct qec_xd *xd = sc->sc_rb.rb_rxd; 679 unsigned int bix, len; 680 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 681 #ifdef QEDEBUG 682 int npackets = 0; 683 #endif 684 685 bix = sc->sc_rb.rb_rdtail; 686 687 /* 688 * Process all buffers with valid data. 689 */ 690 for (;;) { 691 len = xd[bix].xd_flags; 692 if (len & QEC_XD_OWN) 693 break; 694 695 #ifdef QEDEBUG 696 npackets++; 697 #endif 698 699 len &= QEC_XD_LENGTH; 700 len -= 4; 701 qe_read(sc, bix, len); 702 703 /* ... */ 704 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 705 QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH); 706 707 if (++bix == QEC_XD_RING_MAXSIZE) 708 bix = 0; 709 } 710 #ifdef QEDEBUG 711 if (npackets == 0 && sc->sc_debug) 712 printf("%s: rint: no packets; rb index %d; status 0x%x\n", 713 sc->sc_dev.dv_xname, bix, len); 714 #endif 715 716 sc->sc_rb.rb_rdtail = bix; 717 718 return (1); 719 } 720 721 /* 722 * Error interrupt. 723 */ 724 int 725 qe_eint(sc, why) 726 struct qe_softc *sc; 727 u_int32_t why; 728 { 729 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 730 int r = 0, rst = 0; 731 732 if (why & QE_CR_STAT_EDEFER) { 733 printf("%s: excessive tx defers.\n", sc->sc_dev.dv_xname); 734 r |= 1; 735 ifp->if_oerrors++; 736 } 737 738 if (why & QE_CR_STAT_CLOSS) { 739 ifp->if_oerrors++; 740 r |= 1; 741 } 742 743 if (why & QE_CR_STAT_ERETRIES) { 744 printf("%s: excessive tx retries\n", sc->sc_dev.dv_xname); 745 ifp->if_oerrors++; 746 r |= 1; 747 rst = 1; 748 } 749 750 751 if (why & QE_CR_STAT_LCOLL) { 752 printf("%s: late tx transmission\n", sc->sc_dev.dv_xname); 753 ifp->if_oerrors++; 754 r |= 1; 755 rst = 1; 756 } 757 758 if (why & QE_CR_STAT_FUFLOW) { 759 printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname); 760 ifp->if_oerrors++; 761 r |= 1; 762 rst = 1; 763 } 764 765 if (why & QE_CR_STAT_JERROR) { 766 printf("%s: jabber seen\n", sc->sc_dev.dv_xname); 767 r |= 1; 768 } 769 770 if (why & QE_CR_STAT_BERROR) { 771 printf("%s: babble seen\n", sc->sc_dev.dv_xname); 772 r |= 1; 773 } 774 775 if (why & QE_CR_STAT_TCCOFLOW) { 776 ifp->if_collisions += 256; 777 ifp->if_oerrors += 256; 778 r |= 1; 779 } 780 781 if (why & QE_CR_STAT_TXDERROR) { 782 printf("%s: tx descriptor is bad\n", sc->sc_dev.dv_xname); 783 rst = 1; 784 r |= 1; 785 } 786 787 if (why & QE_CR_STAT_TXLERR) { 788 printf("%s: tx late error\n", sc->sc_dev.dv_xname); 789 ifp->if_oerrors++; 790 rst = 1; 791 r |= 1; 792 } 793 794 if (why & QE_CR_STAT_TXPERR) { 795 printf("%s: tx dma parity error\n", sc->sc_dev.dv_xname); 796 ifp->if_oerrors++; 797 rst = 1; 798 r |= 1; 799 } 800 801 if (why & QE_CR_STAT_TXSERR) { 802 printf("%s: tx dma sbus error ack\n", sc->sc_dev.dv_xname); 803 ifp->if_oerrors++; 804 rst = 1; 805 r |= 1; 806 } 807 808 if (why & QE_CR_STAT_RCCOFLOW) { 809 ifp->if_collisions += 256; 810 ifp->if_ierrors += 256; 811 r |= 1; 812 } 813 814 if (why & QE_CR_STAT_RUOFLOW) { 815 ifp->if_ierrors += 256; 816 r |= 1; 817 } 818 819 if (why & QE_CR_STAT_MCOFLOW) { 820 ifp->if_ierrors += 256; 821 r |= 1; 822 } 823 824 if (why & QE_CR_STAT_RXFOFLOW) { 825 printf("%s: rx fifo overflow\n", sc->sc_dev.dv_xname); 826 ifp->if_ierrors++; 827 r |= 1; 828 } 829 830 if (why & QE_CR_STAT_RLCOLL) { 831 printf("%s: rx late collision\n", sc->sc_dev.dv_xname); 832 ifp->if_ierrors++; 833 ifp->if_collisions++; 834 r |= 1; 835 } 836 837 if (why & QE_CR_STAT_FCOFLOW) { 838 ifp->if_ierrors += 256; 839 r |= 1; 840 } 841 842 if (why & QE_CR_STAT_CECOFLOW) { 843 ifp->if_ierrors += 256; 844 r |= 1; 845 } 846 847 if (why & QE_CR_STAT_RXDROP) { 848 printf("%s: rx packet dropped\n", sc->sc_dev.dv_xname); 849 ifp->if_ierrors++; 850 r |= 1; 851 } 852 853 if (why & QE_CR_STAT_RXSMALL) { 854 printf("%s: rx buffer too small\n", sc->sc_dev.dv_xname); 855 ifp->if_ierrors++; 856 r |= 1; 857 rst = 1; 858 } 859 860 if (why & QE_CR_STAT_RXLERR) { 861 printf("%s: rx late error\n", sc->sc_dev.dv_xname); 862 ifp->if_ierrors++; 863 r |= 1; 864 rst = 1; 865 } 866 867 if (why & QE_CR_STAT_RXPERR) { 868 printf("%s: rx dma parity error\n", sc->sc_dev.dv_xname); 869 ifp->if_ierrors++; 870 r |= 1; 871 rst = 1; 872 } 873 874 if (why & QE_CR_STAT_RXSERR) { 875 printf("%s: rx dma sbus error ack\n", sc->sc_dev.dv_xname); 876 ifp->if_ierrors++; 877 r |= 1; 878 rst = 1; 879 } 880 881 if (r == 0) 882 printf("%s: unexpected interrupt error: %08x\n", 883 sc->sc_dev.dv_xname, why); 884 885 if (rst) { 886 printf("%s: resetting...\n", sc->sc_dev.dv_xname); 887 qereset(sc); 888 return (-1); 889 } 890 891 return (r); 892 } 893 894 int 895 qeioctl(ifp, cmd, data) 896 struct ifnet *ifp; 897 u_long cmd; 898 caddr_t data; 899 { 900 struct qe_softc *sc = ifp->if_softc; 901 struct ifaddr *ifa = (struct ifaddr *)data; 902 struct ifreq *ifr = (struct ifreq *)data; 903 int s, error = 0; 904 905 s = splnet(); 906 907 switch (cmd) { 908 case SIOCSIFADDR: 909 ifp->if_flags |= IFF_UP; 910 switch (ifa->ifa_addr->sa_family) { 911 #ifdef INET 912 case AF_INET: 913 qeinit(sc); 914 arp_ifinit(&sc->sc_arpcom, ifa); 915 break; 916 #endif /* INET */ 917 default: 918 qeinit(sc); 919 break; 920 } 921 break; 922 923 case SIOCSIFFLAGS: 924 if ((ifp->if_flags & IFF_UP) == 0 && 925 (ifp->if_flags & IFF_RUNNING) != 0) { 926 /* 927 * If interface is marked down and it is running, then 928 * stop it. 929 */ 930 qestop(sc); 931 ifp->if_flags &= ~IFF_RUNNING; 932 } else if ((ifp->if_flags & IFF_UP) != 0 && 933 (ifp->if_flags & IFF_RUNNING) == 0) { 934 /* 935 * If interface is marked up and it is stopped, then 936 * start it. 937 */ 938 qeinit(sc); 939 } else { 940 /* 941 * Reset the interface to pick up changes in any other 942 * flags that affect hardware registers. 943 */ 944 qestop(sc); 945 qeinit(sc); 946 } 947 #ifdef QEDEBUG 948 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 949 #endif 950 break; 951 952 case SIOCGIFMEDIA: 953 case SIOCSIFMEDIA: 954 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 955 break; 956 957 default: 958 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 959 } 960 961 if (error == ENETRESET) { 962 if (ifp->if_flags & IFF_RUNNING) 963 qe_mcreset(sc); 964 error = 0; 965 } 966 967 splx(s); 968 return (error); 969 } 970 971 972 void 973 qeinit(sc) 974 struct qe_softc *sc; 975 { 976 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 977 bus_space_tag_t t = sc->sc_bustag; 978 bus_space_handle_t cr = sc->sc_cr; 979 bus_space_handle_t mr = sc->sc_mr; 980 struct qec_softc *qec = sc->sc_qec; 981 u_int32_t qecaddr; 982 u_int8_t *ea; 983 int s; 984 985 s = splnet(); 986 987 qestop(sc); 988 989 /* 990 * Allocate descriptor ring and buffers 991 */ 992 qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ); 993 994 /* Channel registers: */ 995 bus_space_write_4(t, cr, QE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 996 bus_space_write_4(t, cr, QE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 997 998 bus_space_write_4(t, cr, QE_CRI_RIMASK, 0); 999 bus_space_write_4(t, cr, QE_CRI_TIMASK, 0); 1000 bus_space_write_4(t, cr, QE_CRI_QMASK, 0); 1001 bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL); 1002 bus_space_write_4(t, cr, QE_CRI_CCNT, 0); 1003 bus_space_write_4(t, cr, QE_CRI_PIPG, 0); 1004 1005 qecaddr = sc->sc_channel * qec->sc_msize; 1006 bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr); 1007 bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr); 1008 bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1009 bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1010 1011 /* 1012 * When switching from mace<->qec always guarantee an sbus 1013 * turnaround (if last op was read, perform a dummy write, and 1014 * vice versa). 1015 */ 1016 bus_space_read_4(t, cr, QE_CRI_QMASK); 1017 1018 /* MACE registers: */ 1019 bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL); 1020 bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT); 1021 bus_space_write_1(t, mr, QE_MRI_RCVFC, 0); 1022 1023 /* 1024 * Mask MACE's receive interrupt, since we're being notified 1025 * by the QEC after DMA completes. 1026 */ 1027 bus_space_write_1(t, mr, QE_MRI_IMR, 1028 QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM); 1029 1030 bus_space_write_1(t, mr, QE_MRI_BIUCC, 1031 QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS); 1032 1033 bus_space_write_1(t, mr, QE_MRI_FIFOFC, 1034 QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 | 1035 QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU); 1036 1037 bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP); 1038 1039 /* 1040 * Station address 1041 */ 1042 ea = sc->sc_arpcom.ac_enaddr; 1043 bus_space_write_1(t, mr, QE_MRI_IAC, 1044 QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR); 1045 bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6); 1046 1047 /* Apply media settings */ 1048 qe_ifmedia_upd(ifp); 1049 1050 /* 1051 * Clear Logical address filter 1052 */ 1053 bus_space_write_1(t, mr, QE_MRI_IAC, 1054 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1055 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8); 1056 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1057 1058 /* Clear missed packet count (register cleared on read) */ 1059 (void)bus_space_read_1(t, mr, QE_MRI_MPC); 1060 1061 #if 0 1062 /* test register: */ 1063 bus_space_write_1(t, mr, QE_MRI_UTR, 0); 1064 #endif 1065 1066 /* Reset multicast filter */ 1067 qe_mcreset(sc); 1068 1069 ifp->if_flags |= IFF_RUNNING; 1070 ifp->if_flags &= ~IFF_OACTIVE; 1071 splx(s); 1072 } 1073 1074 /* 1075 * Reset multicast filter. 1076 */ 1077 void 1078 qe_mcreset(sc) 1079 struct qe_softc *sc; 1080 { 1081 struct arpcom *ac = &sc->sc_arpcom; 1082 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1083 bus_space_tag_t t = sc->sc_bustag; 1084 bus_space_handle_t mr = sc->sc_mr; 1085 struct ether_multi *enm; 1086 struct ether_multistep step; 1087 u_int32_t crc; 1088 u_int16_t hash[4]; 1089 u_int8_t octet, maccc, *ladrp = (u_int8_t *)&hash[0]; 1090 int i, j; 1091 1092 /* We also enable transmitter & receiver here */ 1093 maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV; 1094 1095 if (ifp->if_flags & IFF_PROMISC) { 1096 maccc |= QE_MR_MACCC_PROM; 1097 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1098 return; 1099 } 1100 1101 if (ac->ac_multirangecnt > 0) 1102 ifp->if_flags |= IFF_ALLMULTI; 1103 1104 if (ifp->if_flags & IFF_ALLMULTI) { 1105 bus_space_write_1(t, mr, QE_MRI_IAC, 1106 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1107 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1108 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1109 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1110 return; 1111 } 1112 1113 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1114 1115 ETHER_FIRST_MULTI(step, ac, enm); 1116 while (enm != NULL) { 1117 crc = 0xffffffff; 1118 1119 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1120 octet = enm->enm_addrlo[i]; 1121 1122 for (j = 0; j < 8; j++) { 1123 if ((crc & 1) ^ (octet & 1)) { 1124 crc >>= 1; 1125 crc ^= MC_POLY_LE; 1126 } 1127 else 1128 crc >>= 1; 1129 octet >>= 1; 1130 } 1131 } 1132 1133 crc >>= 26; 1134 hash[crc >> 4] |= 1 << (crc & 0xf); 1135 ETHER_NEXT_MULTI(step, enm); 1136 } 1137 1138 bus_space_write_1(t, mr, QE_MRI_IAC, 1139 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1140 bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8); 1141 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1142 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1143 } 1144 1145 /* 1146 * Get current media settings. 1147 */ 1148 void 1149 qe_ifmedia_sts(ifp, ifmr) 1150 struct ifnet *ifp; 1151 struct ifmediareq *ifmr; 1152 { 1153 struct qe_softc *sc = ifp->if_softc; 1154 u_int8_t phycc; 1155 1156 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1157 phycc = bus_space_read_1(sc->sc_bustag, sc->sc_mr, QE_MRI_PHYCC); 1158 if ((phycc & QE_MR_PHYCC_DLNKTST) == 0) { 1159 ifmr->ifm_status |= IFM_AVALID; 1160 if (phycc & QE_MR_PHYCC_LNKFL) 1161 ifmr->ifm_status &= ~IFM_ACTIVE; 1162 else 1163 ifmr->ifm_status |= IFM_ACTIVE; 1164 } 1165 } 1166 1167 /* 1168 * Set media options. 1169 */ 1170 int 1171 qe_ifmedia_upd(ifp) 1172 struct ifnet *ifp; 1173 { 1174 struct qe_softc *sc = ifp->if_softc; 1175 int media = sc->sc_ifmedia.ifm_media; 1176 1177 if (IFM_TYPE(media) != IFM_ETHER) 1178 return (EINVAL); 1179 1180 if (IFM_SUBTYPE(media) != IFM_10_T) 1181 return (EINVAL); 1182 1183 return (0); 1184 } 1185