1 /* $OpenBSD: esp_sbus.c,v 1.23 2010/06/28 18:31:02 krw Exp $ */ 2 /* $NetBSD: esp_sbus.c,v 1.14 2001/04/25 17:53:37 bouyer Exp $ */ 3 4 /*- 5 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 10 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/buf.h> 39 #include <sys/malloc.h> 40 41 #include <scsi/scsi_all.h> 42 #include <scsi/scsiconf.h> 43 #include <scsi/scsi_message.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 #include <machine/autoconf.h> 48 49 #include <dev/ic/lsi64854reg.h> 50 #include <dev/ic/lsi64854var.h> 51 52 #include <dev/ic/ncr53c9xreg.h> 53 #include <dev/ic/ncr53c9xvar.h> 54 55 #include <dev/sbus/sbusvar.h> 56 57 struct scsi_adapter esp_switch = { 58 ncr53c9x_scsi_cmd, 59 scsi_minphys, /* no max at this level; handled by DMA code */ 60 NULL, 61 NULL, 62 }; 63 64 /* #define ESP_SBUS_DEBUG */ 65 66 static int esp_unit_offset; 67 68 struct esp_softc { 69 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 70 71 bus_space_tag_t sc_bustag; 72 bus_dma_tag_t sc_dmatag; 73 74 bus_space_handle_t sc_reg; /* the registers */ 75 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 76 77 int sc_pri; /* SBUS priority */ 78 }; 79 80 void espattach_sbus(struct device *, struct device *, void *); 81 void espattach_dma(struct device *, struct device *, void *); 82 int espmatch_sbus(struct device *, void *, void *); 83 84 85 /* Linkup to the rest of the kernel */ 86 struct cfattach esp_sbus_ca = { 87 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 88 }; 89 struct cfattach esp_dma_ca = { 90 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 91 }; 92 93 /* 94 * Functions and the switch for the MI code. 95 */ 96 static u_char esp_read_reg(struct ncr53c9x_softc *, int); 97 static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 98 static u_char esp_rdreg1(struct ncr53c9x_softc *, int); 99 static void esp_wrreg1(struct ncr53c9x_softc *, int, u_char); 100 static int esp_dma_isintr(struct ncr53c9x_softc *); 101 static void esp_dma_reset(struct ncr53c9x_softc *); 102 static int esp_dma_intr(struct ncr53c9x_softc *); 103 static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, 104 size_t *, int, size_t *); 105 static void esp_dma_go(struct ncr53c9x_softc *); 106 static void esp_dma_stop(struct ncr53c9x_softc *); 107 static int esp_dma_isactive(struct ncr53c9x_softc *); 108 109 static struct ncr53c9x_glue esp_sbus_glue = { 110 esp_read_reg, 111 esp_write_reg, 112 esp_dma_isintr, 113 esp_dma_reset, 114 esp_dma_intr, 115 esp_dma_setup, 116 esp_dma_go, 117 esp_dma_stop, 118 esp_dma_isactive, 119 NULL, /* gl_clear_latched_intr */ 120 }; 121 122 static struct ncr53c9x_glue esp_sbus_glue1 = { 123 esp_rdreg1, 124 esp_wrreg1, 125 esp_dma_isintr, 126 esp_dma_reset, 127 esp_dma_intr, 128 esp_dma_setup, 129 esp_dma_go, 130 esp_dma_stop, 131 esp_dma_isactive, 132 NULL, /* gl_clear_latched_intr */ 133 }; 134 135 static void espattach(struct esp_softc *, struct ncr53c9x_glue *); 136 137 int 138 espmatch_sbus(struct device *parent, void *vcf, void *aux) 139 { 140 struct cfdata *cf = vcf; 141 int rv; 142 struct sbus_attach_args *sa = aux; 143 144 if (strcmp("SUNW,fas", sa->sa_name) == 0) 145 return 1; 146 147 rv = (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0 || 148 strcmp("ptscII", sa->sa_name) == 0); 149 return (rv); 150 } 151 152 void 153 espattach_sbus(struct device *parent, struct device *self, void *aux) 154 { 155 struct esp_softc *esc = (void *)self; 156 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 157 struct sbus_attach_args *sa = aux; 158 struct lsi64854_softc *lsc; 159 int burst, sbusburst; 160 161 esc->sc_bustag = sa->sa_bustag; 162 esc->sc_dmatag = sa->sa_dmatag; 163 164 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 165 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 166 if (sc->sc_freq < 0) 167 sc->sc_freq = sa->sa_frequency; 168 169 #ifdef ESP_SBUS_DEBUG 170 printf("%s: espattach_sbus: sc_id %d, freq %d\n", 171 self->dv_xname, sc->sc_id, sc->sc_freq); 172 #endif 173 174 if (strcmp("SUNW,fas", sa->sa_name) == 0) { 175 /* 176 * offset searches for other esp/dma devices. 177 */ 178 esp_unit_offset++; 179 180 /* 181 * fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x) 182 */ 183 if (sa->sa_nreg != 2) { 184 printf("%s: %d register spaces\n", self->dv_xname, sa->sa_nreg); 185 return; 186 } 187 188 /* 189 * allocate space for dma, in SUNW,fas there are no separate 190 * dma device 191 */ 192 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT); 193 194 if (lsc == NULL) { 195 printf("%s: out of memory (lsi64854_softc)\n", 196 self->dv_xname); 197 return; 198 } 199 esc->sc_dma = lsc; 200 201 lsc->sc_bustag = sa->sa_bustag; 202 lsc->sc_dmatag = sa->sa_dmatag; 203 204 bcopy(sc->sc_dev.dv_xname, lsc->sc_dev.dv_xname, 205 sizeof (lsc->sc_dev.dv_xname)); 206 207 /* Map dma registers */ 208 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, 209 sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size, 210 0, 0, &lsc->sc_regs) != 0) { 211 printf("%s: cannot map dma registers\n", self->dv_xname); 212 return; 213 } 214 215 /* 216 * XXX is this common(from bpp.c), the same in dma_sbus...etc. 217 * 218 * Get transfer burst size from PROM and plug it into the 219 * controller registers. This is needed on the Sun4m; do 220 * others need it too? 221 */ 222 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 223 if (sbusburst == 0) 224 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 225 226 burst = getpropint(sa->sa_node, "burst-sizes", -1); 227 228 #ifdef ESP_SBUS_DEBUG 229 printf("espattach_sbus: burst 0x%x, sbus 0x%x\n", 230 burst, sbusburst); 231 #endif 232 233 if (burst == -1) 234 /* take SBus burst sizes */ 235 burst = sbusburst; 236 237 /* Clamp at parent's burst sizes */ 238 burst &= sbusburst; 239 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 240 (burst & SBUS_BURST_16) ? 16 : 0; 241 242 lsc->sc_channel = L64854_CHANNEL_SCSI; 243 lsc->sc_client = sc; 244 245 lsi64854_attach(lsc); 246 247 /* 248 * map SCSI core registers 249 */ 250 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot, 251 sa->sa_reg[1].sbr_offset, sa->sa_reg[1].sbr_size, 252 0, 0, &esc->sc_reg) != 0) { 253 printf("%s: cannot map scsi core registers\n", 254 self->dv_xname); 255 return; 256 } 257 258 if (sa->sa_nintr == 0) { 259 printf("%s: no interrupt property\n", self->dv_xname); 260 return; 261 } 262 263 esc->sc_pri = sa->sa_pri; 264 265 printf("%s", self->dv_xname); 266 espattach(esc, &esp_sbus_glue); 267 268 return; 269 } 270 271 /* 272 * Find the DMA by poking around the dma device structures 273 * 274 * What happens here is that if the dma driver has not been 275 * configured, then this returns a NULL pointer. Then when the 276 * dma actually gets configured, it does the opposing test, and 277 * if the sc->sc_esp field in its softc is NULL, then tries to 278 * find the matching esp driver. 279 */ 280 esc->sc_dma = (struct lsi64854_softc *) 281 getdevunit("dma", sc->sc_dev.dv_unit - esp_unit_offset); 282 283 /* 284 * and a back pointer to us, for DMA 285 */ 286 if (esc->sc_dma) 287 esc->sc_dma->sc_client = sc; 288 else { 289 printf("\n"); 290 panic("espattach: no dma found"); 291 } 292 293 /* 294 * The `ESC' DMA chip must be reset before we can access 295 * the esp registers. 296 */ 297 if (esc->sc_dma->sc_rev == DMAREV_ESC) 298 DMA_RESET(esc->sc_dma); 299 300 /* 301 * Map my registers in, if they aren't already in virtual 302 * address space. 303 */ 304 if (sa->sa_npromvaddrs) { 305 if (bus_space_map(sa->sa_bustag, sa->sa_promvaddrs[0], 306 sa->sa_size, BUS_SPACE_MAP_PROMADDRESS, 307 &esc->sc_reg) != 0) { 308 printf("%s @ sbus: cannot map registers\n", 309 self->dv_xname); 310 return; 311 } 312 } else { 313 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 314 sa->sa_offset, sa->sa_size, 0, 0, &esc->sc_reg) != 0) { 315 printf("%s @ sbus: cannot map registers\n", 316 self->dv_xname); 317 return; 318 } 319 } 320 321 if (sa->sa_nintr == 0) { 322 /* 323 * No interrupt properties: we quit; this might 324 * happen on e.g. a Sparc X terminal. 325 */ 326 printf("\n%s: no interrupt property\n", self->dv_xname); 327 return; 328 } 329 330 esc->sc_pri = sa->sa_pri; 331 332 if (strcmp("ptscII", sa->sa_name) == 0) { 333 espattach(esc, &esp_sbus_glue1); 334 } else { 335 espattach(esc, &esp_sbus_glue); 336 } 337 } 338 339 void 340 espattach_dma(struct device *parent, struct device *self, void *aux) 341 { 342 struct esp_softc *esc = (void *)self; 343 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 344 struct sbus_attach_args *sa = aux; 345 346 if (strcmp("ptscII", sa->sa_name) == 0) { 347 return; 348 } 349 350 esc->sc_bustag = sa->sa_bustag; 351 esc->sc_dmatag = sa->sa_dmatag; 352 353 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 354 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 355 356 esc->sc_dma = (struct lsi64854_softc *)parent; 357 esc->sc_dma->sc_client = sc; 358 359 /* 360 * Map my registers in, if they aren't already in virtual 361 * address space. 362 */ 363 if (sa->sa_npromvaddrs) { 364 if (bus_space_map(sa->sa_bustag, sa->sa_promvaddrs[0], 365 sa->sa_size /* ??? */, BUS_SPACE_MAP_PROMADDRESS, 366 &esc->sc_reg) != 0) { 367 printf("%s @ dma: cannot map registers\n", 368 self->dv_xname); 369 return; 370 } 371 } else { 372 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, sa->sa_offset, 373 sa->sa_size, 0, 0, &esc->sc_reg) != 0) { 374 printf("%s @ dma: cannot map registers\n", 375 self->dv_xname); 376 return; 377 } 378 } 379 380 if (sa->sa_nintr == 0) { 381 /* 382 * No interrupt properties: we quit; this might 383 * happen on e.g. a Sparc X terminal. 384 */ 385 printf("\n%s: no interrupt property\n", self->dv_xname); 386 return; 387 } 388 389 esc->sc_pri = sa->sa_pri; 390 391 espattach(esc, &esp_sbus_glue); 392 } 393 394 395 /* 396 * Attach this instance, and then all the sub-devices 397 */ 398 void 399 espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep) 400 { 401 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 402 void *icookie; 403 unsigned int uid = 0; 404 405 /* 406 * Set up glue for MI code early; we use some of it here. 407 */ 408 sc->sc_glue = gluep; 409 410 /* gimme MHz */ 411 sc->sc_freq /= 1000000; 412 413 /* 414 * XXX More of this should be in ncr53c9x_attach(), but 415 * XXX should we really poke around the chip that much in 416 * XXX the MI code? Think about this more... 417 */ 418 419 /* 420 * It is necessary to try to load the 2nd config register here, 421 * to find out what rev the esp chip is, else the ncr53c9x_reset 422 * will not set up the defaults correctly. 423 */ 424 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 425 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 426 sc->sc_cfg3 = NCRCFG3_CDB; 427 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 428 429 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 430 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 431 sc->sc_rev = NCR_VARIANT_ESP100; 432 } else { 433 sc->sc_cfg2 = NCRCFG2_SCSI2; 434 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 435 sc->sc_cfg3 = 0; 436 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 437 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 438 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 439 if (NCR_READ_REG(sc, NCR_CFG3) != 440 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 441 sc->sc_rev = NCR_VARIANT_ESP100A; 442 } else { 443 /* NCRCFG2_FE enables > 64K transfers */ 444 sc->sc_cfg2 |= NCRCFG2_FE; 445 sc->sc_cfg3 = 0; 446 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 447 sc->sc_rev = NCR_VARIANT_ESP200; 448 449 /* XXX spec says it's valid after power up or chip reset */ 450 uid = NCR_READ_REG(sc, NCR_UID); 451 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 452 sc->sc_rev = NCR_VARIANT_FAS366; 453 } 454 } 455 456 #ifdef ESP_SBUS_DEBUG 457 printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid); 458 #endif 459 460 /* 461 * XXX minsync and maxxfer _should_ be set up in MI code, 462 * XXX but it appears to have some dependency on what sort 463 * XXX of DMA we're hooked up to, etc. 464 */ 465 466 /* 467 * This is the value used to start sync negotiations 468 * Note that the NCR register "SYNCTP" is programmed 469 * in "clocks per byte", and has a minimum value of 4. 470 * The SCSI period used in negotiation is one-fourth 471 * of the time (in nanoseconds) needed to transfer one byte. 472 * Since the chip's clock is given in MHz, we have the following 473 * formula: 4 * period = (1000 / freq) * 4 474 */ 475 sc->sc_minsync = 1000 / sc->sc_freq; 476 477 /* 478 * Alas, we must now modify the value a bit, because it's 479 * only valid when can switch on FASTCLK and FASTSCSI bits 480 * in config register 3... 481 */ 482 switch (sc->sc_rev) { 483 case NCR_VARIANT_ESP100: 484 sc->sc_maxxfer = 64 * 1024; 485 sc->sc_minsync = 0; /* No synch on old chip? */ 486 break; 487 488 case NCR_VARIANT_ESP100A: 489 sc->sc_maxxfer = 64 * 1024; 490 /* Min clocks/byte is 5 */ 491 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 492 break; 493 494 case NCR_VARIANT_ESP200: 495 case NCR_VARIANT_FAS366: 496 sc->sc_maxxfer = 16 * 1024 * 1024; 497 /* XXX - do actually set FAST* bits */ 498 break; 499 } 500 501 /* Establish interrupt channel */ 502 icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO, 0, 503 ncr53c9x_intr, sc, sc->sc_dev.dv_xname); 504 505 /* Turn on target selection using the `dma' method */ 506 if (sc->sc_rev != NCR_VARIANT_FAS366) 507 sc->sc_features |= NCR_F_DMASELECT; 508 509 /* Do the common parts of attachment. */ 510 ncr53c9x_attach(sc, &esp_switch); 511 } 512 513 /* 514 * Glue functions. 515 */ 516 517 #ifdef ESP_SBUS_DEBUG 518 int esp_sbus_debug = 0; 519 520 static struct { 521 char *r_name; 522 int r_flag; 523 } esp__read_regnames [] = { 524 { "TCL", 0}, /* 0/00 */ 525 { "TCM", 0}, /* 1/04 */ 526 { "FIFO", 0}, /* 2/08 */ 527 { "CMD", 0}, /* 3/0c */ 528 { "STAT", 0}, /* 4/10 */ 529 { "INTR", 0}, /* 5/14 */ 530 { "STEP", 0}, /* 6/18 */ 531 { "FFLAGS", 1}, /* 7/1c */ 532 { "CFG1", 1}, /* 8/20 */ 533 { "STAT2", 0}, /* 9/24 */ 534 { "CFG4", 1}, /* a/28 */ 535 { "CFG2", 1}, /* b/2c */ 536 { "CFG3", 1}, /* c/30 */ 537 { "-none", 1}, /* d/34 */ 538 { "TCH", 1}, /* e/38 */ 539 { "TCX", 1}, /* f/3c */ 540 }; 541 542 static struct { 543 char *r_name; 544 int r_flag; 545 } esp__write_regnames[] = { 546 { "TCL", 1}, /* 0/00 */ 547 { "TCM", 1}, /* 1/04 */ 548 { "FIFO", 0}, /* 2/08 */ 549 { "CMD", 0}, /* 3/0c */ 550 { "SELID", 1}, /* 4/10 */ 551 { "TIMEOUT", 1}, /* 5/14 */ 552 { "SYNCTP", 1}, /* 6/18 */ 553 { "SYNCOFF", 1}, /* 7/1c */ 554 { "CFG1", 1}, /* 8/20 */ 555 { "CCF", 1}, /* 9/24 */ 556 { "TEST", 1}, /* a/28 */ 557 { "CFG2", 1}, /* b/2c */ 558 { "CFG3", 1}, /* c/30 */ 559 { "-none", 1}, /* d/34 */ 560 { "TCH", 1}, /* e/38 */ 561 { "TCX", 1}, /* f/3c */ 562 }; 563 #endif 564 565 u_char 566 esp_read_reg(struct ncr53c9x_softc *sc, int reg) 567 { 568 struct esp_softc *esc = (struct esp_softc *)sc; 569 u_char v; 570 571 v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4); 572 #ifdef ESP_SBUS_DEBUG 573 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 574 printf("RD:%x <%s> %x\n", reg * 4, 575 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 576 #endif 577 return v; 578 } 579 580 void 581 esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v) 582 { 583 struct esp_softc *esc = (struct esp_softc *)sc; 584 585 #ifdef ESP_SBUS_DEBUG 586 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 587 printf("WR:%x <%s> %x\n", reg * 4, 588 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 589 #endif 590 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 591 } 592 593 u_char 594 esp_rdreg1(struct ncr53c9x_softc *sc, int reg) 595 { 596 struct esp_softc *esc = (struct esp_softc *)sc; 597 598 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg)); 599 } 600 601 void 602 esp_wrreg1(struct ncr53c9x_softc *sc, int reg, u_char v) 603 { 604 struct esp_softc *esc = (struct esp_softc *)sc; 605 606 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 607 } 608 609 int 610 esp_dma_isintr(struct ncr53c9x_softc *sc) 611 { 612 struct esp_softc *esc = (struct esp_softc *)sc; 613 614 return (DMA_ISINTR(esc->sc_dma)); 615 } 616 617 void 618 esp_dma_reset(struct ncr53c9x_softc *sc) 619 { 620 struct esp_softc *esc = (struct esp_softc *)sc; 621 622 DMA_RESET(esc->sc_dma); 623 } 624 625 int 626 esp_dma_intr(struct ncr53c9x_softc *sc) 627 { 628 struct esp_softc *esc = (struct esp_softc *)sc; 629 630 return (DMA_INTR(esc->sc_dma)); 631 } 632 633 int 634 esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 635 int datain, size_t *dmasize) 636 { 637 struct esp_softc *esc = (struct esp_softc *)sc; 638 639 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 640 } 641 642 void 643 esp_dma_go(struct ncr53c9x_softc *sc) 644 { 645 struct esp_softc *esc = (struct esp_softc *)sc; 646 647 DMA_GO(esc->sc_dma); 648 } 649 650 void 651 esp_dma_stop(struct ncr53c9x_softc *sc) 652 { 653 struct esp_softc *esc = (struct esp_softc *)sc; 654 u_int32_t csr; 655 656 csr = L64854_GCSR(esc->sc_dma); 657 csr &= ~D_EN_DMA; 658 L64854_SCSR(esc->sc_dma, csr); 659 } 660 661 int 662 esp_dma_isactive(struct ncr53c9x_softc *sc) 663 { 664 struct esp_softc *esc = (struct esp_softc *)sc; 665 666 return (DMA_ISACTIVE(esc->sc_dma)); 667 } 668 669 #if defined(DDB) && defined(notyet) 670 #include <machine/db_machdep.h> 671 #include <ddb/db_output.h> 672 673 void db_esp(db_expr_t, int, db_expr_t, char *); 674 675 void 676 db_esp(db_expr_t addr, int have_addr, db_expr_t count, char *modif) 677 { 678 struct ncr53c9x_softc *sc; 679 struct ncr53c9x_ecb *ecb; 680 struct ncr53c9x_linfo *li; 681 int u, t, i; 682 683 for (u=0; u<10; u++) { 684 sc = (struct ncr53c9x_softc *) 685 getdevunit("esp", u); 686 if (!sc) continue; 687 688 db_printf("esp%d: nexus %p phase %x prev %x dp %p dleft %lx ify %x\n", 689 u, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 690 sc->sc_dp, sc->sc_dleft, sc->sc_msgify); 691 db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n", 692 sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0], 693 sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3], 694 sc->sc_imess[0]); 695 db_printf("ready: "); 696 TAILQ_FOREACH(ecb, &sc->ready_list, chain) { 697 db_printf("ecb %p ", ecb); 698 if (ecb == TAILQ_NEXT(ecb, chain)) { 699 db_printf("\nWARNING: tailq loop on ecb %p", ecb); 700 break; 701 } 702 } 703 db_printf("\n"); 704 705 for (t=0; t<NCR_NTARG; t++) { 706 LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) { 707 db_printf("t%d lun %d untagged %p busy %d used %x\n", 708 t, (int)li->lun, li->untagged, li->busy, 709 li->used); 710 for (i=0; i<256; i++) 711 if ((ecb = li->queued[i])) { 712 db_printf("ecb %p tag %x\n", ecb, i); 713 } 714 } 715 } 716 } 717 } 718 #endif 719 720