1 /* $OpenBSD: cgthree.c,v 1.44 2008/12/27 17:23:03 miod Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Jason L. Wright (jason@thought.net) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Effort sponsored in part by the Defense Advanced Research Projects 29 * Agency (DARPA) and Air Force Research Laboratory, Air Force 30 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 31 * 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/errno.h> 38 #include <sys/device.h> 39 #include <sys/ioctl.h> 40 #include <sys/malloc.h> 41 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 #include <machine/autoconf.h> 45 #include <machine/openfirm.h> 46 47 #include <dev/sbus/sbusvar.h> 48 #include <dev/wscons/wsconsio.h> 49 #include <dev/wscons/wsdisplayvar.h> 50 #include <dev/rasops/rasops.h> 51 #include <machine/fbvar.h> 52 53 #include <dev/ic/bt458reg.h> 54 55 #define CGTHREE_CTRL_OFFSET 0x400000 56 #define CGTHREE_CTRL_SIZE (sizeof(u_int32_t) * 8) 57 #define CGTHREE_VID_OFFSET 0x800000 58 #define CGTHREE_VID_SIZE (1024 * 1024) 59 60 union bt_cmap { 61 u_int8_t cm_map[256][3]; /* 256 r/b/g entries */ 62 u_int32_t cm_chip[256 * 3 / 4]; /* the way the chip is loaded */ 63 }; 64 65 #define BT_ADDR 0x00 /* map address register */ 66 #define BT_CMAP 0x04 /* colormap data register */ 67 #define BT_CTRL 0x08 /* control register */ 68 #define BT_OMAP 0x0c /* overlay (cursor) map register */ 69 #define CG3_FBC_CTRL 0x10 /* control */ 70 #define CG3_FBC_STAT 0x11 /* status */ 71 #define CG3_FBC_START 0x12 /* cursor start */ 72 #define CG3_FBC_END 0x13 /* cursor end */ 73 #define CG3_FBC_VCTRL 0x14 /* 12 bytes of timing goo */ 74 75 #define BT_WRITE(sc, reg, val) \ 76 bus_space_write_4((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val)) 77 #define BT_READ(sc, reg) \ 78 bus_space_read_4((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg)) 79 #define BT_BARRIER(sc,reg,flags) \ 80 bus_space_barrier((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), \ 81 sizeof(u_int32_t), (flags)) 82 83 #define BT_D4M3(x) ((((x) >> 2) << 1) + ((x) >> 2)) /* (x / 4) * 3 */ 84 #define BT_D4M4(x) ((x) & ~3) /* (x / 4) * 4 */ 85 86 #define FBC_CTRL_IENAB 0x80 /* interrupt enable */ 87 #define FBC_CTRL_VENAB 0x40 /* video enable */ 88 #define FBC_CTRL_TIME 0x20 /* timing enable */ 89 #define FBC_CTRL_CURS 0x10 /* cursor compare enable */ 90 #define FBC_CTRL_XTAL 0x0c /* xtal select (0,1,2,test): */ 91 #define FBC_CTRL_XTAL_0 0x00 /* 0 */ 92 #define FBC_CTRL_XTAL_1 0x04 /* 0 */ 93 #define FBC_CTRL_XTAL_2 0x08 /* 0 */ 94 #define FBC_CTRL_XTAL_TEST 0x0c /* 0 */ 95 #define FBC_CTRL_DIV 0x03 /* divisor (1,2,3,4): */ 96 #define FBC_CTRL_DIV_1 0x00 /* / 1 */ 97 #define FBC_CTRL_DIV_2 0x01 /* / 2 */ 98 #define FBC_CTRL_DIV_3 0x02 /* / 3 */ 99 #define FBC_CTRL_DIV_4 0x03 /* / 4 */ 100 101 #define FBC_STAT_INTR 0x80 /* interrupt pending */ 102 #define FBC_STAT_RES 0x70 /* monitor sense: */ 103 #define FBC_STAT_RES_1024 0x10 /* 1024x768 */ 104 #define FBC_STAT_RES_1280 0x40 /* 1280x1024 */ 105 #define FBC_STAT_RES_1152 0x30 /* 1152x900 */ 106 #define FBC_STAT_RES_1152A 0x40 /* 1152x900x76, A */ 107 #define FBC_STAT_RES_1600 0x50 /* 1600x1200 */ 108 #define FBC_STAT_RES_1152B 0x60 /* 1152x900x86, B */ 109 #define FBC_STAT_ID 0x0f /* id mask: */ 110 #define FBC_STAT_ID_COLOR 0x01 /* color */ 111 #define FBC_STAT_ID_MONO 0x02 /* monochrome */ 112 #define FBC_STAT_ID_MONOECL 0x03 /* monochrome, ecl */ 113 114 #define FBC_READ(sc, reg) \ 115 bus_space_read_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg)) 116 #define FBC_WRITE(sc, reg, val) \ 117 bus_space_write_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val)) 118 119 struct cgthree_softc { 120 struct sunfb sc_sunfb; 121 bus_space_tag_t sc_bustag; 122 bus_addr_t sc_paddr; 123 bus_space_handle_t sc_ctrl_regs; 124 bus_space_handle_t sc_vid_regs; 125 int sc_nscreens; 126 union bt_cmap sc_cmap; 127 u_int sc_mode; 128 }; 129 130 int cgthree_ioctl(void *, u_long, caddr_t, int, struct proc *); 131 paddr_t cgthree_mmap(void *, off_t, int); 132 int cgthree_is_console(int); 133 void cgthree_loadcmap(struct cgthree_softc *, u_int, u_int); 134 int cg3_bt_putcmap(union bt_cmap *, struct wsdisplay_cmap *); 135 int cg3_bt_getcmap(union bt_cmap *, struct wsdisplay_cmap *); 136 void cgthree_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t); 137 void cgthree_burner(void *, u_int, u_int); 138 void cgthree_reset(struct cgthree_softc *); 139 140 struct wsdisplay_accessops cgthree_accessops = { 141 cgthree_ioctl, 142 cgthree_mmap, 143 NULL, /* alloc_screen */ 144 NULL, /* free_screen */ 145 NULL, /* show_screen */ 146 NULL, /* load_font */ 147 NULL, /* scrollback */ 148 NULL, /* getchar */ 149 cgthree_burner, 150 }; 151 152 int cgthreematch(struct device *, void *, void *); 153 void cgthreeattach(struct device *, struct device *, void *); 154 155 struct cfattach cgthree_ca = { 156 sizeof (struct cgthree_softc), cgthreematch, cgthreeattach 157 }; 158 159 struct cfdriver cgthree_cd = { 160 NULL, "cgthree", DV_DULL 161 }; 162 163 #define CG3_TYPE_DEFAULT 0 164 #define CG3_TYPE_76HZ 1 165 #define CG3_TYPE_SMALL 2 166 167 struct cg3_videoctrl { 168 u_int8_t sense; 169 u_int8_t vctrl[12]; 170 u_int8_t ctrl; 171 } cg3_videoctrl[] = { 172 { /* cpd-1790 */ 173 FBC_STAT_RES_1152 | FBC_STAT_ID_COLOR, 174 { 0xbb, 0x2b, 0x04, 0x14, 0xae, 0x03, 175 0xa8, 0x24, 0x01, 0x05, 0xff, 0x01 }, 176 FBC_CTRL_XTAL_0 | FBC_CTRL_DIV_1 177 }, 178 { /* gdm-20e20 */ 179 FBC_STAT_RES_1152A | FBC_STAT_ID_COLOR, 180 { 0xb7, 0x27, 0x03, 0x0f, 0xae, 0x03, 181 0xae, 0x2a, 0x01, 0x09, 0xff, 0x01 }, 182 FBC_CTRL_XTAL_1 | FBC_CTRL_DIV_1 183 }, 184 { /* defaults, should be last */ 185 0xff, 186 { 0xbb, 0x2b, 0x03, 0x0b, 0xb3, 0x03, 187 0xaf, 0x2b, 0x02, 0x0a, 0xff, 0x01 }, 188 0, 189 }, 190 }; 191 192 int 193 cgthreematch(struct device *parent, void *vcf, void *aux) 194 { 195 struct cfdata *cf = vcf; 196 struct sbus_attach_args *sa = aux; 197 198 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 199 } 200 201 void 202 cgthreeattach(struct device *parent, struct device *self, void *aux) 203 { 204 struct cgthree_softc *sc = (struct cgthree_softc *)self; 205 struct sbus_attach_args *sa = aux; 206 int node, console; 207 const char *nam; 208 209 node = sa->sa_node; 210 sc->sc_bustag = sa->sa_bustag; 211 sc->sc_paddr = sbus_bus_addr(sa->sa_bustag, sa->sa_slot, sa->sa_offset); 212 213 fb_setsize(&sc->sc_sunfb, 8, 1152, 900, node, 0); 214 215 if (sa->sa_nreg != 1) { 216 printf(": expected %d registers, got %d\n", 1, sa->sa_nreg); 217 goto fail; 218 } 219 220 /* 221 * Map just CTRL and video RAM. 222 */ 223 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, 224 sa->sa_reg[0].sbr_offset + CGTHREE_CTRL_OFFSET, 225 CGTHREE_CTRL_SIZE, 0, 0, &sc->sc_ctrl_regs) != 0) { 226 printf(": cannot map ctrl registers\n"); 227 goto fail_ctrl; 228 } 229 230 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, 231 sa->sa_reg[0].sbr_offset + CGTHREE_VID_OFFSET, 232 sc->sc_sunfb.sf_fbsize, BUS_SPACE_MAP_LINEAR, 233 0, &sc->sc_vid_regs) != 0) { 234 printf(": cannot map vid registers\n"); 235 goto fail_vid; 236 } 237 238 nam = getpropstring(node, "model"); 239 if (*nam == '\0') 240 nam = sa->sa_name; 241 printf(": %s", nam); 242 243 console = cgthree_is_console(node); 244 245 cgthree_reset(sc); 246 cgthree_burner(sc, 1, 0); 247 248 sc->sc_sunfb.sf_ro.ri_bits = (void *)bus_space_vaddr(sc->sc_bustag, 249 sc->sc_vid_regs); 250 sc->sc_sunfb.sf_ro.ri_hw = sc; 251 252 printf(", %dx%d\n", sc->sc_sunfb.sf_width, sc->sc_sunfb.sf_height); 253 254 fbwscons_init(&sc->sc_sunfb, 0, console); 255 fbwscons_setcolormap(&sc->sc_sunfb, cgthree_setcolor); 256 257 if (console) 258 fbwscons_console_init(&sc->sc_sunfb, -1); 259 260 fbwscons_attach(&sc->sc_sunfb, &cgthree_accessops, console); 261 262 return; 263 264 fail_vid: 265 bus_space_unmap(sa->sa_bustag, sc->sc_ctrl_regs, CGTHREE_CTRL_SIZE); 266 fail_ctrl: 267 fail: 268 ; 269 } 270 271 int 272 cgthree_ioctl(void *v, u_long cmd, caddr_t data, int flags, struct proc *p) 273 { 274 struct cgthree_softc *sc = v; 275 struct wsdisplay_fbinfo *wdf; 276 struct wsdisplay_cmap *cm; 277 int error; 278 279 switch (cmd) { 280 case WSDISPLAYIO_GTYPE: 281 *(u_int *)data = WSDISPLAY_TYPE_SUNCG3; 282 break; 283 case WSDISPLAYIO_SMODE: 284 sc->sc_mode = *(u_int *)data; 285 break; 286 case WSDISPLAYIO_GINFO: 287 wdf = (void *)data; 288 wdf->height = sc->sc_sunfb.sf_height; 289 wdf->width = sc->sc_sunfb.sf_width; 290 wdf->depth = sc->sc_sunfb.sf_depth; 291 wdf->cmsize = 256; 292 break; 293 case WSDISPLAYIO_LINEBYTES: 294 *(u_int *)data = sc->sc_sunfb.sf_linebytes; 295 break; 296 297 case WSDISPLAYIO_GETCMAP: 298 cm = (struct wsdisplay_cmap *)data; 299 error = cg3_bt_getcmap(&sc->sc_cmap, cm); 300 if (error) 301 return (error); 302 break; 303 304 case WSDISPLAYIO_PUTCMAP: 305 cm = (struct wsdisplay_cmap *)data; 306 error = cg3_bt_putcmap(&sc->sc_cmap, cm); 307 if (error) 308 return (error); 309 cgthree_loadcmap(sc, cm->index, cm->count); 310 break; 311 312 case WSDISPLAYIO_SVIDEO: 313 case WSDISPLAYIO_GVIDEO: 314 break; 315 316 case WSDISPLAYIO_GCURPOS: 317 case WSDISPLAYIO_SCURPOS: 318 case WSDISPLAYIO_GCURMAX: 319 case WSDISPLAYIO_GCURSOR: 320 case WSDISPLAYIO_SCURSOR: 321 default: 322 return -1; /* not supported yet */ 323 } 324 325 return (0); 326 } 327 328 #define START (128 * 1024 + 128 * 1024) 329 #define NOOVERLAY (0x04000000) 330 331 paddr_t 332 cgthree_mmap(void *v, off_t offset, int prot) 333 { 334 struct cgthree_softc *sc = v; 335 336 if (offset & PGOFSET || offset < 0) 337 return (-1); 338 339 switch (sc->sc_mode) { 340 case WSDISPLAYIO_MODE_MAPPED: 341 if (offset >= NOOVERLAY) 342 offset -= NOOVERLAY; 343 else if (offset >= START) 344 offset -= START; 345 else 346 offset = 0; 347 if (offset >= sc->sc_sunfb.sf_fbsize) 348 return (-1); 349 return (bus_space_mmap(sc->sc_bustag, sc->sc_paddr, 350 CGTHREE_VID_OFFSET + offset, prot, BUS_SPACE_MAP_LINEAR)); 351 case WSDISPLAYIO_MODE_DUMBFB: 352 if (offset < sc->sc_sunfb.sf_fbsize) 353 return (bus_space_mmap(sc->sc_bustag, sc->sc_paddr, 354 CGTHREE_VID_OFFSET + offset, prot, 355 BUS_SPACE_MAP_LINEAR)); 356 break; 357 } 358 return (-1); 359 } 360 361 int 362 cgthree_is_console(int node) 363 { 364 extern int fbnode; 365 366 return (fbnode == node); 367 } 368 369 void 370 cgthree_setcolor(void *v, u_int index, u_int8_t r, u_int8_t g, u_int8_t b) 371 { 372 struct cgthree_softc *sc = v; 373 union bt_cmap *bcm = &sc->sc_cmap; 374 375 bcm->cm_map[index][0] = r; 376 bcm->cm_map[index][1] = g; 377 bcm->cm_map[index][2] = b; 378 cgthree_loadcmap(sc, index, 1); 379 } 380 381 void 382 cgthree_loadcmap(struct cgthree_softc *sc, u_int start, u_int ncolors) 383 { 384 u_int cstart; 385 int count; 386 387 cstart = BT_D4M3(start); 388 count = BT_D4M3(start + ncolors - 1) - BT_D4M3(start) + 3; 389 BT_WRITE(sc, BT_ADDR, BT_D4M4(start)); 390 while (--count >= 0) { 391 BT_WRITE(sc, BT_CMAP, sc->sc_cmap.cm_chip[cstart]); 392 cstart++; 393 } 394 } 395 396 int 397 cg3_bt_getcmap(union bt_cmap *bcm, struct wsdisplay_cmap *rcm) 398 { 399 u_int index = rcm->index, count = rcm->count, i; 400 int error; 401 402 if (index >= 256 || count > 256 - index) 403 return (EINVAL); 404 for (i = 0; i < count; i++) { 405 if ((error = copyout(&bcm->cm_map[index + i][0], 406 &rcm->red[i], 1)) != 0) 407 return (error); 408 if ((error = copyout(&bcm->cm_map[index + i][1], 409 &rcm->green[i], 1)) != 0) 410 return (error); 411 if ((error = copyout(&bcm->cm_map[index + i][2], 412 &rcm->blue[i], 1)) != 0) 413 return (error); 414 } 415 return (0); 416 } 417 418 int 419 cg3_bt_putcmap(union bt_cmap *bcm, struct wsdisplay_cmap *rcm) 420 { 421 u_int index = rcm->index, count = rcm->count, i; 422 int error; 423 424 if (index >= 256 || count > 256 - index) 425 return (EINVAL); 426 for (i = 0; i < count; i++) { 427 if ((error = copyin(&rcm->red[i], 428 &bcm->cm_map[index + i][0], 1)) != 0) 429 return (error); 430 if ((error = copyin(&rcm->green[i], 431 &bcm->cm_map[index + i][1], 1)) != 0) 432 return (error); 433 if ((error = copyin(&rcm->blue[i], 434 &bcm->cm_map[index + i][2], 1)) != 0) 435 return (error); 436 } 437 return (0); 438 } 439 440 void 441 cgthree_reset(struct cgthree_softc *sc) 442 { 443 int i, j; 444 u_int8_t sts, ctrl; 445 446 sts = FBC_READ(sc, CG3_FBC_STAT); 447 ctrl = FBC_READ(sc, CG3_FBC_CTRL); 448 449 if (ctrl & FBC_CTRL_TIME) { 450 /* already initialized */ 451 return; 452 } 453 454 for (i = 0; i < nitems(cg3_videoctrl); i++) { 455 if (cg3_videoctrl[i].sense == 0xff || 456 (cg3_videoctrl[i].sense == 457 (sts & (FBC_STAT_RES | FBC_STAT_ID)))) { 458 for (j = 0; j < 12; j++) 459 FBC_WRITE(sc, CG3_FBC_VCTRL + j, 460 cg3_videoctrl[i].vctrl[j]); 461 ctrl &= ~(FBC_CTRL_XTAL | FBC_CTRL_DIV); 462 ctrl |= cg3_videoctrl[i].ctrl | 463 FBC_CTRL_TIME; 464 FBC_WRITE(sc, CG3_FBC_CTRL, ctrl); 465 break; 466 } 467 } 468 469 /* enable all the bit planes */ 470 BT_WRITE(sc, BT_ADDR, BT_RMR); 471 BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE); 472 BT_WRITE(sc, BT_CTRL, 0xff); 473 BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE); 474 475 /* no plane should blink */ 476 BT_WRITE(sc, BT_ADDR, BT_BMR); 477 BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE); 478 BT_WRITE(sc, BT_CTRL, 0x00); 479 BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE); 480 481 /* 482 * enable the RAMDAC, disable blink, disable overlay 0 and 1, 483 * use 4:1 multiplexor. 484 */ 485 BT_WRITE(sc, BT_ADDR, BT_CR); 486 BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE); 487 BT_WRITE(sc, BT_CTRL, 488 (BTCR_MPLX_4 | BTCR_RAMENA | BTCR_BLINK_6464)); 489 BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE); 490 491 /* disable the D/A read pins */ 492 BT_WRITE(sc, BT_ADDR, BT_CTR); 493 BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE); 494 BT_WRITE(sc, BT_CTRL, 0x00); 495 BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE); 496 } 497 498 void 499 cgthree_burner(void *vsc, u_int on, u_int flags) 500 { 501 struct cgthree_softc *sc = vsc; 502 int s; 503 u_int8_t fbc; 504 505 s = splhigh(); 506 fbc = FBC_READ(sc, CG3_FBC_CTRL); 507 if (on) 508 fbc |= FBC_CTRL_VENAB | FBC_CTRL_TIME; 509 else { 510 fbc &= ~FBC_CTRL_VENAB; 511 if (flags & WSDISPLAY_BURN_VBLANK) 512 fbc &= ~FBC_CTRL_TIME; 513 } 514 FBC_WRITE(sc, CG3_FBC_CTRL, fbc); 515 splx(s); 516 } 517