1 /* $OpenBSD: be.c,v 1.41 2016/04/13 11:36:00 mpi Exp $ */ 2 /* $NetBSD: be.c,v 1.26 2001/03/20 15:39:20 pk Exp $ */ 3 4 /*- 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 */ 57 58 #include "bpfilter.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/timeout.h> 63 #include <sys/kernel.h> 64 #include <sys/errno.h> 65 #include <sys/ioctl.h> 66 #include <sys/mbuf.h> 67 #include <sys/socket.h> 68 #include <sys/syslog.h> 69 #include <sys/device.h> 70 #include <sys/malloc.h> 71 72 #include <net/if.h> 73 #include <net/if_media.h> 74 75 #include <netinet/in.h> 76 #include <netinet/if_ether.h> 77 78 #if NBPFILTER > 0 79 #include <net/bpf.h> 80 #endif 81 82 #include <machine/bus.h> 83 #include <machine/intr.h> 84 #include <machine/autoconf.h> 85 86 #include <dev/sbus/sbusvar.h> 87 88 #include <dev/mii/mii.h> 89 #include <dev/mii/miivar.h> 90 91 #include <dev/sbus/qecreg.h> 92 #include <dev/sbus/qecvar.h> 93 #include <dev/sbus/bereg.h> 94 95 struct be_softc { 96 struct device sc_dev; 97 bus_space_tag_t sc_bustag; /* bus & dma tags */ 98 bus_dma_tag_t sc_dmatag; 99 bus_dmamap_t sc_dmamap; 100 struct arpcom sc_arpcom; 101 /*struct ifmedia sc_ifmedia; -* interface media */ 102 struct mii_data sc_mii; /* MII media control */ 103 #define sc_media sc_mii.mii_media/* shorthand */ 104 int sc_phys[2]; /* MII instance -> phy */ 105 106 struct timeout sc_tick_ch; 107 108 /* 109 * Some `mii_softc' items we need to emulate MII operation 110 * for our internal transceiver. 111 */ 112 int sc_mii_inst; /* instance of internal phy */ 113 uint64_t sc_mii_active; /* currently active medium */ 114 int sc_mii_ticks; /* tick counter */ 115 int sc_mii_flags; /* phy status flags */ 116 #define MIIF_HAVELINK 0x04000000 117 int sc_intphy_curspeed; /* Established link speed */ 118 119 struct qec_softc *sc_qec; /* QEC parent */ 120 121 bus_space_handle_t sc_qr; /* QEC registers */ 122 bus_space_handle_t sc_br; /* BE registers */ 123 bus_space_handle_t sc_cr; /* channel registers */ 124 bus_space_handle_t sc_tr; /* transceiver registers */ 125 126 u_int sc_rev; 127 128 int sc_channel; /* channel number */ 129 int sc_burst; 130 131 struct qec_ring sc_rb; /* Packet Ring Buffer */ 132 }; 133 134 int bematch(struct device *, void *, void *); 135 void beattach(struct device *, struct device *, void *); 136 137 void beinit(struct be_softc *); 138 void bestart(struct ifnet *); 139 void bestop(struct be_softc *); 140 void bewatchdog(struct ifnet *); 141 int beioctl(struct ifnet *, u_long, caddr_t); 142 void bereset(struct be_softc *); 143 144 int beintr(void *); 145 int berint(struct be_softc *); 146 int betint(struct be_softc *); 147 int beqint(struct be_softc *, u_int32_t); 148 int beeint(struct be_softc *, u_int32_t); 149 150 static void be_read(struct be_softc *, int, int); 151 static int be_put(struct be_softc *, int, struct mbuf *); 152 static struct mbuf *be_get(struct be_softc *, int, int); 153 154 void be_pal_gate(struct be_softc *, int); 155 156 /* ifmedia callbacks */ 157 void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 158 int be_ifmedia_upd(struct ifnet *); 159 160 void be_mcreset(struct be_softc *); 161 162 /* MII methods & callbacks */ 163 static int be_mii_readreg(struct device *, int, int); 164 static void be_mii_writereg(struct device *, int, int, int); 165 static void be_mii_statchg(struct device *); 166 167 /* MII helpers */ 168 static void be_mii_sync(struct be_softc *); 169 static void be_mii_sendbits(struct be_softc *, int, u_int32_t, int); 170 static int be_mii_reset(struct be_softc *, int); 171 static int be_tcvr_read_bit(struct be_softc *, int); 172 static void be_tcvr_write_bit(struct be_softc *, int, int); 173 174 void be_tick(void *); 175 void be_intphy_auto(struct be_softc *); 176 void be_intphy_status(struct be_softc *); 177 int be_intphy_service(struct be_softc *, struct mii_data *, int); 178 179 180 struct cfattach be_ca = { 181 sizeof(struct be_softc), bematch, beattach 182 }; 183 184 struct cfdriver be_cd = { 185 NULL, "be", DV_IFNET 186 }; 187 188 int 189 bematch(struct device *parent, void *vcf, void *aux) 190 { 191 struct cfdata *cf = vcf; 192 struct sbus_attach_args *sa = aux; 193 194 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 195 } 196 197 void 198 beattach(struct device *parent, struct device *self, void *aux) 199 { 200 struct sbus_attach_args *sa = aux; 201 struct qec_softc *qec = (struct qec_softc *)parent; 202 struct be_softc *sc = (struct be_softc *)self; 203 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 204 struct mii_data *mii = &sc->sc_mii; 205 struct mii_softc *child; 206 int node = sa->sa_node; 207 bus_dma_tag_t dmatag = sa->sa_dmatag; 208 bus_dma_segment_t seg; 209 bus_size_t size; 210 uint64_t instance; 211 int rseg, error; 212 u_int32_t v; 213 extern void myetheraddr(u_char *); 214 215 /* Pass on the bus tags */ 216 sc->sc_bustag = sa->sa_bustag; 217 sc->sc_dmatag = sa->sa_dmatag; 218 219 if (sa->sa_nreg < 3) { 220 printf("%s: only %d register sets\n", 221 self->dv_xname, sa->sa_nreg); 222 return; 223 } 224 225 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, 226 (bus_addr_t)sa->sa_reg[0].sbr_offset, 227 (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0, &sc->sc_cr) != 0) { 228 printf("beattach: cannot map registers\n"); 229 return; 230 } 231 232 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot, 233 (bus_addr_t)sa->sa_reg[1].sbr_offset, 234 (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0, &sc->sc_br) != 0) { 235 printf("beattach: cannot map registers\n"); 236 return; 237 } 238 239 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[2].sbr_slot, 240 (bus_addr_t)sa->sa_reg[2].sbr_offset, 241 (bus_size_t)sa->sa_reg[2].sbr_size, 0, 0, &sc->sc_tr) != 0) { 242 printf("beattach: cannot map registers\n"); 243 return; 244 } 245 246 sc->sc_qec = qec; 247 sc->sc_qr = qec->sc_regs; 248 249 sc->sc_rev = getpropint(node, "board-version", -1); 250 printf(" rev %x", sc->sc_rev); 251 252 bestop(sc); 253 254 sc->sc_channel = getpropint(node, "channel#", -1); 255 if (sc->sc_channel == -1) 256 sc->sc_channel = 0; 257 258 sc->sc_burst = getpropint(node, "burst-sizes", -1); 259 if (sc->sc_burst == -1) 260 sc->sc_burst = qec->sc_burst; 261 262 /* Clamp at parent's burst sizes */ 263 sc->sc_burst &= qec->sc_burst; 264 265 /* Establish interrupt handler */ 266 if (sa->sa_nintr == 0 || bus_intr_establish(sa->sa_bustag, sa->sa_pri, 267 IPL_NET, 0, beintr, sc, self->dv_xname) == NULL) { 268 printf(": no interrupt established\n"); 269 return; 270 } 271 272 myetheraddr(sc->sc_arpcom.ac_enaddr); 273 printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 274 275 /* 276 * Allocate descriptor ring and buffers. 277 */ 278 279 /* for now, allocate as many bufs as there are ring descriptors */ 280 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 281 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 282 283 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 284 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 285 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 286 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 287 288 /* Get a DMA handle */ 289 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 290 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 291 printf("%s: DMA map create error %d\n", self->dv_xname, error); 292 return; 293 } 294 295 /* Allocate DMA buffer */ 296 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 297 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 298 printf("%s: DMA buffer alloc error %d\n", 299 self->dv_xname, error); 300 return; 301 } 302 303 /* Map DMA memory in CPU addressable space */ 304 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 305 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 306 printf("%s: DMA buffer map error %d\n", 307 self->dv_xname, error); 308 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 309 return; 310 } 311 312 /* Load the buffer */ 313 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 314 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 315 printf("%s: DMA buffer map load error %d\n", 316 self->dv_xname, error); 317 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 318 bus_dmamem_free(dmatag, &seg, rseg); 319 return; 320 } 321 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 322 323 /* 324 * Initialize our media structures and MII info. 325 */ 326 mii->mii_ifp = ifp; 327 mii->mii_readreg = be_mii_readreg; 328 mii->mii_writereg = be_mii_writereg; 329 mii->mii_statchg = be_mii_statchg; 330 331 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 332 333 timeout_set(&sc->sc_tick_ch, be_tick, sc); 334 335 /* 336 * Initialize transceiver and determine which PHY connection to use. 337 */ 338 be_mii_sync(sc); 339 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 340 341 instance = 0; 342 343 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 344 345 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 346 MII_OFFSET_ANY, 0); 347 348 child = LIST_FIRST(&mii->mii_phys); 349 if (child == NULL) { 350 /* No PHY attached */ 351 ifmedia_add(&sc->sc_media, 352 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 353 0, NULL); 354 ifmedia_set(&sc->sc_media, 355 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 356 } else { 357 /* 358 * Note: we support just one PHY on the external 359 * MII connector. 360 */ 361 #ifdef DIAGNOSTIC 362 if (LIST_NEXT(child, mii_list) != NULL) { 363 printf("%s: spurious MII device %s attached\n", 364 sc->sc_dev.dv_xname, 365 child->mii_dev.dv_xname); 366 } 367 #endif 368 if (child->mii_phy != BE_PHY_EXTERNAL || 369 child->mii_inst > 0) { 370 printf("%s: cannot accommodate MII device %s" 371 " at phy %d, instance %lld\n", 372 sc->sc_dev.dv_xname, 373 child->mii_dev.dv_xname, 374 child->mii_phy, child->mii_inst); 375 } else { 376 sc->sc_phys[instance] = child->mii_phy; 377 } 378 379 /* 380 * XXX - we can really do the following ONLY if the 381 * phy indeed has the auto negotiation capability!! 382 */ 383 ifmedia_set(&sc->sc_media, 384 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 385 386 /* Mark our current media setting */ 387 be_pal_gate(sc, BE_PHY_EXTERNAL); 388 instance++; 389 } 390 391 } 392 393 if ((v & MGMT_PAL_INT_MDIO) != 0) { 394 /* 395 * The be internal phy looks vaguely like MII hardware, 396 * but not enough to be able to use the MII device 397 * layer. Hence, we have to take care of media selection 398 * ourselves. 399 */ 400 401 sc->sc_mii_inst = instance; 402 sc->sc_phys[instance] = BE_PHY_INTERNAL; 403 404 /* Use `ifm_data' to store BMCR bits */ 405 ifmedia_add(&sc->sc_media, 406 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 0, NULL); 407 ifmedia_add(&sc->sc_media, 408 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 409 BMCR_S100, NULL); 410 ifmedia_add(&sc->sc_media, 411 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 0, NULL); 412 413 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 414 self->dv_xname); 415 416 be_mii_reset(sc, BE_PHY_INTERNAL); 417 /* Only set default medium here if there's no external PHY */ 418 if (instance == 0) { 419 be_pal_gate(sc, BE_PHY_INTERNAL); 420 ifmedia_set(&sc->sc_media, 421 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 422 } else 423 be_mii_writereg((void *)sc, 424 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 425 } 426 427 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 428 ifp->if_softc = sc; 429 ifp->if_start = bestart; 430 ifp->if_ioctl = beioctl; 431 ifp->if_watchdog = bewatchdog; 432 ifp->if_flags = 433 IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 434 435 /* Attach the interface. */ 436 if_attach(ifp); 437 ether_ifattach(ifp); 438 } 439 440 441 /* 442 * Routine to copy from mbuf chain to transmit buffer in 443 * network buffer memory. 444 */ 445 static __inline__ int 446 be_put(struct be_softc *sc, int idx, struct mbuf *m) 447 { 448 struct mbuf *n; 449 int len, tlen = 0, boff = 0; 450 caddr_t bp; 451 452 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 453 454 for (; m; m = n) { 455 len = m->m_len; 456 if (len == 0) { 457 n = m_free(m); 458 continue; 459 } 460 bcopy(mtod(m, caddr_t), bp+boff, len); 461 boff += len; 462 tlen += len; 463 n = m_free(m); 464 } 465 return (tlen); 466 } 467 468 /* 469 * Pull data off an interface. 470 * Len is the length of data, with local net header stripped. 471 * We copy the data into mbufs. When full cluster sized units are present, 472 * we copy into clusters. 473 */ 474 static __inline__ struct mbuf * 475 be_get(struct be_softc *sc, int idx, int totlen) 476 { 477 struct mbuf *m; 478 struct mbuf *top, **mp; 479 int len, pad, boff = 0; 480 caddr_t bp; 481 482 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 483 484 MGETHDR(m, M_DONTWAIT, MT_DATA); 485 if (m == NULL) 486 return (NULL); 487 m->m_pkthdr.len = totlen; 488 489 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 490 m->m_data += pad; 491 len = MHLEN - pad; 492 top = NULL; 493 mp = ⊤ 494 495 while (totlen > 0) { 496 if (top) { 497 MGET(m, M_DONTWAIT, MT_DATA); 498 if (m == NULL) { 499 m_freem(top); 500 return (NULL); 501 } 502 len = MLEN; 503 } 504 if (top && totlen >= MINCLSIZE) { 505 MCLGET(m, M_DONTWAIT); 506 if (m->m_flags & M_EXT) 507 len = MCLBYTES; 508 } 509 m->m_len = len = min(totlen, len); 510 bcopy(bp + boff, mtod(m, caddr_t), len); 511 boff += len; 512 totlen -= len; 513 *mp = m; 514 mp = &m->m_next; 515 } 516 517 return (top); 518 } 519 520 /* 521 * Pass a packet to the higher levels. 522 */ 523 static __inline__ void 524 be_read(struct be_softc *sc, int idx, int len) 525 { 526 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 527 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 528 struct mbuf *m; 529 530 if (len <= sizeof(struct ether_header) || 531 len > ETHERMTU + sizeof(struct ether_header)) { 532 533 printf("%s: invalid packet size %d; dropping\n", 534 ifp->if_xname, len); 535 536 ifp->if_ierrors++; 537 return; 538 } 539 540 /* 541 * Pull packet off interface. 542 */ 543 m = be_get(sc, idx, len); 544 if (m == NULL) { 545 ifp->if_ierrors++; 546 return; 547 } 548 549 ml_enqueue(&ml, m); 550 if_input(ifp, &ml); 551 } 552 553 /* 554 * Start output on interface. 555 * We make two assumptions here: 556 * 1) that the current priority is set to splnet _before_ this code 557 * is called *and* is returned to the appropriate priority after 558 * return 559 * 2) that the IFF_OACTIVE flag is checked before this code is called 560 * (i.e. that the output part of the interface is idle) 561 */ 562 void 563 bestart(struct ifnet *ifp) 564 { 565 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 566 struct qec_xd *txd = sc->sc_rb.rb_txd; 567 struct mbuf *m; 568 unsigned int bix, len; 569 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 570 571 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 572 return; 573 574 bix = sc->sc_rb.rb_tdhead; 575 576 for (;;) { 577 IFQ_DEQUEUE(&ifp->if_snd, m); 578 if (m == NULL) 579 break; 580 581 #if NBPFILTER > 0 582 /* 583 * If BPF is listening on this interface, let it see the 584 * packet before we commit it to the wire. 585 */ 586 if (ifp->if_bpf) 587 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 588 #endif 589 590 /* 591 * Copy the mbuf chain into the transmit buffer. 592 */ 593 len = be_put(sc, bix, m); 594 595 /* 596 * Initialize transmit registers and start transmission 597 */ 598 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 599 (len & QEC_XD_LENGTH); 600 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 601 BE_CR_CTRL_TWAKEUP); 602 603 if (++bix == QEC_XD_RING_MAXSIZE) 604 bix = 0; 605 606 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 607 ifq_set_oactive(&ifp->if_snd); 608 break; 609 } 610 } 611 612 sc->sc_rb.rb_tdhead = bix; 613 } 614 615 void 616 bestop(struct be_softc *sc) 617 { 618 int n; 619 bus_space_tag_t t = sc->sc_bustag; 620 bus_space_handle_t br = sc->sc_br; 621 622 timeout_del(&sc->sc_tick_ch); 623 624 /* Down the MII. */ 625 mii_down(&sc->sc_mii); 626 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 627 628 /* Stop the transmitter */ 629 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 630 for (n = 32; n > 0; n--) { 631 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 632 break; 633 DELAY(20); 634 } 635 636 /* Stop the receiver */ 637 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 638 for (n = 32; n > 0; n--) { 639 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 640 break; 641 DELAY(20); 642 } 643 } 644 645 /* 646 * Reset interface. 647 */ 648 void 649 bereset(struct be_softc *sc) 650 { 651 int s; 652 653 s = splnet(); 654 bestop(sc); 655 if ((sc->sc_arpcom.ac_if.if_flags & IFF_UP) != 0) 656 beinit(sc); 657 splx(s); 658 } 659 660 void 661 bewatchdog(struct ifnet *ifp) 662 { 663 struct be_softc *sc = ifp->if_softc; 664 665 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 666 ++sc->sc_arpcom.ac_if.if_oerrors; 667 bereset(sc); 668 } 669 670 int 671 beintr(void *v) 672 { 673 struct be_softc *sc = (struct be_softc *)v; 674 bus_space_tag_t t = sc->sc_bustag; 675 u_int32_t whyq, whyb, whyc; 676 int r = 0; 677 678 /* Read QEC status, channel status and BE status */ 679 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 680 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 681 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 682 683 if (whyq & QEC_STAT_BM) 684 r |= beeint(sc, whyb); 685 686 if (whyq & QEC_STAT_ER) 687 r |= beqint(sc, whyc); 688 689 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 690 r |= betint(sc); 691 692 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 693 r |= berint(sc); 694 695 return (r); 696 } 697 698 /* 699 * QEC Interrupt. 700 */ 701 int 702 beqint(struct be_softc *sc, u_int32_t why) 703 { 704 int r = 0, rst = 0; 705 706 if (why & BE_CR_STAT_TXIRQ) 707 r |= 1; 708 if (why & BE_CR_STAT_RXIRQ) 709 r |= 1; 710 711 if (why & BE_CR_STAT_BERROR) { 712 r |= 1; 713 rst = 1; 714 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 715 } 716 717 if (why & BE_CR_STAT_TXDERR) { 718 r |= 1; 719 rst = 1; 720 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 721 } 722 723 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 724 r |= 1; 725 rst = 1; 726 printf("%s: tx dma error ( ", sc->sc_dev.dv_xname); 727 if (why & BE_CR_STAT_TXLERR) 728 printf("Late "); 729 if (why & BE_CR_STAT_TXPERR) 730 printf("Parity "); 731 if (why & BE_CR_STAT_TXSERR) 732 printf("Generic "); 733 printf(")\n"); 734 } 735 736 if (why & BE_CR_STAT_RXDROP) { 737 r |= 1; 738 rst = 1; 739 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 740 } 741 742 if (why & BE_CR_STAT_RXSMALL) { 743 r |= 1; 744 rst = 1; 745 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 746 } 747 748 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 749 r |= 1; 750 rst = 1; 751 printf("%s: rx dma error ( ", sc->sc_dev.dv_xname); 752 if (why & BE_CR_STAT_RXLERR) 753 printf("Late "); 754 if (why & BE_CR_STAT_RXPERR) 755 printf("Parity "); 756 if (why & BE_CR_STAT_RXSERR) 757 printf("Generic "); 758 printf(")\n"); 759 } 760 761 if (!r) { 762 rst = 1; 763 printf("%s: unexpected error interrupt %08x\n", 764 sc->sc_dev.dv_xname, why); 765 } 766 767 if (rst) { 768 printf("%s: resetting\n", sc->sc_dev.dv_xname); 769 bereset(sc); 770 } 771 772 return (r); 773 } 774 775 /* 776 * Error interrupt. 777 */ 778 int 779 beeint(struct be_softc *sc, u_int32_t why) 780 { 781 int r = 0, rst = 0; 782 783 if (why & BE_BR_STAT_RFIFOVF) { 784 r |= 1; 785 rst = 1; 786 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 787 } 788 if (why & BE_BR_STAT_TFIFO_UND) { 789 r |= 1; 790 rst = 1; 791 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 792 } 793 if (why & BE_BR_STAT_MAXPKTERR) { 794 r |= 1; 795 rst = 1; 796 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 797 } 798 799 if (!r) { 800 rst = 1; 801 printf("%s: unexpected error interrupt %08x\n", 802 sc->sc_dev.dv_xname, why); 803 } 804 805 if (rst) { 806 printf("%s: resetting\n", sc->sc_dev.dv_xname); 807 bereset(sc); 808 } 809 810 return (r); 811 } 812 813 /* 814 * Transmit interrupt. 815 */ 816 int 817 betint(struct be_softc *sc) 818 { 819 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 820 bus_space_tag_t t = sc->sc_bustag; 821 bus_space_handle_t br = sc->sc_br; 822 unsigned int bix, txflags; 823 824 /* 825 * Unload collision counters 826 */ 827 ifp->if_collisions += 828 bus_space_read_4(t, br, BE_BRI_NCCNT) + 829 bus_space_read_4(t, br, BE_BRI_FCCNT) + 830 bus_space_read_4(t, br, BE_BRI_EXCNT) + 831 bus_space_read_4(t, br, BE_BRI_LTCNT); 832 833 /* 834 * the clear the hardware counters 835 */ 836 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 837 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 838 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 839 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 840 841 bix = sc->sc_rb.rb_tdtail; 842 843 for (;;) { 844 if (sc->sc_rb.rb_td_nbusy <= 0) 845 break; 846 847 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 848 849 if (txflags & QEC_XD_OWN) 850 break; 851 852 ifq_clr_oactive(&ifp->if_snd); 853 ifp->if_opackets++; 854 855 if (++bix == QEC_XD_RING_MAXSIZE) 856 bix = 0; 857 858 --sc->sc_rb.rb_td_nbusy; 859 } 860 861 sc->sc_rb.rb_tdtail = bix; 862 863 bestart(ifp); 864 865 if (sc->sc_rb.rb_td_nbusy == 0) 866 ifp->if_timer = 0; 867 868 return (1); 869 } 870 871 /* 872 * Receive interrupt. 873 */ 874 int 875 berint(struct be_softc *sc) 876 { 877 struct qec_xd *xd = sc->sc_rb.rb_rxd; 878 unsigned int bix, len; 879 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 880 881 bix = sc->sc_rb.rb_rdtail; 882 883 /* 884 * Process all buffers with valid data. 885 */ 886 for (;;) { 887 len = xd[bix].xd_flags; 888 if (len & QEC_XD_OWN) 889 break; 890 891 len &= QEC_XD_LENGTH; 892 be_read(sc, bix, len); 893 894 /* ... */ 895 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 896 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 897 898 if (++bix == QEC_XD_RING_MAXSIZE) 899 bix = 0; 900 } 901 902 sc->sc_rb.rb_rdtail = bix; 903 904 return (1); 905 } 906 907 int 908 beioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 909 { 910 struct be_softc *sc = ifp->if_softc; 911 struct ifreq *ifr = (struct ifreq *)data; 912 int s, error = 0; 913 914 s = splnet(); 915 916 switch (cmd) { 917 case SIOCSIFADDR: 918 ifp->if_flags |= IFF_UP; 919 beinit(sc); 920 break; 921 922 case SIOCSIFFLAGS: 923 if ((ifp->if_flags & IFF_UP) == 0 && 924 (ifp->if_flags & IFF_RUNNING) != 0) { 925 /* 926 * If interface is marked down and it is running, then 927 * stop it. 928 */ 929 bestop(sc); 930 ifp->if_flags &= ~IFF_RUNNING; 931 } else if ((ifp->if_flags & IFF_UP) != 0 && 932 (ifp->if_flags & IFF_RUNNING) == 0) { 933 /* 934 * If interface is marked up and it is stopped, then 935 * start it. 936 */ 937 beinit(sc); 938 } else { 939 /* 940 * Reset the interface to pick up changes in any other 941 * flags that affect hardware registers. 942 */ 943 bestop(sc); 944 beinit(sc); 945 } 946 #ifdef BEDEBUG 947 if (ifp->if_flags & IFF_DEBUG) 948 sc->sc_debug = 1; 949 else 950 sc->sc_debug = 0; 951 #endif 952 break; 953 954 case SIOCGIFMEDIA: 955 case SIOCSIFMEDIA: 956 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 957 break; 958 959 default: 960 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 961 } 962 963 if (error == ENETRESET) { 964 if (ifp->if_flags & IFF_RUNNING) 965 be_mcreset(sc); 966 error = 0; 967 } 968 969 splx(s); 970 return (error); 971 } 972 973 974 void 975 beinit(struct be_softc *sc) 976 { 977 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 978 bus_space_tag_t t = sc->sc_bustag; 979 bus_space_handle_t br = sc->sc_br; 980 bus_space_handle_t cr = sc->sc_cr; 981 struct qec_softc *qec = sc->sc_qec; 982 u_int32_t v; 983 u_int32_t qecaddr; 984 u_int8_t *ea; 985 int s; 986 987 s = splnet(); 988 989 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 990 991 bestop(sc); 992 993 ea = sc->sc_arpcom.ac_enaddr; 994 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 995 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 996 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 997 998 /* Clear hash table */ 999 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1000 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1001 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1002 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1003 1004 /* Re-initialize RX configuration */ 1005 v = BE_BR_RXCFG_FIFO; 1006 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1007 1008 be_mcreset(sc); 1009 1010 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1011 1012 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1013 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1014 1015 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1016 1017 /* 1018 * Turn off counter expiration interrupts as well as 1019 * 'gotframe' and 'sentframe' 1020 */ 1021 bus_space_write_4(t, br, BE_BRI_IMASK, 1022 BE_BR_IMASK_GOTFRAME | 1023 BE_BR_IMASK_RCNTEXP | 1024 BE_BR_IMASK_ACNTEXP | 1025 BE_BR_IMASK_CCNTEXP | 1026 BE_BR_IMASK_LCNTEXP | 1027 BE_BR_IMASK_CVCNTEXP | 1028 BE_BR_IMASK_SENTFRAME | 1029 BE_BR_IMASK_NCNTEXP | 1030 BE_BR_IMASK_ECNTEXP | 1031 BE_BR_IMASK_LCCNTEXP | 1032 BE_BR_IMASK_FCNTEXP | 1033 BE_BR_IMASK_DTIMEXP); 1034 1035 /* Channel registers: */ 1036 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1037 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1038 1039 qecaddr = sc->sc_channel * qec->sc_msize; 1040 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1041 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1042 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1043 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1044 1045 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1046 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1047 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1048 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1049 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1050 1051 /* Enable transmitter */ 1052 bus_space_write_4(t, br, BE_BRI_TXCFG, 1053 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1054 1055 /* Enable receiver */ 1056 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1057 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1058 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1059 1060 ifp->if_flags |= IFF_RUNNING; 1061 ifq_clr_oactive(&ifp->if_snd); 1062 1063 be_ifmedia_upd(ifp); 1064 timeout_add_sec(&sc->sc_tick_ch, 1); 1065 splx(s); 1066 } 1067 1068 void 1069 be_mcreset(struct be_softc *sc) 1070 { 1071 struct arpcom *ac = &sc->sc_arpcom; 1072 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1073 bus_space_tag_t t = sc->sc_bustag; 1074 bus_space_handle_t br = sc->sc_br; 1075 u_int32_t crc; 1076 u_int16_t hash[4]; 1077 u_int8_t octet; 1078 u_int32_t v; 1079 int i, j; 1080 struct ether_multi *enm; 1081 struct ether_multistep step; 1082 1083 if (ifp->if_flags & IFF_PROMISC) { 1084 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1085 v |= BE_BR_RXCFG_PMISC; 1086 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1087 return; 1088 } 1089 1090 if (ac->ac_multirangecnt > 0) 1091 ifp->if_flags |= IFF_ALLMULTI; 1092 1093 if (ifp->if_flags & IFF_ALLMULTI) { 1094 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1095 goto chipit; 1096 } 1097 1098 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1099 1100 ETHER_FIRST_MULTI(step, ac, enm); 1101 while (enm != NULL) { 1102 crc = 0xffffffff; 1103 1104 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1105 octet = enm->enm_addrlo[i]; 1106 1107 for (j = 0; j < 8; j++) { 1108 if ((crc & 1) ^ (octet & 1)) { 1109 crc >>= 1; 1110 crc ^= MC_POLY_LE; 1111 } 1112 else 1113 crc >>= 1; 1114 octet >>= 1; 1115 } 1116 } 1117 1118 crc >>= 26; 1119 hash[crc >> 4] |= 1 << (crc & 0xf); 1120 ETHER_NEXT_MULTI(step, enm); 1121 } 1122 1123 ifp->if_flags &= ~IFF_ALLMULTI; 1124 1125 chipit: 1126 /* Enable the hash filter */ 1127 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1128 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1129 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1130 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1131 1132 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1133 v &= ~BE_BR_RXCFG_PMISC; 1134 v |= BE_BR_RXCFG_HENABLE; 1135 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1136 } 1137 1138 /* 1139 * Set the tcvr to an idle state 1140 */ 1141 void 1142 be_mii_sync(struct be_softc *sc) 1143 { 1144 bus_space_tag_t t = sc->sc_bustag; 1145 bus_space_handle_t tr = sc->sc_tr; 1146 int n = 32; 1147 1148 while (n--) { 1149 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1150 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1151 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1152 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1153 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1154 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1155 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1156 } 1157 } 1158 1159 void 1160 be_pal_gate(struct be_softc *sc, int phy) 1161 { 1162 bus_space_tag_t t = sc->sc_bustag; 1163 bus_space_handle_t tr = sc->sc_tr; 1164 u_int32_t v; 1165 1166 be_mii_sync(sc); 1167 1168 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1169 if (phy == BE_PHY_INTERNAL) 1170 v &= ~TCVR_PAL_SERIAL; 1171 1172 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1173 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1174 } 1175 1176 static int 1177 be_tcvr_read_bit(struct be_softc *sc, int phy) 1178 { 1179 bus_space_tag_t t = sc->sc_bustag; 1180 bus_space_handle_t tr = sc->sc_tr; 1181 int ret; 1182 1183 if (phy == BE_PHY_INTERNAL) { 1184 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1185 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1186 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1187 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1188 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1189 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1190 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1191 } else { 1192 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1193 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1194 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1195 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1196 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1197 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1198 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1199 } 1200 1201 return (ret); 1202 } 1203 1204 static void 1205 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1206 { 1207 bus_space_tag_t t = sc->sc_bustag; 1208 bus_space_handle_t tr = sc->sc_tr; 1209 u_int32_t v; 1210 1211 if (phy == BE_PHY_INTERNAL) { 1212 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1213 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1214 } else { 1215 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1216 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1217 } 1218 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1219 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1220 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1221 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1222 } 1223 1224 static void 1225 be_mii_sendbits(struct be_softc *sc, int phy, u_int32_t data, int nbits) 1226 { 1227 int i; 1228 1229 for (i = 1 << (nbits - 1); i != 0; i >>= 1) 1230 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1231 } 1232 1233 static int 1234 be_mii_readreg(struct device *self, int phy, int reg) 1235 { 1236 struct be_softc *sc = (struct be_softc *)self; 1237 int val = 0, i; 1238 1239 /* 1240 * Read the PHY register by manually driving the MII control lines. 1241 */ 1242 be_mii_sync(sc); 1243 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1244 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1245 be_mii_sendbits(sc, phy, phy, 5); 1246 be_mii_sendbits(sc, phy, reg, 5); 1247 1248 (void) be_tcvr_read_bit(sc, phy); 1249 (void) be_tcvr_read_bit(sc, phy); 1250 1251 for (i = 15; i >= 0; i--) 1252 val |= (be_tcvr_read_bit(sc, phy) << i); 1253 1254 (void) be_tcvr_read_bit(sc, phy); 1255 (void) be_tcvr_read_bit(sc, phy); 1256 (void) be_tcvr_read_bit(sc, phy); 1257 1258 return (val); 1259 } 1260 1261 void 1262 be_mii_writereg(struct device *self, int phy, int reg, int val) 1263 { 1264 struct be_softc *sc = (struct be_softc *)self; 1265 int i; 1266 1267 /* 1268 * Write the PHY register by manually driving the MII control lines. 1269 */ 1270 be_mii_sync(sc); 1271 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1272 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1273 be_mii_sendbits(sc, phy, phy, 5); 1274 be_mii_sendbits(sc, phy, reg, 5); 1275 1276 be_tcvr_write_bit(sc, phy, 1); 1277 be_tcvr_write_bit(sc, phy, 0); 1278 1279 for (i = 15; i >= 0; i--) 1280 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1281 } 1282 1283 int 1284 be_mii_reset(struct be_softc *sc, int phy) 1285 { 1286 int n; 1287 1288 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1289 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1290 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1291 1292 for (n = 16; n >= 0; n--) { 1293 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1294 if ((bmcr & BMCR_RESET) == 0) 1295 break; 1296 DELAY(20); 1297 } 1298 if (n == 0) { 1299 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1300 return (EIO); 1301 } 1302 1303 return (0); 1304 } 1305 1306 void 1307 be_tick(void *arg) 1308 { 1309 struct be_softc *sc = arg; 1310 int s = splnet(); 1311 1312 mii_tick(&sc->sc_mii); 1313 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1314 1315 timeout_add_sec(&sc->sc_tick_ch, 1); 1316 splx(s); 1317 } 1318 1319 void 1320 be_mii_statchg(struct device *self) 1321 { 1322 struct be_softc *sc = (struct be_softc *)self; 1323 bus_space_tag_t t = sc->sc_bustag; 1324 bus_space_handle_t br = sc->sc_br; 1325 u_int64_t instance; 1326 u_int32_t v; 1327 1328 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1329 #ifdef DIAGNOSTIC 1330 if (instance > 1) 1331 panic("be_mii_statchg: instance %lld out of range", instance); 1332 #endif 1333 1334 /* Update duplex mode in TX configuration */ 1335 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1336 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1337 v |= BE_BR_TXCFG_FULLDPLX; 1338 else 1339 v &= ~BE_BR_TXCFG_FULLDPLX; 1340 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1341 1342 /* Change to appropriate gate in transceiver PAL */ 1343 be_pal_gate(sc, sc->sc_phys[instance]); 1344 } 1345 1346 /* 1347 * Get current media settings. 1348 */ 1349 void 1350 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1351 { 1352 struct be_softc *sc = ifp->if_softc; 1353 1354 mii_pollstat(&sc->sc_mii); 1355 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1356 1357 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1358 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1359 return; 1360 } 1361 1362 /* 1363 * Set media options. 1364 */ 1365 int 1366 be_ifmedia_upd(struct ifnet *ifp) 1367 { 1368 struct be_softc *sc = ifp->if_softc; 1369 int error; 1370 1371 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1372 return (error); 1373 1374 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1375 } 1376 1377 /* 1378 * Service routine for our pseudo-MII internal transceiver. 1379 */ 1380 int 1381 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1382 { 1383 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1384 int bmcr, bmsr; 1385 int error; 1386 1387 switch (cmd) { 1388 case MII_POLLSTAT: 1389 /* 1390 * If we're not polling our PHY instance, just return. 1391 */ 1392 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1393 return (0); 1394 1395 break; 1396 1397 case MII_MEDIACHG: 1398 1399 /* 1400 * If the media indicates a different PHY instance, 1401 * isolate ourselves. 1402 */ 1403 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1404 bmcr = be_mii_readreg((void *)sc, 1405 BE_PHY_INTERNAL, MII_BMCR); 1406 be_mii_writereg((void *)sc, 1407 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1408 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1409 sc->sc_intphy_curspeed = 0; 1410 return (0); 1411 } 1412 1413 1414 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1415 return (error); 1416 1417 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1418 1419 /* 1420 * Select the new mode and take out of isolation 1421 */ 1422 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1423 bmcr |= BMCR_S100; 1424 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1425 bmcr &= ~BMCR_S100; 1426 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1427 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1428 bmcr &= ~BMCR_S100; 1429 bmcr |= sc->sc_intphy_curspeed; 1430 } else { 1431 /* Keep isolated until link is up */ 1432 bmcr |= BMCR_ISO; 1433 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1434 } 1435 } 1436 1437 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1438 bmcr |= BMCR_FDX; 1439 else 1440 bmcr &= ~BMCR_FDX; 1441 1442 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1443 break; 1444 1445 case MII_TICK: 1446 /* 1447 * If we're not currently selected, just return. 1448 */ 1449 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1450 return (0); 1451 1452 /* Only used for automatic media selection */ 1453 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1454 return (0); 1455 1456 /* Is the interface even up? */ 1457 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1458 return (0); 1459 1460 /* 1461 * Check link status; if we don't have a link, try another 1462 * speed. We can't detect duplex mode, so half-duplex is 1463 * what we have to settle for. 1464 */ 1465 1466 /* Read twice in case the register is latched */ 1467 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1468 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1469 1470 if ((bmsr & BMSR_LINK) != 0) { 1471 /* We have a carrier */ 1472 bmcr = be_mii_readreg((void *)sc, 1473 BE_PHY_INTERNAL, MII_BMCR); 1474 1475 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1476 bmcr = be_mii_readreg((void *)sc, 1477 BE_PHY_INTERNAL, MII_BMCR); 1478 1479 sc->sc_mii_flags |= MIIF_HAVELINK; 1480 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1481 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1482 1483 bmcr &= ~BMCR_ISO; 1484 be_mii_writereg((void *)sc, 1485 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1486 1487 printf("%s: link up at %s Mbps\n", 1488 sc->sc_dev.dv_xname, 1489 (bmcr & BMCR_S100) ? "100" : "10"); 1490 } 1491 sc->sc_mii_ticks = 0; 1492 return (0); 1493 } 1494 1495 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1496 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1497 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1498 sc->sc_intphy_curspeed = 0; 1499 printf("%s: link down\n", sc->sc_dev.dv_xname); 1500 } 1501 1502 /* Only retry autonegotiation every 5 seconds. */ 1503 if (++sc->sc_mii_ticks < 5) 1504 return(0); 1505 1506 sc->sc_mii_ticks = 0; 1507 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1508 /* Just flip the fast speed bit */ 1509 bmcr ^= BMCR_S100; 1510 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1511 1512 break; 1513 1514 case MII_DOWN: 1515 /* Isolate this phy */ 1516 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1517 be_mii_writereg((void *)sc, 1518 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1519 return (0); 1520 } 1521 1522 /* Update the media status. */ 1523 be_intphy_status(sc); 1524 1525 /* Callback if something changed. */ 1526 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1527 (*mii->mii_statchg)((struct device *)sc); 1528 sc->sc_mii_active = mii->mii_media_active; 1529 } 1530 return (0); 1531 } 1532 1533 /* 1534 * Determine status of internal transceiver 1535 */ 1536 void 1537 be_intphy_status(struct be_softc *sc) 1538 { 1539 struct mii_data *mii = &sc->sc_mii; 1540 uint64_t media_active, media_status; 1541 int bmcr, bmsr; 1542 1543 media_status = IFM_AVALID; 1544 media_active = 0; 1545 1546 /* 1547 * Internal transceiver; do the work here. 1548 */ 1549 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1550 1551 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1552 case (BMCR_S100 | BMCR_FDX): 1553 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1554 break; 1555 case BMCR_S100: 1556 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1557 break; 1558 case BMCR_FDX: 1559 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1560 break; 1561 case 0: 1562 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1563 break; 1564 } 1565 1566 /* Read twice in case the register is latched */ 1567 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1568 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1569 if (bmsr & BMSR_LINK) 1570 media_status |= IFM_ACTIVE; 1571 1572 mii->mii_media_status = media_status; 1573 mii->mii_media_active = media_active; 1574 } 1575