1 /* $OpenBSD: be.c,v 1.26 2013/11/26 09:50:33 mpi Exp $ */ 2 /* $NetBSD: be.c,v 1.26 2001/03/20 15:39:20 pk Exp $ */ 3 4 /*- 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 */ 57 58 #include "bpfilter.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/timeout.h> 63 #include <sys/kernel.h> 64 #include <sys/errno.h> 65 #include <sys/ioctl.h> 66 #include <sys/mbuf.h> 67 #include <sys/socket.h> 68 #include <sys/syslog.h> 69 #include <sys/device.h> 70 #include <sys/malloc.h> 71 72 #include <net/if.h> 73 #include <net/if_dl.h> 74 #include <net/if_types.h> 75 #include <net/netisr.h> 76 #include <net/if_media.h> 77 78 #ifdef INET 79 #include <netinet/in.h> 80 #include <netinet/in_systm.h> 81 #include <netinet/ip.h> 82 #include <netinet/if_ether.h> 83 #endif 84 85 #if NBPFILTER > 0 86 #include <net/bpf.h> 87 #endif 88 89 #include <machine/bus.h> 90 #include <machine/intr.h> 91 #include <machine/autoconf.h> 92 93 #include <dev/sbus/sbusvar.h> 94 95 #include <dev/mii/mii.h> 96 #include <dev/mii/miivar.h> 97 98 #include <dev/sbus/qecreg.h> 99 #include <dev/sbus/qecvar.h> 100 #include <dev/sbus/bereg.h> 101 102 struct be_softc { 103 struct device sc_dev; 104 bus_space_tag_t sc_bustag; /* bus & dma tags */ 105 bus_dma_tag_t sc_dmatag; 106 bus_dmamap_t sc_dmamap; 107 struct arpcom sc_arpcom; 108 /*struct ifmedia sc_ifmedia; -* interface media */ 109 struct mii_data sc_mii; /* MII media control */ 110 #define sc_media sc_mii.mii_media/* shorthand */ 111 int sc_phys[2]; /* MII instance -> phy */ 112 113 struct timeout sc_tick_ch; 114 115 /* 116 * Some `mii_softc' items we need to emulate MII operation 117 * for our internal transceiver. 118 */ 119 int sc_mii_inst; /* instance of internal phy */ 120 int sc_mii_active; /* currently active medium */ 121 int sc_mii_ticks; /* tick counter */ 122 int sc_mii_flags; /* phy status flags */ 123 #define MIIF_HAVELINK 0x04000000 124 int sc_intphy_curspeed; /* Established link speed */ 125 126 struct qec_softc *sc_qec; /* QEC parent */ 127 128 bus_space_handle_t sc_qr; /* QEC registers */ 129 bus_space_handle_t sc_br; /* BE registers */ 130 bus_space_handle_t sc_cr; /* channel registers */ 131 bus_space_handle_t sc_tr; /* transceiver registers */ 132 133 u_int sc_rev; 134 135 int sc_channel; /* channel number */ 136 int sc_burst; 137 138 struct qec_ring sc_rb; /* Packet Ring Buffer */ 139 }; 140 141 int bematch(struct device *, void *, void *); 142 void beattach(struct device *, struct device *, void *); 143 144 void beinit(struct be_softc *); 145 void bestart(struct ifnet *); 146 void bestop(struct be_softc *); 147 void bewatchdog(struct ifnet *); 148 int beioctl(struct ifnet *, u_long, caddr_t); 149 void bereset(struct be_softc *); 150 151 int beintr(void *); 152 int berint(struct be_softc *); 153 int betint(struct be_softc *); 154 int beqint(struct be_softc *, u_int32_t); 155 int beeint(struct be_softc *, u_int32_t); 156 157 static void be_read(struct be_softc *, int, int); 158 static int be_put(struct be_softc *, int, struct mbuf *); 159 static struct mbuf *be_get(struct be_softc *, int, int); 160 161 void be_pal_gate(struct be_softc *, int); 162 163 /* ifmedia callbacks */ 164 void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 165 int be_ifmedia_upd(struct ifnet *); 166 167 void be_mcreset(struct be_softc *); 168 169 /* MII methods & callbacks */ 170 static int be_mii_readreg(struct device *, int, int); 171 static void be_mii_writereg(struct device *, int, int, int); 172 static void be_mii_statchg(struct device *); 173 174 /* MII helpers */ 175 static void be_mii_sync(struct be_softc *); 176 static void be_mii_sendbits(struct be_softc *, int, u_int32_t, int); 177 static int be_mii_reset(struct be_softc *, int); 178 static int be_tcvr_read_bit(struct be_softc *, int); 179 static void be_tcvr_write_bit(struct be_softc *, int, int); 180 181 void be_tick(void *); 182 void be_intphy_auto(struct be_softc *); 183 void be_intphy_status(struct be_softc *); 184 int be_intphy_service(struct be_softc *, struct mii_data *, int); 185 186 187 struct cfattach be_ca = { 188 sizeof(struct be_softc), bematch, beattach 189 }; 190 191 struct cfdriver be_cd = { 192 NULL, "be", DV_IFNET 193 }; 194 195 int 196 bematch(struct device *parent, void *vcf, void *aux) 197 { 198 struct cfdata *cf = vcf; 199 struct sbus_attach_args *sa = aux; 200 201 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 202 } 203 204 void 205 beattach(struct device *parent, struct device *self, void *aux) 206 { 207 struct sbus_attach_args *sa = aux; 208 struct qec_softc *qec = (struct qec_softc *)parent; 209 struct be_softc *sc = (struct be_softc *)self; 210 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 211 struct mii_data *mii = &sc->sc_mii; 212 struct mii_softc *child; 213 int node = sa->sa_node; 214 bus_dma_tag_t dmatag = sa->sa_dmatag; 215 bus_dma_segment_t seg; 216 bus_size_t size; 217 int instance; 218 int rseg, error; 219 u_int32_t v; 220 extern void myetheraddr(u_char *); 221 222 /* Pass on the bus tags */ 223 sc->sc_bustag = sa->sa_bustag; 224 sc->sc_dmatag = sa->sa_dmatag; 225 226 if (sa->sa_nreg < 3) { 227 printf("%s: only %d register sets\n", 228 self->dv_xname, sa->sa_nreg); 229 return; 230 } 231 232 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, 233 (bus_addr_t)sa->sa_reg[0].sbr_offset, 234 (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0, &sc->sc_cr) != 0) { 235 printf("beattach: cannot map registers\n"); 236 return; 237 } 238 239 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot, 240 (bus_addr_t)sa->sa_reg[1].sbr_offset, 241 (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0, &sc->sc_br) != 0) { 242 printf("beattach: cannot map registers\n"); 243 return; 244 } 245 246 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[2].sbr_slot, 247 (bus_addr_t)sa->sa_reg[2].sbr_offset, 248 (bus_size_t)sa->sa_reg[2].sbr_size, 0, 0, &sc->sc_tr) != 0) { 249 printf("beattach: cannot map registers\n"); 250 return; 251 } 252 253 sc->sc_qec = qec; 254 sc->sc_qr = qec->sc_regs; 255 256 sc->sc_rev = getpropint(node, "board-version", -1); 257 printf(" rev %x", sc->sc_rev); 258 259 bestop(sc); 260 261 sc->sc_channel = getpropint(node, "channel#", -1); 262 if (sc->sc_channel == -1) 263 sc->sc_channel = 0; 264 265 sc->sc_burst = getpropint(node, "burst-sizes", -1); 266 if (sc->sc_burst == -1) 267 sc->sc_burst = qec->sc_burst; 268 269 /* Clamp at parent's burst sizes */ 270 sc->sc_burst &= qec->sc_burst; 271 272 /* Establish interrupt handler */ 273 if (sa->sa_nintr == 0 || bus_intr_establish(sa->sa_bustag, sa->sa_pri, 274 IPL_NET, 0, beintr, sc, self->dv_xname) == NULL) { 275 printf(": no interrupt established\n"); 276 return; 277 } 278 279 myetheraddr(sc->sc_arpcom.ac_enaddr); 280 printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 281 282 /* 283 * Allocate descriptor ring and buffers. 284 */ 285 286 /* for now, allocate as many bufs as there are ring descriptors */ 287 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 288 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 289 290 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 291 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 292 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 293 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 294 295 /* Get a DMA handle */ 296 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 297 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 298 printf("%s: DMA map create error %d\n", self->dv_xname, error); 299 return; 300 } 301 302 /* Allocate DMA buffer */ 303 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 304 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 305 printf("%s: DMA buffer alloc error %d\n", 306 self->dv_xname, error); 307 return; 308 } 309 310 /* Map DMA memory in CPU addressable space */ 311 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 312 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 313 printf("%s: DMA buffer map error %d\n", 314 self->dv_xname, error); 315 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 316 return; 317 } 318 319 /* Load the buffer */ 320 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 321 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 322 printf("%s: DMA buffer map load error %d\n", 323 self->dv_xname, error); 324 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 325 bus_dmamem_free(dmatag, &seg, rseg); 326 return; 327 } 328 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 329 330 /* 331 * Initialize our media structures and MII info. 332 */ 333 mii->mii_ifp = ifp; 334 mii->mii_readreg = be_mii_readreg; 335 mii->mii_writereg = be_mii_writereg; 336 mii->mii_statchg = be_mii_statchg; 337 338 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 339 340 timeout_set(&sc->sc_tick_ch, be_tick, sc); 341 342 /* 343 * Initialize transceiver and determine which PHY connection to use. 344 */ 345 be_mii_sync(sc); 346 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 347 348 instance = 0; 349 350 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 351 352 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 353 MII_OFFSET_ANY, 0); 354 355 child = LIST_FIRST(&mii->mii_phys); 356 if (child == NULL) { 357 /* No PHY attached */ 358 ifmedia_add(&sc->sc_media, 359 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 360 0, NULL); 361 ifmedia_set(&sc->sc_media, 362 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 363 } else { 364 /* 365 * Note: we support just one PHY on the external 366 * MII connector. 367 */ 368 #ifdef DIAGNOSTIC 369 if (LIST_NEXT(child, mii_list) != NULL) { 370 printf("%s: spurious MII device %s attached\n", 371 sc->sc_dev.dv_xname, 372 child->mii_dev.dv_xname); 373 } 374 #endif 375 if (child->mii_phy != BE_PHY_EXTERNAL || 376 child->mii_inst > 0) { 377 printf("%s: cannot accommodate MII device %s" 378 " at phy %d, instance %d\n", 379 sc->sc_dev.dv_xname, 380 child->mii_dev.dv_xname, 381 child->mii_phy, child->mii_inst); 382 } else { 383 sc->sc_phys[instance] = child->mii_phy; 384 } 385 386 /* 387 * XXX - we can really do the following ONLY if the 388 * phy indeed has the auto negotiation capability!! 389 */ 390 ifmedia_set(&sc->sc_media, 391 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 392 393 /* Mark our current media setting */ 394 be_pal_gate(sc, BE_PHY_EXTERNAL); 395 instance++; 396 } 397 398 } 399 400 if ((v & MGMT_PAL_INT_MDIO) != 0) { 401 /* 402 * The be internal phy looks vaguely like MII hardware, 403 * but not enough to be able to use the MII device 404 * layer. Hence, we have to take care of media selection 405 * ourselves. 406 */ 407 408 sc->sc_mii_inst = instance; 409 sc->sc_phys[instance] = BE_PHY_INTERNAL; 410 411 /* Use `ifm_data' to store BMCR bits */ 412 ifmedia_add(&sc->sc_media, 413 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 0, NULL); 414 ifmedia_add(&sc->sc_media, 415 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 416 BMCR_S100, NULL); 417 ifmedia_add(&sc->sc_media, 418 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 0, NULL); 419 420 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 421 self->dv_xname); 422 423 be_mii_reset(sc, BE_PHY_INTERNAL); 424 /* Only set default medium here if there's no external PHY */ 425 if (instance == 0) { 426 be_pal_gate(sc, BE_PHY_INTERNAL); 427 ifmedia_set(&sc->sc_media, 428 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 429 } else 430 be_mii_writereg((void *)sc, 431 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 432 } 433 434 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 435 ifp->if_softc = sc; 436 ifp->if_start = bestart; 437 ifp->if_ioctl = beioctl; 438 ifp->if_watchdog = bewatchdog; 439 ifp->if_flags = 440 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 441 IFQ_SET_READY(&ifp->if_snd); 442 443 /* Attach the interface. */ 444 if_attach(ifp); 445 ether_ifattach(ifp); 446 } 447 448 449 /* 450 * Routine to copy from mbuf chain to transmit buffer in 451 * network buffer memory. 452 */ 453 static __inline__ int 454 be_put(struct be_softc *sc, int idx, struct mbuf *m) 455 { 456 struct mbuf *n; 457 int len, tlen = 0, boff = 0; 458 caddr_t bp; 459 460 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 461 462 for (; m; m = n) { 463 len = m->m_len; 464 if (len == 0) { 465 MFREE(m, n); 466 continue; 467 } 468 bcopy(mtod(m, caddr_t), bp+boff, len); 469 boff += len; 470 tlen += len; 471 MFREE(m, n); 472 } 473 return (tlen); 474 } 475 476 /* 477 * Pull data off an interface. 478 * Len is the length of data, with local net header stripped. 479 * We copy the data into mbufs. When full cluster sized units are present, 480 * we copy into clusters. 481 */ 482 static __inline__ struct mbuf * 483 be_get(struct be_softc *sc, int idx, int totlen) 484 { 485 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 486 struct mbuf *m; 487 struct mbuf *top, **mp; 488 int len, pad, boff = 0; 489 caddr_t bp; 490 491 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 492 493 MGETHDR(m, M_DONTWAIT, MT_DATA); 494 if (m == NULL) 495 return (NULL); 496 m->m_pkthdr.rcvif = ifp; 497 m->m_pkthdr.len = totlen; 498 499 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 500 m->m_data += pad; 501 len = MHLEN - pad; 502 top = NULL; 503 mp = ⊤ 504 505 while (totlen > 0) { 506 if (top) { 507 MGET(m, M_DONTWAIT, MT_DATA); 508 if (m == NULL) { 509 m_freem(top); 510 return (NULL); 511 } 512 len = MLEN; 513 } 514 if (top && totlen >= MINCLSIZE) { 515 MCLGET(m, M_DONTWAIT); 516 if (m->m_flags & M_EXT) 517 len = MCLBYTES; 518 } 519 m->m_len = len = min(totlen, len); 520 bcopy(bp + boff, mtod(m, caddr_t), len); 521 boff += len; 522 totlen -= len; 523 *mp = m; 524 mp = &m->m_next; 525 } 526 527 return (top); 528 } 529 530 /* 531 * Pass a packet to the higher levels. 532 */ 533 static __inline__ void 534 be_read(struct be_softc *sc, int idx, int len) 535 { 536 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 537 struct mbuf *m; 538 539 if (len <= sizeof(struct ether_header) || 540 len > ETHERMTU + sizeof(struct ether_header)) { 541 542 printf("%s: invalid packet size %d; dropping\n", 543 ifp->if_xname, len); 544 545 ifp->if_ierrors++; 546 return; 547 } 548 549 /* 550 * Pull packet off interface. 551 */ 552 m = be_get(sc, idx, len); 553 if (m == NULL) { 554 ifp->if_ierrors++; 555 return; 556 } 557 ifp->if_ipackets++; 558 559 #if NBPFILTER > 0 560 /* 561 * Check if there's a BPF listener on this interface. 562 * If so, hand off the raw packet to BPF. 563 */ 564 if (ifp->if_bpf) 565 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 566 #endif 567 /* Pass the packet up. */ 568 ether_input_mbuf(ifp, m); 569 } 570 571 /* 572 * Start output on interface. 573 * We make two assumptions here: 574 * 1) that the current priority is set to splnet _before_ this code 575 * is called *and* is returned to the appropriate priority after 576 * return 577 * 2) that the IFF_OACTIVE flag is checked before this code is called 578 * (i.e. that the output part of the interface is idle) 579 */ 580 void 581 bestart(struct ifnet *ifp) 582 { 583 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 584 struct qec_xd *txd = sc->sc_rb.rb_txd; 585 struct mbuf *m; 586 unsigned int bix, len; 587 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 588 589 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 590 return; 591 592 bix = sc->sc_rb.rb_tdhead; 593 594 for (;;) { 595 IFQ_DEQUEUE(&ifp->if_snd, m); 596 if (m == 0) 597 break; 598 599 #if NBPFILTER > 0 600 /* 601 * If BPF is listening on this interface, let it see the 602 * packet before we commit it to the wire. 603 */ 604 if (ifp->if_bpf) 605 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 606 #endif 607 608 /* 609 * Copy the mbuf chain into the transmit buffer. 610 */ 611 len = be_put(sc, bix, m); 612 613 /* 614 * Initialize transmit registers and start transmission 615 */ 616 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 617 (len & QEC_XD_LENGTH); 618 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 619 BE_CR_CTRL_TWAKEUP); 620 621 if (++bix == QEC_XD_RING_MAXSIZE) 622 bix = 0; 623 624 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 625 ifp->if_flags |= IFF_OACTIVE; 626 break; 627 } 628 } 629 630 sc->sc_rb.rb_tdhead = bix; 631 } 632 633 void 634 bestop(struct be_softc *sc) 635 { 636 int n; 637 bus_space_tag_t t = sc->sc_bustag; 638 bus_space_handle_t br = sc->sc_br; 639 640 timeout_del(&sc->sc_tick_ch); 641 642 /* Down the MII. */ 643 mii_down(&sc->sc_mii); 644 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 645 646 /* Stop the transmitter */ 647 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 648 for (n = 32; n > 0; n--) { 649 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 650 break; 651 DELAY(20); 652 } 653 654 /* Stop the receiver */ 655 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 656 for (n = 32; n > 0; n--) { 657 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 658 break; 659 DELAY(20); 660 } 661 } 662 663 /* 664 * Reset interface. 665 */ 666 void 667 bereset(struct be_softc *sc) 668 { 669 int s; 670 671 s = splnet(); 672 bestop(sc); 673 if ((sc->sc_arpcom.ac_if.if_flags & IFF_UP) != 0) 674 beinit(sc); 675 splx(s); 676 } 677 678 void 679 bewatchdog(struct ifnet *ifp) 680 { 681 struct be_softc *sc = ifp->if_softc; 682 683 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 684 ++sc->sc_arpcom.ac_if.if_oerrors; 685 bereset(sc); 686 } 687 688 int 689 beintr(void *v) 690 { 691 struct be_softc *sc = (struct be_softc *)v; 692 bus_space_tag_t t = sc->sc_bustag; 693 u_int32_t whyq, whyb, whyc; 694 int r = 0; 695 696 /* Read QEC status, channel status and BE status */ 697 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 698 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 699 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 700 701 if (whyq & QEC_STAT_BM) 702 r |= beeint(sc, whyb); 703 704 if (whyq & QEC_STAT_ER) 705 r |= beqint(sc, whyc); 706 707 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 708 r |= betint(sc); 709 710 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 711 r |= berint(sc); 712 713 return (r); 714 } 715 716 /* 717 * QEC Interrupt. 718 */ 719 int 720 beqint(struct be_softc *sc, u_int32_t why) 721 { 722 int r = 0, rst = 0; 723 724 if (why & BE_CR_STAT_TXIRQ) 725 r |= 1; 726 if (why & BE_CR_STAT_RXIRQ) 727 r |= 1; 728 729 if (why & BE_CR_STAT_BERROR) { 730 r |= 1; 731 rst = 1; 732 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 733 } 734 735 if (why & BE_CR_STAT_TXDERR) { 736 r |= 1; 737 rst = 1; 738 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 739 } 740 741 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 742 r |= 1; 743 rst = 1; 744 printf("%s: tx dma error ( ", sc->sc_dev.dv_xname); 745 if (why & BE_CR_STAT_TXLERR) 746 printf("Late "); 747 if (why & BE_CR_STAT_TXPERR) 748 printf("Parity "); 749 if (why & BE_CR_STAT_TXSERR) 750 printf("Generic "); 751 printf(")\n"); 752 } 753 754 if (why & BE_CR_STAT_RXDROP) { 755 r |= 1; 756 rst = 1; 757 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 758 } 759 760 if (why & BE_CR_STAT_RXSMALL) { 761 r |= 1; 762 rst = 1; 763 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 764 } 765 766 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 767 r |= 1; 768 rst = 1; 769 printf("%s: rx dma error ( ", sc->sc_dev.dv_xname); 770 if (why & BE_CR_STAT_RXLERR) 771 printf("Late "); 772 if (why & BE_CR_STAT_RXPERR) 773 printf("Parity "); 774 if (why & BE_CR_STAT_RXSERR) 775 printf("Generic "); 776 printf(")\n"); 777 } 778 779 if (!r) { 780 rst = 1; 781 printf("%s: unexpected error interrupt %08x\n", 782 sc->sc_dev.dv_xname, why); 783 } 784 785 if (rst) { 786 printf("%s: resetting\n", sc->sc_dev.dv_xname); 787 bereset(sc); 788 } 789 790 return (r); 791 } 792 793 /* 794 * Error interrupt. 795 */ 796 int 797 beeint(struct be_softc *sc, u_int32_t why) 798 { 799 int r = 0, rst = 0; 800 801 if (why & BE_BR_STAT_RFIFOVF) { 802 r |= 1; 803 rst = 1; 804 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 805 } 806 if (why & BE_BR_STAT_TFIFO_UND) { 807 r |= 1; 808 rst = 1; 809 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 810 } 811 if (why & BE_BR_STAT_MAXPKTERR) { 812 r |= 1; 813 rst = 1; 814 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 815 } 816 817 if (!r) { 818 rst = 1; 819 printf("%s: unexpected error interrupt %08x\n", 820 sc->sc_dev.dv_xname, why); 821 } 822 823 if (rst) { 824 printf("%s: resetting\n", sc->sc_dev.dv_xname); 825 bereset(sc); 826 } 827 828 return (r); 829 } 830 831 /* 832 * Transmit interrupt. 833 */ 834 int 835 betint(struct be_softc *sc) 836 { 837 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 838 bus_space_tag_t t = sc->sc_bustag; 839 bus_space_handle_t br = sc->sc_br; 840 unsigned int bix, txflags; 841 842 /* 843 * Unload collision counters 844 */ 845 ifp->if_collisions += 846 bus_space_read_4(t, br, BE_BRI_NCCNT) + 847 bus_space_read_4(t, br, BE_BRI_FCCNT) + 848 bus_space_read_4(t, br, BE_BRI_EXCNT) + 849 bus_space_read_4(t, br, BE_BRI_LTCNT); 850 851 /* 852 * the clear the hardware counters 853 */ 854 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 855 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 856 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 857 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 858 859 bix = sc->sc_rb.rb_tdtail; 860 861 for (;;) { 862 if (sc->sc_rb.rb_td_nbusy <= 0) 863 break; 864 865 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 866 867 if (txflags & QEC_XD_OWN) 868 break; 869 870 ifp->if_flags &= ~IFF_OACTIVE; 871 ifp->if_opackets++; 872 873 if (++bix == QEC_XD_RING_MAXSIZE) 874 bix = 0; 875 876 --sc->sc_rb.rb_td_nbusy; 877 } 878 879 sc->sc_rb.rb_tdtail = bix; 880 881 bestart(ifp); 882 883 if (sc->sc_rb.rb_td_nbusy == 0) 884 ifp->if_timer = 0; 885 886 return (1); 887 } 888 889 /* 890 * Receive interrupt. 891 */ 892 int 893 berint(struct be_softc *sc) 894 { 895 struct qec_xd *xd = sc->sc_rb.rb_rxd; 896 unsigned int bix, len; 897 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 898 899 bix = sc->sc_rb.rb_rdtail; 900 901 /* 902 * Process all buffers with valid data. 903 */ 904 for (;;) { 905 len = xd[bix].xd_flags; 906 if (len & QEC_XD_OWN) 907 break; 908 909 len &= QEC_XD_LENGTH; 910 be_read(sc, bix, len); 911 912 /* ... */ 913 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 914 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 915 916 if (++bix == QEC_XD_RING_MAXSIZE) 917 bix = 0; 918 } 919 920 sc->sc_rb.rb_rdtail = bix; 921 922 return (1); 923 } 924 925 int 926 beioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 927 { 928 struct be_softc *sc = ifp->if_softc; 929 struct ifaddr *ifa = (struct ifaddr *)data; 930 struct ifreq *ifr = (struct ifreq *)data; 931 int s, error = 0; 932 933 s = splnet(); 934 935 switch (cmd) { 936 case SIOCSIFADDR: 937 ifp->if_flags |= IFF_UP; 938 switch (ifa->ifa_addr->sa_family) { 939 #ifdef INET 940 case AF_INET: 941 beinit(sc); 942 arp_ifinit(&sc->sc_arpcom, ifa); 943 break; 944 #endif /* INET */ 945 default: 946 beinit(sc); 947 break; 948 } 949 break; 950 951 case SIOCSIFFLAGS: 952 if ((ifp->if_flags & IFF_UP) == 0 && 953 (ifp->if_flags & IFF_RUNNING) != 0) { 954 /* 955 * If interface is marked down and it is running, then 956 * stop it. 957 */ 958 bestop(sc); 959 ifp->if_flags &= ~IFF_RUNNING; 960 } else if ((ifp->if_flags & IFF_UP) != 0 && 961 (ifp->if_flags & IFF_RUNNING) == 0) { 962 /* 963 * If interface is marked up and it is stopped, then 964 * start it. 965 */ 966 beinit(sc); 967 } else { 968 /* 969 * Reset the interface to pick up changes in any other 970 * flags that affect hardware registers. 971 */ 972 bestop(sc); 973 beinit(sc); 974 } 975 #ifdef BEDEBUG 976 if (ifp->if_flags & IFF_DEBUG) 977 sc->sc_debug = 1; 978 else 979 sc->sc_debug = 0; 980 #endif 981 break; 982 983 case SIOCGIFMEDIA: 984 case SIOCSIFMEDIA: 985 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 986 break; 987 988 default: 989 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 990 } 991 992 if (error == ENETRESET) { 993 if (ifp->if_flags & IFF_RUNNING) 994 be_mcreset(sc); 995 error = 0; 996 } 997 998 splx(s); 999 return (error); 1000 } 1001 1002 1003 void 1004 beinit(struct be_softc *sc) 1005 { 1006 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1007 bus_space_tag_t t = sc->sc_bustag; 1008 bus_space_handle_t br = sc->sc_br; 1009 bus_space_handle_t cr = sc->sc_cr; 1010 struct qec_softc *qec = sc->sc_qec; 1011 u_int32_t v; 1012 u_int32_t qecaddr; 1013 u_int8_t *ea; 1014 int s; 1015 1016 s = splnet(); 1017 1018 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1019 1020 bestop(sc); 1021 1022 ea = sc->sc_arpcom.ac_enaddr; 1023 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1024 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1025 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1026 1027 /* Clear hash table */ 1028 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1029 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1030 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1031 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1032 1033 /* Re-initialize RX configuration */ 1034 v = BE_BR_RXCFG_FIFO; 1035 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1036 1037 be_mcreset(sc); 1038 1039 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1040 1041 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1042 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1043 1044 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1045 1046 /* 1047 * Turn off counter expiration interrupts as well as 1048 * 'gotframe' and 'sentframe' 1049 */ 1050 bus_space_write_4(t, br, BE_BRI_IMASK, 1051 BE_BR_IMASK_GOTFRAME | 1052 BE_BR_IMASK_RCNTEXP | 1053 BE_BR_IMASK_ACNTEXP | 1054 BE_BR_IMASK_CCNTEXP | 1055 BE_BR_IMASK_LCNTEXP | 1056 BE_BR_IMASK_CVCNTEXP | 1057 BE_BR_IMASK_SENTFRAME | 1058 BE_BR_IMASK_NCNTEXP | 1059 BE_BR_IMASK_ECNTEXP | 1060 BE_BR_IMASK_LCCNTEXP | 1061 BE_BR_IMASK_FCNTEXP | 1062 BE_BR_IMASK_DTIMEXP); 1063 1064 /* Channel registers: */ 1065 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1066 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1067 1068 qecaddr = sc->sc_channel * qec->sc_msize; 1069 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1070 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1071 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1072 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1073 1074 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1075 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1076 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1077 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1078 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1079 1080 /* Enable transmitter */ 1081 bus_space_write_4(t, br, BE_BRI_TXCFG, 1082 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1083 1084 /* Enable receiver */ 1085 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1086 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1087 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1088 1089 ifp->if_flags |= IFF_RUNNING; 1090 ifp->if_flags &= ~IFF_OACTIVE; 1091 1092 be_ifmedia_upd(ifp); 1093 timeout_add_sec(&sc->sc_tick_ch, 1); 1094 splx(s); 1095 } 1096 1097 void 1098 be_mcreset(struct be_softc *sc) 1099 { 1100 struct arpcom *ac = &sc->sc_arpcom; 1101 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1102 bus_space_tag_t t = sc->sc_bustag; 1103 bus_space_handle_t br = sc->sc_br; 1104 u_int32_t crc; 1105 u_int16_t hash[4]; 1106 u_int8_t octet; 1107 u_int32_t v; 1108 int i, j; 1109 struct ether_multi *enm; 1110 struct ether_multistep step; 1111 1112 if (ifp->if_flags & IFF_PROMISC) { 1113 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1114 v |= BE_BR_RXCFG_PMISC; 1115 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1116 return; 1117 } 1118 1119 if (ac->ac_multirangecnt > 0) 1120 ifp->if_flags |= IFF_ALLMULTI; 1121 1122 if (ifp->if_flags & IFF_ALLMULTI) { 1123 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1124 goto chipit; 1125 } 1126 1127 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1128 1129 ETHER_FIRST_MULTI(step, ac, enm); 1130 while (enm != NULL) { 1131 crc = 0xffffffff; 1132 1133 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1134 octet = enm->enm_addrlo[i]; 1135 1136 for (j = 0; j < 8; j++) { 1137 if ((crc & 1) ^ (octet & 1)) { 1138 crc >>= 1; 1139 crc ^= MC_POLY_LE; 1140 } 1141 else 1142 crc >>= 1; 1143 octet >>= 1; 1144 } 1145 } 1146 1147 crc >>= 26; 1148 hash[crc >> 4] |= 1 << (crc & 0xf); 1149 ETHER_NEXT_MULTI(step, enm); 1150 } 1151 1152 ifp->if_flags &= ~IFF_ALLMULTI; 1153 1154 chipit: 1155 /* Enable the hash filter */ 1156 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1157 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1158 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1159 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1160 1161 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1162 v &= ~BE_BR_RXCFG_PMISC; 1163 v |= BE_BR_RXCFG_HENABLE; 1164 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1165 } 1166 1167 /* 1168 * Set the tcvr to an idle state 1169 */ 1170 void 1171 be_mii_sync(struct be_softc *sc) 1172 { 1173 bus_space_tag_t t = sc->sc_bustag; 1174 bus_space_handle_t tr = sc->sc_tr; 1175 int n = 32; 1176 1177 while (n--) { 1178 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1179 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1180 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1181 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1182 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1183 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1184 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1185 } 1186 } 1187 1188 void 1189 be_pal_gate(struct be_softc *sc, int phy) 1190 { 1191 bus_space_tag_t t = sc->sc_bustag; 1192 bus_space_handle_t tr = sc->sc_tr; 1193 u_int32_t v; 1194 1195 be_mii_sync(sc); 1196 1197 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1198 if (phy == BE_PHY_INTERNAL) 1199 v &= ~TCVR_PAL_SERIAL; 1200 1201 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1202 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1203 } 1204 1205 static int 1206 be_tcvr_read_bit(struct be_softc *sc, int phy) 1207 { 1208 bus_space_tag_t t = sc->sc_bustag; 1209 bus_space_handle_t tr = sc->sc_tr; 1210 int ret; 1211 1212 if (phy == BE_PHY_INTERNAL) { 1213 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1214 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1215 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1216 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1217 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1218 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1219 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1220 } else { 1221 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1222 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1223 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1224 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1225 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1226 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1227 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1228 } 1229 1230 return (ret); 1231 } 1232 1233 static void 1234 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1235 { 1236 bus_space_tag_t t = sc->sc_bustag; 1237 bus_space_handle_t tr = sc->sc_tr; 1238 u_int32_t v; 1239 1240 if (phy == BE_PHY_INTERNAL) { 1241 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1242 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1243 } else { 1244 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1245 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1246 } 1247 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1248 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1249 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1250 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1251 } 1252 1253 static void 1254 be_mii_sendbits(struct be_softc *sc, int phy, u_int32_t data, int nbits) 1255 { 1256 int i; 1257 1258 for (i = 1 << (nbits - 1); i != 0; i >>= 1) 1259 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1260 } 1261 1262 static int 1263 be_mii_readreg(struct device *self, int phy, int reg) 1264 { 1265 struct be_softc *sc = (struct be_softc *)self; 1266 int val = 0, i; 1267 1268 /* 1269 * Read the PHY register by manually driving the MII control lines. 1270 */ 1271 be_mii_sync(sc); 1272 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1273 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1274 be_mii_sendbits(sc, phy, phy, 5); 1275 be_mii_sendbits(sc, phy, reg, 5); 1276 1277 (void) be_tcvr_read_bit(sc, phy); 1278 (void) be_tcvr_read_bit(sc, phy); 1279 1280 for (i = 15; i >= 0; i--) 1281 val |= (be_tcvr_read_bit(sc, phy) << i); 1282 1283 (void) be_tcvr_read_bit(sc, phy); 1284 (void) be_tcvr_read_bit(sc, phy); 1285 (void) be_tcvr_read_bit(sc, phy); 1286 1287 return (val); 1288 } 1289 1290 void 1291 be_mii_writereg(struct device *self, int phy, int reg, int val) 1292 { 1293 struct be_softc *sc = (struct be_softc *)self; 1294 int i; 1295 1296 /* 1297 * Write the PHY register by manually driving the MII control lines. 1298 */ 1299 be_mii_sync(sc); 1300 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1301 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1302 be_mii_sendbits(sc, phy, phy, 5); 1303 be_mii_sendbits(sc, phy, reg, 5); 1304 1305 be_tcvr_write_bit(sc, phy, 1); 1306 be_tcvr_write_bit(sc, phy, 0); 1307 1308 for (i = 15; i >= 0; i--) 1309 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1310 } 1311 1312 int 1313 be_mii_reset(struct be_softc *sc, int phy) 1314 { 1315 int n; 1316 1317 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1318 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1319 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1320 1321 for (n = 16; n >= 0; n--) { 1322 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1323 if ((bmcr & BMCR_RESET) == 0) 1324 break; 1325 DELAY(20); 1326 } 1327 if (n == 0) { 1328 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1329 return (EIO); 1330 } 1331 1332 return (0); 1333 } 1334 1335 void 1336 be_tick(void *arg) 1337 { 1338 struct be_softc *sc = arg; 1339 int s = splnet(); 1340 1341 mii_tick(&sc->sc_mii); 1342 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1343 1344 timeout_add_sec(&sc->sc_tick_ch, 1); 1345 splx(s); 1346 } 1347 1348 void 1349 be_mii_statchg(struct device *self) 1350 { 1351 struct be_softc *sc = (struct be_softc *)self; 1352 bus_space_tag_t t = sc->sc_bustag; 1353 bus_space_handle_t br = sc->sc_br; 1354 u_int instance; 1355 u_int32_t v; 1356 1357 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1358 #ifdef DIAGNOSTIC 1359 if (instance > 1) 1360 panic("be_mii_statchg: instance %d out of range", instance); 1361 #endif 1362 1363 /* Update duplex mode in TX configuration */ 1364 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1365 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1366 v |= BE_BR_TXCFG_FULLDPLX; 1367 else 1368 v &= ~BE_BR_TXCFG_FULLDPLX; 1369 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1370 1371 /* Change to appropriate gate in transceiver PAL */ 1372 be_pal_gate(sc, sc->sc_phys[instance]); 1373 } 1374 1375 /* 1376 * Get current media settings. 1377 */ 1378 void 1379 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1380 { 1381 struct be_softc *sc = ifp->if_softc; 1382 1383 mii_pollstat(&sc->sc_mii); 1384 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1385 1386 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1387 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1388 return; 1389 } 1390 1391 /* 1392 * Set media options. 1393 */ 1394 int 1395 be_ifmedia_upd(struct ifnet *ifp) 1396 { 1397 struct be_softc *sc = ifp->if_softc; 1398 int error; 1399 1400 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1401 return (error); 1402 1403 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1404 } 1405 1406 /* 1407 * Service routine for our pseudo-MII internal transceiver. 1408 */ 1409 int 1410 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1411 { 1412 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1413 int bmcr, bmsr; 1414 int error; 1415 1416 switch (cmd) { 1417 case MII_POLLSTAT: 1418 /* 1419 * If we're not polling our PHY instance, just return. 1420 */ 1421 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1422 return (0); 1423 1424 break; 1425 1426 case MII_MEDIACHG: 1427 1428 /* 1429 * If the media indicates a different PHY instance, 1430 * isolate ourselves. 1431 */ 1432 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1433 bmcr = be_mii_readreg((void *)sc, 1434 BE_PHY_INTERNAL, MII_BMCR); 1435 be_mii_writereg((void *)sc, 1436 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1437 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1438 sc->sc_intphy_curspeed = 0; 1439 return (0); 1440 } 1441 1442 1443 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1444 return (error); 1445 1446 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1447 1448 /* 1449 * Select the new mode and take out of isolation 1450 */ 1451 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1452 bmcr |= BMCR_S100; 1453 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1454 bmcr &= ~BMCR_S100; 1455 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1456 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1457 bmcr &= ~BMCR_S100; 1458 bmcr |= sc->sc_intphy_curspeed; 1459 } else { 1460 /* Keep isolated until link is up */ 1461 bmcr |= BMCR_ISO; 1462 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1463 } 1464 } 1465 1466 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1467 bmcr |= BMCR_FDX; 1468 else 1469 bmcr &= ~BMCR_FDX; 1470 1471 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1472 break; 1473 1474 case MII_TICK: 1475 /* 1476 * If we're not currently selected, just return. 1477 */ 1478 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1479 return (0); 1480 1481 /* Only used for automatic media selection */ 1482 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1483 return (0); 1484 1485 /* Is the interface even up? */ 1486 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1487 return (0); 1488 1489 /* 1490 * Check link status; if we don't have a link, try another 1491 * speed. We can't detect duplex mode, so half-duplex is 1492 * what we have to settle for. 1493 */ 1494 1495 /* Read twice in case the register is latched */ 1496 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1497 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1498 1499 if ((bmsr & BMSR_LINK) != 0) { 1500 /* We have a carrier */ 1501 bmcr = be_mii_readreg((void *)sc, 1502 BE_PHY_INTERNAL, MII_BMCR); 1503 1504 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1505 bmcr = be_mii_readreg((void *)sc, 1506 BE_PHY_INTERNAL, MII_BMCR); 1507 1508 sc->sc_mii_flags |= MIIF_HAVELINK; 1509 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1510 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1511 1512 bmcr &= ~BMCR_ISO; 1513 be_mii_writereg((void *)sc, 1514 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1515 1516 printf("%s: link up at %s Mbps\n", 1517 sc->sc_dev.dv_xname, 1518 (bmcr & BMCR_S100) ? "100" : "10"); 1519 } 1520 sc->sc_mii_ticks = 0; 1521 return (0); 1522 } 1523 1524 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1525 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1526 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1527 sc->sc_intphy_curspeed = 0; 1528 printf("%s: link down\n", sc->sc_dev.dv_xname); 1529 } 1530 1531 /* Only retry autonegotiation every 5 seconds. */ 1532 if (++sc->sc_mii_ticks < 5) 1533 return(0); 1534 1535 sc->sc_mii_ticks = 0; 1536 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1537 /* Just flip the fast speed bit */ 1538 bmcr ^= BMCR_S100; 1539 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1540 1541 break; 1542 1543 case MII_DOWN: 1544 /* Isolate this phy */ 1545 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1546 be_mii_writereg((void *)sc, 1547 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1548 return (0); 1549 } 1550 1551 /* Update the media status. */ 1552 be_intphy_status(sc); 1553 1554 /* Callback if something changed. */ 1555 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1556 (*mii->mii_statchg)((struct device *)sc); 1557 sc->sc_mii_active = mii->mii_media_active; 1558 } 1559 return (0); 1560 } 1561 1562 /* 1563 * Determine status of internal transceiver 1564 */ 1565 void 1566 be_intphy_status(struct be_softc *sc) 1567 { 1568 struct mii_data *mii = &sc->sc_mii; 1569 int media_active, media_status; 1570 int bmcr, bmsr; 1571 1572 media_status = IFM_AVALID; 1573 media_active = 0; 1574 1575 /* 1576 * Internal transceiver; do the work here. 1577 */ 1578 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1579 1580 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1581 case (BMCR_S100 | BMCR_FDX): 1582 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1583 break; 1584 case BMCR_S100: 1585 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1586 break; 1587 case BMCR_FDX: 1588 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1589 break; 1590 case 0: 1591 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1592 break; 1593 } 1594 1595 /* Read twice in case the register is latched */ 1596 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1597 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1598 if (bmsr & BMSR_LINK) 1599 media_status |= IFM_ACTIVE; 1600 1601 mii->mii_media_status = media_status; 1602 mii->mii_media_active = media_active; 1603 } 1604