1 /* $OpenBSD: if_xe.c,v 1.44 2014/07/12 18:48:52 tedu Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Niklas Hallqvist, 18 * C Stone and Job de Haas. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * A driver for Xircom ethernet PC-cards. 36 * 37 * The driver has been inspired by the xirc2ps_cs.c driver found in Linux' 38 * PCMCIA package written by Werner Koch <werner.koch@guug.de>: 39 * [xirc2ps_cs.c wk 14.04.97] (1.31 1998/12/09 19:32:55) 40 * I will note that no code was used verbatim from that driver as it is under 41 * the much too strong GNU General Public License, it was only used as a 42 * "specification" of sorts. 43 * Other inspirations have been if_fxp.c, if_ep_pcmcia.c and elink3.c as 44 * they were found in OpenBSD 2.4. 45 */ 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/ioctl.h> 53 #include <sys/mbuf.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/socket.h> 57 #include <sys/syslog.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_types.h> 63 64 #ifdef INET 65 #include <netinet/in.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/ip.h> 68 #include <netinet/if_ether.h> 69 #endif 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 /* 76 * Maximum number of bytes to read per interrupt. Linux recommends 77 * somewhere between 2000-22000. 78 * XXX This is currently a hard maximum. 79 */ 80 #define MAX_BYTES_INTR 12000 81 82 #include <dev/mii/miivar.h> 83 84 #include <dev/pcmcia/pcmciareg.h> 85 #include <dev/pcmcia/pcmciavar.h> 86 #include <dev/pcmcia/pcmciadevs.h> 87 #include <dev/pcmcia/if_xereg.h> 88 89 #ifdef __GNUC__ 90 #define INLINE __inline 91 #else 92 #define INLINE 93 #endif /* __GNUC__ */ 94 95 #ifdef XEDEBUG 96 97 #define XED_CONFIG 0x1 98 #define XED_MII 0x2 99 #define XED_INTR 0x4 100 #define XED_FIFO 0x8 101 102 #ifndef XEDEBUG_DEF 103 #define XEDEBUG_DEF (XED_CONFIG|XED_INTR) 104 #endif /* XEDEBUG_DEF */ 105 106 int xedebug = XEDEBUG_DEF; 107 108 #define DPRINTF(cat, x) if (xedebug & (cat)) printf x 109 110 #else /* XEDEBUG */ 111 #define DPRINTF(cat, x) (void)0 112 #endif /* XEDEBUG */ 113 114 int xe_pcmcia_match(struct device *, void *, void *); 115 void xe_pcmcia_attach(struct device *, struct device *, void *); 116 int xe_pcmcia_detach(struct device *, int); 117 int xe_pcmcia_activate(struct device *, int); 118 119 /* 120 * In case this chipset ever turns up out of pcmcia attachments (very 121 * unlikely) do the driver splitup. 122 */ 123 struct xe_softc { 124 struct device sc_dev; /* Generic device info */ 125 u_int32_t sc_flags; /* Misc. flags */ 126 void *sc_ih; /* Interrupt handler */ 127 struct arpcom sc_arpcom; /* Ethernet common part */ 128 struct ifmedia sc_media; /* Media control */ 129 struct mii_data sc_mii; /* MII media information */ 130 int sc_all_mcasts; /* Receive all multicasts */ 131 bus_space_tag_t sc_bst; /* Bus cookie */ 132 bus_space_handle_t sc_bsh; /* Bus I/O handle */ 133 bus_size_t sc_offset; /* Offset of registers */ 134 u_int8_t sc_rev; /* Chip revision */ 135 }; 136 137 #define XEF_MOHAWK 0x001 138 #define XEF_DINGO 0x002 139 #define XEF_MODEM 0x004 140 #define XEF_UNSUPPORTED 0x008 141 #define XEF_CE 0x010 142 #define XEF_CE2 0x020 143 #define XEF_CE3 0x040 144 #define XEF_CE33 0x080 145 #define XEF_CE56 0x100 146 147 struct xe_pcmcia_softc { 148 struct xe_softc sc_xe; /* Generic device info */ 149 struct pcmcia_mem_handle sc_pcmh; /* PCMCIA memspace info */ 150 int sc_mem_window; /* mem window */ 151 struct pcmcia_io_handle sc_pcioh; /* iospace info */ 152 int sc_io_window; /* io window info */ 153 struct pcmcia_function *sc_pf; /* PCMCIA function */ 154 }; 155 156 /* Autoconfig definition of driver back-end */ 157 struct cfdriver xe_cd = { 158 NULL, "xe", DV_IFNET 159 }; 160 161 struct cfattach xe_pcmcia_ca = { 162 sizeof (struct xe_pcmcia_softc), xe_pcmcia_match, xe_pcmcia_attach, 163 xe_pcmcia_detach, xe_pcmcia_activate 164 }; 165 166 void xe_cycle_power(struct xe_softc *); 167 void xe_full_reset(struct xe_softc *); 168 void xe_init(struct xe_softc *); 169 int xe_intr(void *); 170 int xe_ioctl(struct ifnet *, u_long, caddr_t); 171 int xe_mdi_read(struct device *, int, int); 172 void xe_mdi_write(struct device *, int, int, int); 173 int xe_mediachange(struct ifnet *); 174 void xe_mediastatus(struct ifnet *, struct ifmediareq *); 175 int xe_pcmcia_funce_enaddr(struct device *, u_int8_t *); 176 u_int32_t xe_pcmcia_interpret_manfid(struct device *); 177 int xe_pcmcia_lan_nid_ciscallback(struct pcmcia_tuple *, void *); 178 int xe_pcmcia_manfid_ciscallback(struct pcmcia_tuple *, void *); 179 u_int16_t xe_get(struct xe_softc *); 180 void xe_reset(struct xe_softc *); 181 void xe_set_address(struct xe_softc *); 182 void xe_start(struct ifnet *); 183 void xe_statchg(struct device *); 184 void xe_stop(struct xe_softc *); 185 void xe_watchdog(struct ifnet *); 186 #ifdef XEDEBUG 187 void xe_reg_dump(struct xe_softc *); 188 #endif /* XEDEBUG */ 189 190 int 191 xe_pcmcia_match(parent, match, aux) 192 struct device *parent; 193 void *match, *aux; 194 { 195 struct pcmcia_attach_args *pa = aux; 196 197 if (pa->pf->function != PCMCIA_FUNCTION_NETWORK) 198 return (0); 199 200 switch (pa->manufacturer) { 201 case PCMCIA_VENDOR_COMPAQ: 202 case PCMCIA_VENDOR_COMPAQ2: 203 return (0); 204 205 case PCMCIA_VENDOR_INTEL: 206 case PCMCIA_VENDOR_XIRCOM: 207 /* XXX Per-productid checking here. */ 208 return (1); 209 210 default: 211 return (0); 212 } 213 } 214 215 void 216 xe_pcmcia_attach(parent, self, aux) 217 struct device *parent, *self; 218 void *aux; 219 { 220 struct xe_pcmcia_softc *psc = (struct xe_pcmcia_softc *)self; 221 struct xe_softc *sc = &psc->sc_xe; 222 struct pcmcia_attach_args *pa = aux; 223 struct pcmcia_function *pf = pa->pf; 224 struct pcmcia_config_entry *cfe = NULL; 225 struct ifnet *ifp; 226 u_int8_t myla[ETHER_ADDR_LEN], *enaddr = NULL; 227 int state = 0; 228 struct pcmcia_mem_handle pcmh; 229 int ccr_window; 230 bus_size_t ccr_offset; 231 const char *intrstr; 232 233 psc->sc_pf = pf; 234 235 #if 0 236 /* Figure out what card we are. */ 237 sc->sc_flags = xe_pcmcia_interpret_manfid(parent); 238 #endif 239 if (sc->sc_flags & XEF_UNSUPPORTED) { 240 printf(": card unsupported\n"); 241 goto bad; 242 } 243 244 /* Tell the pcmcia framework where the CCR is. */ 245 pf->ccr_base = 0x800; 246 pf->ccr_mask = 0x67; 247 248 /* Fake a cfe. */ 249 SIMPLEQ_FIRST(&pa->pf->cfe_head) = cfe = (struct pcmcia_config_entry *) 250 malloc(sizeof *cfe, M_DEVBUF, M_NOWAIT | M_ZERO); 251 if (!cfe) { 252 printf(": function enable failed\n"); 253 return; 254 } 255 256 /* 257 * XXX Use preprocessor symbols instead. 258 * Enable ethernet & its interrupts, wiring them to -INT 259 * No I/O base. 260 */ 261 cfe->number = 0x5; 262 cfe->flags = 0; /* XXX Check! */ 263 cfe->iftype = PCMCIA_IFTYPE_IO; 264 cfe->num_iospace = 0; 265 cfe->num_memspace = 0; 266 cfe->irqmask = 0x8eb0; 267 268 /* Enable the card. */ 269 pcmcia_function_init(pa->pf, cfe); 270 if (pcmcia_function_enable(pa->pf)) { 271 printf(": function enable failed\n"); 272 goto bad; 273 } 274 275 state++; 276 277 if (pcmcia_io_alloc(pa->pf, 0, 16, 16, &psc->sc_pcioh)) { 278 printf(": io allocation failed\n"); 279 goto bad; 280 } 281 282 state++; 283 284 if (pcmcia_io_map(pa->pf, PCMCIA_WIDTH_IO16, 0, 16, &psc->sc_pcioh, 285 &psc->sc_io_window)) { 286 printf(": can't map io space\n"); 287 goto bad; 288 } 289 sc->sc_bst = psc->sc_pcioh.iot; 290 sc->sc_bsh = psc->sc_pcioh.ioh; 291 sc->sc_offset = 0; 292 293 printf(" port 0x%lx/%d", psc->sc_pcioh.addr, 16); 294 295 #if 0 296 if (pcmcia_mem_alloc(pf, 16, &psc->sc_pcmh)) { 297 printf(": pcmcia memory allocation failed\n"); 298 goto bad; 299 } 300 state++; 301 302 if (pcmcia_mem_map(pf, PCMCIA_MEM_ATTR, 0x300, 16, &psc->sc_pcmh, 303 &sc->sc_offset, &psc->sc_mem_window)) { 304 printf(": pcmcia memory mapping failed\n"); 305 goto bad; 306 } 307 308 sc->sc_bst = psc->sc_pcmh.memt; 309 sc->sc_bsh = psc->sc_pcmh.memh; 310 #endif 311 312 /* Figure out what card we are. */ 313 sc->sc_flags = xe_pcmcia_interpret_manfid(parent); 314 315 /* 316 * Configuration as advised by DINGO documentation. 317 * We only know about this flag after the manfid interpretation. 318 * Dingo has some extra configuration registers in the CCR space. 319 */ 320 if (sc->sc_flags & XEF_DINGO) { 321 if (pcmcia_mem_alloc(pf, PCMCIA_CCR_SIZE_DINGO, &pcmh)) { 322 DPRINTF(XED_CONFIG, ("bad mem alloc\n")); 323 goto bad; 324 } 325 326 if (pcmcia_mem_map(pf, PCMCIA_MEM_ATTR, pf->ccr_base, 327 PCMCIA_CCR_SIZE_DINGO, &pcmh, &ccr_offset, 328 &ccr_window)) { 329 DPRINTF(XED_CONFIG, ("bad mem map\n")); 330 pcmcia_mem_free(pf, &pcmh); 331 goto bad; 332 } 333 334 bus_space_write_1(pcmh.memt, pcmh.memh, 335 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 336 bus_space_write_1(pcmh.memt, pcmh.memh, 337 ccr_offset + PCMCIA_CCR_DCOR1, 338 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 339 bus_space_write_1(pcmh.memt, pcmh.memh, 340 ccr_offset + PCMCIA_CCR_DCOR2, 0); 341 bus_space_write_1(pcmh.memt, pcmh.memh, 342 ccr_offset + PCMCIA_CCR_DCOR3, 0); 343 bus_space_write_1(pcmh.memt, pcmh.memh, 344 ccr_offset + PCMCIA_CCR_DCOR4, 0); 345 346 /* We don't need them anymore and can free them (I think). */ 347 pcmcia_mem_unmap(pf, ccr_window); 348 pcmcia_mem_free(pf, &pcmh); 349 } 350 351 /* 352 * Try to get the ethernet address from FUNCE/LAN_NID tuple. 353 */ 354 if (xe_pcmcia_funce_enaddr(parent, myla)) 355 enaddr = myla; 356 ifp = &sc->sc_arpcom.ac_if; 357 if (enaddr) 358 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 359 else { 360 printf(", unable to get ethernet address\n"); 361 goto bad; 362 } 363 364 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 365 ifp->if_softc = sc; 366 ifp->if_flags = 367 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 368 ifp->if_ioctl = xe_ioctl; 369 ifp->if_start = xe_start; 370 ifp->if_watchdog = xe_watchdog; 371 IFQ_SET_READY(&ifp->if_snd); 372 373 /* Establish the interrupt. */ 374 sc->sc_ih = pcmcia_intr_establish(pa->pf, IPL_NET, xe_intr, sc, 375 sc->sc_dev.dv_xname); 376 if (sc->sc_ih == NULL) { 377 printf(", couldn't establish interrupt\n"); 378 goto bad; 379 } 380 intrstr = pcmcia_intr_string(psc->sc_pf, sc->sc_ih); 381 printf("%s%s: address %s\n", *intrstr ? ", " : "", intrstr, 382 ether_sprintf(sc->sc_arpcom.ac_enaddr)); 383 384 /* Reset and initialize the card. */ 385 xe_full_reset(sc); 386 387 /* Initialize our media structures and probe the phy. */ 388 sc->sc_mii.mii_ifp = ifp; 389 sc->sc_mii.mii_readreg = xe_mdi_read; 390 sc->sc_mii.mii_writereg = xe_mdi_write; 391 sc->sc_mii.mii_statchg = xe_statchg; 392 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, xe_mediachange, 393 xe_mediastatus); 394 DPRINTF(XED_MII | XED_CONFIG, 395 ("bmsr %x\n", xe_mdi_read(&sc->sc_dev, 0, 1))); 396 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 397 0); 398 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 399 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 400 NULL); 401 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 402 403 /* 404 * Attach the interface. 405 */ 406 if_attach(ifp); 407 ether_ifattach(ifp); 408 409 /* 410 * Reset and initialize the card again for DINGO (as found in Linux 411 * driver). Without this Dingo will get a watchdog timeout the first 412 * time. The ugly media tickling seems to be necessary for getting 413 * autonegotiation to work too. 414 */ 415 if (sc->sc_flags & XEF_DINGO) { 416 xe_full_reset(sc); 417 xe_init(sc); 418 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 419 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE); 420 xe_stop(sc); 421 } 422 return; 423 424 bad: 425 if (state > 2) 426 pcmcia_io_unmap(pf, psc->sc_io_window); 427 if (state > 1) 428 pcmcia_io_free(pf, &psc->sc_pcioh); 429 if (state > 0) 430 pcmcia_function_disable(pa->pf); 431 free(cfe, M_DEVBUF, 0); 432 } 433 434 int 435 xe_pcmcia_detach(dev, flags) 436 struct device *dev; 437 int flags; 438 { 439 struct xe_pcmcia_softc *psc = (struct xe_pcmcia_softc *)dev; 440 struct xe_softc *sc = &psc->sc_xe; 441 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 442 int rv = 0; 443 444 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 445 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 446 447 pcmcia_io_unmap(psc->sc_pf, psc->sc_io_window); 448 pcmcia_io_free(psc->sc_pf, &psc->sc_pcioh); 449 450 ether_ifdetach(ifp); 451 if_detach(ifp); 452 453 return (rv); 454 } 455 456 int 457 xe_pcmcia_activate(dev, act) 458 struct device *dev; 459 int act; 460 { 461 struct xe_pcmcia_softc *sc = (struct xe_pcmcia_softc *)dev; 462 struct ifnet *ifp = &sc->sc_xe.sc_arpcom.ac_if; 463 464 switch (act) { 465 case DVACT_SUSPEND: 466 if (ifp->if_flags & IFF_RUNNING) 467 xe_stop(&sc->sc_xe); 468 ifp->if_flags &= ~IFF_RUNNING; 469 if (sc->sc_xe.sc_ih) 470 pcmcia_intr_disestablish(sc->sc_pf, sc->sc_xe.sc_ih); 471 sc->sc_xe.sc_ih = NULL; 472 pcmcia_function_disable(sc->sc_pf); 473 break; 474 case DVACT_RESUME: 475 pcmcia_function_enable(sc->sc_pf); 476 sc->sc_xe.sc_ih = pcmcia_intr_establish(sc->sc_pf, IPL_NET, 477 xe_intr, sc, sc->sc_xe.sc_dev.dv_xname); 478 /* XXX this is a ridiculous */ 479 xe_reset(&sc->sc_xe); 480 if ((ifp->if_flags & IFF_UP) == 0) 481 xe_stop(&sc->sc_xe); 482 break; 483 case DVACT_DEACTIVATE: 484 ifp->if_timer = 0; 485 ifp->if_flags &= ~IFF_RUNNING; 486 if (sc->sc_xe.sc_ih) 487 pcmcia_intr_disestablish(sc->sc_pf, sc->sc_xe.sc_ih); 488 sc->sc_xe.sc_ih = NULL; 489 pcmcia_function_disable(sc->sc_pf); 490 break; 491 } 492 return (0); 493 } 494 495 /* 496 * XXX These two functions might be OK to factor out into pcmcia.c since 497 * if_sm_pcmcia.c uses similar ones. 498 */ 499 int 500 xe_pcmcia_funce_enaddr(parent, myla) 501 struct device *parent; 502 u_int8_t *myla; 503 { 504 /* XXX The Linux driver has more ways to do this in case of failure. */ 505 return (pcmcia_scan_cis(parent, xe_pcmcia_lan_nid_ciscallback, myla)); 506 } 507 508 int 509 xe_pcmcia_lan_nid_ciscallback(tuple, arg) 510 struct pcmcia_tuple *tuple; 511 void *arg; 512 { 513 u_int8_t *myla = arg; 514 int i; 515 516 if (tuple->code == PCMCIA_CISTPL_FUNCE) { 517 if (tuple->length < 2) 518 return (0); 519 520 switch (pcmcia_tuple_read_1(tuple, 0)) { 521 case PCMCIA_TPLFE_TYPE_LAN_NID: 522 if (pcmcia_tuple_read_1(tuple, 1) != ETHER_ADDR_LEN) 523 return (0); 524 break; 525 526 case 0x02: 527 /* 528 * Not sure about this, I don't have a CE2 529 * that puts the ethernet addr here. 530 */ 531 if (pcmcia_tuple_read_1(tuple, 1) != 13) 532 return (0); 533 break; 534 535 default: 536 return (0); 537 } 538 539 for (i = 0; i < ETHER_ADDR_LEN; i++) 540 myla[i] = pcmcia_tuple_read_1(tuple, i + 2); 541 return (1); 542 } 543 544 /* Yet another spot where this might be. */ 545 if (tuple->code == 0x89) { 546 pcmcia_tuple_read_1(tuple, 1); 547 for (i = 0; i < ETHER_ADDR_LEN; i++) 548 myla[i] = pcmcia_tuple_read_1(tuple, i + 2); 549 return (1); 550 } 551 return (0); 552 } 553 554 u_int32_t 555 xe_pcmcia_interpret_manfid (parent) 556 struct device *parent; 557 { 558 u_int32_t flags = 0; 559 struct pcmcia_softc *psc = (struct pcmcia_softc *)parent; 560 char *tptr; 561 562 if (!pcmcia_scan_cis(parent, xe_pcmcia_manfid_ciscallback, &flags)) 563 return (XEF_UNSUPPORTED); 564 565 if (flags & XEF_CE) { 566 tptr = memchr(psc->card.cis1_info[2], 'C', 567 strlen(psc->card.cis1_info[2])); 568 /* XXX not sure if other CE2s hide "CE2" in different places */ 569 if (tptr && *(tptr + 1) == 'E' && *(tptr + 2) == '2') { 570 flags ^= (XEF_CE | XEF_UNSUPPORTED); 571 flags |= XEF_CE2; 572 } 573 } 574 return (flags); 575 } 576 577 int 578 xe_pcmcia_manfid_ciscallback(tuple, arg) 579 struct pcmcia_tuple *tuple; 580 void *arg; 581 { 582 u_int32_t *flagsp = arg; 583 u_int8_t media, product; 584 585 if (tuple->code == PCMCIA_CISTPL_MANFID) { 586 if (tuple->length < 2) 587 return (0); 588 589 media = pcmcia_tuple_read_1(tuple, 3); 590 product = pcmcia_tuple_read_1(tuple, 4); 591 592 if (!(product & XEPROD_CREDITCARD) || 593 !(media & XEMEDIA_ETHER)) { 594 *flagsp |= XEF_UNSUPPORTED; 595 return (1); 596 } 597 598 if (media & XEMEDIA_MODEM) 599 *flagsp |= XEF_MODEM; 600 601 switch (product & XEPROD_IDMASK) { 602 case 1: 603 /* XXX Can be CE2 too (we double-check later). */ 604 *flagsp |= XEF_CE | XEF_UNSUPPORTED; 605 break; 606 case 2: 607 *flagsp |= XEF_CE2; 608 break; 609 case 3: 610 if (!(*flagsp & XEF_MODEM)) 611 *flagsp |= XEF_MOHAWK; 612 *flagsp |= XEF_CE3; 613 break; 614 case 4: 615 *flagsp |= XEF_CE33; 616 break; 617 case 5: 618 *flagsp |= XEF_CE56 | XEF_MOHAWK; 619 break; 620 case 6: 621 case 7: 622 *flagsp |= XEF_CE56 | XEF_MOHAWK | XEF_DINGO; 623 break; 624 default: 625 *flagsp |= XEF_UNSUPPORTED; 626 break; 627 } 628 629 return (1); 630 } 631 return (0); 632 } 633 634 int 635 xe_intr(arg) 636 void *arg; 637 { 638 struct xe_softc *sc = arg; 639 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 640 u_int8_t esr, rsr, isr, rx_status, savedpage; 641 u_int16_t tx_status, recvcount = 0, tempint; 642 643 ifp->if_timer = 0; /* turn watchdog timer off */ 644 645 if (sc->sc_flags & XEF_MOHAWK) { 646 /* Disable interrupt (Linux does it). */ 647 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 648 0); 649 } 650 651 savedpage = 652 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + PR); 653 654 PAGE(sc, 0); 655 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ESR); 656 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ISR0); 657 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 658 659 /* Check to see if card has been ejected. */ 660 if (isr == 0xff) { 661 printf("%s: interrupt for dead card\n", sc->sc_dev.dv_xname); 662 goto end; 663 } 664 665 PAGE(sc, 40); 666 rx_status = 667 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RXST0); 668 tx_status = 669 bus_space_read_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST0); 670 671 /* 672 * XXX Linux writes to RXST0 and TXST* here. My CE2 works just fine 673 * without it, and I can't see an obvious reason for it. 674 */ 675 676 PAGE(sc, 0); 677 while (esr & FULL_PKT_RCV) { 678 if (!(rsr & RSR_RX_OK)) 679 break; 680 681 /* Compare bytes read this interrupt to hard maximum. */ 682 if (recvcount > MAX_BYTES_INTR) { 683 DPRINTF(XED_INTR, 684 ("%s: too many bytes this interrupt\n", 685 sc->sc_dev.dv_xname)); 686 ifp->if_iqdrops++; 687 /* Drop packet. */ 688 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 689 sc->sc_offset + DO0, DO_SKIP_RX_PKT); 690 } 691 tempint = xe_get(sc); 692 recvcount += tempint; 693 ifp->if_ibytes += tempint; 694 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 695 sc->sc_offset + ESR); 696 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 697 sc->sc_offset + RSR); 698 } 699 700 /* Packet too long? */ 701 if (rsr & RSR_TOO_LONG) { 702 ifp->if_ierrors++; 703 DPRINTF(XED_INTR, 704 ("%s: packet too long\n", sc->sc_dev.dv_xname)); 705 } 706 707 /* CRC error? */ 708 if (rsr & RSR_CRCERR) { 709 ifp->if_ierrors++; 710 DPRINTF(XED_INTR, 711 ("%s: CRC error detected\n", sc->sc_dev.dv_xname)); 712 } 713 714 /* Alignment error? */ 715 if (rsr & RSR_ALIGNERR) { 716 ifp->if_ierrors++; 717 DPRINTF(XED_INTR, 718 ("%s: alignment error detected\n", sc->sc_dev.dv_xname)); 719 } 720 721 /* Check for rx overrun. */ 722 if (rx_status & RX_OVERRUN) { 723 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 724 CLR_RX_OVERRUN); 725 DPRINTF(XED_INTR, ("overrun cleared\n")); 726 } 727 728 /* Try to start more packets transmitting. */ 729 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 730 xe_start(ifp); 731 732 /* Detected excessive collisions? */ 733 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 734 DPRINTF(XED_INTR, 735 ("%s: excessive collisions\n", sc->sc_dev.dv_xname)); 736 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 737 RESTART_TX); 738 ifp->if_oerrors++; 739 } 740 741 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 742 ifp->if_oerrors++; 743 744 end: 745 /* Reenable interrupts. */ 746 PAGE(sc, savedpage); 747 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 748 ENABLE_INT); 749 750 return (1); 751 } 752 753 u_int16_t 754 xe_get(sc) 755 struct xe_softc *sc; 756 { 757 u_int8_t rsr; 758 struct mbuf *top, **mp, *m; 759 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 760 u_int16_t pktlen, len, recvcount = 0; 761 u_int8_t *data; 762 763 PAGE(sc, 0); 764 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 765 766 pktlen = 767 bus_space_read_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RBC0) & 768 RBC_COUNT_MASK; 769 if (pktlen == 0) { 770 /* 771 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 772 * when MPE is set. It is not known why. 773 */ 774 return (0); 775 } 776 recvcount += pktlen; 777 778 MGETHDR(m, M_DONTWAIT, MT_DATA); 779 if (m == 0) 780 return (recvcount); 781 m->m_pkthdr.rcvif = ifp; 782 m->m_pkthdr.len = pktlen; 783 len = MHLEN; 784 top = 0; 785 mp = ⊤ 786 787 while (pktlen > 0) { 788 if (top) { 789 MGET(m, M_DONTWAIT, MT_DATA); 790 if (m == 0) { 791 m_freem(top); 792 return (recvcount); 793 } 794 len = MLEN; 795 } 796 if (pktlen >= MINCLSIZE) { 797 MCLGET(m, M_DONTWAIT); 798 if (!(m->m_flags & M_EXT)) { 799 m_freem(m); 800 m_freem(top); 801 return (recvcount); 802 } 803 len = MCLBYTES; 804 } 805 if (!top) { 806 caddr_t newdata = (caddr_t)ALIGN(m->m_data + 807 sizeof (struct ether_header)) - 808 sizeof (struct ether_header); 809 len -= newdata - m->m_data; 810 m->m_data = newdata; 811 } 812 len = min(pktlen, len); 813 814 data = mtod(m, u_int8_t *); 815 if (len > 1) { 816 len &= ~1; 817 bus_space_read_raw_multi_2(sc->sc_bst, sc->sc_bsh, 818 sc->sc_offset + EDP, data, len); 819 } else 820 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 821 sc->sc_offset + EDP); 822 m->m_len = len; 823 pktlen -= len; 824 *mp = m; 825 mp = &m->m_next; 826 } 827 828 /* Skip Rx packet. */ 829 bus_space_write_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + DO0, 830 DO_SKIP_RX_PKT); 831 832 ifp->if_ipackets++; 833 834 #if NBPFILTER > 0 835 if (ifp->if_bpf) 836 bpf_mtap(ifp->if_bpf, top, BPF_DIRECTION_IN); 837 #endif 838 839 ether_input_mbuf(ifp, top); 840 return (recvcount); 841 } 842 843 844 /* 845 * Serial management for the MII. 846 * The DELAY's below stem from the fact that the maximum frequency 847 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 848 * go much faster than that. 849 */ 850 851 /* Let the MII serial management be idle for one period. */ 852 static INLINE void xe_mdi_idle(struct xe_softc *); 853 static INLINE void 854 xe_mdi_idle(sc) 855 struct xe_softc *sc; 856 { 857 bus_space_tag_t bst = sc->sc_bst; 858 bus_space_handle_t bsh = sc->sc_bsh; 859 bus_size_t offset = sc->sc_offset; 860 861 /* Drive MDC low... */ 862 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 863 DELAY(1); 864 865 /* and high again. */ 866 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 867 DELAY(1); 868 } 869 870 /* Pulse out one bit of data. */ 871 static INLINE void xe_mdi_pulse(struct xe_softc *, int); 872 static INLINE void 873 xe_mdi_pulse(sc, data) 874 struct xe_softc *sc; 875 int data; 876 { 877 bus_space_tag_t bst = sc->sc_bst; 878 bus_space_handle_t bsh = sc->sc_bsh; 879 bus_size_t offset = sc->sc_offset; 880 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 881 882 /* First latch the data bit MDIO with clock bit MDC low...*/ 883 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_LOW); 884 DELAY(1); 885 886 /* then raise the clock again, preserving the data bit. */ 887 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_HIGH); 888 DELAY(1); 889 } 890 891 /* Probe one bit of data. */ 892 static INLINE int xe_mdi_probe(struct xe_softc *sc); 893 static INLINE int 894 xe_mdi_probe(sc) 895 struct xe_softc *sc; 896 { 897 bus_space_tag_t bst = sc->sc_bst; 898 bus_space_handle_t bsh = sc->sc_bsh; 899 bus_size_t offset = sc->sc_offset; 900 u_int8_t x; 901 902 /* Pull clock bit MDCK low... */ 903 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 904 DELAY(1); 905 906 /* Read data and drive clock high again. */ 907 x = bus_space_read_1(bst, bsh, offset + GP2) & MDIO; 908 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 909 DELAY(1); 910 911 return (x); 912 } 913 914 /* Pulse out a sequence of data bits. */ 915 static INLINE void xe_mdi_pulse_bits(struct xe_softc *, u_int32_t, int); 916 static INLINE void 917 xe_mdi_pulse_bits(sc, data, len) 918 struct xe_softc *sc; 919 u_int32_t data; 920 int len; 921 { 922 u_int32_t mask; 923 924 for (mask = 1 << (len - 1); mask; mask >>= 1) 925 xe_mdi_pulse(sc, data & mask); 926 } 927 928 /* Read a PHY register. */ 929 int 930 xe_mdi_read(self, phy, reg) 931 struct device *self; 932 int phy; 933 int reg; 934 { 935 struct xe_softc *sc = (struct xe_softc *)self; 936 int i; 937 u_int32_t mask; 938 u_int32_t data = 0; 939 940 PAGE(sc, 2); 941 for (i = 0; i < 32; i++) /* Synchronize. */ 942 xe_mdi_pulse(sc, 1); 943 xe_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 944 xe_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 945 xe_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 946 xe_mdi_idle(sc); /* Turn around. */ 947 xe_mdi_probe(sc); /* Drop initial zero bit. */ 948 949 for (mask = 1 << 15; mask; mask >>= 1) 950 if (xe_mdi_probe(sc)) 951 data |= mask; 952 xe_mdi_idle(sc); 953 954 DPRINTF(XED_MII, 955 ("xe_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 956 return (data); 957 } 958 959 /* Write a PHY register. */ 960 void 961 xe_mdi_write(self, phy, reg, value) 962 struct device *self; 963 int phy; 964 int reg; 965 int value; 966 { 967 struct xe_softc *sc = (struct xe_softc *)self; 968 int i; 969 970 PAGE(sc, 2); 971 for (i = 0; i < 32; i++) /* Synchronize. */ 972 xe_mdi_pulse(sc, 1); 973 xe_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 974 xe_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 975 xe_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 976 xe_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 977 xe_mdi_pulse_bits(sc, value, 16); /* Write the data */ 978 xe_mdi_idle(sc); /* Idle away. */ 979 980 DPRINTF(XED_MII, 981 ("xe_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 982 } 983 984 void 985 xe_statchg(self) 986 struct device *self; 987 { 988 } 989 990 /* 991 * Change media according to request. 992 */ 993 int 994 xe_mediachange(ifp) 995 struct ifnet *ifp; 996 { 997 if (ifp->if_flags & IFF_UP) 998 xe_init(ifp->if_softc); 999 return (0); 1000 } 1001 1002 /* 1003 * Notify the world which media we're using. 1004 */ 1005 void 1006 xe_mediastatus(ifp, ifmr) 1007 struct ifnet *ifp; 1008 struct ifmediareq *ifmr; 1009 { 1010 struct xe_softc *sc = ifp->if_softc; 1011 1012 mii_pollstat(&sc->sc_mii); 1013 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1014 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1015 } 1016 1017 void 1018 xe_reset(sc) 1019 struct xe_softc *sc; 1020 { 1021 int s; 1022 1023 s = splnet(); 1024 xe_stop(sc); 1025 xe_full_reset(sc); 1026 xe_init(sc); 1027 splx(s); 1028 } 1029 1030 void 1031 xe_watchdog(ifp) 1032 struct ifnet *ifp; 1033 { 1034 struct xe_softc *sc = ifp->if_softc; 1035 1036 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1037 ++sc->sc_arpcom.ac_if.if_oerrors; 1038 1039 xe_reset(sc); 1040 } 1041 1042 void 1043 xe_stop(sc) 1044 register struct xe_softc *sc; 1045 { 1046 /* Disable interrupts. */ 1047 PAGE(sc, 0); 1048 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 0); 1049 1050 PAGE(sc, 1); 1051 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + IMR0, 0); 1052 1053 /* Power down, wait. */ 1054 PAGE(sc, 4); 1055 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + GP1, 0); 1056 DELAY(40000); 1057 1058 /* Cancel watchdog timer. */ 1059 sc->sc_arpcom.ac_if.if_timer = 0; 1060 } 1061 1062 void 1063 xe_init(sc) 1064 struct xe_softc *sc; 1065 { 1066 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1067 int s; 1068 1069 DPRINTF(XED_CONFIG, ("xe_init\n")); 1070 1071 s = splnet(); 1072 1073 xe_set_address(sc); 1074 1075 /* Set current media. */ 1076 mii_mediachg(&sc->sc_mii); 1077 1078 ifp->if_flags |= IFF_RUNNING; 1079 ifp->if_flags &= ~IFF_OACTIVE; 1080 splx(s); 1081 } 1082 1083 /* 1084 * Start outputting on the interface. 1085 * Always called as splnet(). 1086 */ 1087 void 1088 xe_start(ifp) 1089 struct ifnet *ifp; 1090 { 1091 struct xe_softc *sc = ifp->if_softc; 1092 bus_space_tag_t bst = sc->sc_bst; 1093 bus_space_handle_t bsh = sc->sc_bsh; 1094 bus_size_t offset = sc->sc_offset; 1095 unsigned int s, len, pad = 0; 1096 struct mbuf *m0, *m; 1097 u_int16_t space; 1098 1099 /* Don't transmit if interface is busy or not running. */ 1100 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1101 return; 1102 1103 /* Peek at the next packet. */ 1104 IFQ_POLL(&ifp->if_snd, m0); 1105 if (m0 == 0) 1106 return; 1107 1108 /* We need to use m->m_pkthdr.len, so require the header. */ 1109 if (!(m0->m_flags & M_PKTHDR)) 1110 panic("xe_start: no header mbuf"); 1111 1112 len = m0->m_pkthdr.len; 1113 1114 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 1115 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 1116 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 1117 1118 PAGE(sc, 0); 1119 space = bus_space_read_2(bst, bsh, offset + TSO0) & 0x7fff; 1120 if (len + pad + 2 > space) { 1121 DPRINTF(XED_FIFO, 1122 ("%s: not enough space in output FIFO (%d > %d)\n", 1123 sc->sc_dev.dv_xname, len + pad + 2, space)); 1124 return; 1125 } 1126 1127 IFQ_DEQUEUE(&ifp->if_snd, m0); 1128 1129 #if NBPFILTER > 0 1130 if (ifp->if_bpf) 1131 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 1132 #endif 1133 1134 /* 1135 * Do the output at splhigh() so that an interrupt from another device 1136 * won't cause a FIFO underrun. 1137 */ 1138 s = splhigh(); 1139 1140 bus_space_write_2(bst, bsh, offset + TSO2, (u_int16_t)len + pad + 2); 1141 bus_space_write_2(bst, bsh, offset + EDP, (u_int16_t)len + pad); 1142 for (m = m0; m; ) { 1143 if (m->m_len > 1) 1144 bus_space_write_raw_multi_2(bst, bsh, offset + EDP, 1145 mtod(m, u_int8_t *), m->m_len & ~1); 1146 if (m->m_len & 1) 1147 bus_space_write_1(bst, bsh, offset + EDP, 1148 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1149 MFREE(m, m0); 1150 m = m0; 1151 } 1152 if (sc->sc_flags & XEF_MOHAWK) 1153 bus_space_write_1(bst, bsh, offset + CR, TX_PKT | ENABLE_INT); 1154 else { 1155 for (; pad > 1; pad -= 2) 1156 bus_space_write_2(bst, bsh, offset + EDP, 0); 1157 if (pad == 1) 1158 bus_space_write_1(bst, bsh, offset + EDP, 0); 1159 } 1160 1161 splx(s); 1162 1163 ifp->if_timer = 5; 1164 ++ifp->if_opackets; 1165 } 1166 1167 int 1168 xe_ioctl(ifp, command, data) 1169 struct ifnet *ifp; 1170 u_long command; 1171 caddr_t data; 1172 { 1173 struct xe_softc *sc = ifp->if_softc; 1174 struct ifaddr *ifa = (struct ifaddr *)data; 1175 struct ifreq *ifr = (struct ifreq *)data; 1176 int s, error = 0; 1177 1178 s = splnet(); 1179 1180 switch (command) { 1181 case SIOCSIFADDR: 1182 ifp->if_flags |= IFF_UP; 1183 xe_init(sc); 1184 #ifdef INET 1185 if (ifa->ifa_addr->sa_family == AF_INET) 1186 arp_ifinit(&sc->sc_arpcom, ifa); 1187 #endif /* INET */ 1188 break; 1189 1190 case SIOCSIFFLAGS: 1191 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1192 1193 PAGE(sc, 0x42); 1194 if ((ifp->if_flags & IFF_PROMISC) || 1195 (ifp->if_flags & IFF_ALLMULTI)) 1196 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1197 sc->sc_offset + SWC1, 1198 SWC1_PROMISC | SWC1_MCAST_PROM); 1199 else 1200 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1201 sc->sc_offset + SWC1, 0); 1202 1203 /* 1204 * If interface is marked up and not running, then start it. 1205 * If it is marked down and running, stop it. 1206 * XXX If it's up then re-initialize it. This is so flags 1207 * such as IFF_PROMISC are handled. 1208 */ 1209 if (ifp->if_flags & IFF_UP) { 1210 xe_init(sc); 1211 } else { 1212 if (ifp->if_flags & IFF_RUNNING) 1213 xe_stop(sc); 1214 } 1215 break; 1216 1217 case SIOCADDMULTI: 1218 case SIOCDELMULTI: 1219 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1220 error = (command == SIOCADDMULTI) ? 1221 ether_addmulti(ifr, &sc->sc_arpcom) : 1222 ether_delmulti(ifr, &sc->sc_arpcom); 1223 1224 if (error == ENETRESET) { 1225 /* 1226 * Multicast list has changed; set the hardware 1227 * filter accordingly. 1228 */ 1229 if (!sc->sc_all_mcasts && 1230 !(ifp->if_flags & IFF_PROMISC)) 1231 xe_set_address(sc); 1232 1233 /* 1234 * xe_set_address() can turn on all_mcasts if we run 1235 * out of space, so check it again rather than else {}. 1236 */ 1237 if (sc->sc_all_mcasts) 1238 xe_init(sc); 1239 error = 0; 1240 } 1241 break; 1242 1243 case SIOCSIFMEDIA: 1244 case SIOCGIFMEDIA: 1245 error = 1246 ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1247 break; 1248 1249 default: 1250 error = ENOTTY; 1251 } 1252 1253 splx(s); 1254 return (error); 1255 } 1256 1257 void 1258 xe_set_address(sc) 1259 struct xe_softc *sc; 1260 { 1261 bus_space_tag_t bst = sc->sc_bst; 1262 bus_space_handle_t bsh = sc->sc_bsh; 1263 bus_size_t offset = sc->sc_offset; 1264 struct arpcom *arp = &sc->sc_arpcom; 1265 struct ether_multi *enm; 1266 struct ether_multistep step; 1267 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1268 int i, page, pos, num; 1269 1270 PAGE(sc, 0x50); 1271 for (i = 0; i < 6; i++) { 1272 bus_space_write_1(bst, bsh, offset + IA + i, 1273 sc->sc_arpcom.ac_enaddr[(sc->sc_flags & XEF_MOHAWK) ? 1274 5 - i : i]); 1275 } 1276 1277 if (arp->ac_multirangecnt > 0) { 1278 ifp->if_flags |= IFF_ALLMULTI; 1279 sc->sc_all_mcasts=1; 1280 } else if (arp->ac_multicnt > 0) { 1281 if (arp->ac_multicnt > 9) { 1282 PAGE(sc, 0x42); 1283 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1284 sc->sc_offset + SWC1, 1285 SWC1_PROMISC | SWC1_MCAST_PROM); 1286 return; 1287 } 1288 1289 ETHER_FIRST_MULTI(step, arp, enm); 1290 1291 pos = IA + 6; 1292 for (page = 0x50, num = arp->ac_multicnt; num > 0 && enm; 1293 num--) { 1294 for (i = 0; i < 6; i++) { 1295 bus_space_write_1(bst, bsh, offset + pos, 1296 enm->enm_addrlo[ 1297 (sc->sc_flags & XEF_MOHAWK) ? 5 - i : i]); 1298 1299 if (++pos > 15) { 1300 pos = IA; 1301 page++; 1302 PAGE(sc, page); 1303 } 1304 } 1305 } 1306 } 1307 } 1308 1309 void 1310 xe_cycle_power(sc) 1311 struct xe_softc *sc; 1312 { 1313 bus_space_tag_t bst = sc->sc_bst; 1314 bus_space_handle_t bsh = sc->sc_bsh; 1315 bus_size_t offset = sc->sc_offset; 1316 1317 PAGE(sc, 4); 1318 DELAY(1); 1319 bus_space_write_1(bst, bsh, offset + GP1, 0); 1320 DELAY(40000); 1321 if (sc->sc_flags & XEF_MOHAWK) 1322 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP); 1323 else 1324 /* XXX What is bit 2 (aka AIC)? */ 1325 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP | 4); 1326 DELAY(20000); 1327 } 1328 1329 void 1330 xe_full_reset(sc) 1331 struct xe_softc *sc; 1332 { 1333 bus_space_tag_t bst = sc->sc_bst; 1334 bus_space_handle_t bsh = sc->sc_bsh; 1335 bus_size_t offset = sc->sc_offset; 1336 1337 /* Do an as extensive reset as possible on all functions. */ 1338 xe_cycle_power(sc); 1339 bus_space_write_1(bst, bsh, offset + CR, SOFT_RESET); 1340 DELAY(20000); 1341 bus_space_write_1(bst, bsh, offset + CR, 0); 1342 DELAY(20000); 1343 if (sc->sc_flags & XEF_MOHAWK) { 1344 PAGE(sc, 4); 1345 /* 1346 * Drive GP1 low to power up ML6692 and GP2 high to power up 1347 * the 10MHz chip. XXX What chip is that? The phy? 1348 */ 1349 bus_space_write_1(bst, bsh, offset + GP0, 1350 GP1_OUT | GP2_OUT | GP2_WR); 1351 } 1352 DELAY(500000); 1353 1354 /* Get revision information. XXX Symbolic constants. */ 1355 sc->sc_rev = bus_space_read_1(bst, bsh, offset + BV) & 1356 ((sc->sc_flags & XEF_MOHAWK) ? 0x70 : 0x30) >> 4; 1357 1358 /* Media selection. XXX Maybe manual overriding too? */ 1359 if (!(sc->sc_flags & XEF_MOHAWK)) { 1360 PAGE(sc, 4); 1361 /* 1362 * XXX I have no idea what this really does, it is from the 1363 * Linux driver. 1364 */ 1365 bus_space_write_1(bst, bsh, offset + GP0, GP1_OUT); 1366 } 1367 DELAY(40000); 1368 1369 /* Setup the ethernet interrupt mask. */ 1370 PAGE(sc, 1); 1371 bus_space_write_1(bst, bsh, offset + IMR0, 1372 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 1373 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 1374 #if 0 1375 bus_space_write_1(bst, bsh, offset + IMR0, 0xff); 1376 #endif 1377 if (!(sc->sc_flags & XEF_DINGO)) 1378 /* XXX What is this? Not for Dingo at least. */ 1379 bus_space_write_1(bst, bsh, offset + IMR1, 1); 1380 1381 /* 1382 * Disable source insertion. 1383 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1384 */ 1385 if (!(sc->sc_flags & XEF_DINGO)) { 1386 PAGE(sc, 0x42); 1387 bus_space_write_1(bst, bsh, offset + SWC0, 0x20); 1388 } 1389 1390 /* Set the local memory dividing line. */ 1391 if (sc->sc_rev != 1) { 1392 PAGE(sc, 2); 1393 /* XXX Symbolic constant preferrable. */ 1394 bus_space_write_2(bst, bsh, offset + RBS0, 0x2000); 1395 } 1396 1397 xe_set_address(sc); 1398 1399 /* 1400 * Apparently the receive byte pointer can be bad after a reset, so 1401 * we hardwire it correctly. 1402 */ 1403 PAGE(sc, 0); 1404 bus_space_write_2(bst, bsh, offset + DO0, DO_CHG_OFFSET); 1405 1406 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1407 PAGE(sc, 0x40); 1408 bus_space_write_1(bst, bsh, offset + RX0MSK, 1409 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1410 bus_space_write_1(bst, bsh, offset + TX0MSK, 1411 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1412 SQE | TX_ABORT | TX_OK); 1413 if (!(sc->sc_flags & XEF_DINGO)) 1414 /* XXX From Linux, dunno what 0xb0 means. */ 1415 bus_space_write_1(bst, bsh, offset + TX1MSK, 0xb0); 1416 bus_space_write_1(bst, bsh, offset + RXST0, 0); 1417 bus_space_write_1(bst, bsh, offset + TXST0, 0); 1418 bus_space_write_1(bst, bsh, offset + TXST1, 0); 1419 1420 /* Enable MII function if available. */ 1421 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 1422 PAGE(sc, 2); 1423 bus_space_write_1(bst, bsh, offset + MSR, 1424 bus_space_read_1(bst, bsh, offset + MSR) | SELECT_MII); 1425 DELAY(20000); 1426 } else { 1427 PAGE(sc, 0); 1428 1429 /* XXX Do we need to do this? */ 1430 PAGE(sc, 0x42); 1431 bus_space_write_1(bst, bsh, offset + SWC1, SWC1_AUTO_MEDIA); 1432 DELAY(50000); 1433 1434 /* XXX Linux probes the media here. */ 1435 } 1436 1437 /* Configure the LED registers. */ 1438 PAGE(sc, 2); 1439 1440 /* XXX This is not good for 10base2. */ 1441 bus_space_write_1(bst, bsh, offset + LED, 1442 LED_TX_ACT << LED1_SHIFT | LED_10MB_LINK << LED0_SHIFT); 1443 if (sc->sc_flags & XEF_DINGO) 1444 bus_space_write_1(bst, bsh, offset + LED3, 1445 LED_100MB_LINK << LED3_SHIFT); 1446 1447 /* Enable receiver and go online. */ 1448 PAGE(sc, 0x40); 1449 bus_space_write_1(bst, bsh, offset + CMD0, ENABLE_RX | ONLINE); 1450 1451 #if 0 1452 /* XXX Linux does this here - is it necessary? */ 1453 PAGE(sc, 1); 1454 bus_space_write_1(bst, bsh, offset + IMR0, 0xff); 1455 if (!(sc->sc_flags & XEF_DINGO)) 1456 /* XXX What is this? Not for Dingo at least. */ 1457 bus_space_write_1(bst, bsh, offset + IMR1, 1); 1458 #endif 1459 1460 /* Enable interrupts. */ 1461 PAGE(sc, 0); 1462 bus_space_write_1(bst, bsh, offset + CR, ENABLE_INT); 1463 1464 /* XXX This is pure magic for me, found in the Linux driver. */ 1465 if ((sc->sc_flags & (XEF_DINGO | XEF_MODEM)) == XEF_MODEM) { 1466 if ((bus_space_read_1(bst, bsh, offset + 0x10) & 0x01) == 0) 1467 /* Unmask the master interrupt bit. */ 1468 bus_space_write_1(bst, bsh, offset + 0x10, 0x11); 1469 } 1470 1471 /* 1472 * The Linux driver says this: 1473 * We should switch back to page 0 to avoid a bug in revision 0 1474 * where regs with offset below 8 can't be read after an access 1475 * to the MAC registers. 1476 */ 1477 PAGE(sc, 0); 1478 } 1479 1480 #ifdef XEDEBUG 1481 void 1482 xe_reg_dump(sc) 1483 struct xe_softc *sc; 1484 { 1485 int page, i; 1486 bus_space_tag_t bst = sc->sc_bst; 1487 bus_space_handle_t bsh = sc->sc_bsh; 1488 bus_size_t offset = sc->sc_offset; 1489 1490 printf("%x: Common registers: ", sc->sc_dev.dv_xname); 1491 for (i = 0; i < 8; i++) { 1492 printf(" %2.2x", bus_space_read_1(bst, bsh, offset + i)); 1493 } 1494 printf("\n"); 1495 1496 for (page = 0; page < 8; page++) { 1497 printf("%s: Register page %2.2x: ", sc->sc_dev.dv_xname, page); 1498 PAGE(sc, page); 1499 for (i = 8; i < 16; i++) { 1500 printf(" %2.2x", 1501 bus_space_read_1(bst, bsh, offset + i)); 1502 } 1503 printf("\n"); 1504 } 1505 1506 for (page = 0x40; page < 0x5f; page++) { 1507 if (page == 0x43 || (page >= 0x46 && page <= 0x4f) || 1508 (page >= 0x51 && page <= 0x5e)) 1509 continue; 1510 printf("%s: Register page %2.2x: ", sc->sc_dev.dv_xname, page); 1511 PAGE(sc, page); 1512 for (i = 8; i < 16; i++) { 1513 printf(" %2.2x", 1514 bus_space_read_1(bst, bsh, offset + i)); 1515 } 1516 printf("\n"); 1517 } 1518 } 1519 #endif /* XEDEBUG */ 1520