1 /* $OpenBSD: vmwpvs.c,v 1.22 2020/07/20 14:41:14 krw Exp $ */ 2 3 /* 4 * Copyright (c) 2013 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/param.h> 20 #include <sys/systm.h> 21 #include <sys/device.h> 22 #include <sys/ioctl.h> 23 #include <sys/malloc.h> 24 #include <sys/kernel.h> 25 #include <sys/rwlock.h> 26 #include <sys/dkio.h> 27 #include <sys/task.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcireg.h> 32 #include <dev/pci/pcivar.h> 33 #include <dev/pci/pcidevs.h> 34 35 #include <scsi/scsi_all.h> 36 #include <scsi/scsi_message.h> 37 #include <scsi/scsiconf.h> 38 39 /* pushbuttons */ 40 #define VMWPVS_OPENINGS 64 /* according to the linux driver */ 41 #define VMWPVS_RING_PAGES 2 42 #define VMWPVS_MAXSGL (MAXPHYS / PAGE_SIZE) 43 #define VMWPVS_SENSELEN roundup(sizeof(struct scsi_sense_data), 16) 44 45 /* "chip" definitions */ 46 47 #define VMWPVS_R_COMMAND 0x0000 48 #define VMWPVS_R_COMMAND_DATA 0x0004 49 #define VMWPVS_R_COMMAND_STATUS 0x0008 50 #define VMWPVS_R_LAST_STS_0 0x0100 51 #define VMWPVS_R_LAST_STS_1 0x0104 52 #define VMWPVS_R_LAST_STS_2 0x0108 53 #define VMWPVS_R_LAST_STS_3 0x010c 54 #define VMWPVS_R_INTR_STATUS 0x100c 55 #define VMWPVS_R_INTR_MASK 0x2010 56 #define VMWPVS_R_KICK_NON_RW_IO 0x3014 57 #define VMWPVS_R_DEBUG 0x3018 58 #define VMWPVS_R_KICK_RW_IO 0x4018 59 60 #define VMWPVS_INTR_CMPL_0 (1 << 0) 61 #define VMWPVS_INTR_CMPL_1 (1 << 1) 62 #define VMWPVS_INTR_CMPL_MASK (VMWPVS_INTR_CMPL_0 | VMWPVS_INTR_CMPL_1) 63 #define VMWPVS_INTR_MSG_0 (1 << 2) 64 #define VMWPVS_INTR_MSG_1 (1 << 3) 65 #define VMWPVS_INTR_MSG_MASK (VMWPVS_INTR_MSG_0 | VMWPVS_INTR_MSG_1) 66 #define VMWPVS_INTR_ALL_MASK (VMWPVS_INTR_CMPL_MASK | VMWPVS_INTR_MSG_MASK) 67 68 #define VMWPVS_PAGE_SHIFT 12 69 #define VMWPVS_PAGE_SIZE (1 << VMWPVS_PAGE_SHIFT) 70 71 #define VMWPVS_NPG_COMMAND 1 72 #define VMWPVS_NPG_INTR_STATUS 1 73 #define VMWPVS_NPG_MISC 2 74 #define VMWPVS_NPG_KICK_IO 2 75 #define VMWPVS_NPG_MSI_X 2 76 77 #define VMWPVS_PG_COMMAND 0 78 #define VMWPVS_PG_INTR_STATUS (VMWPVS_PG_COMMAND + \ 79 VMWPVS_NPG_COMMAND * VMWPVS_PAGE_SIZE) 80 #define VMWPVS_PG_MISC (VMWPVS_PG_INTR_STATUS + \ 81 VMWPVS_NPG_INTR_STATUS * VMWPVS_PAGE_SIZE) 82 #define VMWPVS_PG_KICK_IO (VMWPVS_PG_MISC + \ 83 VMWPVS_NPG_MISC * VMWPVS_PAGE_SIZE) 84 #define VMWPVS_PG_MSI_X (VMWPVS_PG_KICK_IO + \ 85 VMWPVS_NPG_KICK_IO * VMWPVS_PAGE_SIZE) 86 #define VMMPVS_PG_LEN (VMWPVS_PG_MSI_X + \ 87 VMWPVS_NPG_MSI_X * VMWPVS_PAGE_SIZE) 88 89 struct vmwpvw_ring_state { 90 u_int32_t req_prod; 91 u_int32_t req_cons; 92 u_int32_t req_entries; /* log 2 */ 93 94 u_int32_t cmp_prod; 95 u_int32_t cmp_cons; 96 u_int32_t cmp_entries; /* log 2 */ 97 98 u_int32_t __reserved[26]; 99 100 u_int32_t msg_prod; 101 u_int32_t msg_cons; 102 u_int32_t msg_entries; /* log 2 */ 103 } __packed; 104 105 struct vmwpvs_ring_req { 106 u_int64_t context; 107 108 u_int64_t data_addr; 109 u_int64_t data_len; 110 111 u_int64_t sense_addr; 112 u_int32_t sense_len; 113 114 u_int32_t flags; 115 #define VMWPVS_REQ_SGL (1 << 0) 116 #define VMWPVS_REQ_OOBCDB (1 << 1) 117 #define VMWPVS_REQ_DIR_NONE (1 << 2) 118 #define VMWPVS_REQ_DIR_IN (1 << 3) 119 #define VMWPVS_REQ_DIR_OUT (1 << 4) 120 121 u_int8_t cdb[16]; 122 u_int8_t cdblen; 123 u_int8_t lun[8]; 124 u_int8_t tag; 125 u_int8_t bus; 126 u_int8_t target; 127 u_int8_t vcpu_hint; 128 129 u_int8_t __reserved[59]; 130 } __packed; 131 #define VMWPVS_REQ_COUNT ((VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE) / \ 132 sizeof(struct vmwpvs_ring_req)) 133 134 struct vmwpvs_ring_cmp { 135 u_int64_t context; 136 u_int64_t data_len; 137 u_int32_t sense_len; 138 u_int16_t host_status; 139 u_int16_t scsi_status; 140 u_int32_t __reserved[2]; 141 } __packed; 142 #define VMWPVS_CMP_COUNT ((VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE) / \ 143 sizeof(struct vmwpvs_ring_cmp)) 144 145 struct vmwpvs_sge { 146 u_int64_t addr; 147 u_int32_t len; 148 u_int32_t flags; 149 } __packed; 150 151 struct vmwpvs_ring_msg { 152 u_int32_t type; 153 u_int32_t __args[31]; 154 } __packed; 155 #define VMWPVS_MSG_COUNT ((VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE) / \ 156 sizeof(struct vmwpvs_ring_msg)) 157 158 #define VMWPVS_MSG_T_ADDED 0 159 #define VMWPVS_MSG_T_REMOVED 1 160 161 struct vmwpvs_ring_msg_dev { 162 u_int32_t type; 163 u_int32_t bus; 164 u_int32_t target; 165 u_int8_t lun[8]; 166 167 u_int32_t __pad[27]; 168 } __packed; 169 170 struct vmwpvs_cfg_cmd { 171 u_int64_t cmp_addr; 172 u_int32_t pg_addr; 173 u_int32_t pg_addr_type; 174 u_int32_t pg_num; 175 u_int32_t __reserved; 176 } __packed; 177 178 #define VMWPVS_MAX_RING_PAGES 32 179 struct vmwpvs_setup_rings_cmd { 180 u_int32_t req_pages; 181 u_int32_t cmp_pages; 182 u_int64_t state_ppn; 183 u_int64_t req_page_ppn[VMWPVS_MAX_RING_PAGES]; 184 u_int64_t cmp_page_ppn[VMWPVS_MAX_RING_PAGES]; 185 } __packed; 186 187 #define VMWPVS_MAX_MSG_RING_PAGES 16 188 struct vmwpvs_setup_rings_msg { 189 u_int32_t msg_pages; 190 u_int32_t __reserved; 191 u_int64_t msg_page_ppn[VMWPVS_MAX_MSG_RING_PAGES]; 192 } __packed; 193 194 #define VMWPVS_CMD_FIRST 0 195 #define VMWPVS_CMD_ADAPTER_RESET 1 196 #define VMWPVS_CMD_ISSUE_SCSI 2 197 #define VMWPVS_CMD_SETUP_RINGS 3 198 #define VMWPVS_CMD_RESET_BUS 4 199 #define VMWPVS_CMD_RESET_DEVICE 5 200 #define VMWPVS_CMD_ABORT_CMD 6 201 #define VMWPVS_CMD_CONFIG 7 202 #define VMWPVS_CMD_SETUP_MSG_RING 8 203 #define VMWPVS_CMD_DEVICE_UNPLUG 9 204 #define VMWPVS_CMD_LAST 10 205 206 #define VMWPVS_CFGPG_CONTROLLER 0x1958 207 #define VMWPVS_CFGPG_PHY 0x1959 208 #define VMWPVS_CFGPG_DEVICE 0x195a 209 210 #define VMWPVS_CFGPGADDR_CONTROLLER 0x2120 211 #define VMWPVS_CFGPGADDR_TARGET 0x2121 212 #define VMWPVS_CFGPGADDR_PHY 0x2122 213 214 struct vmwpvs_cfg_pg_header { 215 u_int32_t pg_num; 216 u_int16_t num_dwords; 217 u_int16_t host_status; 218 u_int16_t scsi_status; 219 u_int16_t __reserved[3]; 220 } __packed; 221 222 #define VMWPVS_HOST_STATUS_SUCCESS 0x00 223 #define VMWPVS_HOST_STATUS_LINKED_CMD_COMPLETED 0x0a 224 #define VMWPVS_HOST_STATUS_LINKED_CMD_COMPLETED_WITH_FLAG 0x0b 225 #define VMWPVS_HOST_STATUS_UNDERRUN 0x0c 226 #define VMWPVS_HOST_STATUS_SELTIMEOUT 0x11 227 #define VMWPVS_HOST_STATUS_DATARUN 0x12 228 #define VMWPVS_HOST_STATUS_BUSFREE 0x13 229 #define VMWPVS_HOST_STATUS_INVPHASE 0x14 230 #define VMWPVS_HOST_STATUS_LUNMISMATCH 0x17 231 #define VMWPVS_HOST_STATUS_INVPARAM 0x1a 232 #define VMWPVS_HOST_STATUS_SENSEFAILED 0x1b 233 #define VMWPVS_HOST_STATUS_TAGREJECT 0x1c 234 #define VMWPVS_HOST_STATUS_BADMSG 0x1d 235 #define VMWPVS_HOST_STATUS_HAHARDWARE 0x20 236 #define VMWPVS_HOST_STATUS_NORESPONSE 0x21 237 #define VMWPVS_HOST_STATUS_SENT_RST 0x22 238 #define VMWPVS_HOST_STATUS_RECV_RST 0x23 239 #define VMWPVS_HOST_STATUS_DISCONNECT 0x24 240 #define VMWPVS_HOST_STATUS_BUS_RESET 0x25 241 #define VMWPVS_HOST_STATUS_ABORT_QUEUE 0x26 242 #define VMWPVS_HOST_STATUS_HA_SOFTWARE 0x27 243 #define VMWPVS_HOST_STATUS_HA_TIMEOUT 0x30 244 #define VMWPVS_HOST_STATUS_SCSI_PARITY 0x34 245 246 #define VMWPVS_SCSI_STATUS_OK 0x00 247 #define VMWPVS_SCSI_STATUS_CHECK 0x02 248 249 struct vmwpvs_cfg_pg_controller { 250 struct vmwpvs_cfg_pg_header header; 251 252 u_int64_t wwnn; 253 u_int16_t manufacturer[64]; 254 u_int16_t serial_number[64]; 255 u_int16_t oprom_version[32]; 256 u_int16_t hardware_version[32]; 257 u_int16_t firmware_version[32]; 258 u_int32_t num_phys; 259 u_int8_t use_consec_phy_wwns; 260 u_int8_t __reserved[3]; 261 } __packed; 262 263 /* driver stuff */ 264 265 struct vmwpvs_dmamem { 266 bus_dmamap_t dm_map; 267 bus_dma_segment_t dm_seg; 268 size_t dm_size; 269 caddr_t dm_kva; 270 }; 271 #define VMWPVS_DMA_MAP(_dm) (_dm)->dm_map 272 #define VMWPVS_DMA_DVA(_dm) (_dm)->dm_map->dm_segs[0].ds_addr 273 #define VMWPVS_DMA_KVA(_dm) (void *)(_dm)->dm_kva 274 275 struct vmwpvs_sgl { 276 struct vmwpvs_sge list[VMWPVS_MAXSGL]; 277 } __packed; 278 279 struct vmwpvs_ccb { 280 SIMPLEQ_ENTRY(vmwpvs_ccb) 281 ccb_entry; 282 283 bus_dmamap_t ccb_dmamap; 284 struct scsi_xfer *ccb_xs; 285 u_int64_t ccb_ctx; 286 287 struct vmwpvs_sgl *ccb_sgl; 288 bus_addr_t ccb_sgl_offset; 289 290 void *ccb_sense; 291 bus_addr_t ccb_sense_offset; 292 }; 293 SIMPLEQ_HEAD(vmwpvs_ccb_list, vmwpvs_ccb); 294 295 struct vmwpvs_softc { 296 struct device sc_dev; 297 298 pci_chipset_tag_t sc_pc; 299 pcitag_t sc_tag; 300 301 bus_space_tag_t sc_iot; 302 bus_space_handle_t sc_ioh; 303 bus_size_t sc_ios; 304 bus_dma_tag_t sc_dmat; 305 306 struct vmwpvs_dmamem *sc_req_ring; 307 struct vmwpvs_dmamem *sc_cmp_ring; 308 struct vmwpvs_dmamem *sc_msg_ring; 309 struct vmwpvs_dmamem *sc_ring_state; 310 struct mutex sc_ring_mtx; 311 312 struct vmwpvs_dmamem *sc_sgls; 313 struct vmwpvs_dmamem *sc_sense; 314 struct vmwpvs_ccb *sc_ccbs; 315 struct vmwpvs_ccb_list sc_ccb_list; 316 struct mutex sc_ccb_mtx; 317 318 void *sc_ih; 319 320 struct task sc_msg_task; 321 322 u_int sc_bus_width; 323 324 struct scsi_link sc_link; 325 struct scsi_iopool sc_iopool; 326 struct scsibus_softc *sc_scsibus; 327 }; 328 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 329 330 int vmwpvs_match(struct device *, void *, void *); 331 void vmwpvs_attach(struct device *, struct device *, void *); 332 333 int vmwpvs_intx(void *); 334 int vmwpvs_intr(void *); 335 336 #define vmwpvs_read(_s, _r) \ 337 bus_space_read_4((_s)->sc_iot, (_s)->sc_ioh, (_r)) 338 #define vmwpvs_write(_s, _r, _v) \ 339 bus_space_write_4((_s)->sc_iot, (_s)->sc_ioh, (_r), (_v)) 340 #define vmwpvs_barrier(_s, _r, _l, _d) \ 341 bus_space_barrier((_s)->sc_iot, (_s)->sc_ioh, (_r), (_l), (_d)) 342 343 struct cfattach vmwpvs_ca = { 344 sizeof(struct vmwpvs_softc), 345 vmwpvs_match, 346 vmwpvs_attach, 347 NULL 348 }; 349 350 struct cfdriver vmwpvs_cd = { 351 NULL, 352 "vmwpvs", 353 DV_DULL 354 }; 355 356 void vmwpvs_scsi_cmd(struct scsi_xfer *); 357 358 struct scsi_adapter vmwpvs_switch = { 359 vmwpvs_scsi_cmd, NULL, NULL, NULL, NULL 360 }; 361 362 #define dwordsof(s) (sizeof(s) / sizeof(u_int32_t)) 363 364 void vmwpvs_ccb_put(void *, void *); 365 void * vmwpvs_ccb_get(void *); 366 367 struct vmwpvs_dmamem * 368 vmwpvs_dmamem_alloc(struct vmwpvs_softc *, size_t); 369 struct vmwpvs_dmamem * 370 vmwpvs_dmamem_zalloc(struct vmwpvs_softc *, size_t); 371 void vmwpvs_dmamem_free(struct vmwpvs_softc *, 372 struct vmwpvs_dmamem *); 373 374 void vmwpvs_cmd(struct vmwpvs_softc *, u_int32_t, void *, size_t); 375 int vmwpvs_get_config(struct vmwpvs_softc *); 376 void vmwpvs_setup_rings(struct vmwpvs_softc *); 377 void vmwpvs_setup_msg_ring(struct vmwpvs_softc *); 378 void vmwpvs_msg_task(void *); 379 380 struct vmwpvs_ccb * 381 vmwpvs_scsi_cmd_poll(struct vmwpvs_softc *); 382 struct vmwpvs_ccb * 383 vmwpvs_scsi_cmd_done(struct vmwpvs_softc *, 384 struct vmwpvs_ring_cmp *); 385 386 int 387 vmwpvs_match(struct device *parent, void *match, void *aux) 388 { 389 struct pci_attach_args *pa = aux; 390 391 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VMWARE && 392 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VMWARE_PVSCSI) 393 return (1); 394 395 return (0); 396 } 397 398 void 399 vmwpvs_attach(struct device *parent, struct device *self, void *aux) 400 { 401 struct vmwpvs_softc *sc = (struct vmwpvs_softc *)self; 402 struct pci_attach_args *pa = aux; 403 struct scsibus_attach_args saa; 404 pcireg_t memtype; 405 u_int i, r, use_msg; 406 int (*isr)(void *) = vmwpvs_intx; 407 u_int32_t intmask; 408 pci_intr_handle_t ih; 409 410 struct vmwpvs_ccb *ccb; 411 struct vmwpvs_sgl *sgls; 412 u_int8_t *sense; 413 414 sc->sc_pc = pa->pa_pc; 415 sc->sc_tag = pa->pa_tag; 416 sc->sc_dmat = pa->pa_dmat; 417 418 sc->sc_bus_width = 16; 419 mtx_init(&sc->sc_ring_mtx, IPL_BIO); 420 mtx_init(&sc->sc_ccb_mtx, IPL_BIO); 421 task_set(&sc->sc_msg_task, vmwpvs_msg_task, sc); 422 SIMPLEQ_INIT(&sc->sc_ccb_list); 423 424 for (r = PCI_MAPREG_START; r < PCI_MAPREG_END; r += sizeof(memtype)) { 425 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, r); 426 if ((memtype & PCI_MAPREG_TYPE_MASK) == PCI_MAPREG_TYPE_MEM) 427 break; 428 } 429 if (r >= PCI_MAPREG_END) { 430 printf(": unable to locate registers\n"); 431 return; 432 } 433 434 if (pci_mapreg_map(pa, r, memtype, 0, &sc->sc_iot, &sc->sc_ioh, 435 NULL, &sc->sc_ios, VMMPVS_PG_LEN) != 0) { 436 printf(": unable to map registers\n"); 437 return; 438 } 439 440 /* hook up the interrupt */ 441 vmwpvs_write(sc, VMWPVS_R_INTR_MASK, 0); 442 443 if (pci_intr_map_msi(pa, &ih) == 0) 444 isr = vmwpvs_intr; 445 else if (pci_intr_map(pa, &ih) != 0) { 446 printf(": unable to map interrupt\n"); 447 goto unmap; 448 } 449 printf(": %s\n", pci_intr_string(sc->sc_pc, ih)); 450 451 /* do we have msg support? */ 452 vmwpvs_write(sc, VMWPVS_R_COMMAND, VMWPVS_CMD_SETUP_MSG_RING); 453 use_msg = (vmwpvs_read(sc, VMWPVS_R_COMMAND_STATUS) != 0xffffffff); 454 455 if (vmwpvs_get_config(sc) != 0) { 456 printf("%s: get configuration failed\n", DEVNAME(sc)); 457 goto unmap; 458 } 459 460 sc->sc_ring_state = vmwpvs_dmamem_zalloc(sc, VMWPVS_PAGE_SIZE); 461 if (sc->sc_ring_state == NULL) { 462 printf("%s: unable to allocate ring state\n", DEVNAME(sc)); 463 goto unmap; 464 } 465 466 sc->sc_req_ring = vmwpvs_dmamem_zalloc(sc, 467 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE); 468 if (sc->sc_req_ring == NULL) { 469 printf("%s: unable to allocate req ring\n", DEVNAME(sc)); 470 goto free_ring_state; 471 } 472 473 sc->sc_cmp_ring = vmwpvs_dmamem_zalloc(sc, 474 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE); 475 if (sc->sc_cmp_ring == NULL) { 476 printf("%s: unable to allocate cmp ring\n", DEVNAME(sc)); 477 goto free_req_ring; 478 } 479 480 if (use_msg) { 481 sc->sc_msg_ring = vmwpvs_dmamem_zalloc(sc, 482 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE); 483 if (sc->sc_msg_ring == NULL) { 484 printf("%s: unable to allocate msg ring\n", 485 DEVNAME(sc)); 486 goto free_cmp_ring; 487 } 488 } 489 490 r = (VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE) / 491 sizeof(struct vmwpvs_ring_req); 492 493 sc->sc_sgls = vmwpvs_dmamem_alloc(sc, r * sizeof(struct vmwpvs_sgl)); 494 if (sc->sc_sgls == NULL) { 495 printf("%s: unable to allocate sgls\n", DEVNAME(sc)); 496 goto free_msg_ring; 497 } 498 499 sc->sc_sense = vmwpvs_dmamem_alloc(sc, r * VMWPVS_SENSELEN); 500 if (sc->sc_sense == NULL) { 501 printf("%s: unable to allocate sense data\n", DEVNAME(sc)); 502 goto free_sgl; 503 } 504 505 sc->sc_ccbs = mallocarray(r, sizeof(struct vmwpvs_ccb), 506 M_DEVBUF, M_WAITOK); 507 /* cant fail */ 508 509 sgls = VMWPVS_DMA_KVA(sc->sc_sgls); 510 sense = VMWPVS_DMA_KVA(sc->sc_sense); 511 for (i = 0; i < r; i++) { 512 ccb = &sc->sc_ccbs[i]; 513 514 if (bus_dmamap_create(sc->sc_dmat, MAXPHYS, 515 VMWPVS_MAXSGL, MAXPHYS, 0, 516 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 517 &ccb->ccb_dmamap) != 0) { 518 printf("%s: unable to create ccb map\n", DEVNAME(sc)); 519 goto free_ccbs; 520 } 521 522 ccb->ccb_ctx = 0xdeadbeef00000000ULL | (u_int64_t)i; 523 524 ccb->ccb_sgl_offset = i * sizeof(*sgls); 525 ccb->ccb_sgl = &sgls[i]; 526 527 ccb->ccb_sense_offset = i * VMWPVS_SENSELEN; 528 ccb->ccb_sense = sense + ccb->ccb_sense_offset; 529 530 vmwpvs_ccb_put(sc, ccb); 531 } 532 533 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_BIO, 534 isr, sc, DEVNAME(sc)); 535 if (sc->sc_ih == NULL) 536 goto free_msg_ring; 537 538 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_cmp_ring), 0, 539 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD); 540 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_req_ring), 0, 541 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREWRITE); 542 if (use_msg) { 543 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_msg_ring), 0, 544 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD); 545 } 546 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 547 VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 548 549 intmask = VMWPVS_INTR_CMPL_MASK; 550 551 vmwpvs_setup_rings(sc); 552 if (use_msg) { 553 vmwpvs_setup_msg_ring(sc); 554 intmask |= VMWPVS_INTR_MSG_MASK; 555 } 556 557 vmwpvs_write(sc, VMWPVS_R_INTR_MASK, intmask); 558 559 scsi_iopool_init(&sc->sc_iopool, sc, vmwpvs_ccb_get, vmwpvs_ccb_put); 560 561 saa.saa_adapter = &vmwpvs_switch; 562 saa.saa_adapter_softc = sc; 563 saa.saa_adapter_target = SDEV_NO_ADAPTER_TARGET; 564 saa.saa_adapter_buswidth = sc->sc_bus_width; 565 saa.saa_luns = 8; 566 saa.saa_openings = VMWPVS_OPENINGS; 567 saa.saa_pool = &sc->sc_iopool; 568 saa.saa_quirks = saa.saa_flags = 0; 569 saa.saa_wwpn = saa.saa_wwnn = 0; 570 571 sc->sc_scsibus = (struct scsibus_softc *)config_found(&sc->sc_dev, &saa, 572 scsiprint); 573 574 return; 575 free_ccbs: 576 while ((ccb = vmwpvs_ccb_get(sc)) != NULL) 577 bus_dmamap_destroy(sc->sc_dmat, ccb->ccb_dmamap); 578 free(sc->sc_ccbs, M_DEVBUF, r * sizeof(struct vmwpvs_ccb)); 579 /* free_sense: */ 580 vmwpvs_dmamem_free(sc, sc->sc_sense); 581 free_sgl: 582 vmwpvs_dmamem_free(sc, sc->sc_sgls); 583 free_msg_ring: 584 if (use_msg) 585 vmwpvs_dmamem_free(sc, sc->sc_msg_ring); 586 free_cmp_ring: 587 vmwpvs_dmamem_free(sc, sc->sc_cmp_ring); 588 free_req_ring: 589 vmwpvs_dmamem_free(sc, sc->sc_req_ring); 590 free_ring_state: 591 vmwpvs_dmamem_free(sc, sc->sc_ring_state); 592 unmap: 593 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 594 sc->sc_ios = 0; 595 } 596 597 void 598 vmwpvs_setup_rings(struct vmwpvs_softc *sc) 599 { 600 struct vmwpvs_setup_rings_cmd cmd; 601 u_int64_t ppn; 602 u_int i; 603 604 memset(&cmd, 0, sizeof(cmd)); 605 cmd.req_pages = VMWPVS_RING_PAGES; 606 cmd.cmp_pages = VMWPVS_RING_PAGES; 607 cmd.state_ppn = VMWPVS_DMA_DVA(sc->sc_ring_state) >> VMWPVS_PAGE_SHIFT; 608 609 ppn = VMWPVS_DMA_DVA(sc->sc_req_ring) >> VMWPVS_PAGE_SHIFT; 610 for (i = 0; i < VMWPVS_RING_PAGES; i++) 611 cmd.req_page_ppn[i] = ppn + i; 612 613 ppn = VMWPVS_DMA_DVA(sc->sc_cmp_ring) >> VMWPVS_PAGE_SHIFT; 614 for (i = 0; i < VMWPVS_RING_PAGES; i++) 615 cmd.cmp_page_ppn[i] = ppn + i; 616 617 vmwpvs_cmd(sc, VMWPVS_CMD_SETUP_RINGS, &cmd, sizeof(cmd)); 618 } 619 620 void 621 vmwpvs_setup_msg_ring(struct vmwpvs_softc *sc) 622 { 623 struct vmwpvs_setup_rings_msg cmd; 624 u_int64_t ppn; 625 u_int i; 626 627 memset(&cmd, 0, sizeof(cmd)); 628 cmd.msg_pages = VMWPVS_RING_PAGES; 629 630 ppn = VMWPVS_DMA_DVA(sc->sc_msg_ring) >> VMWPVS_PAGE_SHIFT; 631 for (i = 0; i < VMWPVS_RING_PAGES; i++) 632 cmd.msg_page_ppn[i] = ppn + i; 633 634 vmwpvs_cmd(sc, VMWPVS_CMD_SETUP_MSG_RING, &cmd, sizeof(cmd)); 635 } 636 637 int 638 vmwpvs_get_config(struct vmwpvs_softc *sc) 639 { 640 struct vmwpvs_cfg_cmd cmd; 641 struct vmwpvs_dmamem *dm; 642 struct vmwpvs_cfg_pg_controller *pg; 643 struct vmwpvs_cfg_pg_header *hdr; 644 int rv = 0; 645 646 dm = vmwpvs_dmamem_alloc(sc, VMWPVS_PAGE_SIZE); 647 if (dm == NULL) 648 return (ENOMEM); 649 650 memset(&cmd, 0, sizeof(cmd)); 651 cmd.cmp_addr = VMWPVS_DMA_DVA(dm); 652 cmd.pg_addr_type = VMWPVS_CFGPGADDR_CONTROLLER; 653 cmd.pg_num = VMWPVS_CFGPG_CONTROLLER; 654 655 pg = VMWPVS_DMA_KVA(dm); 656 memset(pg, 0, VMWPVS_PAGE_SIZE); 657 hdr = &pg->header; 658 hdr->host_status = VMWPVS_HOST_STATUS_INVPARAM; 659 hdr->scsi_status = VMWPVS_SCSI_STATUS_CHECK; 660 661 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(dm), 0, VMWPVS_PAGE_SIZE, 662 BUS_DMASYNC_PREREAD); 663 vmwpvs_cmd(sc, VMWPVS_CMD_CONFIG, &cmd, sizeof(cmd)); 664 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(dm), 0, VMWPVS_PAGE_SIZE, 665 BUS_DMASYNC_POSTREAD); 666 667 if (hdr->host_status != VMWPVS_HOST_STATUS_SUCCESS || 668 hdr->scsi_status != VMWPVS_SCSI_STATUS_OK) { 669 rv = EIO; 670 goto done; 671 } 672 673 sc->sc_bus_width = pg->num_phys; 674 675 done: 676 vmwpvs_dmamem_free(sc, dm); 677 678 return (rv); 679 680 } 681 682 void 683 vmwpvs_cmd(struct vmwpvs_softc *sc, u_int32_t cmd, void *buf, size_t len) 684 { 685 u_int32_t *p = buf; 686 u_int i; 687 688 len /= sizeof(*p); 689 690 vmwpvs_write(sc, VMWPVS_R_COMMAND, cmd); 691 for (i = 0; i < len; i++) 692 vmwpvs_write(sc, VMWPVS_R_COMMAND_DATA, p[i]); 693 } 694 695 int 696 vmwpvs_intx(void *xsc) 697 { 698 struct vmwpvs_softc *sc = xsc; 699 u_int32_t status; 700 701 status = vmwpvs_read(sc, VMWPVS_R_INTR_STATUS); 702 if ((status & VMWPVS_INTR_ALL_MASK) == 0) 703 return (0); 704 705 vmwpvs_write(sc, VMWPVS_R_INTR_STATUS, status); 706 707 return (vmwpvs_intr(sc)); 708 } 709 710 int 711 vmwpvs_intr(void *xsc) 712 { 713 struct vmwpvs_softc *sc = xsc; 714 volatile struct vmwpvw_ring_state *s = 715 VMWPVS_DMA_KVA(sc->sc_ring_state); 716 struct vmwpvs_ring_cmp *ring = VMWPVS_DMA_KVA(sc->sc_cmp_ring); 717 struct vmwpvs_ccb_list list = SIMPLEQ_HEAD_INITIALIZER(list); 718 struct vmwpvs_ccb *ccb; 719 u_int32_t cons, prod; 720 int msg; 721 722 mtx_enter(&sc->sc_ring_mtx); 723 724 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 725 VMWPVS_PAGE_SIZE, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 726 cons = s->cmp_cons; 727 prod = s->cmp_prod; 728 s->cmp_cons = prod; 729 730 msg = (sc->sc_msg_ring != NULL && s->msg_cons != s->msg_prod); 731 732 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 733 VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 734 735 if (cons != prod) { 736 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_cmp_ring), 737 0, VMWPVS_PAGE_SIZE, BUS_DMASYNC_POSTREAD); 738 739 do { 740 ccb = vmwpvs_scsi_cmd_done(sc, 741 &ring[cons++ % VMWPVS_CMP_COUNT]); 742 SIMPLEQ_INSERT_TAIL(&list, ccb, ccb_entry); 743 } while (cons != prod); 744 745 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_cmp_ring), 746 0, VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD); 747 } 748 749 mtx_leave(&sc->sc_ring_mtx); 750 751 while ((ccb = SIMPLEQ_FIRST(&list)) != NULL) { 752 SIMPLEQ_REMOVE_HEAD(&list, ccb_entry); 753 scsi_done(ccb->ccb_xs); 754 } 755 756 if (msg) 757 task_add(systq, &sc->sc_msg_task); 758 759 return (1); 760 } 761 762 void 763 vmwpvs_msg_task(void *xsc) 764 { 765 struct vmwpvs_softc *sc = xsc; 766 volatile struct vmwpvw_ring_state *s = 767 VMWPVS_DMA_KVA(sc->sc_ring_state); 768 struct vmwpvs_ring_msg *ring = VMWPVS_DMA_KVA(sc->sc_msg_ring); 769 struct vmwpvs_ring_msg *msg; 770 struct vmwpvs_ring_msg_dev *dvmsg; 771 u_int32_t cons, prod; 772 773 mtx_enter(&sc->sc_ring_mtx); 774 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 775 VMWPVS_PAGE_SIZE, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 776 cons = s->msg_cons; 777 prod = s->msg_prod; 778 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 779 VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 780 mtx_leave(&sc->sc_ring_mtx); 781 782 /* 783 * we dont have to lock around the msg ring cos the system taskq has 784 * only one thread. 785 */ 786 787 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_msg_ring), 0, 788 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE, BUS_DMASYNC_POSTREAD); 789 while (cons != prod) { 790 msg = &ring[cons++ % VMWPVS_MSG_COUNT]; 791 792 switch (letoh32(msg->type)) { 793 case VMWPVS_MSG_T_ADDED: 794 dvmsg = (struct vmwpvs_ring_msg_dev *)msg; 795 if (letoh32(dvmsg->bus) != 0) { 796 printf("%s: ignoring request to add device" 797 " on bus %d\n", DEVNAME(sc), 798 letoh32(msg->type)); 799 break; 800 } 801 802 if (scsi_probe_lun(sc->sc_scsibus, 803 letoh32(dvmsg->target), dvmsg->lun[1]) != 0) { 804 printf("%s: error probing target %d lun %d\n", 805 DEVNAME(sc), letoh32(dvmsg->target), 806 dvmsg->lun[1]); 807 }; 808 break; 809 810 case VMWPVS_MSG_T_REMOVED: 811 dvmsg = (struct vmwpvs_ring_msg_dev *)msg; 812 if (letoh32(dvmsg->bus) != 0) { 813 printf("%s: ignorint request to remove device" 814 " on bus %d\n", DEVNAME(sc), 815 letoh32(msg->type)); 816 break; 817 } 818 819 if (scsi_detach_lun(sc->sc_scsibus, 820 letoh32(dvmsg->target), dvmsg->lun[1], 821 DETACH_FORCE) != 0) { 822 printf("%s: error detaching target %d lun %d\n", 823 DEVNAME(sc), letoh32(dvmsg->target), 824 dvmsg->lun[1]); 825 }; 826 break; 827 828 default: 829 printf("%s: unknown msg type %u\n", DEVNAME(sc), 830 letoh32(msg->type)); 831 break; 832 } 833 } 834 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_msg_ring), 0, 835 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD); 836 837 mtx_enter(&sc->sc_ring_mtx); 838 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 839 VMWPVS_PAGE_SIZE, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 840 s->msg_cons = prod; 841 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 842 VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 843 mtx_leave(&sc->sc_ring_mtx); 844 } 845 846 void 847 vmwpvs_scsi_cmd(struct scsi_xfer *xs) 848 { 849 struct scsi_link *link = xs->sc_link; 850 struct vmwpvs_softc *sc = link->bus->sb_adapter_softc; 851 struct vmwpvs_ccb *ccb = xs->io; 852 bus_dmamap_t dmap = ccb->ccb_dmamap; 853 volatile struct vmwpvw_ring_state *s = 854 VMWPVS_DMA_KVA(sc->sc_ring_state); 855 struct vmwpvs_ring_req *ring = VMWPVS_DMA_KVA(sc->sc_req_ring), *r; 856 u_int32_t prod; 857 struct vmwpvs_ccb_list list; 858 int error; 859 u_int i; 860 861 ccb->ccb_xs = xs; 862 863 if (xs->datalen > 0) { 864 error = bus_dmamap_load(sc->sc_dmat, dmap, 865 xs->data, xs->datalen, NULL, (xs->flags & SCSI_NOSLEEP) ? 866 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 867 if (error) { 868 xs->error = XS_DRIVER_STUFFUP; 869 scsi_done(xs); 870 return; 871 } 872 873 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 874 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : 875 BUS_DMASYNC_PREWRITE); 876 } 877 878 mtx_enter(&sc->sc_ring_mtx); 879 880 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 881 VMWPVS_PAGE_SIZE, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 882 883 prod = s->req_prod; 884 r = &ring[prod % VMWPVS_REQ_COUNT]; 885 886 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_req_ring), 887 prod * sizeof(*r), sizeof(*r), BUS_DMASYNC_POSTWRITE); 888 889 memset(r, 0, sizeof(*r)); 890 r->context = ccb->ccb_ctx; 891 892 if (xs->datalen > 0) { 893 r->data_len = xs->datalen; 894 if (dmap->dm_nsegs == 1) { 895 r->data_addr = dmap->dm_segs[0].ds_addr; 896 } else { 897 struct vmwpvs_sge *sgl = ccb->ccb_sgl->list, *sge; 898 899 r->data_addr = VMWPVS_DMA_DVA(sc->sc_sgls) + 900 ccb->ccb_sgl_offset; 901 r->flags = VMWPVS_REQ_SGL; 902 903 for (i = 0; i < dmap->dm_nsegs; i++) { 904 sge = &sgl[i]; 905 sge->addr = dmap->dm_segs[i].ds_addr; 906 sge->len = dmap->dm_segs[i].ds_len; 907 sge->flags = 0; 908 } 909 910 bus_dmamap_sync(sc->sc_dmat, 911 VMWPVS_DMA_MAP(sc->sc_sgls), ccb->ccb_sgl_offset, 912 sizeof(*sge) * dmap->dm_nsegs, 913 BUS_DMASYNC_PREWRITE); 914 } 915 } 916 r->sense_addr = VMWPVS_DMA_DVA(sc->sc_sense) + ccb->ccb_sense_offset; 917 r->sense_len = sizeof(xs->sense); 918 919 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_req_ring), 0, 920 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE, BUS_DMASYNC_POSTWRITE); 921 922 switch (xs->flags & (SCSI_DATA_IN | SCSI_DATA_OUT)) { 923 case SCSI_DATA_IN: 924 r->flags |= VMWPVS_REQ_DIR_IN; 925 break; 926 case SCSI_DATA_OUT: 927 r->flags |= VMWPVS_REQ_DIR_OUT; 928 break; 929 default: 930 r->flags |= VMWPVS_REQ_DIR_NONE; 931 break; 932 } 933 934 memcpy(r->cdb, xs->cmd, xs->cmdlen); 935 r->cdblen = xs->cmdlen; 936 r->lun[1] = link->lun; /* ugly :( */ 937 r->tag = MSG_SIMPLE_Q_TAG; 938 r->bus = 0; 939 r->target = link->target; 940 r->vcpu_hint = 0; 941 942 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_req_ring), 0, 943 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREWRITE); 944 945 s->req_prod = prod + 1; 946 947 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 948 VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 949 950 vmwpvs_write(sc, xs->bp == NULL ? 951 VMWPVS_R_KICK_NON_RW_IO : VMWPVS_R_KICK_RW_IO, 0); 952 953 if (!ISSET(xs->flags, SCSI_POLL)) { 954 mtx_leave(&sc->sc_ring_mtx); 955 return; 956 } 957 958 SIMPLEQ_INIT(&list); 959 do { 960 ccb = vmwpvs_scsi_cmd_poll(sc); 961 SIMPLEQ_INSERT_TAIL(&list, ccb, ccb_entry); 962 } while (xs->io != ccb); 963 964 mtx_leave(&sc->sc_ring_mtx); 965 966 while ((ccb = SIMPLEQ_FIRST(&list)) != NULL) { 967 SIMPLEQ_REMOVE_HEAD(&list, ccb_entry); 968 scsi_done(ccb->ccb_xs); 969 } 970 } 971 972 struct vmwpvs_ccb * 973 vmwpvs_scsi_cmd_poll(struct vmwpvs_softc *sc) 974 { 975 volatile struct vmwpvw_ring_state *s = 976 VMWPVS_DMA_KVA(sc->sc_ring_state); 977 struct vmwpvs_ring_cmp *ring = VMWPVS_DMA_KVA(sc->sc_cmp_ring); 978 struct vmwpvs_ccb *ccb; 979 u_int32_t prod, cons; 980 981 for (;;) { 982 bus_dmamap_sync(sc->sc_dmat, 983 VMWPVS_DMA_MAP(sc->sc_ring_state), 0, VMWPVS_PAGE_SIZE, 984 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 985 986 cons = s->cmp_cons; 987 prod = s->cmp_prod; 988 989 if (cons != prod) 990 s->cmp_cons = cons + 1; 991 992 bus_dmamap_sync(sc->sc_dmat, 993 VMWPVS_DMA_MAP(sc->sc_ring_state), 0, VMWPVS_PAGE_SIZE, 994 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 995 996 if (cons != prod) 997 break; 998 else 999 delay(1000); 1000 } 1001 1002 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_cmp_ring), 1003 0, VMWPVS_PAGE_SIZE * VMWPVS_RING_PAGES, 1004 BUS_DMASYNC_POSTREAD); 1005 ccb = vmwpvs_scsi_cmd_done(sc, &ring[cons % VMWPVS_CMP_COUNT]); 1006 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_cmp_ring), 1007 0, VMWPVS_PAGE_SIZE * VMWPVS_RING_PAGES, 1008 BUS_DMASYNC_PREREAD); 1009 1010 return (ccb); 1011 } 1012 1013 struct vmwpvs_ccb * 1014 vmwpvs_scsi_cmd_done(struct vmwpvs_softc *sc, struct vmwpvs_ring_cmp *c) 1015 { 1016 u_int64_t ctx = c->context; 1017 struct vmwpvs_ccb *ccb = &sc->sc_ccbs[ctx & 0xffffffff]; 1018 bus_dmamap_t dmap = ccb->ccb_dmamap; 1019 struct scsi_xfer *xs = ccb->ccb_xs; 1020 1021 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_sense), 1022 ccb->ccb_sense_offset, sizeof(xs->sense), BUS_DMASYNC_POSTREAD); 1023 1024 if (xs->datalen > 0) { 1025 if (dmap->dm_nsegs > 1) { 1026 bus_dmamap_sync(sc->sc_dmat, 1027 VMWPVS_DMA_MAP(sc->sc_sgls), ccb->ccb_sgl_offset, 1028 sizeof(struct vmwpvs_sge) * dmap->dm_nsegs, 1029 BUS_DMASYNC_POSTWRITE); 1030 } 1031 1032 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 1033 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1034 BUS_DMASYNC_POSTWRITE); 1035 1036 bus_dmamap_unload(sc->sc_dmat, dmap); 1037 } 1038 1039 xs->status = c->scsi_status; 1040 switch (c->host_status) { 1041 case VMWPVS_HOST_STATUS_SUCCESS: 1042 case VMWPVS_HOST_STATUS_LINKED_CMD_COMPLETED: 1043 case VMWPVS_HOST_STATUS_LINKED_CMD_COMPLETED_WITH_FLAG: 1044 if (c->scsi_status == VMWPVS_SCSI_STATUS_CHECK) { 1045 memcpy(&xs->sense, ccb->ccb_sense, sizeof(xs->sense)); 1046 xs->error = XS_SENSE; 1047 } else 1048 xs->error = XS_NOERROR; 1049 xs->resid = 0; 1050 break; 1051 1052 case VMWPVS_HOST_STATUS_UNDERRUN: 1053 case VMWPVS_HOST_STATUS_DATARUN: 1054 xs->resid = xs->datalen - c->data_len; 1055 xs->error = XS_NOERROR; 1056 break; 1057 1058 case VMWPVS_HOST_STATUS_SELTIMEOUT: 1059 xs->error = XS_SELTIMEOUT; 1060 break; 1061 1062 default: 1063 printf("%s: %s:%d h:0x%x s:0x%x\n", DEVNAME(sc), 1064 __FUNCTION__, __LINE__, c->host_status, c->scsi_status); 1065 xs->error = XS_DRIVER_STUFFUP; 1066 break; 1067 } 1068 1069 return (ccb); 1070 } 1071 1072 void * 1073 vmwpvs_ccb_get(void *xsc) 1074 { 1075 struct vmwpvs_softc *sc = xsc; 1076 struct vmwpvs_ccb *ccb; 1077 1078 mtx_enter(&sc->sc_ccb_mtx); 1079 ccb = SIMPLEQ_FIRST(&sc->sc_ccb_list); 1080 if (ccb != NULL) 1081 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_list, ccb_entry); 1082 mtx_leave(&sc->sc_ccb_mtx); 1083 1084 return (ccb); 1085 } 1086 1087 void 1088 vmwpvs_ccb_put(void *xsc, void *io) 1089 { 1090 struct vmwpvs_softc *sc = xsc; 1091 struct vmwpvs_ccb *ccb = io; 1092 1093 mtx_enter(&sc->sc_ccb_mtx); 1094 SIMPLEQ_INSERT_HEAD(&sc->sc_ccb_list, ccb, ccb_entry); 1095 mtx_leave(&sc->sc_ccb_mtx); 1096 } 1097 1098 struct vmwpvs_dmamem * 1099 vmwpvs_dmamem_alloc(struct vmwpvs_softc *sc, size_t size) 1100 { 1101 struct vmwpvs_dmamem *dm; 1102 int nsegs; 1103 1104 dm = malloc(sizeof(*dm), M_DEVBUF, M_NOWAIT | M_ZERO); 1105 if (dm == NULL) 1106 return (NULL); 1107 1108 dm->dm_size = size; 1109 1110 if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1111 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dm->dm_map) != 0) 1112 goto dmfree; 1113 1114 if (bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &dm->dm_seg, 1115 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO) != 0) 1116 goto destroy; 1117 1118 if (bus_dmamem_map(sc->sc_dmat, &dm->dm_seg, nsegs, size, 1119 &dm->dm_kva, BUS_DMA_NOWAIT) != 0) 1120 goto free; 1121 1122 if (bus_dmamap_load(sc->sc_dmat, dm->dm_map, dm->dm_kva, size, 1123 NULL, BUS_DMA_NOWAIT) != 0) 1124 goto unmap; 1125 1126 return (dm); 1127 1128 unmap: 1129 bus_dmamem_unmap(sc->sc_dmat, dm->dm_kva, size); 1130 free: 1131 bus_dmamem_free(sc->sc_dmat, &dm->dm_seg, 1); 1132 destroy: 1133 bus_dmamap_destroy(sc->sc_dmat, dm->dm_map); 1134 dmfree: 1135 free(dm, M_DEVBUF, sizeof *dm); 1136 1137 return (NULL); 1138 } 1139 1140 struct vmwpvs_dmamem * 1141 vmwpvs_dmamem_zalloc(struct vmwpvs_softc *sc, size_t size) 1142 { 1143 struct vmwpvs_dmamem *dm; 1144 1145 dm = vmwpvs_dmamem_alloc(sc, size); 1146 if (dm == NULL) 1147 return (NULL); 1148 1149 memset(VMWPVS_DMA_KVA(dm), 0, size); 1150 1151 return (dm); 1152 } 1153 1154 void 1155 vmwpvs_dmamem_free(struct vmwpvs_softc *sc, struct vmwpvs_dmamem *dm) 1156 { 1157 bus_dmamap_unload(sc->sc_dmat, dm->dm_map); 1158 bus_dmamem_unmap(sc->sc_dmat, dm->dm_kva, dm->dm_size); 1159 bus_dmamem_free(sc->sc_dmat, &dm->dm_seg, 1); 1160 bus_dmamap_destroy(sc->sc_dmat, dm->dm_map); 1161 free(dm, M_DEVBUF, sizeof *dm); 1162 } 1163