1 /* $OpenBSD: tga.c,v 1.20 2003/04/29 21:58:35 miod Exp $ */ 2 /* $NetBSD: tga.c,v 1.40 2002/03/13 15:05:18 ad Exp $ */ 3 4 /* 5 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Author: Chris G. Demetriou 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/conf.h> 36 #include <sys/malloc.h> 37 #include <sys/buf.h> 38 #include <sys/ioctl.h> 39 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcidevs.h> 46 #include <dev/pci/tgareg.h> 47 #include <dev/pci/tgavar.h> 48 #include <dev/ic/bt485reg.h> 49 #include <dev/ic/bt485var.h> 50 #include <dev/ic/bt463reg.h> 51 #include <dev/ic/bt463var.h> 52 #include <dev/ic/ibm561var.h> 53 54 #include <dev/wscons/wsconsio.h> 55 #include <dev/wscons/wscons_raster.h> 56 #include <dev/rasops/rasops.h> 57 #include <dev/wsfont/wsfont.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #ifdef __alpha__ 62 #include <machine/pte.h> 63 #endif 64 #ifdef __mips__ 65 #include <mips/pte.h> 66 #endif 67 68 int tgamatch(struct device *, struct cfdata *, void *); 69 void tgaattach(struct device *, struct device *, void *); 70 int tgaprint(void *, const char *); 71 72 struct cfdriver tga_cd = { 73 NULL, "tga", DV_DULL 74 }; 75 76 struct cfattach tga_ca = { 77 sizeof(struct tga_softc), (cfmatch_t)tgamatch, tgaattach, 78 }; 79 80 int tga_identify(struct tga_devconfig *); 81 const struct tga_conf *tga_getconf(int); 82 void tga_getdevconfig(bus_space_tag_t memt, pci_chipset_tag_t pc, 83 pcitag_t tag, struct tga_devconfig *dc); 84 unsigned tga_getdotclock(struct tga_devconfig *dc); 85 86 struct tga_devconfig tga_console_dc; 87 88 int tga_ioctl(void *, u_long, caddr_t, int, struct proc *); 89 paddr_t tga_mmap(void *, off_t, int); 90 void tga_copyrows(void *, int, int, int); 91 void tga_copycols(void *, int, int, int, int); 92 int tga_alloc_screen(void *, const struct wsscreen_descr *, 93 void **, int *, int *, long *); 94 void tga_free_screen(void *, void *); 95 int tga_show_screen(void *, void *, int, 96 void (*) (void *, int, int), void *); 97 void tga_burner(void *, u_int, u_int); 98 int tga_rop(struct rasops_info *, int, int, int, int, int, 99 struct rasops_info *, int, int); 100 int tga_rop_vtov(struct rasops_info *, int, int, int, int, 101 int, struct rasops_info *, int, int ); 102 void tga_putchar(void *c, int row, int col, u_int uc, long attr); 103 void tga_eraserows(void *, int, int, long); 104 void tga_erasecols(void *, int, int, int, long); 105 void tga2_init(struct tga_devconfig *); 106 107 void tga_config_interrupts(struct device *); 108 109 /* RAMDAC interface functions */ 110 int tga_sched_update(void *, void (*)(void *)); 111 void tga_ramdac_wr(void *, u_int, u_int8_t); 112 u_int8_t tga_ramdac_rd(void *, u_int); 113 void tga_bt463_wr(void *, u_int, u_int8_t); 114 u_int8_t tga_bt463_rd(void *, u_int); 115 void tga2_ramdac_wr(void *, u_int, u_int8_t); 116 u_int8_t tga2_ramdac_rd(void *, u_int); 117 118 /* Interrupt handler */ 119 int tga_intr(void *); 120 121 /* The NULL entries will get filled in by rasops_init(). 122 * XXX and the non-NULL ones will be overwritten; reset after calling it. 123 */ 124 struct wsdisplay_emulops tga_emulops = { 125 NULL, 126 NULL, 127 tga_putchar, 128 tga_copycols, 129 tga_erasecols, 130 tga_copyrows, 131 tga_eraserows, 132 NULL, 133 }; 134 135 struct wsscreen_descr tga_stdscreen = { 136 "std", 137 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 138 &tga_emulops, 139 0, 0, 140 WSSCREEN_REVERSE 141 }; 142 143 const struct wsscreen_descr *_tga_scrlist[] = { 144 &tga_stdscreen, 145 /* XXX other formats, graphics screen? */ 146 }; 147 148 struct wsscreen_list tga_screenlist = { 149 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 150 }; 151 152 struct wsdisplay_accessops tga_accessops = { 153 tga_ioctl, 154 tga_mmap, 155 tga_alloc_screen, 156 tga_free_screen, 157 tga_show_screen, 158 NULL, /* load_font */ 159 NULL, /* scrollback */ 160 NULL, /* getchar */ 161 tga_burner, 162 }; 163 164 void tga_blank(struct tga_devconfig *); 165 void tga_unblank(struct tga_devconfig *); 166 167 #ifdef TGA_DEBUG 168 #define DPRINTF(...) printf (__VA_ARGS__) 169 #define DPRINTFN(n, ...) if (tgadebug > (n)) printf (__VA_ARGS__) 170 int tgadebug = 0; 171 #else 172 #define DPRINTF(...) 173 #define DPRINTFN(n,...) 174 #endif 175 176 const struct pci_matchid tga_devices[] = { 177 { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21030 }, 178 { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_PBXGB }, 179 }; 180 181 int 182 tgamatch(parent, match, aux) 183 struct device *parent; 184 struct cfdata *match; 185 void *aux; 186 { 187 if (pci_matchbyid((struct pci_attach_args *)aux, tga_devices, 188 sizeof(tga_devices) / sizeof(tga_devices[0]))) 189 return (10); /* need to return more than vga_pci here! */ 190 191 return (0); 192 } 193 194 void 195 tga_getdevconfig(memt, pc, tag, dc) 196 bus_space_tag_t memt; 197 pci_chipset_tag_t pc; 198 pcitag_t tag; 199 struct tga_devconfig *dc; 200 { 201 const struct tga_conf *tgac; 202 struct rasops_info *rip; 203 int cookie; 204 bus_size_t pcisize; 205 int i, cacheable; 206 207 dc->dc_memt = memt; 208 209 dc->dc_pcitag = tag; 210 211 DPRINTF("tga_getdevconfig: Getting map info\n"); 212 /* XXX magic number */ 213 if (pci_mapreg_info(pc, tag, 0x10, 214 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 215 &dc->dc_pcipaddr, &pcisize, &cacheable)) 216 return; 217 if (!cacheable) 218 panic("tga memory not cacheable"); 219 220 DPRINTF("tga_getdevconfig: preparing to map\n"); 221 #ifdef __OpenBSD__ 222 if (bus_space_map(memt, dc->dc_pcipaddr, pcisize, 1, &dc->dc_memh)) 223 return; 224 dc->dc_vaddr = dc->dc_memh; 225 #else 226 if (bus_space_map(memt, dc->dc_pcipaddr, pcisize, 227 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 228 return; 229 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 230 #endif 231 DPRINTF("tga_getdevconfig: mapped\n"); 232 233 #ifdef __alpha__ 234 dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr); /* XXX */ 235 #endif 236 #ifdef arc 237 bus_space_paddr(memt, dc->dc_memh, &dc->dc_paddr); 238 #endif 239 DPRINTF("tga_getdevconfig: allocating subregion\n"); 240 bus_space_subregion(dc->dc_memt, dc->dc_memh, 241 TGA_MEM_CREGS, TGA_CREGS_SIZE, 242 &dc->dc_regs); 243 244 DPRINTF("tga_getdevconfig: going to identify\n"); 245 dc->dc_tga_type = tga_identify(dc); 246 247 DPRINTF("tga_getdevconfig: preparing to get config\n"); 248 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 249 if (tgac == NULL) 250 return; 251 252 #if 0 253 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 254 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 255 panic("tga_getdevconfig: memory size mismatch?"); 256 #endif 257 258 DPRINTF("tga_getdevconfig: get revno\n"); 259 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 260 case 0x01: 261 case 0x02: 262 case 0x03: 263 case 0x04: 264 dc->dc_tga2 = 0; 265 break; 266 case 0x20: 267 case 0x21: 268 case 0x22: 269 dc->dc_tga2 = 1; 270 break; 271 default: 272 panic("tga_getdevconfig: TGA Revision not recognized"); 273 } 274 275 if (dc->dc_tga2) { 276 tga2_init(dc); 277 } 278 279 i = TGARREG(dc, TGA_REG_VHCR) & 0x1ff; 280 DPRINTF("tga_getdevconfig: TGA_REG_VHCR & 0x1ff = %d\n", i); 281 switch (i) { /* XXX */ 282 case 0: 283 dc->dc_wid = 8192; 284 break; 285 286 case 1: 287 dc->dc_wid = 8196; 288 break; 289 290 default: 291 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 292 break; 293 } 294 295 DPRINTF("tga_getdevconfig: dc->dc_wid = %d\n", dc->dc_wid); 296 /* 297 * XXX XXX Turning off "odd" shouldn't be necessary, 298 * XXX XXX but I can't make X work with the weird size. 299 */ 300 DPRINTF("tga_getdevconfig: beginning magic incantation\n"); 301 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 302 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 303 TGAWREG(dc, TGA_REG_VHCR, 304 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 305 dc->dc_wid -= 4; 306 } 307 308 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 309 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 310 DPRINTF("tga_getdevconfig: rowbytes = %d, tgac_phys_depth = %d\n" 311 " dc_wid = %d, dc_ht = %d\n", 312 dc->dc_rowbytes, dc->dc_tgaconf->tgac_phys_depth, 313 dc->dc_wid, dc->dc_ht); 314 315 /* XXX this seems to be what DEC does */ 316 DPRINTF("tga_getdevconfig: more magic\n"); 317 TGAWREG(dc, TGA_REG_CCBR, 0); 318 TGAWREG(dc, TGA_REG_VVBR, 1); 319 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 320 1 * tgac->tgac_vvbr_units; 321 dc->dc_blanked = 1; 322 tga_unblank(dc); 323 324 DPRINTF("tga_getdevconfig: dc_videobase = 0x%016llx\n" 325 " dc_vaddr = 0x%016llx\n" 326 " tgac_dbuf[0] = %d\n" 327 " tgac_vvbr_units = %d\n", 328 dc->dc_videobase, dc->dc_vaddr, tgac->tgac_dbuf[0], 329 tgac->tgac_vvbr_units); 330 331 /* 332 * Set all bits in the pixel mask, to enable writes to all pixels. 333 * It seems that the console firmware clears some of them 334 * under some circumstances, which causes cute vertical stripes. 335 */ 336 DPRINTF("tga_getdevconfig: set pixel mask\n"); 337 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 338 339 /* clear the screen */ 340 DPRINTF("tga_getdevconfig: clear screen\n"); 341 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 342 *(u_int32_t *)(dc->dc_videobase + i) = 0; 343 344 DPRINTF("tga_getdevconfig: raster ops\n"); 345 /* Initialize rasops descriptor */ 346 rip = &dc->dc_rinfo; 347 rip->ri_flg = RI_CENTER; 348 rip->ri_depth = tgac->tgac_phys_depth; 349 rip->ri_bits = (void *)dc->dc_videobase; 350 rip->ri_width = dc->dc_wid; 351 rip->ri_height = dc->dc_ht; 352 rip->ri_stride = dc->dc_rowbytes; 353 rip->ri_hw = dc; 354 355 if (tgac->tgac_phys_depth == 32) { 356 rip->ri_rnum = 8; 357 rip->ri_gnum = 8; 358 rip->ri_bnum = 8; 359 rip->ri_rpos = 16; 360 rip->ri_gpos = 8; 361 rip->ri_bpos = 0; 362 } 363 364 DPRINTF("tga_getdevconfig: wsfont_init\n"); 365 wsfont_init(); 366 if (rip->ri_width > 80*12) 367 /* High res screen, choose a big font */ 368 cookie = wsfont_find(NULL, 12, 0, 0); 369 else 370 /* lower res, choose a 8 pixel wide font */ 371 cookie = wsfont_find(NULL, 8, 0, 0); 372 if (cookie <= 0) 373 cookie = wsfont_find(NULL, 0, 0, 0); 374 if (cookie <= 0) { 375 printf("tga: no appropriate fonts.\n"); 376 return; 377 } 378 379 /* the accelerated tga_putchar() needs LSbit left */ 380 if (wsfont_lock(cookie, &rip->ri_font, 381 WSDISPLAY_FONTORDER_R2L, WSDISPLAY_FONTORDER_L2R) <= 0) { 382 printf("tga: couldn't lock font\n"); 383 return; 384 } 385 rip->ri_wsfcookie = cookie; 386 /* fill screen size */ 387 rasops_init(rip, rip->ri_height / rip->ri_font->fontheight, 388 rip->ri_width / rip->ri_font->fontwidth); 389 390 /* add our accelerated functions */ 391 /* XXX shouldn't have to do this; rasops should leave non-NULL 392 * XXX entries alone. 393 */ 394 rip->ri_ops.copyrows = tga_copyrows; 395 rip->ri_ops.eraserows = tga_eraserows; 396 rip->ri_ops.erasecols = tga_erasecols; 397 rip->ri_ops.copycols = tga_copycols; 398 rip->ri_ops.putchar = tga_putchar; 399 400 tga_stdscreen.nrows = rip->ri_rows; 401 tga_stdscreen.ncols = rip->ri_cols; 402 tga_stdscreen.textops = &rip->ri_ops; 403 tga_stdscreen.capabilities = rip->ri_caps; 404 405 dc->dc_intrenabled = 0; 406 } 407 408 void 409 tgaattach(parent, self, aux) 410 struct device *parent, *self; 411 void *aux; 412 { 413 struct pci_attach_args *pa = aux; 414 struct tga_softc *sc = (struct tga_softc *)self; 415 struct wsemuldisplaydev_attach_args aa; 416 pci_intr_handle_t intrh; 417 const char *intrstr; 418 u_int8_t rev; 419 int console; 420 421 #if defined(__alpha__) || defined(arc) 422 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 423 #else 424 console = 0; 425 #endif 426 if (console) { 427 sc->sc_dc = &tga_console_dc; 428 sc->nscreens = 1; 429 } else { 430 sc->sc_dc = (struct tga_devconfig *) 431 malloc(sizeof(struct tga_devconfig), M_DEVBUF, M_NOWAIT); 432 if (sc->sc_dc == NULL) 433 return; 434 bzero(sc->sc_dc, sizeof(struct tga_devconfig)); 435 tga_getdevconfig(pa->pa_memt, pa->pa_pc, pa->pa_tag, 436 sc->sc_dc); 437 } 438 if (sc->sc_dc->dc_vaddr == NULL) { 439 printf(": couldn't map memory space; punt!\n"); 440 return; 441 } 442 443 /* XXX say what's going on. */ 444 intrstr = NULL; 445 if (pci_intr_map(pa, &intrh)) { 446 printf(": couldn't map interrupt"); 447 return; 448 } 449 intrstr = pci_intr_string(pa->pa_pc, intrh); 450 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 451 sc->sc_dc, sc->sc_dev.dv_xname); 452 if (sc->sc_intr == NULL) { 453 printf(": couldn't establish interrupt"); 454 if (intrstr != NULL) 455 printf("at %s", intrstr); 456 printf("\n"); 457 return; 458 } 459 460 rev = PCI_REVISION(pa->pa_class); 461 switch (rev) { 462 case 0x1: 463 case 0x2: 464 case 0x3: 465 printf(": DC21030 step %c", 'A' + rev - 1); 466 break; 467 case 0x20: 468 printf(": TGA2 abstract software model"); 469 break; 470 case 0x21: 471 case 0x22: 472 printf(": TGA2 pass %d", rev - 0x20); 473 break; 474 475 default: 476 printf("unknown stepping (0x%x)", rev); 477 break; 478 } 479 printf(", "); 480 481 /* 482 * Get RAMDAC function vectors and call the RAMDAC functions 483 * to allocate its private storage and pass that back to us. 484 */ 485 486 DPRINTF("tgaattach: Get RAMDAC functions\n"); 487 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 488 if (!sc->sc_dc->dc_tga2) { 489 DPRINTF("tgaattach: !sc->sc_dc->dc_tga2\n"); 490 DPRINTF("tgaattach: sc->sc_dc->dc_tgaconf->ramdac_funcs %s " 491 "bt485_funcs\n", 492 (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 493 ? "==" : "!="); 494 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 495 sc->sc_dc->dc_ramdac_cookie = 496 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 497 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 498 else 499 sc->sc_dc->dc_ramdac_cookie = 500 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 501 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 502 } else { 503 DPRINTF("tgaattach: sc->sc_dc->dc_tga2\n"); 504 sc->sc_dc->dc_ramdac_cookie = 505 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 506 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 507 508 /* XXX this is a bit of a hack, setting the dotclock here */ 509 if (sc->sc_dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 510 (*sc->sc_dc->dc_ramdac_funcs->ramdac_set_dotclock) 511 (sc->sc_dc->dc_ramdac_cookie, 512 tga_getdotclock(sc->sc_dc)); 513 } 514 DPRINTF("tgaattach: sc->sc_dc->dc_ramdac_cookie = 0x%016llx\n", 515 sc->sc_dc->dc_ramdac_cookie); 516 /* 517 * Initialize the RAMDAC. Initialization includes disabling 518 * cursor, setting a sane colormap, etc. 519 */ 520 DPRINTF("tgaattach: Initializing RAMDAC.\n"); 521 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 522 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 523 524 if (sc->sc_dc->dc_tgaconf == NULL) { 525 printf("unknown board configuration\n"); 526 return; 527 } 528 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 529 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 530 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 531 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 532 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 533 534 if (intrstr != NULL) 535 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 536 intrstr); 537 538 aa.console = console; 539 aa.scrdata = &tga_screenlist; 540 aa.accessops = &tga_accessops; 541 aa.accesscookie = sc; 542 543 config_found(self, &aa, wsemuldisplaydevprint); 544 545 #ifdef __NetBSD__ 546 config_interrupts(self, tga_config_interrupts); 547 #else 548 tga_config_interrupts(self); 549 #endif 550 } 551 552 void 553 tga_config_interrupts (d) 554 struct device *d; 555 { 556 struct tga_softc *sc = (struct tga_softc *)d; 557 sc->sc_dc->dc_intrenabled = 1; 558 } 559 560 561 int 562 tga_ioctl(v, cmd, data, flag, p) 563 void *v; 564 u_long cmd; 565 caddr_t data; 566 int flag; 567 struct proc *p; 568 { 569 struct tga_softc *sc = v; 570 struct tga_devconfig *dc = sc->sc_dc; 571 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 572 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 573 574 switch (cmd) { 575 case WSDISPLAYIO_GTYPE: 576 *(u_int *)data = WSDISPLAY_TYPE_TGA; 577 return (0); 578 579 case WSDISPLAYIO_SMODE: 580 sc->sc_mode = *(u_int *)data; 581 switch (sc->sc_mode) { 582 case WSDISPLAYIO_MODE_DUMBFB: 583 /* in dump fb mode start the framebuffer at 0 */ 584 TGAWREG(dc, TGA_REG_VVBR, 0); 585 break; 586 default: 587 /* XXX it this useful, except for not breaking Xtga? */ 588 TGAWREG(dc, TGA_REG_VVBR, 1); 589 break; 590 } 591 return (0); 592 593 case WSDISPLAYIO_GINFO: 594 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 595 wsd_fbip->height = sc->sc_dc->dc_ht; 596 wsd_fbip->width = sc->sc_dc->dc_wid; 597 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 598 wsd_fbip->cmsize = 1024; /* XXX ??? */ 599 #undef wsd_fbip 600 return (0); 601 602 case WSDISPLAYIO_LINEBYTES: 603 *(u_int *)data = sc->sc_dc->dc_rowbytes; 604 return 0; 605 case WSDISPLAYIO_GETCMAP: 606 return (*dcrf->ramdac_get_cmap)(dcrc, 607 (struct wsdisplay_cmap *)data); 608 609 case WSDISPLAYIO_PUTCMAP: 610 return (*dcrf->ramdac_set_cmap)(dcrc, 611 (struct wsdisplay_cmap *)data); 612 613 case WSDISPLAYIO_SVIDEO: 614 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 615 tga_blank(sc->sc_dc); 616 else 617 tga_unblank(sc->sc_dc); 618 return (0); 619 620 case WSDISPLAYIO_GVIDEO: 621 *(u_int *)data = dc->dc_blanked ? 622 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 623 return (0); 624 625 case WSDISPLAYIO_GCURPOS: 626 return (*dcrf->ramdac_get_curpos)(dcrc, 627 (struct wsdisplay_curpos *)data); 628 629 case WSDISPLAYIO_SCURPOS: 630 return (*dcrf->ramdac_set_curpos)(dcrc, 631 (struct wsdisplay_curpos *)data); 632 633 case WSDISPLAYIO_GCURMAX: 634 return (*dcrf->ramdac_get_curmax)(dcrc, 635 (struct wsdisplay_curpos *)data); 636 637 case WSDISPLAYIO_GCURSOR: 638 return (*dcrf->ramdac_get_cursor)(dcrc, 639 (struct wsdisplay_cursor *)data); 640 641 case WSDISPLAYIO_SCURSOR: 642 return (*dcrf->ramdac_set_cursor)(dcrc, 643 (struct wsdisplay_cursor *)data); 644 } 645 return (-1); 646 } 647 648 int 649 tga_sched_update(v, f) 650 void *v; 651 void (*f)(void *); 652 { 653 struct tga_devconfig *dc = v; 654 655 if (dc->dc_intrenabled) { 656 /* Arrange for f to be called at the next end-of-frame interrupt */ 657 dc->dc_ramdac_intr = f; 658 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 659 } else { 660 /* Spin until the end-of-frame, then call f */ 661 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 662 TGAREGWB(dc, TGA_REG_SISR, 1); 663 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 664 ; 665 f(dc->dc_ramdac_cookie); 666 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 667 TGAREGWB(dc, TGA_REG_SISR, 1); 668 } 669 670 return 0; 671 } 672 673 int 674 tga_intr(v) 675 void *v; 676 { 677 struct tga_devconfig *dc = v; 678 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 679 680 u_int32_t reg; 681 682 reg = TGARREG(dc, TGA_REG_SISR); 683 if (( reg & 0x00010001) != 0x00010001) { 684 /* Odd. We never set any of the other interrupt enables. */ 685 if ((reg & 0x1f) != 0) { 686 /* Clear the mysterious pending interrupts. */ 687 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 688 TGAREGWB(dc, TGA_REG_SISR, 1); 689 /* This was our interrupt, even if we're puzzled as to why 690 * we got it. Don't make the interrupt handler think it 691 * was a stray. 692 */ 693 return -1; 694 } else { 695 return 0; 696 } 697 } 698 /* if we have something to do, do it */ 699 if (dc->dc_ramdac_intr) { 700 dc->dc_ramdac_intr(dcrc); 701 dc->dc_ramdac_intr = NULL; 702 } 703 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 704 TGAREGWB(dc, TGA_REG_SISR, 1); 705 return (1); 706 } 707 708 paddr_t 709 tga_mmap(v, offset, prot) 710 void *v; 711 off_t offset; 712 int prot; 713 { 714 struct tga_softc *sc = v; 715 struct tga_devconfig *dc = sc->sc_dc; 716 717 if (offset >= dc->dc_tgaconf->tgac_cspace_size || offset < 0) 718 return -1; 719 720 if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) { 721 /* 722 * The framebuffer starts at the upper half of tga mem 723 */ 724 offset += dc->dc_tgaconf->tgac_cspace_size / 2; 725 } 726 #if defined(__alpha__) 727 return alpha_btop(sc->sc_dc->dc_paddr + offset); 728 #elif defined(__mips__) 729 return mips_btop(sc->sc_dc->dc_paddr + offset); 730 #else 731 return (-1); 732 #endif 733 } 734 735 int 736 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 737 void *v; 738 const struct wsscreen_descr *type; 739 void **cookiep; 740 int *curxp, *curyp; 741 long *attrp; 742 { 743 struct tga_softc *sc = v; 744 long defattr; 745 746 if (sc->nscreens > 0) 747 return (ENOMEM); 748 749 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 750 *curxp = 0; 751 *curyp = 0; 752 sc->sc_dc->dc_rinfo.ri_ops.alloc_attr(&sc->sc_dc->dc_rinfo, 753 0, 0, 0, &defattr); 754 *attrp = defattr; 755 sc->nscreens++; 756 return (0); 757 } 758 759 void 760 tga_free_screen(v, cookie) 761 void *v; 762 void *cookie; 763 { 764 struct tga_softc *sc = v; 765 766 if (sc->sc_dc == &tga_console_dc) 767 panic("tga_free_screen: console"); 768 769 sc->nscreens--; 770 } 771 772 int 773 tga_show_screen(v, cookie, waitok, cb, cbarg) 774 void *v; 775 void *cookie; 776 int waitok; 777 void (*cb)(void *, int, int); 778 void *cbarg; 779 { 780 781 return (0); 782 } 783 784 int 785 tga_cnattach(iot, memt, pc, bus, device, function) 786 bus_space_tag_t iot, memt; 787 pci_chipset_tag_t pc; 788 int bus, device, function; 789 { 790 struct tga_devconfig *dcp = &tga_console_dc; 791 long defattr; 792 793 tga_getdevconfig(memt, pc, 794 pci_make_tag(pc, bus, device, function), dcp); 795 796 /* sanity checks */ 797 if (dcp->dc_vaddr == NULL) 798 panic("tga_console(%d, %d): couldn't map memory space", 799 device, function); 800 if (dcp->dc_tgaconf == NULL) 801 panic("tga_console(%d, %d): unknown board configuration", 802 device, function); 803 804 /* 805 * Initialize the RAMDAC but DO NOT allocate any private storage. 806 * Initialization includes disabling cursor, setting a sane 807 * colormap, etc. It will be reinitialized in tgaattach(). 808 */ 809 if (dcp->dc_tga2) { 810 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 811 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 812 tga2_ramdac_rd); 813 else 814 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 815 tga2_ramdac_rd, tga_getdotclock(dcp)); 816 } else { 817 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 818 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 819 tga_ramdac_rd); 820 else { 821 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 822 tga_bt463_rd); 823 } 824 } 825 dcp->dc_rinfo.ri_ops.alloc_attr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 826 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 827 828 return(0); 829 } 830 831 /* 832 * Functions to blank and unblank the display. 833 */ 834 void 835 tga_burner(v, on, flags) 836 void *v; 837 u_int on, flags; 838 { 839 struct tga_softc *sc = v; 840 841 if (on) { 842 tga_unblank(sc->sc_dc); 843 } else { 844 tga_blank(sc->sc_dc); 845 } 846 } 847 848 void 849 tga_blank(dc) 850 struct tga_devconfig *dc; 851 { 852 853 if (!dc->dc_blanked) { 854 dc->dc_blanked = 1; 855 /* XXX */ 856 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 857 } 858 } 859 860 void 861 tga_unblank(dc) 862 struct tga_devconfig *dc; 863 { 864 865 if (dc->dc_blanked) { 866 dc->dc_blanked = 0; 867 /* XXX */ 868 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 869 } 870 } 871 872 /* 873 * Functions to manipulate the built-in cursor handing hardware. 874 */ 875 int 876 tga_builtin_set_cursor(dc, cursorp) 877 struct tga_devconfig *dc; 878 struct wsdisplay_cursor *cursorp; 879 { 880 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 881 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 882 u_int count, v; 883 int error; 884 885 v = cursorp->which; 886 if (v & WSDISPLAY_CURSOR_DOCMAP) { 887 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 888 if (error) 889 return (error); 890 } 891 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 892 if ((u_int)cursorp->size.x != 64 || 893 (u_int)cursorp->size.y > 64) 894 return (EINVAL); 895 } 896 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 897 return EINVAL; 898 899 /* parameters are OK; do it */ 900 if (v & WSDISPLAY_CURSOR_DOCUR) { 901 if (cursorp->enable) 902 /* XXX */ 903 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04); 904 else 905 /* XXX */ 906 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04); 907 } 908 if (v & WSDISPLAY_CURSOR_DOPOS) { 909 TGAWREG(dc, TGA_REG_CXYR, 910 ((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff)); 911 } 912 if (v & WSDISPLAY_CURSOR_DOCMAP) { 913 /* can't fail. */ 914 dcrf->ramdac_set_curcmap(dcrc, cursorp); 915 } 916 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 917 /* The cursor is 2 bits deep, and there is no mask */ 918 count = (cursorp->size.y * 64 * 2) / NBBY; 919 TGAWREG(dc, TGA_REG_CCBR, 920 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10)); 921 if ((error = copyin(cursorp->image,(char *)(dc->dc_vaddr + 922 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), count)) != 0) 923 return (error); 924 } 925 return (0); 926 } 927 928 int 929 tga_builtin_get_cursor(dc, cursorp) 930 struct tga_devconfig *dc; 931 struct wsdisplay_cursor *cursorp; 932 { 933 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 934 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 935 int error; 936 u_int count; 937 938 cursorp->which = WSDISPLAY_CURSOR_DOALL & 939 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 940 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 941 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 942 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 943 cursorp->size.x = 64; 944 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 945 946 if (cursorp->image != NULL) { 947 count = (cursorp->size.y * 64 * 2) / NBBY; 948 error = copyout((char *)(dc->dc_vaddr + 949 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 950 cursorp->image, count); 951 if (error) 952 return (error); 953 /* No mask */ 954 } 955 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 956 return (error); 957 } 958 959 int 960 tga_builtin_set_curpos(dc, curposp) 961 struct tga_devconfig *dc; 962 struct wsdisplay_curpos *curposp; 963 { 964 965 TGAWREG(dc, TGA_REG_CXYR, 966 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 967 return (0); 968 } 969 970 int 971 tga_builtin_get_curpos(dc, curposp) 972 struct tga_devconfig *dc; 973 struct wsdisplay_curpos *curposp; 974 { 975 976 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 977 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 978 return (0); 979 } 980 981 int 982 tga_builtin_get_curmax(dc, curposp) 983 struct tga_devconfig *dc; 984 struct wsdisplay_curpos *curposp; 985 { 986 987 curposp->x = curposp->y = 64; 988 return (0); 989 } 990 991 /* 992 * Copy columns (characters) in a row (line). 993 */ 994 void 995 tga_copycols(id, row, srccol, dstcol, ncols) 996 void *id; 997 int row, srccol, dstcol, ncols; 998 { 999 struct rasops_info *ri = id; 1000 int y, srcx, dstx, nx; 1001 1002 y = ri->ri_font->fontheight * row; 1003 srcx = ri->ri_font->fontwidth * srccol; 1004 dstx = ri->ri_font->fontwidth * dstcol; 1005 nx = ri->ri_font->fontwidth * ncols; 1006 1007 tga_rop(ri, dstx, y, 1008 nx, ri->ri_font->fontheight, RAS_SRC, 1009 ri, srcx, y); 1010 } 1011 1012 /* 1013 * Copy rows (lines). 1014 */ 1015 void 1016 tga_copyrows(id, srcrow, dstrow, nrows) 1017 void *id; 1018 int srcrow, dstrow, nrows; 1019 { 1020 struct rasops_info *ri = id; 1021 int srcy, dsty, ny; 1022 1023 srcy = ri->ri_font->fontheight * srcrow; 1024 dsty = ri->ri_font->fontheight * dstrow; 1025 ny = ri->ri_font->fontheight * nrows; 1026 1027 tga_rop(ri, 0, dsty, 1028 ri->ri_emuwidth, ny, RAS_SRC, 1029 ri, 0, srcy); 1030 } 1031 1032 /* Do we need the src? */ 1033 int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 1034 1035 /* A mapping between our API and the TGA card */ 1036 int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 1037 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 1038 }; 1039 1040 /* 1041 * Generic TGA raster op. 1042 * This covers all possible raster ops, and 1043 * clips the sizes and all of that. 1044 */ 1045 int 1046 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy) 1047 struct rasops_info *dst; 1048 int dx, dy, w, h, rop; 1049 struct rasops_info *src; 1050 int sx, sy; 1051 { 1052 if (!dst) 1053 return -1; 1054 if (needsrc[RAS_GETOP(rop)]) { 1055 if (src == NULL) 1056 return -1; /* We want a src */ 1057 /* Clip against src */ 1058 if (sx < 0) { 1059 w += sx; 1060 sx = 0; 1061 } 1062 if (sy < 0) { 1063 h += sy; 1064 sy = 0; 1065 } 1066 if (sx + w > src->ri_emuwidth) 1067 w = src->ri_emuwidth - sx; 1068 if (sy + h > src->ri_emuheight) 1069 h = src->ri_emuheight - sy; 1070 } else { 1071 if (src != NULL) 1072 return -1; /* We need no src */ 1073 } 1074 /* Clip against dst. We modify src regardless of using it, 1075 * since it really doesn't matter. 1076 */ 1077 if (dx < 0) { 1078 w += dx; 1079 sx -= dx; 1080 dx = 0; 1081 } 1082 if (dy < 0) { 1083 h += dy; 1084 sy -= dy; 1085 dy = 0; 1086 } 1087 if (dx + w > dst->ri_emuwidth) 1088 w = dst->ri_emuwidth - dx; 1089 if (dy + h > dst->ri_emuheight) 1090 h = dst->ri_emuheight - dy; 1091 if (w <= 0 || h <= 0) 1092 return 0; /* Vacuously true; */ 1093 if (!src) { 1094 /* XXX Punt! */ 1095 return -1; 1096 } 1097 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1098 } 1099 1100 1101 1102 /* 1103 * Video to Video raster ops. 1104 * This function deals with all raster ops that have a src and dst 1105 * that are on the card. 1106 */ 1107 int 1108 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy) 1109 struct rasops_info *dst; 1110 int dx, dy, w, h, rop; 1111 struct rasops_info *src; 1112 int sx, sy; 1113 { 1114 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 1115 int srcb, dstb, tga_srcb, tga_dstb; 1116 int x, y, wb; 1117 int xstart, xend, xdir; 1118 int ystart, yend, ydir, yinc; 1119 int xleft, lastx, lastleft; 1120 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1121 1122 /* 1123 * I don't yet want to deal with unaligned guys, really. And we don't 1124 * deal with copies from one card to another. 1125 */ 1126 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1127 /* XXX Punt! */ 1128 /* XXX should never happen, since it's only being used to 1129 * XXX copy 8-pixel-wide characters. 1130 */ 1131 return -1; 1132 } 1133 1134 wb = w * (dst->ri_depth / 8); 1135 if (sy >= dy) { 1136 ystart = 0; 1137 yend = h; 1138 ydir = 1; 1139 } else { 1140 ystart = h; 1141 yend = 0; 1142 ydir = -1; 1143 } 1144 if (sx >= dx) { /* moving to the left */ 1145 xstart = 0; 1146 xend = w * (dst->ri_depth / 8) - 4; 1147 xdir = 1; 1148 } else { /* moving to the right */ 1149 xstart = wb - ( wb >= 4*64 ? 4*64 : wb >= 64 ? 64 : 4 ); 1150 xend = 0; 1151 xdir = -1; 1152 } 1153 #define XINC4 4 1154 #define XINC64 64 1155 #define XINC256 (64*4) 1156 yinc = ydir * dst->ri_stride; 1157 ystart *= dst->ri_stride; 1158 yend *= dst->ri_stride; 1159 1160 srcb = sy * src->ri_stride + sx * (src->ri_depth/8); 1161 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); 1162 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1163 (sx + src->ri_xorigin) * (src->ri_depth/8); 1164 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1165 (dx + dst->ri_xorigin) * (dst->ri_depth/8); 1166 1167 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1168 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1169 1170 /* 1171 * we have 3 sizes of pixels to move in X direction: 1172 * 4 * 64 (unrolled TGA ops) 1173 * 64 (single TGA op) 1174 * 4 (CPU, using long word) 1175 */ 1176 1177 if (xdir == 1) { /* move to the left */ 1178 1179 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1180 1181 /* 4*64 byte chunks */ 1182 for (xleft = wb, x = xstart; 1183 x <= xend && xleft >= 4*64; 1184 x += XINC256, xleft -= XINC256) { 1185 1186 /* XXX XXX Eight writes to different addresses should fill 1187 * XXX XXX up the write buffers on 21064 and 21164 chips, 1188 * XXX XXX but later CPUs might have larger write buffers which 1189 * XXX XXX require further unrolling of this loop, or the 1190 * XXX XXX insertion of memory barriers. 1191 */ 1192 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1193 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1194 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64); 1195 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64); 1196 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64); 1197 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64); 1198 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64); 1199 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64); 1200 } 1201 1202 /* 64 byte chunks */ 1203 for ( ; x <= xend && xleft >= 64; 1204 x += XINC64, xleft -= XINC64) { 1205 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1206 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1207 } 1208 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1209 1210 } 1211 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1212 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1213 1214 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1215 /* 4 byte granularity */ 1216 for (x = lastx, xleft = lastleft; 1217 x <= xend && xleft >= 4; 1218 x += XINC4, xleft -= XINC4) { 1219 *(uint32_t *)(dst->ri_bits + dstb + y + x) = 1220 *(uint32_t *)(dst->ri_bits + srcb + y + x); 1221 } 1222 } 1223 } 1224 else { /* above move to the left, below move to the right */ 1225 1226 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1227 1228 /* 4*64 byte chunks */ 1229 for (xleft = wb, x = xstart; 1230 x >= xend && xleft >= 4*64; 1231 x -= XINC256, xleft -= XINC256) { 1232 1233 /* XXX XXX Eight writes to different addresses should fill 1234 * XXX XXX up the write buffers on 21064 and 21164 chips, 1235 * XXX XXX but later CPUs might have larger write buffers which 1236 * XXX XXX require further unrolling of this loop, or the 1237 * XXX XXX insertion of memory barriers. 1238 */ 1239 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 3 * 64); 1240 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 3 * 64); 1241 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 2 * 64); 1242 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 2 * 64); 1243 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 1 * 64); 1244 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 1 * 64); 1245 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 0 * 64); 1246 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 0 * 64); 1247 } 1248 1249 if (xleft) x += XINC256 - XINC64; 1250 1251 /* 64 byte chunks */ 1252 for ( ; x >= xend && xleft >= 64; 1253 x -= XINC64, xleft -= XINC64) { 1254 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1255 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1256 } 1257 if (xleft) x += XINC64 - XINC4; 1258 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1259 } 1260 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1261 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1262 1263 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1264 /* 4 byte granularity */ 1265 for (x = lastx, xleft = lastleft; 1266 x >= xend && xleft >= 4; 1267 x -= XINC4, xleft -= XINC4) { 1268 *(uint32_t *)(dst->ri_bits + dstb + y + x) = 1269 *(uint32_t *)(dst->ri_bits + srcb + y + x); 1270 } 1271 } 1272 } 1273 return 0; 1274 } 1275 1276 1277 void tga_putchar (c, row, col, uc, attr) 1278 void *c; 1279 int row, col; 1280 u_int uc; 1281 long attr; 1282 { 1283 struct rasops_info *ri = c; 1284 struct tga_devconfig *dc = ri->ri_hw; 1285 int fs, height, width; 1286 u_char *fr; 1287 int32_t *rp; 1288 1289 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1290 1291 height = ri->ri_font->fontheight; 1292 width = ri->ri_font->fontwidth; 1293 1294 uc -= ri->ri_font->firstchar; 1295 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1296 fs = ri->ri_font->stride; 1297 1298 /* Set foreground and background color. XXX memoize this somehow? 1299 * The rasops code has already expanded the color entry to 32 bits 1300 * for us, even for 8-bit displays, so we don't have to do anything. 1301 */ 1302 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1303 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1304 1305 /* Set raster operation to "copy"... */ 1306 if (ri->ri_depth == 8) 1307 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1308 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1309 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1310 1311 /* Set which pixels we're drawing (of a possible 32). */ 1312 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1313 1314 /* Set drawing mode to opaque stipple. */ 1315 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1316 1317 /* Insert write barrier before actually sending data */ 1318 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1319 TGAREGWB(dc, TGA_REG_GMOR, 1); 1320 1321 while (height--) { 1322 /* The actual stipple write */ 1323 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1324 1325 fr += fs; 1326 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1327 } 1328 1329 /* Do underline */ 1330 if ((attr & 1) != 0) { 1331 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1)); 1332 *rp = 0xffffffff; 1333 } 1334 1335 /* Set grapics mode back to normal. */ 1336 TGAWREG(dc, TGA_REG_GMOR, 0); 1337 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1338 1339 } 1340 1341 void 1342 tga_eraserows(c, row, num, attr) 1343 void *c; 1344 int row, num; 1345 long attr; 1346 { 1347 struct rasops_info *ri = c; 1348 struct tga_devconfig *dc = ri->ri_hw; 1349 int32_t color, lines, pixels; 1350 int32_t *rp; 1351 1352 color = ri->ri_devcmap[(attr >> 16) & 15]; 1353 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1354 lines = num * ri->ri_font->fontheight; 1355 pixels = ri->ri_emuwidth - 1; 1356 1357 /* Set fill color in block-color registers */ 1358 TGAWREG(dc, TGA_REG_GBCR0, color); 1359 TGAWREG(dc, TGA_REG_GBCR1, color); 1360 if (ri->ri_depth != 8) { 1361 TGAWREG(dc, TGA_REG_GBCR2, color); 1362 TGAWREG(dc, TGA_REG_GBCR3, color); 1363 TGAWREG(dc, TGA_REG_GBCR4, color); 1364 TGAWREG(dc, TGA_REG_GBCR5, color); 1365 TGAWREG(dc, TGA_REG_GBCR6, color); 1366 TGAWREG(dc, TGA_REG_GBCR7, color); 1367 } 1368 1369 /* Set raster operation to "copy"... */ 1370 if (ri->ri_depth == 8) 1371 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1372 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1373 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1374 1375 /* Set which pixels we're drawing (of a possible 32). */ 1376 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1377 1378 /* Set drawing mode to block fill. */ 1379 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1380 1381 /* Insert write barrier before actually sending data */ 1382 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1383 TGAREGWB(dc, TGA_REG_GMOR, 1); 1384 1385 while (lines--) { 1386 *rp = pixels; 1387 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1388 } 1389 1390 /* Set grapics mode back to normal. */ 1391 TGAWREG(dc, TGA_REG_GMOR, 0); 1392 1393 } 1394 1395 void 1396 tga_erasecols (c, row, col, num, attr) 1397 void *c; 1398 int row, col, num; 1399 long attr; 1400 { 1401 struct rasops_info *ri = c; 1402 struct tga_devconfig *dc = ri->ri_hw; 1403 int32_t color, lines, pixels; 1404 int32_t *rp; 1405 1406 color = ri->ri_devcmap[(attr >> 16) & 15]; 1407 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1408 lines = ri->ri_font->fontheight; 1409 pixels = (num * ri->ri_font->fontwidth) - 1; 1410 1411 /* Set fill color in block-color registers */ 1412 TGAWREG(dc, TGA_REG_GBCR0, color); 1413 TGAWREG(dc, TGA_REG_GBCR1, color); 1414 if (ri->ri_depth != 8) { 1415 TGAWREG(dc, TGA_REG_GBCR2, color); 1416 TGAWREG(dc, TGA_REG_GBCR3, color); 1417 TGAWREG(dc, TGA_REG_GBCR4, color); 1418 TGAWREG(dc, TGA_REG_GBCR5, color); 1419 TGAWREG(dc, TGA_REG_GBCR6, color); 1420 TGAWREG(dc, TGA_REG_GBCR7, color); 1421 } 1422 1423 /* Set raster operation to "copy"... */ 1424 if (ri->ri_depth == 8) 1425 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1426 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1427 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1428 1429 /* Set which pixels we're drawing (of a possible 32). */ 1430 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1431 1432 /* Set drawing mode to block fill. */ 1433 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1434 1435 /* Insert write barrier before actually sending data */ 1436 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1437 TGAREGWB(dc, TGA_REG_GMOR, 1); 1438 1439 while (lines--) { 1440 *rp = pixels; 1441 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1442 } 1443 1444 /* Set grapics mode back to normal. */ 1445 TGAWREG(dc, TGA_REG_GMOR, 0); 1446 } 1447 1448 1449 void 1450 tga_ramdac_wr(v, btreg, val) 1451 void *v; 1452 u_int btreg; 1453 u_int8_t val; 1454 { 1455 struct tga_devconfig *dc = v; 1456 1457 if (btreg > BT485_REG_MAX) 1458 panic("tga_ramdac_wr: reg %d out of range", btreg); 1459 1460 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1461 TGAREGWB(dc, TGA_REG_EPDR, 1); 1462 } 1463 1464 void 1465 tga2_ramdac_wr(v, btreg, val) 1466 void *v; 1467 u_int btreg; 1468 u_int8_t val; 1469 { 1470 struct tga_devconfig *dc = v; 1471 bus_space_handle_t ramdac; 1472 1473 if (btreg > BT485_REG_MAX) 1474 panic("tga_ramdac_wr: reg %d out of range", btreg); 1475 1476 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1477 (0xe << 12) + (btreg << 8), 4, &ramdac); 1478 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1479 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1480 } 1481 1482 u_int8_t 1483 tga_bt463_rd(v, btreg) 1484 void *v; 1485 u_int btreg; 1486 { 1487 struct tga_devconfig *dc = v; 1488 tga_reg_t rdval; 1489 1490 /* 1491 * Strobe CE# (high->low->high) since status and data are latched on 1492 * the falling and rising edges (repsectively) of this active-low signal. 1493 */ 1494 1495 TGAREGWB(dc, TGA_REG_EPSR, 1); 1496 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1497 TGAREGWB(dc, TGA_REG_EPSR, 1); 1498 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1499 1500 TGAREGRB(dc, TGA_REG_EPSR, 1); 1501 1502 rdval = TGARREG(dc, TGA_REG_EPDR); 1503 TGAREGWB(dc, TGA_REG_EPSR, 1); 1504 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1505 1506 return (rdval >> 16) & 0xff; 1507 } 1508 1509 void 1510 tga_bt463_wr(v, btreg, val) 1511 void *v; 1512 u_int btreg; 1513 u_int8_t val; 1514 { 1515 struct tga_devconfig *dc = v; 1516 1517 /* 1518 * In spite of the 21030 documentation, to set the MPU bus bits for 1519 * a write, you set them in the upper bits of EPDR, not EPSR. 1520 */ 1521 1522 /* 1523 * Strobe CE# (high->low->high) since status and data are latched on 1524 * the falling and rising edges of this active-low signal. 1525 */ 1526 1527 TGAREGWB(dc, TGA_REG_EPDR, 1); 1528 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1529 TGAREGWB(dc, TGA_REG_EPDR, 1); 1530 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1531 TGAREGWB(dc, TGA_REG_EPDR, 1); 1532 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1533 1534 } 1535 1536 u_int8_t 1537 tga_ramdac_rd(v, btreg) 1538 void *v; 1539 u_int btreg; 1540 { 1541 struct tga_devconfig *dc = v; 1542 tga_reg_t rdval; 1543 1544 if (btreg > BT485_REG_MAX) 1545 panic("tga_ramdac_rd: reg %d out of range", btreg); 1546 1547 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1548 TGAREGWB(dc, TGA_REG_EPSR, 1); 1549 1550 rdval = TGARREG(dc, TGA_REG_EPDR); 1551 return (rdval >> 16) & 0xff; /* XXX */ 1552 } 1553 1554 u_int8_t 1555 tga2_ramdac_rd(v, btreg) 1556 void *v; 1557 u_int btreg; 1558 { 1559 struct tga_devconfig *dc = v; 1560 bus_space_handle_t ramdac; 1561 u_int8_t retval; 1562 1563 if (btreg > BT485_REG_MAX) 1564 panic("tga_ramdac_rd: reg %d out of range", btreg); 1565 1566 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1567 (0xe << 12) + (btreg << 8), 4, &ramdac); 1568 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1569 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1570 return retval; 1571 } 1572 1573 #include <dev/ic/decmonitors.c> 1574 void tga2_ics9110_wr( 1575 struct tga_devconfig *dc, 1576 int dotclock 1577 ); 1578 1579 struct monitor *tga_getmonitor(struct tga_devconfig *dc); 1580 1581 void 1582 tga2_init(dc) 1583 struct tga_devconfig *dc; 1584 { 1585 struct monitor *m = tga_getmonitor(dc); 1586 1587 1588 /* Deal with the dot clocks. 1589 */ 1590 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1591 /* Set this up as a reference clock for the 1592 * ibm561's PLL. 1593 */ 1594 tga2_ics9110_wr(dc, 14300000); 1595 /* XXX Can't set up the dotclock properly, until such time 1596 * as the RAMDAC is configured. 1597 */ 1598 } else { 1599 /* otherwise the ics9110 is our clock. */ 1600 tga2_ics9110_wr(dc, m->dotclock); 1601 } 1602 #if 0 1603 TGAWREG(dc, TGA_REG_VHCR, 1604 ((m->hbp / 4) << 21) | 1605 ((m->hsync / 4) << 14) | 1606 (((m->hfp - 4) / 4) << 9) | 1607 ((m->cols + 4) / 4)); 1608 #else 1609 TGAWREG(dc, TGA_REG_VHCR, 1610 ((m->hbp / 4) << 21) | 1611 ((m->hsync / 4) << 14) | 1612 (((m->hfp) / 4) << 9) | 1613 ((m->cols) / 4)); 1614 #endif 1615 TGAWREG(dc, TGA_REG_VVCR, 1616 (m->vbp << 22) | 1617 (m->vsync << 16) | 1618 (m->vfp << 11) | 1619 (m->rows)); 1620 TGAWREG(dc, TGA_REG_VVBR, 1); 1621 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1622 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1623 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1624 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1625 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1626 } 1627 1628 void 1629 tga2_ics9110_wr(dc, dotclock) 1630 struct tga_devconfig *dc; 1631 int dotclock; 1632 { 1633 bus_space_handle_t clock; 1634 u_int32_t valU; 1635 int N, M, R, V, X; 1636 int i; 1637 1638 switch (dotclock) { 1639 case 130808000: 1640 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1641 case 119840000: 1642 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1643 case 108180000: 1644 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1645 case 103994000: 1646 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1647 case 175000000: 1648 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1649 case 75000000: 1650 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1651 case 74000000: 1652 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1653 case 69000000: 1654 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1655 case 65000000: 1656 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1657 case 50000000: 1658 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1659 case 40000000: 1660 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1661 case 31500000: 1662 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1663 case 25175000: 1664 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1665 case 135000000: 1666 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1667 case 110000000: 1668 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1669 case 202500000: 1670 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1671 case 14300000: /* this one is just a ref clock */ 1672 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1673 default: 1674 panic("unrecognized clock rate %d", dotclock); 1675 } 1676 1677 /* XXX -- hard coded, bad */ 1678 valU = N | ( M << 7 ) | (V << 14); 1679 valU |= (X << 15) | (R << 17); 1680 valU |= 0x17 << 19; 1681 1682 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1683 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1684 1685 for (i = 24; i > 0; i--) { 1686 u_int32_t writeval; 1687 1688 writeval = valU & 0x1; 1689 if (i == 1) 1690 writeval |= 0x2; 1691 valU >>= 1; 1692 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1693 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1694 } 1695 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1696 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1697 &clock); /* XXX */ 1698 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1699 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1700 } 1701 1702 struct monitor * 1703 tga_getmonitor(dc) 1704 struct tga_devconfig *dc; 1705 { 1706 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1707 } 1708 1709 unsigned 1710 tga_getdotclock(dc) 1711 struct tga_devconfig *dc; 1712 { 1713 return tga_getmonitor(dc)->dotclock; 1714 } 1715