1 /* $OpenBSD: tga.c,v 1.43 2022/07/15 17:57:26 kettenis Exp $ */ 2 /* $NetBSD: tga.c,v 1.40 2002/03/13 15:05:18 ad Exp $ */ 3 4 /* 5 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Author: Chris G. Demetriou 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/conf.h> 36 #include <sys/malloc.h> 37 #include <sys/buf.h> 38 #include <sys/ioctl.h> 39 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcidevs.h> 46 #include <dev/pci/tgareg.h> 47 #include <dev/pci/tgavar.h> 48 #include <dev/ic/bt485reg.h> 49 #include <dev/ic/bt485var.h> 50 #include <dev/ic/bt463reg.h> 51 #include <dev/ic/bt463var.h> 52 #include <dev/ic/ibm561var.h> 53 54 #include <dev/wscons/wsconsio.h> 55 #include <dev/rasops/rasops.h> 56 #include <dev/wsfont/wsfont.h> 57 58 #if defined(__alpha__) || defined(__mips__) 59 #include <uvm/uvm_extern.h> 60 #endif 61 62 #ifdef __alpha__ 63 #include <machine/pte.h> 64 #endif 65 #ifdef __mips__ 66 #include <mips/pte.h> 67 #endif 68 69 int tgamatch(struct device *, struct cfdata *, void *); 70 void tgaattach(struct device *, struct device *, void *); 71 int tgaprint(void *, const char *); 72 73 struct cfdriver tga_cd = { 74 NULL, "tga", DV_DULL 75 }; 76 77 const struct cfattach tga_ca = { 78 sizeof(struct tga_softc), (cfmatch_t)tgamatch, tgaattach, 79 }; 80 81 int tga_identify(struct tga_devconfig *); 82 const struct tga_conf *tga_getconf(int); 83 void tga_getdevconfig(bus_space_tag_t memt, pci_chipset_tag_t pc, 84 pcitag_t tag, struct tga_devconfig *dc); 85 unsigned tga_getdotclock(struct tga_devconfig *dc); 86 87 struct tga_devconfig tga_console_dc; 88 89 int tga_ioctl(void *, u_long, caddr_t, int, struct proc *); 90 paddr_t tga_mmap(void *, off_t, int); 91 int tga_alloc_screen(void *, const struct wsscreen_descr *, 92 void **, int *, int *, uint32_t *); 93 void tga_free_screen(void *, void *); 94 int tga_show_screen(void *, void *, int, 95 void (*) (void *, int, int), void *); 96 int tga_load_font(void *, void *, struct wsdisplay_font *); 97 int tga_list_font(void *, struct wsdisplay_font *); 98 void tga_burner(void *, u_int, u_int); 99 100 int tga_copyrows(void *, int, int, int); 101 int tga_copycols(void *, int, int, int, int); 102 int tga_eraserows(void *, int, int, uint32_t); 103 int tga_erasecols(void *, int, int, int, uint32_t); 104 int tga_putchar(void *c, int row, int col, u_int uc, uint32_t attr); 105 106 int tga_rop(struct rasops_info *, int, int, int, int, 107 struct rasops_info *, int, int); 108 int tga_rop_vtov(struct rasops_info *, int, int, int, 109 int, struct rasops_info *, int, int ); 110 void tga2_init(struct tga_devconfig *); 111 112 void tga_config_interrupts(struct device *); 113 114 /* RAMDAC interface functions */ 115 int tga_sched_update(void *, void (*)(void *)); 116 void tga_ramdac_wr(void *, u_int, u_int8_t); 117 u_int8_t tga_ramdac_rd(void *, u_int); 118 void tga_bt463_wr(void *, u_int, u_int8_t); 119 u_int8_t tga_bt463_rd(void *, u_int); 120 void tga2_ramdac_wr(void *, u_int, u_int8_t); 121 u_int8_t tga2_ramdac_rd(void *, u_int); 122 123 /* Interrupt handler */ 124 int tga_intr(void *); 125 126 /* The NULL entries will get filled in by rasops_init(). 127 * XXX and the non-NULL ones will be overwritten; reset after calling it. 128 */ 129 struct wsdisplay_emulops tga_emulops = { 130 NULL, 131 NULL, 132 tga_putchar, 133 tga_copycols, 134 tga_erasecols, 135 tga_copyrows, 136 tga_eraserows, 137 NULL, 138 NULL 139 }; 140 141 struct wsscreen_descr tga_stdscreen = { 142 "std", 143 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 144 &tga_emulops, 145 0, 0, 146 WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 147 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE 148 }; 149 150 const struct wsscreen_descr *_tga_scrlist[] = { 151 &tga_stdscreen, 152 /* XXX other formats, graphics screen? */ 153 }; 154 155 struct wsscreen_list tga_screenlist = { 156 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 157 }; 158 159 struct wsdisplay_accessops tga_accessops = { 160 .ioctl = tga_ioctl, 161 .mmap = tga_mmap, 162 .alloc_screen = tga_alloc_screen, 163 .free_screen = tga_free_screen, 164 .show_screen = tga_show_screen, 165 .load_font = tga_load_font, 166 .list_font = tga_list_font, 167 .burn_screen = tga_burner 168 }; 169 170 void tga_blank(struct tga_devconfig *); 171 void tga_unblank(struct tga_devconfig *); 172 173 #ifdef TGA_DEBUG 174 #define DPRINTF(...) printf (__VA_ARGS__) 175 #define DPRINTFN(n, ...) if (tgadebug > (n)) printf (__VA_ARGS__) 176 int tgadebug = 0; 177 #else 178 #define DPRINTF(...) 179 #define DPRINTFN(n,...) 180 #endif 181 182 const struct pci_matchid tga_devices[] = { 183 { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21030 }, 184 { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_PBXGB }, 185 }; 186 187 int 188 tgamatch(parent, match, aux) 189 struct device *parent; 190 struct cfdata *match; 191 void *aux; 192 { 193 if (pci_matchbyid((struct pci_attach_args *)aux, tga_devices, 194 sizeof(tga_devices) / sizeof(tga_devices[0]))) 195 return (10); /* need to return more than vga_pci here! */ 196 197 return (0); 198 } 199 200 void 201 tga_getdevconfig(memt, pc, tag, dc) 202 bus_space_tag_t memt; 203 pci_chipset_tag_t pc; 204 pcitag_t tag; 205 struct tga_devconfig *dc; 206 { 207 const struct tga_conf *tgac; 208 struct rasops_info *rip; 209 int cookie; 210 bus_size_t pcisize; 211 int i; 212 213 dc->dc_memt = memt; 214 215 dc->dc_pcitag = tag; 216 217 DPRINTF("tga_getdevconfig: Getting map info\n"); 218 /* XXX magic number */ 219 if (pci_mapreg_info(pc, tag, 0x10, 220 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 221 &dc->dc_pcipaddr, &pcisize, NULL)) 222 return; 223 224 DPRINTF("tga_getdevconfig: preparing to map\n"); 225 if (bus_space_map(memt, dc->dc_pcipaddr, pcisize, 226 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 227 return; 228 #ifdef __OpenBSD__ 229 dc->dc_vaddr = dc->dc_memh; 230 #else 231 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 232 #endif 233 DPRINTF("tga_getdevconfig: mapped\n"); 234 235 #ifdef __alpha__ 236 dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr); /* XXX */ 237 #endif 238 DPRINTF("tga_getdevconfig: allocating subregion\n"); 239 bus_space_subregion(dc->dc_memt, dc->dc_memh, 240 TGA_MEM_CREGS, TGA_CREGS_SIZE, 241 &dc->dc_regs); 242 243 DPRINTF("tga_getdevconfig: going to identify\n"); 244 dc->dc_tga_type = tga_identify(dc); 245 246 DPRINTF("tga_getdevconfig: preparing to get config\n"); 247 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 248 if (tgac == NULL) 249 return; 250 251 #if 0 252 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 253 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 254 panic("tga_getdevconfig: memory size mismatch?"); 255 #endif 256 257 DPRINTF("tga_getdevconfig: get revno\n"); 258 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 259 case 0x01: 260 case 0x02: 261 case 0x03: 262 case 0x04: 263 dc->dc_tga2 = 0; 264 break; 265 case 0x20: 266 case 0x21: 267 case 0x22: 268 dc->dc_tga2 = 1; 269 break; 270 default: 271 panic("tga_getdevconfig: TGA Revision not recognized"); 272 } 273 274 if (dc->dc_tga2) { 275 tga2_init(dc); 276 } 277 278 i = TGARREG(dc, TGA_REG_VHCR) & 0x1ff; 279 DPRINTF("tga_getdevconfig: TGA_REG_VHCR & 0x1ff = %d\n", i); 280 switch (i) { /* XXX */ 281 case 0: 282 dc->dc_wid = 8192; 283 break; 284 285 case 1: 286 dc->dc_wid = 8196; 287 break; 288 289 default: 290 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 291 break; 292 } 293 294 DPRINTF("tga_getdevconfig: dc->dc_wid = %d\n", dc->dc_wid); 295 /* 296 * XXX XXX Turning off "odd" shouldn't be necessary, 297 * XXX XXX but I can't make X work with the weird size. 298 */ 299 DPRINTF("tga_getdevconfig: beginning magic incantation\n"); 300 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 301 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 302 TGAWREG(dc, TGA_REG_VHCR, 303 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 304 dc->dc_wid -= 4; 305 } 306 307 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 308 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 309 DPRINTF("tga_getdevconfig: rowbytes = %d, tgac_phys_depth = %d\n" 310 " dc_wid = %d, dc_ht = %d\n", 311 dc->dc_rowbytes, dc->dc_tgaconf->tgac_phys_depth, 312 dc->dc_wid, dc->dc_ht); 313 314 /* XXX this seems to be what DEC does */ 315 DPRINTF("tga_getdevconfig: more magic\n"); 316 TGAWREG(dc, TGA_REG_CCBR, 0); 317 TGAWREG(dc, TGA_REG_VVBR, 1); 318 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 319 1 * tgac->tgac_vvbr_units; 320 dc->dc_blanked = 1; 321 tga_unblank(dc); 322 323 DPRINTF("tga_getdevconfig: dc_videobase = 0x%016llx\n" 324 " dc_vaddr = 0x%016llx\n" 325 " tgac_dbuf[0] = %d\n" 326 " tgac_vvbr_units = %d\n", 327 dc->dc_videobase, dc->dc_vaddr, tgac->tgac_dbuf[0], 328 tgac->tgac_vvbr_units); 329 330 /* 331 * Set all bits in the pixel mask, to enable writes to all pixels. 332 * It seems that the console firmware clears some of them 333 * under some circumstances, which causes cute vertical stripes. 334 */ 335 DPRINTF("tga_getdevconfig: set pixel mask\n"); 336 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 337 338 /* clear the screen */ 339 DPRINTF("tga_getdevconfig: clear screen\n"); 340 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 341 *(u_int32_t *)(dc->dc_videobase + i) = 0; 342 343 DPRINTF("tga_getdevconfig: raster ops\n"); 344 /* Initialize rasops descriptor */ 345 rip = &dc->dc_rinfo; 346 rip->ri_flg = RI_CENTER; 347 rip->ri_depth = tgac->tgac_phys_depth; 348 rip->ri_bits = (void *)dc->dc_videobase; 349 rip->ri_width = dc->dc_wid; 350 rip->ri_height = dc->dc_ht; 351 rip->ri_stride = dc->dc_rowbytes; 352 rip->ri_hw = dc; 353 354 if (tgac->tgac_phys_depth == 32) { 355 rip->ri_rnum = 8; 356 rip->ri_gnum = 8; 357 rip->ri_bnum = 8; 358 rip->ri_rpos = 16; 359 rip->ri_gpos = 8; 360 rip->ri_bpos = 0; 361 } 362 363 DPRINTF("tga_getdevconfig: wsfont_init\n"); 364 wsfont_init(); 365 if (rip->ri_width > 80*12) 366 /* High res screen, choose a big font */ 367 cookie = wsfont_find(NULL, 12, 0, 0); 368 else 369 /* lower res, choose a 8 pixel wide font */ 370 cookie = wsfont_find(NULL, 8, 0, 0); 371 if (cookie <= 0) 372 cookie = wsfont_find(NULL, 0, 0, 0); 373 if (cookie <= 0) { 374 printf("tga: no appropriate fonts.\n"); 375 return; 376 } 377 378 /* the accelerated tga_putchar() needs LSbit left */ 379 if (wsfont_lock(cookie, &rip->ri_font, 380 WSDISPLAY_FONTORDER_R2L, WSDISPLAY_FONTORDER_L2R) <= 0) { 381 printf("tga: couldn't lock font\n"); 382 return; 383 } 384 rip->ri_wsfcookie = cookie; 385 /* fill screen size */ 386 rasops_init(rip, rip->ri_height / rip->ri_font->fontheight, 387 rip->ri_width / rip->ri_font->fontwidth); 388 389 /* add our accelerated functions */ 390 /* XXX shouldn't have to do this; rasops should leave non-NULL 391 * XXX entries alone. 392 */ 393 rip->ri_ops.copyrows = tga_copyrows; 394 rip->ri_ops.eraserows = tga_eraserows; 395 rip->ri_ops.erasecols = tga_erasecols; 396 rip->ri_ops.copycols = tga_copycols; 397 rip->ri_ops.putchar = tga_putchar; 398 399 tga_stdscreen.nrows = rip->ri_rows; 400 tga_stdscreen.ncols = rip->ri_cols; 401 tga_stdscreen.textops = &rip->ri_ops; 402 tga_stdscreen.capabilities = rip->ri_caps; 403 404 dc->dc_intrenabled = 0; 405 } 406 407 void 408 tgaattach(parent, self, aux) 409 struct device *parent, *self; 410 void *aux; 411 { 412 struct pci_attach_args *pa = aux; 413 struct tga_softc *sc = (struct tga_softc *)self; 414 struct wsemuldisplaydev_attach_args aa; 415 pci_intr_handle_t intrh; 416 const char *intrstr; 417 u_int8_t rev; 418 int console; 419 420 #if defined(__alpha__) 421 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 422 #else 423 console = 0; 424 #endif 425 if (console) { 426 sc->sc_dc = &tga_console_dc; 427 sc->nscreens = 1; 428 } else { 429 sc->sc_dc = malloc(sizeof(struct tga_devconfig), M_DEVBUF, 430 M_NOWAIT | M_ZERO); 431 if (sc->sc_dc == NULL) 432 return; 433 tga_getdevconfig(pa->pa_memt, pa->pa_pc, pa->pa_tag, 434 sc->sc_dc); 435 } 436 if (sc->sc_dc->dc_vaddr == 0) { 437 printf(": can't map mem space\n"); 438 return; 439 } 440 441 /* XXX say what's going on. */ 442 intrstr = NULL; 443 if (pci_intr_map(pa, &intrh)) { 444 printf(": can't map interrupt"); 445 return; 446 } 447 intrstr = pci_intr_string(pa->pa_pc, intrh); 448 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 449 sc->sc_dc, sc->sc_dev.dv_xname); 450 if (sc->sc_intr == NULL) { 451 printf(": can't establish interrupt"); 452 if (intrstr != NULL) 453 printf("at %s", intrstr); 454 printf("\n"); 455 return; 456 } 457 458 rev = PCI_REVISION(pa->pa_class); 459 switch (rev) { 460 case 0x1: 461 case 0x2: 462 case 0x3: 463 printf(": DC21030 step %c", 'A' + rev - 1); 464 break; 465 case 0x20: 466 printf(": TGA2 abstract software model"); 467 break; 468 case 0x21: 469 case 0x22: 470 printf(": TGA2 pass %d", rev - 0x20); 471 break; 472 473 default: 474 printf("unknown stepping (0x%x)", rev); 475 break; 476 } 477 printf(", "); 478 479 /* 480 * Get RAMDAC function vectors and call the RAMDAC functions 481 * to allocate its private storage and pass that back to us. 482 */ 483 484 DPRINTF("tgaattach: Get RAMDAC functions\n"); 485 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 486 if (!sc->sc_dc->dc_tga2) { 487 DPRINTF("tgaattach: !sc->sc_dc->dc_tga2\n"); 488 DPRINTF("tgaattach: sc->sc_dc->dc_tgaconf->ramdac_funcs %s " 489 "bt485_funcs\n", 490 (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 491 ? "==" : "!="); 492 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 493 sc->sc_dc->dc_ramdac_cookie = 494 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 495 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 496 else 497 sc->sc_dc->dc_ramdac_cookie = 498 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 499 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 500 } else { 501 DPRINTF("tgaattach: sc->sc_dc->dc_tga2\n"); 502 sc->sc_dc->dc_ramdac_cookie = 503 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 504 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 505 506 /* XXX this is a bit of a hack, setting the dotclock here */ 507 if (sc->sc_dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 508 (*sc->sc_dc->dc_ramdac_funcs->ramdac_set_dotclock) 509 (sc->sc_dc->dc_ramdac_cookie, 510 tga_getdotclock(sc->sc_dc)); 511 } 512 DPRINTF("tgaattach: sc->sc_dc->dc_ramdac_cookie = 0x%016llx\n", 513 sc->sc_dc->dc_ramdac_cookie); 514 /* 515 * Initialize the RAMDAC. Initialization includes disabling 516 * cursor, setting a sane colormap, etc. 517 */ 518 DPRINTF("tgaattach: Initializing RAMDAC.\n"); 519 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 520 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 521 522 if (sc->sc_dc->dc_tgaconf == NULL) { 523 printf("unknown board configuration\n"); 524 return; 525 } 526 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 527 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 528 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 529 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 530 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 531 532 if (intrstr != NULL) 533 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 534 intrstr); 535 536 aa.console = console; 537 aa.scrdata = &tga_screenlist; 538 aa.accessops = &tga_accessops; 539 aa.accesscookie = sc; 540 aa.defaultscreens = 0; 541 542 config_found(self, &aa, wsemuldisplaydevprint); 543 544 #ifdef __NetBSD__ 545 config_interrupts(self, tga_config_interrupts); 546 #else 547 tga_config_interrupts(self); 548 #endif 549 } 550 551 void 552 tga_config_interrupts (d) 553 struct device *d; 554 { 555 struct tga_softc *sc = (struct tga_softc *)d; 556 sc->sc_dc->dc_intrenabled = 1; 557 } 558 559 560 int 561 tga_ioctl(v, cmd, data, flag, p) 562 void *v; 563 u_long cmd; 564 caddr_t data; 565 int flag; 566 struct proc *p; 567 { 568 struct tga_softc *sc = v; 569 struct tga_devconfig *dc = sc->sc_dc; 570 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 571 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 572 573 switch (cmd) { 574 case WSDISPLAYIO_GTYPE: 575 *(u_int *)data = WSDISPLAY_TYPE_TGA; 576 break; 577 578 case WSDISPLAYIO_SMODE: 579 sc->sc_mode = *(u_int *)data; 580 switch (sc->sc_mode) { 581 case WSDISPLAYIO_MODE_DUMBFB: 582 /* in dump fb mode start the framebuffer at 0 */ 583 TGAWREG(dc, TGA_REG_VVBR, 0); 584 break; 585 default: 586 /* XXX it this useful, except for not breaking Xtga? */ 587 TGAWREG(dc, TGA_REG_VVBR, 1); 588 break; 589 } 590 break; 591 592 case WSDISPLAYIO_GINFO: 593 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 594 wsd_fbip->height = sc->sc_dc->dc_ht; 595 wsd_fbip->width = sc->sc_dc->dc_wid; 596 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 597 wsd_fbip->stride = sc->sc_dc->dc_rowbytes; 598 wsd_fbip->offset = 0; 599 wsd_fbip->cmsize = 1024; /* XXX ??? */ 600 #undef wsd_fbip 601 break; 602 603 case WSDISPLAYIO_LINEBYTES: 604 *(u_int *)data = sc->sc_dc->dc_rowbytes; 605 break; 606 607 case WSDISPLAYIO_GETCMAP: 608 return (*dcrf->ramdac_get_cmap)(dcrc, 609 (struct wsdisplay_cmap *)data); 610 case WSDISPLAYIO_PUTCMAP: 611 return (*dcrf->ramdac_set_cmap)(dcrc, 612 (struct wsdisplay_cmap *)data); 613 614 case WSDISPLAYIO_SVIDEO: 615 case WSDISPLAYIO_GVIDEO: 616 break; 617 618 case WSDISPLAYIO_GCURPOS: 619 return (*dcrf->ramdac_get_curpos)(dcrc, 620 (struct wsdisplay_curpos *)data); 621 622 case WSDISPLAYIO_SCURPOS: 623 return (*dcrf->ramdac_set_curpos)(dcrc, 624 (struct wsdisplay_curpos *)data); 625 626 case WSDISPLAYIO_GCURMAX: 627 return (*dcrf->ramdac_get_curmax)(dcrc, 628 (struct wsdisplay_curpos *)data); 629 630 case WSDISPLAYIO_GCURSOR: 631 return (*dcrf->ramdac_get_cursor)(dcrc, 632 (struct wsdisplay_cursor *)data); 633 634 case WSDISPLAYIO_SCURSOR: 635 return (*dcrf->ramdac_set_cursor)(dcrc, 636 (struct wsdisplay_cursor *)data); 637 638 default: 639 return (-1); 640 } 641 642 return (0); 643 } 644 645 int 646 tga_sched_update(v, f) 647 void *v; 648 void (*f)(void *); 649 { 650 struct tga_devconfig *dc = v; 651 652 if (dc->dc_intrenabled) { 653 /* Arrange for f to be called at the next end-of-frame interrupt */ 654 dc->dc_ramdac_intr = f; 655 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 656 } else { 657 /* Spin until the end-of-frame, then call f */ 658 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 659 TGAREGWB(dc, TGA_REG_SISR, 1); 660 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 661 ; 662 f(dc->dc_ramdac_cookie); 663 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 664 TGAREGWB(dc, TGA_REG_SISR, 1); 665 } 666 667 return 0; 668 } 669 670 int 671 tga_intr(v) 672 void *v; 673 { 674 struct tga_devconfig *dc = v; 675 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 676 677 u_int32_t reg; 678 679 reg = TGARREG(dc, TGA_REG_SISR); 680 if (( reg & 0x00010001) != 0x00010001) { 681 /* Odd. We never set any of the other interrupt enables. */ 682 if ((reg & 0x1f) != 0) { 683 /* Clear the mysterious pending interrupts. */ 684 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 685 TGAREGWB(dc, TGA_REG_SISR, 1); 686 /* This was our interrupt, even if we're puzzled as to why 687 * we got it. Don't make the interrupt handler think it 688 * was a stray. 689 */ 690 return -1; 691 } else { 692 return 0; 693 } 694 } 695 /* if we have something to do, do it */ 696 if (dc->dc_ramdac_intr) { 697 dc->dc_ramdac_intr(dcrc); 698 dc->dc_ramdac_intr = NULL; 699 } 700 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 701 TGAREGWB(dc, TGA_REG_SISR, 1); 702 return (1); 703 } 704 705 paddr_t 706 tga_mmap(v, offset, prot) 707 void *v; 708 off_t offset; 709 int prot; 710 { 711 struct tga_softc *sc = v; 712 struct tga_devconfig *dc = sc->sc_dc; 713 714 if (offset >= dc->dc_tgaconf->tgac_cspace_size || offset < 0) 715 return -1; 716 717 if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) { 718 /* 719 * The framebuffer starts at the upper half of tga mem 720 */ 721 offset += dc->dc_tgaconf->tgac_cspace_size / 2; 722 } 723 #if defined(__alpha__) || defined(__mips__) 724 return (sc->sc_dc->dc_paddr + offset); 725 #else 726 return (-1); 727 #endif 728 } 729 730 int 731 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 732 void *v; 733 const struct wsscreen_descr *type; 734 void **cookiep; 735 int *curxp, *curyp; 736 uint32_t *attrp; 737 { 738 struct tga_softc *sc = v; 739 uint32_t defattr; 740 741 if (sc->nscreens > 0) 742 return (ENOMEM); 743 744 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 745 *curxp = 0; 746 *curyp = 0; 747 sc->sc_dc->dc_rinfo.ri_ops.pack_attr(&sc->sc_dc->dc_rinfo, 748 0, 0, 0, &defattr); 749 *attrp = defattr; 750 sc->nscreens++; 751 return (0); 752 } 753 754 void 755 tga_free_screen(v, cookie) 756 void *v; 757 void *cookie; 758 { 759 struct tga_softc *sc = v; 760 761 if (sc->sc_dc == &tga_console_dc) 762 panic("tga_free_screen: console"); 763 764 sc->nscreens--; 765 } 766 767 int 768 tga_show_screen(v, cookie, waitok, cb, cbarg) 769 void *v; 770 void *cookie; 771 int waitok; 772 void (*cb)(void *, int, int); 773 void *cbarg; 774 { 775 776 return (0); 777 } 778 779 int 780 tga_load_font(void *v, void *emulcookie, struct wsdisplay_font *font) 781 { 782 struct tga_softc *sc = v; 783 struct tga_devconfig *dc = sc->sc_dc; 784 struct rasops_info *ri = &dc->dc_rinfo; 785 int wsfcookie; 786 struct wsdisplay_font *wsf; 787 const char *name; 788 789 /* 790 * We can't use rasops_load_font() directly, as we need to make 791 * sure that, when switching fonts, the font bits are set up in 792 * the correct bit order. 793 */ 794 795 if (font->data != NULL) 796 return rasops_load_font(ri, emulcookie, font); 797 798 /* allow an empty font name to revert to the initial font choice */ 799 name = font->name; 800 if (*name == '\0') 801 name = NULL; 802 803 wsfcookie = wsfont_find(name, ri->ri_font->fontwidth, 804 ri->ri_font->fontheight, 0); 805 if (wsfcookie < 0) { 806 wsfcookie = wsfont_find(name, 0, 0, 0); 807 if (wsfcookie < 0) 808 return ENOENT; 809 else 810 return EINVAL; 811 } 812 if (wsfont_lock(wsfcookie, &wsf, 813 WSDISPLAY_FONTORDER_R2L, WSDISPLAY_FONTORDER_L2R) <= 0) 814 return EINVAL; 815 816 /* if (ri->ri_wsfcookie >= 0) */ 817 wsfont_unlock(ri->ri_wsfcookie); 818 ri->ri_wsfcookie = wsfcookie; 819 ri->ri_font = wsf; 820 ri->ri_fontscale = ri->ri_font->fontheight * ri->ri_font->stride; 821 822 return 0; 823 } 824 825 int 826 tga_list_font(void *v, struct wsdisplay_font *font) 827 { 828 struct tga_softc *sc = v; 829 struct tga_devconfig *dc = sc->sc_dc; 830 struct rasops_info *ri = &dc->dc_rinfo; 831 832 return rasops_list_font(ri, font); 833 } 834 835 int 836 tga_cnattach(iot, memt, pc, bus, device, function) 837 bus_space_tag_t iot, memt; 838 pci_chipset_tag_t pc; 839 int bus, device, function; 840 { 841 struct tga_devconfig *dcp = &tga_console_dc; 842 uint32_t defattr; 843 844 tga_getdevconfig(memt, pc, 845 pci_make_tag(pc, bus, device, function), dcp); 846 847 /* sanity checks */ 848 if (dcp->dc_vaddr == 0) 849 panic("tga_console(%d, %d): can't map mem space", 850 device, function); 851 if (dcp->dc_tgaconf == NULL) 852 panic("tga_console(%d, %d): unknown board configuration", 853 device, function); 854 855 /* 856 * Initialize the RAMDAC but DO NOT allocate any private storage. 857 * Initialization includes disabling cursor, setting a sane 858 * colormap, etc. It will be reinitialized in tgaattach(). 859 */ 860 if (dcp->dc_tga2) { 861 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 862 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 863 tga2_ramdac_rd); 864 else 865 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 866 tga2_ramdac_rd, tga_getdotclock(dcp)); 867 } else { 868 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 869 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 870 tga_ramdac_rd); 871 else { 872 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 873 tga_bt463_rd); 874 } 875 } 876 dcp->dc_rinfo.ri_ops.pack_attr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 877 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 878 879 return(0); 880 } 881 882 /* 883 * Functions to blank and unblank the display. 884 */ 885 void 886 tga_burner(v, on, flags) 887 void *v; 888 u_int on, flags; 889 { 890 struct tga_softc *sc = v; 891 892 if (on) { 893 tga_unblank(sc->sc_dc); 894 } else { 895 tga_blank(sc->sc_dc); 896 } 897 } 898 899 void 900 tga_blank(dc) 901 struct tga_devconfig *dc; 902 { 903 904 if (!dc->dc_blanked) { 905 dc->dc_blanked = 1; 906 /* XXX */ 907 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 908 } 909 } 910 911 void 912 tga_unblank(dc) 913 struct tga_devconfig *dc; 914 { 915 916 if (dc->dc_blanked) { 917 dc->dc_blanked = 0; 918 /* XXX */ 919 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 920 } 921 } 922 923 /* 924 * Functions to manipulate the built-in cursor handing hardware. 925 */ 926 int 927 tga_builtin_set_cursor(dc, cursorp) 928 struct tga_devconfig *dc; 929 struct wsdisplay_cursor *cursorp; 930 { 931 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 932 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 933 u_int count, v; 934 int error; 935 936 v = cursorp->which; 937 if (v & WSDISPLAY_CURSOR_DOCMAP) { 938 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 939 if (error) 940 return (error); 941 } 942 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 943 if ((u_int)cursorp->size.x != 64 || 944 (u_int)cursorp->size.y > 64) 945 return (EINVAL); 946 } 947 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 948 return EINVAL; 949 950 /* parameters are OK; do it */ 951 if (v & WSDISPLAY_CURSOR_DOCUR) { 952 if (cursorp->enable) 953 /* XXX */ 954 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04); 955 else 956 /* XXX */ 957 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04); 958 } 959 if (v & WSDISPLAY_CURSOR_DOPOS) { 960 TGAWREG(dc, TGA_REG_CXYR, 961 ((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff)); 962 } 963 if (v & WSDISPLAY_CURSOR_DOCMAP) { 964 /* can't fail. */ 965 dcrf->ramdac_set_curcmap(dcrc, cursorp); 966 } 967 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 968 /* The cursor is 2 bits deep, and there is no mask */ 969 count = (cursorp->size.y * 64 * 2) / NBBY; 970 TGAWREG(dc, TGA_REG_CCBR, 971 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10)); 972 if ((error = copyin(cursorp->image,(char *)(dc->dc_vaddr + 973 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), count)) != 0) 974 return (error); 975 } 976 return (0); 977 } 978 979 int 980 tga_builtin_get_cursor(dc, cursorp) 981 struct tga_devconfig *dc; 982 struct wsdisplay_cursor *cursorp; 983 { 984 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 985 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 986 int error; 987 u_int count; 988 989 cursorp->which = WSDISPLAY_CURSOR_DOALL & 990 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 991 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 992 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 993 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 994 cursorp->size.x = 64; 995 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 996 997 if (cursorp->image != NULL) { 998 count = (cursorp->size.y * 64 * 2) / NBBY; 999 error = copyout((char *)(dc->dc_vaddr + 1000 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 1001 cursorp->image, count); 1002 if (error) 1003 return (error); 1004 /* No mask */ 1005 } 1006 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 1007 return (error); 1008 } 1009 1010 int 1011 tga_builtin_set_curpos(dc, curposp) 1012 struct tga_devconfig *dc; 1013 struct wsdisplay_curpos *curposp; 1014 { 1015 1016 TGAWREG(dc, TGA_REG_CXYR, 1017 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 1018 return (0); 1019 } 1020 1021 int 1022 tga_builtin_get_curpos(dc, curposp) 1023 struct tga_devconfig *dc; 1024 struct wsdisplay_curpos *curposp; 1025 { 1026 1027 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 1028 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 1029 return (0); 1030 } 1031 1032 int 1033 tga_builtin_get_curmax(dc, curposp) 1034 struct tga_devconfig *dc; 1035 struct wsdisplay_curpos *curposp; 1036 { 1037 1038 curposp->x = curposp->y = 64; 1039 return (0); 1040 } 1041 1042 /* 1043 * Copy columns (characters) in a row (line). 1044 */ 1045 int 1046 tga_copycols(id, row, srccol, dstcol, ncols) 1047 void *id; 1048 int row, srccol, dstcol, ncols; 1049 { 1050 struct rasops_info *ri = id; 1051 int y, srcx, dstx, nx; 1052 1053 y = ri->ri_font->fontheight * row; 1054 srcx = ri->ri_font->fontwidth * srccol; 1055 dstx = ri->ri_font->fontwidth * dstcol; 1056 nx = ri->ri_font->fontwidth * ncols; 1057 1058 tga_rop(ri, dstx, y, nx, ri->ri_font->fontheight, ri, srcx, y); 1059 1060 return 0; 1061 } 1062 1063 /* 1064 * Copy rows (lines). 1065 */ 1066 int 1067 tga_copyrows(id, srcrow, dstrow, nrows) 1068 void *id; 1069 int srcrow, dstrow, nrows; 1070 { 1071 struct rasops_info *ri = id; 1072 int srcy, dsty, ny; 1073 1074 srcy = ri->ri_font->fontheight * srcrow; 1075 dsty = ri->ri_font->fontheight * dstrow; 1076 ny = ri->ri_font->fontheight * nrows; 1077 1078 tga_rop(ri, 0, dsty, ri->ri_emuwidth, ny, ri, 0, srcy); 1079 1080 return 0; 1081 } 1082 1083 /* 1084 * Generic TGA raster op. 1085 * This covers all possible raster ops, and 1086 * clips the sizes and all of that. 1087 */ 1088 int 1089 tga_rop(dst, dx, dy, w, h, src, sx, sy) 1090 struct rasops_info *dst; 1091 int dx, dy, w, h; 1092 struct rasops_info *src; 1093 int sx, sy; 1094 { 1095 if (dst == NULL || src == NULL) 1096 return -1; 1097 1098 /* Clip against src */ 1099 if (sx < 0) { 1100 w += sx; 1101 sx = 0; 1102 } 1103 if (sy < 0) { 1104 h += sy; 1105 sy = 0; 1106 } 1107 if (sx + w > src->ri_emuwidth) 1108 w = src->ri_emuwidth - sx; 1109 if (sy + h > src->ri_emuheight) 1110 h = src->ri_emuheight - sy; 1111 1112 /* Clip against dst. We modify src regardless of using it, 1113 * since it really doesn't matter. 1114 */ 1115 if (dx < 0) { 1116 w += dx; 1117 sx -= dx; 1118 dx = 0; 1119 } 1120 if (dy < 0) { 1121 h += dy; 1122 sy -= dy; 1123 dy = 0; 1124 } 1125 if (dx + w > dst->ri_emuwidth) 1126 w = dst->ri_emuwidth - dx; 1127 if (dy + h > dst->ri_emuheight) 1128 h = dst->ri_emuheight - dy; 1129 if (w <= 0 || h <= 0) 1130 return 0; /* Vacuously true; */ 1131 1132 return tga_rop_vtov(dst, dx, dy, w, h, src, sx, sy); 1133 } 1134 1135 1136 1137 /* 1138 * Video to Video raster ops. 1139 * This function deals with all raster ops that have a src and dst 1140 * that are on the card. 1141 */ 1142 int 1143 tga_rop_vtov(dst, dx, dy, w, h, src, sx, sy) 1144 struct rasops_info *dst; 1145 int dx, dy, w, h; 1146 struct rasops_info *src; 1147 int sx, sy; 1148 { 1149 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 1150 int srcb, dstb, tga_srcb, tga_dstb; 1151 int x, y, wb; 1152 int xstart, xend, xdir; 1153 int ystart, yend, ydir, yinc; 1154 int xleft, lastx, lastleft; 1155 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1156 1157 /* 1158 * I don't yet want to deal with unaligned guys, really. And we don't 1159 * deal with copies from one card to another. 1160 */ 1161 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1162 /* XXX Punt! */ 1163 /* XXX should never happen, since it's only being used to 1164 * XXX copy 8-pixel-wide characters. 1165 */ 1166 return -1; 1167 } 1168 1169 wb = w * (dst->ri_depth / 8); 1170 if (sy >= dy) { 1171 ystart = 0; 1172 yend = h; 1173 ydir = 1; 1174 } else { 1175 ystart = h; 1176 yend = 0; 1177 ydir = -1; 1178 } 1179 if (sx >= dx) { /* moving to the left */ 1180 xstart = 0; 1181 xend = w * (dst->ri_depth / 8) - 4; 1182 xdir = 1; 1183 } else { /* moving to the right */ 1184 xstart = wb - ( wb >= 4*64 ? 4*64 : wb >= 64 ? 64 : 4 ); 1185 xend = 0; 1186 xdir = -1; 1187 } 1188 #define XINC4 4 1189 #define XINC64 64 1190 #define XINC256 (64*4) 1191 yinc = ydir * dst->ri_stride; 1192 ystart *= dst->ri_stride; 1193 yend *= dst->ri_stride; 1194 1195 srcb = sy * src->ri_stride + sx * (src->ri_depth/8); 1196 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); 1197 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1198 (sx + src->ri_xorigin) * (src->ri_depth/8); 1199 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1200 (dx + dst->ri_xorigin) * (dst->ri_depth/8); 1201 1202 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1203 TGAWALREG(dc, TGA_REG_GOPR, 3, 0x0003); /* SRC */ 1204 1205 /* 1206 * we have 3 sizes of pixels to move in X direction: 1207 * 4 * 64 (unrolled TGA ops) 1208 * 64 (single TGA op) 1209 * 4 (CPU, using long word) 1210 */ 1211 1212 if (xdir == 1) { /* move to the left */ 1213 1214 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1215 1216 /* 4*64 byte chunks */ 1217 for (xleft = wb, x = xstart; 1218 x <= xend && xleft >= 4*64; 1219 x += XINC256, xleft -= XINC256) { 1220 1221 /* XXX XXX Eight writes to different addresses should fill 1222 * XXX XXX up the write buffers on 21064 and 21164 chips, 1223 * XXX XXX but later CPUs might have larger write buffers which 1224 * XXX XXX require further unrolling of this loop, or the 1225 * XXX XXX insertion of memory barriers. 1226 */ 1227 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1228 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1229 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64); 1230 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64); 1231 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64); 1232 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64); 1233 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64); 1234 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64); 1235 } 1236 1237 /* 64 byte chunks */ 1238 for ( ; x <= xend && xleft >= 64; 1239 x += XINC64, xleft -= XINC64) { 1240 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1241 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1242 } 1243 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1244 1245 } 1246 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1247 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1248 1249 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1250 /* 4 byte granularity */ 1251 for (x = lastx, xleft = lastleft; 1252 x <= xend && xleft >= 4; 1253 x += XINC4, xleft -= XINC4) { 1254 *(uint32_t *)(dst->ri_bits + dstb + y + x) = 1255 *(uint32_t *)(dst->ri_bits + srcb + y + x); 1256 } 1257 } 1258 } 1259 else { /* above move to the left, below move to the right */ 1260 1261 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1262 1263 /* 4*64 byte chunks */ 1264 for (xleft = wb, x = xstart; 1265 x >= xend && xleft >= 4*64; 1266 x -= XINC256, xleft -= XINC256) { 1267 1268 /* XXX XXX Eight writes to different addresses should fill 1269 * XXX XXX up the write buffers on 21064 and 21164 chips, 1270 * XXX XXX but later CPUs might have larger write buffers which 1271 * XXX XXX require further unrolling of this loop, or the 1272 * XXX XXX insertion of memory barriers. 1273 */ 1274 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 3 * 64); 1275 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 3 * 64); 1276 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 2 * 64); 1277 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 2 * 64); 1278 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 1 * 64); 1279 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 1 * 64); 1280 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 0 * 64); 1281 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 0 * 64); 1282 } 1283 1284 if (xleft) x += XINC256 - XINC64; 1285 1286 /* 64 byte chunks */ 1287 for ( ; x >= xend && xleft >= 64; 1288 x -= XINC64, xleft -= XINC64) { 1289 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1290 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1291 } 1292 if (xleft) x += XINC64 - XINC4; 1293 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1294 } 1295 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1296 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1297 1298 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1299 /* 4 byte granularity */ 1300 for (x = lastx, xleft = lastleft; 1301 x >= xend && xleft >= 4; 1302 x -= XINC4, xleft -= XINC4) { 1303 *(uint32_t *)(dst->ri_bits + dstb + y + x) = 1304 *(uint32_t *)(dst->ri_bits + srcb + y + x); 1305 } 1306 } 1307 } 1308 return 0; 1309 } 1310 1311 1312 int 1313 tga_putchar(c, row, col, uc, attr) 1314 void *c; 1315 int row, col; 1316 u_int uc; 1317 uint32_t attr; 1318 { 1319 struct rasops_info *ri = c; 1320 struct tga_devconfig *dc = ri->ri_hw; 1321 int fs, height, width; 1322 int fg, bg, ul; 1323 u_char *fr; 1324 int32_t *rp; 1325 1326 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1327 1328 height = ri->ri_font->fontheight; 1329 width = ri->ri_font->fontwidth; 1330 1331 uc -= ri->ri_font->firstchar; 1332 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1333 fs = ri->ri_font->stride; 1334 1335 /* Set foreground and background color. XXX memoize this somehow? 1336 * The rasops code has already expanded the color entry to 32 bits 1337 * for us, even for 8-bit displays, so we don't have to do anything. 1338 */ 1339 ri->ri_ops.unpack_attr(c, attr, &fg, &bg, &ul); 1340 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[fg]); 1341 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[bg]); 1342 1343 /* Set raster operation to "copy"... */ 1344 if (ri->ri_depth == 8) 1345 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1346 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1347 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1348 1349 /* Set which pixels we're drawing (of a possible 32). */ 1350 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1351 1352 /* Set drawing mode to opaque stipple. */ 1353 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1354 1355 /* Insert write barrier before actually sending data */ 1356 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1357 TGAREGWB(dc, TGA_REG_GMOR, 1); 1358 1359 while (height--) { 1360 /* The actual stipple write */ 1361 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1362 1363 fr += fs; 1364 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1365 } 1366 1367 /* Do underline */ 1368 if (ul) { 1369 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1)); 1370 *rp = 0xffffffff; 1371 } 1372 1373 /* Set graphics mode back to normal. */ 1374 TGAWREG(dc, TGA_REG_GMOR, 0); 1375 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1376 1377 return 0; 1378 } 1379 1380 int 1381 tga_eraserows(c, row, num, attr) 1382 void *c; 1383 int row, num; 1384 uint32_t attr; 1385 { 1386 struct rasops_info *ri = c; 1387 struct tga_devconfig *dc = ri->ri_hw; 1388 int32_t color, lines, pixels; 1389 int fg, bg; 1390 int32_t *rp; 1391 1392 ri->ri_ops.unpack_attr(c, attr, &fg, &bg, NULL); 1393 color = ri->ri_devcmap[bg]; 1394 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1395 lines = num * ri->ri_font->fontheight; 1396 pixels = ri->ri_emuwidth - 1; 1397 1398 /* Set fill color in block-color registers */ 1399 TGAWREG(dc, TGA_REG_GBCR0, color); 1400 TGAWREG(dc, TGA_REG_GBCR1, color); 1401 if (ri->ri_depth != 8) { 1402 TGAWREG(dc, TGA_REG_GBCR2, color); 1403 TGAWREG(dc, TGA_REG_GBCR3, color); 1404 TGAWREG(dc, TGA_REG_GBCR4, color); 1405 TGAWREG(dc, TGA_REG_GBCR5, color); 1406 TGAWREG(dc, TGA_REG_GBCR6, color); 1407 TGAWREG(dc, TGA_REG_GBCR7, color); 1408 } 1409 1410 /* Set raster operation to "copy"... */ 1411 if (ri->ri_depth == 8) 1412 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1413 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1414 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1415 1416 /* Set which pixels we're drawing (of a possible 32). */ 1417 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1418 1419 /* Set drawing mode to block fill. */ 1420 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1421 1422 /* Insert write barrier before actually sending data */ 1423 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1424 TGAREGWB(dc, TGA_REG_GMOR, 1); 1425 1426 while (lines--) { 1427 *rp = pixels; 1428 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1429 } 1430 1431 /* Set graphics mode back to normal. */ 1432 TGAWREG(dc, TGA_REG_GMOR, 0); 1433 1434 return 0; 1435 } 1436 1437 int 1438 tga_erasecols (c, row, col, num, attr) 1439 void *c; 1440 int row, col, num; 1441 uint32_t attr; 1442 { 1443 struct rasops_info *ri = c; 1444 struct tga_devconfig *dc = ri->ri_hw; 1445 int32_t color, lines, pixels; 1446 int fg, bg; 1447 int32_t *rp; 1448 1449 ri->ri_ops.unpack_attr(c, attr, &fg, &bg, NULL); 1450 color = ri->ri_devcmap[bg]; 1451 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1452 lines = ri->ri_font->fontheight; 1453 pixels = (num * ri->ri_font->fontwidth) - 1; 1454 1455 /* Set fill color in block-color registers */ 1456 TGAWREG(dc, TGA_REG_GBCR0, color); 1457 TGAWREG(dc, TGA_REG_GBCR1, color); 1458 if (ri->ri_depth != 8) { 1459 TGAWREG(dc, TGA_REG_GBCR2, color); 1460 TGAWREG(dc, TGA_REG_GBCR3, color); 1461 TGAWREG(dc, TGA_REG_GBCR4, color); 1462 TGAWREG(dc, TGA_REG_GBCR5, color); 1463 TGAWREG(dc, TGA_REG_GBCR6, color); 1464 TGAWREG(dc, TGA_REG_GBCR7, color); 1465 } 1466 1467 /* Set raster operation to "copy"... */ 1468 if (ri->ri_depth == 8) 1469 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1470 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1471 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1472 1473 /* Set which pixels we're drawing (of a possible 32). */ 1474 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1475 1476 /* Set drawing mode to block fill. */ 1477 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1478 1479 /* Insert write barrier before actually sending data */ 1480 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1481 TGAREGWB(dc, TGA_REG_GMOR, 1); 1482 1483 while (lines--) { 1484 *rp = pixels; 1485 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1486 } 1487 1488 /* Set graphics mode back to normal. */ 1489 TGAWREG(dc, TGA_REG_GMOR, 0); 1490 1491 return 0; 1492 } 1493 1494 1495 void 1496 tga_ramdac_wr(v, btreg, val) 1497 void *v; 1498 u_int btreg; 1499 u_int8_t val; 1500 { 1501 struct tga_devconfig *dc = v; 1502 1503 if (btreg > BT485_REG_MAX) 1504 panic("tga_ramdac_wr: reg %d out of range", btreg); 1505 1506 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1507 TGAREGWB(dc, TGA_REG_EPDR, 1); 1508 } 1509 1510 void 1511 tga2_ramdac_wr(v, btreg, val) 1512 void *v; 1513 u_int btreg; 1514 u_int8_t val; 1515 { 1516 struct tga_devconfig *dc = v; 1517 bus_space_handle_t ramdac; 1518 1519 if (btreg > BT485_REG_MAX) 1520 panic("tga_ramdac_wr: reg %d out of range", btreg); 1521 1522 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1523 (0xe << 12) + (btreg << 8), 4, &ramdac); 1524 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1525 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1526 } 1527 1528 u_int8_t 1529 tga_bt463_rd(v, btreg) 1530 void *v; 1531 u_int btreg; 1532 { 1533 struct tga_devconfig *dc = v; 1534 tga_reg_t rdval; 1535 1536 /* 1537 * Strobe CE# (high->low->high) since status and data are latched on 1538 * the falling and rising edges (respectively) of this active-low signal. 1539 */ 1540 1541 TGAREGWB(dc, TGA_REG_EPSR, 1); 1542 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1543 TGAREGWB(dc, TGA_REG_EPSR, 1); 1544 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1545 1546 TGAREGRB(dc, TGA_REG_EPSR, 1); 1547 1548 rdval = TGARREG(dc, TGA_REG_EPDR); 1549 TGAREGWB(dc, TGA_REG_EPSR, 1); 1550 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1551 1552 return (rdval >> 16) & 0xff; 1553 } 1554 1555 void 1556 tga_bt463_wr(v, btreg, val) 1557 void *v; 1558 u_int btreg; 1559 u_int8_t val; 1560 { 1561 struct tga_devconfig *dc = v; 1562 1563 /* 1564 * In spite of the 21030 documentation, to set the MPU bus bits for 1565 * a write, you set them in the upper bits of EPDR, not EPSR. 1566 */ 1567 1568 /* 1569 * Strobe CE# (high->low->high) since status and data are latched on 1570 * the falling and rising edges of this active-low signal. 1571 */ 1572 1573 TGAREGWB(dc, TGA_REG_EPDR, 1); 1574 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1575 TGAREGWB(dc, TGA_REG_EPDR, 1); 1576 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1577 TGAREGWB(dc, TGA_REG_EPDR, 1); 1578 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1579 1580 } 1581 1582 u_int8_t 1583 tga_ramdac_rd(v, btreg) 1584 void *v; 1585 u_int btreg; 1586 { 1587 struct tga_devconfig *dc = v; 1588 tga_reg_t rdval; 1589 1590 if (btreg > BT485_REG_MAX) 1591 panic("tga_ramdac_rd: reg %d out of range", btreg); 1592 1593 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1594 TGAREGWB(dc, TGA_REG_EPSR, 1); 1595 1596 rdval = TGARREG(dc, TGA_REG_EPDR); 1597 return (rdval >> 16) & 0xff; /* XXX */ 1598 } 1599 1600 u_int8_t 1601 tga2_ramdac_rd(v, btreg) 1602 void *v; 1603 u_int btreg; 1604 { 1605 struct tga_devconfig *dc = v; 1606 bus_space_handle_t ramdac; 1607 u_int8_t retval; 1608 1609 if (btreg > BT485_REG_MAX) 1610 panic("tga_ramdac_rd: reg %d out of range", btreg); 1611 1612 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1613 (0xe << 12) + (btreg << 8), 4, &ramdac); 1614 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1615 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1616 return retval; 1617 } 1618 1619 #include <dev/ic/decmonitors.c> 1620 void tga2_ics9110_wr( 1621 struct tga_devconfig *dc, 1622 int dotclock 1623 ); 1624 1625 struct monitor *tga_getmonitor(struct tga_devconfig *dc); 1626 1627 void 1628 tga2_init(dc) 1629 struct tga_devconfig *dc; 1630 { 1631 struct monitor *m = tga_getmonitor(dc); 1632 1633 1634 /* Deal with the dot clocks. 1635 */ 1636 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1637 /* Set this up as a reference clock for the 1638 * ibm561's PLL. 1639 */ 1640 tga2_ics9110_wr(dc, 14300000); 1641 /* XXX Can't set up the dotclock properly, until such time 1642 * as the RAMDAC is configured. 1643 */ 1644 } else { 1645 /* otherwise the ics9110 is our clock. */ 1646 tga2_ics9110_wr(dc, m->dotclock); 1647 } 1648 #if 0 1649 TGAWREG(dc, TGA_REG_VHCR, 1650 ((m->hbp / 4) << 21) | 1651 ((m->hsync / 4) << 14) | 1652 (((m->hfp - 4) / 4) << 9) | 1653 ((m->cols + 4) / 4)); 1654 #else 1655 TGAWREG(dc, TGA_REG_VHCR, 1656 ((m->hbp / 4) << 21) | 1657 ((m->hsync / 4) << 14) | 1658 (((m->hfp) / 4) << 9) | 1659 ((m->cols) / 4)); 1660 #endif 1661 TGAWREG(dc, TGA_REG_VVCR, 1662 (m->vbp << 22) | 1663 (m->vsync << 16) | 1664 (m->vfp << 11) | 1665 (m->rows)); 1666 TGAWREG(dc, TGA_REG_VVBR, 1); 1667 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1668 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1669 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1670 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1671 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1672 } 1673 1674 void 1675 tga2_ics9110_wr(dc, dotclock) 1676 struct tga_devconfig *dc; 1677 int dotclock; 1678 { 1679 bus_space_handle_t clock; 1680 u_int32_t valU; 1681 int N, M, R, V, X; 1682 int i; 1683 1684 switch (dotclock) { 1685 case 130808000: 1686 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1687 case 119840000: 1688 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1689 case 108180000: 1690 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1691 case 103994000: 1692 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1693 case 175000000: 1694 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1695 case 75000000: 1696 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1697 case 74000000: 1698 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1699 case 69000000: 1700 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1701 case 65000000: 1702 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1703 case 50000000: 1704 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1705 case 40000000: 1706 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1707 case 31500000: 1708 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1709 case 25175000: 1710 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1711 case 135000000: 1712 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1713 case 110000000: 1714 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1715 case 202500000: 1716 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1717 case 14300000: /* this one is just a ref clock */ 1718 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1719 default: 1720 panic("unrecognized clock rate %d", dotclock); 1721 } 1722 1723 /* XXX -- hard coded, bad */ 1724 valU = N | ( M << 7 ) | (V << 14); 1725 valU |= (X << 15) | (R << 17); 1726 valU |= 0x17 << 19; 1727 1728 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1729 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1730 1731 for (i = 24; i > 0; i--) { 1732 u_int32_t writeval; 1733 1734 writeval = valU & 0x1; 1735 if (i == 1) 1736 writeval |= 0x2; 1737 valU >>= 1; 1738 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1739 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1740 } 1741 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1742 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1743 &clock); /* XXX */ 1744 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1745 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1746 } 1747 1748 struct monitor * 1749 tga_getmonitor(dc) 1750 struct tga_devconfig *dc; 1751 { 1752 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1753 } 1754 1755 unsigned 1756 tga_getdotclock(dc) 1757 struct tga_devconfig *dc; 1758 { 1759 return tga_getmonitor(dc)->dotclock; 1760 } 1761