1 /* $OpenBSD: siop_pci_common.c,v 1.12 2003/10/09 17:41:00 mickey Exp $ */ 2 /* $NetBSD: siop_pci_common.c,v 1.17 2002/05/04 18:11:06 bouyer Exp $ */ 3 4 /* 5 * Copyright (c) 2000 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 42 #include <machine/endian.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #include <scsi/scsi_all.h> 49 #include <scsi/scsiconf.h> 50 51 #include <dev/ic/siopreg.h> 52 #include <dev/ic/siopvar_common.h> 53 #include <dev/pci/siop_pci_common.h> 54 55 /* List (array, really :) of chips we know how to handle */ 56 const struct siop_product_desc siop_products[] = { 57 { PCI_PRODUCT_SYMBIOS_810, 58 0x00, 59 SF_PCI_RL | SF_CHIP_LS, 60 4, 8, 3, 250, 0 61 }, 62 { PCI_PRODUCT_SYMBIOS_810, 63 0x10, 64 SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS, 65 4, 8, 3, 250, 0 66 }, 67 { PCI_PRODUCT_SYMBIOS_815, 68 0x00, 69 SF_PCI_RL | SF_PCI_BOF, 70 4, 8, 3, 250, 0 71 }, 72 { PCI_PRODUCT_SYMBIOS_820, 73 0x00, 74 SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE, 75 4, 8, 3, 250, 0 76 }, 77 { PCI_PRODUCT_SYMBIOS_825, 78 0x00, 79 SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE, 80 4, 8, 3, 250, 0 81 }, 82 { PCI_PRODUCT_SYMBIOS_825, 83 0x10, 84 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 85 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 86 SF_BUS_WIDE, 87 7, 8, 3, 250, 4096 88 }, 89 { PCI_PRODUCT_SYMBIOS_860, 90 0x00, 91 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 92 SF_CHIP_PF | SF_CHIP_LS | 93 SF_BUS_ULTRA, 94 4, 8, 5, 125, 0 95 }, 96 { PCI_PRODUCT_SYMBIOS_875, 97 0x00, 98 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 99 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 100 SF_BUS_ULTRA | SF_BUS_WIDE, 101 7, 16, 5, 125, 4096 102 }, 103 { PCI_PRODUCT_SYMBIOS_875, 104 0x02, 105 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 106 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 107 SF_CHIP_LS | SF_CHIP_10REGS | 108 SF_BUS_ULTRA | SF_BUS_WIDE, 109 7, 16, 5, 125, 4096 110 }, 111 { PCI_PRODUCT_SYMBIOS_875J, 112 0x00, 113 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 114 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 115 SF_CHIP_LS | SF_CHIP_10REGS | 116 SF_BUS_ULTRA | SF_BUS_WIDE, 117 7, 16, 5, 125, 4096 118 }, 119 { PCI_PRODUCT_SYMBIOS_885, 120 0x00, 121 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 122 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 123 SF_CHIP_LS | SF_CHIP_10REGS | 124 SF_BUS_ULTRA | SF_BUS_WIDE, 125 7, 16, 5, 125, 4096 126 }, 127 { PCI_PRODUCT_SYMBIOS_895, 128 0x00, 129 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 130 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 131 SF_CHIP_LS | SF_CHIP_10REGS | 132 SF_BUS_ULTRA2 | SF_BUS_WIDE, 133 7, 31, 7, 62, 4096 134 }, 135 { PCI_PRODUCT_SYMBIOS_896, 136 0x00, 137 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 138 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 139 SF_CHIP_LS | SF_CHIP_10REGS | 140 SF_BUS_ULTRA2 | SF_BUS_WIDE, 141 7, 31, 7, 62, 8192 142 }, 143 { PCI_PRODUCT_SYMBIOS_895A, 144 0x00, 145 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 146 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 147 SF_CHIP_LS | SF_CHIP_10REGS | 148 SF_BUS_ULTRA2 | SF_BUS_WIDE, 149 7, 31, 7, 62, 8192 150 }, 151 { PCI_PRODUCT_SYMBIOS_1010, 152 0x00, 153 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 154 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 155 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | 156 SF_CHIP_GEBUG | 157 SF_BUS_ULTRA3 | SF_BUS_WIDE, 158 7, 31, 0, 62, 8192 159 }, 160 { PCI_PRODUCT_SYMBIOS_1010, 161 0x01, 162 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 163 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 164 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT | 165 SF_CHIP_GEBUG | 166 SF_BUS_ULTRA3 | SF_BUS_WIDE, 167 7, 62, 0, 62, 8192 168 }, 169 { PCI_PRODUCT_SYMBIOS_1010_2, 170 0x00, 171 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 172 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 173 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT | 174 SF_BUS_ULTRA3 | SF_BUS_WIDE, 175 7, 62, 0, 62, 8192 176 }, 177 { PCI_PRODUCT_SYMBIOS_1510D, 178 0x00, 179 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 180 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 181 SF_CHIP_LS | SF_CHIP_10REGS | 182 SF_BUS_ULTRA2 | SF_BUS_WIDE, 183 7, 31, 7, 62, 4096 184 }, 185 { 0, 186 0x00, 187 0x00, 188 0, 0, 0, 0, 0 189 }, 190 }; 191 192 const struct siop_product_desc * 193 siop_lookup_product(id, rev) 194 u_int32_t id; 195 int rev; 196 { 197 const struct siop_product_desc *pp; 198 const struct siop_product_desc *rp = NULL; 199 200 if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS) 201 return NULL; 202 203 for (pp = siop_products; pp->product != 0; pp++) { 204 if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev) 205 if (rp == NULL || pp->revision > rp->revision) 206 rp = pp; 207 } 208 return rp; 209 } 210 211 int 212 siop_pci_attach_common(pci_sc, siop_sc, pa, intr) 213 struct siop_pci_common_softc *pci_sc; 214 struct siop_common_softc *siop_sc; 215 struct pci_attach_args *pa; 216 int (*intr) (void*); 217 { 218 pci_chipset_tag_t pc = pa->pa_pc; 219 pcitag_t tag = pa->pa_tag; 220 const char *intrstr; 221 pci_intr_handle_t intrhandle; 222 bus_space_tag_t iot, memt; 223 bus_space_handle_t ioh, memh; 224 pcireg_t memtype; 225 int memh_valid, ioh_valid; 226 bus_addr_t ioaddr, memaddr; 227 bus_size_t memsize, iosize; 228 229 pci_sc->sc_pp = 230 siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class)); 231 if (pci_sc->sc_pp == NULL) { 232 printf(": broken match/attach!\n"); 233 return 0; 234 } 235 /* copy interesting infos about the chip */ 236 siop_sc->features = pci_sc->sc_pp->features; 237 #ifdef __hppa__ 238 /* XXX On board ram doesn't work (yet?) on hppa. */ 239 siop_sc->features &= ~SF_CHIP_RAM; 240 #endif 241 #ifdef SIOP_SYMLED /* XXX Should be a devprop! */ 242 siop_sc->features |= SF_CHIP_LED0; 243 #endif 244 siop_sc->maxburst = pci_sc->sc_pp->maxburst; 245 siop_sc->maxoff = pci_sc->sc_pp->maxoff; 246 siop_sc->clock_div = pci_sc->sc_pp->clock_div; 247 siop_sc->clock_period = pci_sc->sc_pp->clock_period; 248 siop_sc->ram_size = pci_sc->sc_pp->ram_size; 249 250 siop_sc->sc_reset = siop_pci_reset; 251 pci_sc->sc_pc = pc; 252 pci_sc->sc_tag = tag; 253 siop_sc->sc_dmat = pa->pa_dmat; 254 255 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14); 256 switch (memtype) { 257 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 258 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 259 memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0, 260 &memt, &memh, &memaddr, NULL, 0) == 0); 261 break; 262 default: 263 memh_valid = 0; 264 } 265 266 ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, 267 &iot, &ioh, &ioaddr, &iosize, 0) == 0); 268 269 if (memh_valid) { 270 siop_sc->sc_rt = memt; 271 siop_sc->sc_rh = memh; 272 siop_sc->sc_raddr = memaddr; 273 } else if (ioh_valid) { 274 siop_sc->sc_rt = iot; 275 siop_sc->sc_rh = ioh; 276 siop_sc->sc_raddr = ioaddr; 277 } else { 278 printf(": unable to map device registers\n"); 279 return 0; 280 } 281 282 if (pci_intr_map(pa, &intrhandle) != 0) { 283 printf(": couldn't map interrupt\n"); 284 bus_space_unmap(siop_sc->sc_rt, siop_sc->sc_rh, iosize); 285 return 0; 286 } 287 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 288 pci_sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 289 intr, siop_sc, siop_sc->sc_dev.dv_xname); 290 if (pci_sc->sc_ih != NULL) { 291 printf(": %s", 292 intrstr ? intrstr : "?"); 293 } else { 294 printf(": couldn't establish interrupt"); 295 if (intrstr != NULL) 296 printf(" at %s", intrstr); 297 printf("\n"); 298 bus_space_unmap(siop_sc->sc_rt, siop_sc->sc_rh, iosize); 299 return 0; 300 } 301 302 if (siop_sc->features & SF_CHIP_RAM) { 303 int bar; 304 switch (memtype) { 305 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 306 bar = 0x18; 307 break; 308 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 309 bar = 0x1c; 310 break; 311 } 312 if (pci_mapreg_map(pa, bar, memtype, 0, 313 &siop_sc->sc_ramt, &siop_sc->sc_ramh, 314 &siop_sc->sc_scriptaddr, &memsize, 0) == 0) { 315 printf(", using %dK of on-board RAM", memsize / 1024); 316 } else { 317 printf(", can't map on-board RAM"); 318 siop_sc->features &= ~SF_CHIP_RAM; 319 } 320 } 321 322 printf("\n"); 323 324 return 1; 325 } 326 327 void 328 siop_pci_reset(sc) 329 struct siop_common_softc *sc; 330 { 331 int dmode; 332 333 dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE); 334 if (sc->features & SF_PCI_RL) 335 dmode |= DMODE_ERL; 336 if (sc->features & SF_PCI_RM) 337 dmode |= DMODE_ERMP; 338 if (sc->features & SF_PCI_BOF) 339 dmode |= DMODE_BOF; 340 if (sc->features & SF_PCI_CLS) 341 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 342 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) | 343 DCNTL_CLSE); 344 if (sc->features & SF_PCI_WRI) 345 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 346 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 347 CTEST3_WRIE); 348 if (sc->maxburst) { 349 int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh, 350 SIOP_CTEST5); 351 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 352 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) & 353 ~CTEST4_BDIS); 354 dmode &= ~DMODE_BL_MASK; 355 dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK; 356 ctest5 &= ~CTEST5_BBCK; 357 ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK; 358 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5); 359 } else { 360 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 361 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) | 362 CTEST4_BDIS); 363 } 364 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode); 365 } 366