1 /* $OpenBSD: ppb.c,v 1.65 2015/12/01 21:02:04 kettenis Exp $ */ 2 /* $NetBSD: ppb.c,v 1.16 1997/06/06 23:48:05 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Christopher G. Demetriou 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/task.h> 38 #include <sys/timeout.h> 39 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcidevs.h> 43 #include <dev/pci/ppbreg.h> 44 45 #ifndef PCI_IO_START 46 #define PCI_IO_START 0 47 #endif 48 49 #ifndef PCI_IO_END 50 #define PCI_IO_END 0xffffffff 51 #endif 52 53 #ifndef PCI_MEM_START 54 #define PCI_MEM_START 0 55 #endif 56 57 #ifndef PCI_MEM_END 58 #define PCI_MEM_END 0xffffffff 59 #endif 60 61 #define PPB_EXNAMLEN 32 62 63 struct ppb_softc { 64 struct device sc_dev; /* generic device glue */ 65 pci_chipset_tag_t sc_pc; /* our PCI chipset... */ 66 pcitag_t sc_tag; /* ...and tag. */ 67 pci_intr_handle_t sc_ih[4]; 68 void *sc_intrhand; 69 struct extent *sc_busex; 70 struct extent *sc_ioex; 71 struct extent *sc_memex; 72 struct extent *sc_pmemex; 73 struct device *sc_psc; 74 int sc_cap_off; 75 struct task sc_insert_task; 76 struct task sc_rescan_task; 77 struct task sc_remove_task; 78 struct timeout sc_to; 79 80 bus_addr_t sc_iobase, sc_iolimit; 81 bus_addr_t sc_membase, sc_memlimit; 82 bus_addr_t sc_pmembase, sc_pmemlimit; 83 84 pcireg_t sc_csr; 85 pcireg_t sc_bhlcr; 86 pcireg_t sc_bir; 87 pcireg_t sc_bcr; 88 pcireg_t sc_int; 89 pcireg_t sc_slcsr; 90 pcireg_t sc_msi_mc; 91 pcireg_t sc_msi_ma; 92 pcireg_t sc_msi_mau32; 93 pcireg_t sc_msi_md; 94 int sc_pmcsr_state; 95 }; 96 97 int ppbmatch(struct device *, void *, void *); 98 void ppbattach(struct device *, struct device *, void *); 99 int ppbdetach(struct device *self, int flags); 100 int ppbactivate(struct device *self, int act); 101 102 struct cfattach ppb_ca = { 103 sizeof(struct ppb_softc), ppbmatch, ppbattach, ppbdetach, ppbactivate 104 }; 105 106 struct cfdriver ppb_cd = { 107 NULL, "ppb", DV_DULL 108 }; 109 110 void ppb_alloc_busrange(struct ppb_softc *, struct pci_attach_args *, 111 pcireg_t *); 112 void ppb_alloc_resources(struct ppb_softc *, struct pci_attach_args *); 113 int ppb_intr(void *); 114 void ppb_hotplug_insert(void *); 115 void ppb_hotplug_insert_finish(void *); 116 int ppb_hotplug_fixup(struct pci_attach_args *); 117 int ppb_hotplug_fixup_type0(pci_chipset_tag_t, pcitag_t, pcitag_t); 118 int ppb_hotplug_fixup_type1(pci_chipset_tag_t, pcitag_t, pcitag_t); 119 void ppb_hotplug_rescan(void *); 120 void ppb_hotplug_remove(void *); 121 int ppbprint(void *, const char *pnp); 122 123 int 124 ppbmatch(struct device *parent, void *match, void *aux) 125 { 126 struct pci_attach_args *pa = aux; 127 128 /* 129 * This device is mislabeled. It is not a PCI bridge. 130 */ 131 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH && 132 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT82C586_PWR) 133 return (0); 134 /* 135 * Check the ID register to see that it's a PCI bridge. 136 * If it is, we assume that we can deal with it; it _should_ 137 * work in a standardized way... 138 */ 139 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 140 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_PCI) 141 return (1); 142 143 return (0); 144 } 145 146 void 147 ppbattach(struct device *parent, struct device *self, void *aux) 148 { 149 struct ppb_softc *sc = (struct ppb_softc *)self; 150 struct pci_attach_args *pa = aux; 151 pci_chipset_tag_t pc = pa->pa_pc; 152 struct pcibus_attach_args pba; 153 pci_interface_t interface; 154 pci_intr_handle_t ih; 155 pcireg_t busdata, reg, blr; 156 char *name; 157 int sec, sub; 158 int pin; 159 160 sc->sc_pc = pc; 161 sc->sc_tag = pa->pa_tag; 162 163 busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO); 164 165 /* 166 * When the bus number isn't configured, try to allocate one 167 * ourselves. 168 */ 169 if (busdata == 0 && pa->pa_busex) 170 ppb_alloc_busrange(sc, pa, &busdata); 171 172 /* 173 * When the bus number still isn't set correctly, give up. 174 */ 175 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 176 printf(": not configured by system firmware\n"); 177 return; 178 } 179 180 #if 0 181 /* 182 * XXX can't do this, because we're not given our bus number 183 * (we shouldn't need it), and because we've no way to 184 * decompose our tag. 185 */ 186 /* sanity check. */ 187 if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata)) 188 panic("ppbattach: bus in tag (%d) != bus in reg (%d)", 189 pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata)); 190 #endif 191 192 sec = PPB_BUSINFO_SECONDARY(busdata); 193 sub = PPB_BUSINFO_SUBORDINATE(busdata); 194 if (sub > sec) { 195 name = malloc(PPB_EXNAMLEN, M_DEVBUF, M_NOWAIT); 196 if (name) { 197 snprintf(name, PPB_EXNAMLEN, "%s pcibus", sc->sc_dev.dv_xname); 198 sc->sc_busex = extent_create(name, 0, 0xff, 199 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 200 extent_free(sc->sc_busex, sec + 1, 201 sub - sec, EX_NOWAIT); 202 } 203 } 204 205 /* Check for PCI Express capabilities and setup hotplug support. */ 206 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 207 &sc->sc_cap_off, ®) && (reg & PCI_PCIE_XCAP_SI)) { 208 task_set(&sc->sc_insert_task, ppb_hotplug_insert, sc); 209 task_set(&sc->sc_rescan_task, ppb_hotplug_rescan, sc); 210 task_set(&sc->sc_remove_task, ppb_hotplug_remove, sc); 211 timeout_set(&sc->sc_to, ppb_hotplug_insert_finish, sc); 212 213 #ifdef __i386__ 214 if (pci_intr_map(pa, &ih) == 0) 215 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_BIO, 216 ppb_intr, sc, self->dv_xname); 217 #else 218 if (pci_intr_map_msi(pa, &ih) == 0 || 219 pci_intr_map(pa, &ih) == 0) 220 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_BIO, 221 ppb_intr, sc, self->dv_xname); 222 #endif 223 224 if (sc->sc_intrhand) { 225 printf(": %s", pci_intr_string(pc, ih)); 226 227 /* Enable hotplug interrupt. */ 228 reg = pci_conf_read(pc, pa->pa_tag, 229 sc->sc_cap_off + PCI_PCIE_SLCSR); 230 reg |= (PCI_PCIE_SLCSR_HPE | PCI_PCIE_SLCSR_PDE); 231 pci_conf_write(pc, pa->pa_tag, 232 sc->sc_cap_off + PCI_PCIE_SLCSR, reg); 233 } 234 } 235 236 printf("\n"); 237 238 interface = PCI_INTERFACE(pa->pa_class); 239 240 /* 241 * The Intel 82801BAM Hub-to-PCI can decode subtractively but 242 * doesn't advertise itself as such. 243 */ 244 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 245 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BA_HPB || 246 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BAM_HPB)) 247 interface = PPB_INTERFACE_SUBTRACTIVE; 248 249 if (interface != PPB_INTERFACE_SUBTRACTIVE) 250 ppb_alloc_resources(sc, pa); 251 252 for (pin = PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_D; pin++) { 253 pa->pa_intrpin = pa->pa_rawintrpin = pin; 254 pa->pa_intrline = 0; 255 pci_intr_map(pa, &sc->sc_ih[pin - PCI_INTERRUPT_PIN_A]); 256 } 257 258 /* 259 * The UltraSPARC-IIi APB doesn't implement the standard 260 * address range registers. 261 */ 262 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 263 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_SIMBA) 264 goto attach; 265 266 /* Figure out the I/O address range of the bridge. */ 267 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_IOSTATUS); 268 sc->sc_iobase = (blr & 0x000000f0) << 8; 269 sc->sc_iolimit = (blr & 0x000f000) | 0x00000fff; 270 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_IO_HI); 271 sc->sc_iobase |= (blr & 0x0000ffff) << 16; 272 sc->sc_iolimit |= (blr & 0xffff0000); 273 if (sc->sc_iolimit > sc->sc_iobase) { 274 name = malloc(PPB_EXNAMLEN, M_DEVBUF, M_NOWAIT); 275 if (name) { 276 snprintf(name, PPB_EXNAMLEN, "%s pciio", sc->sc_dev.dv_xname); 277 sc->sc_ioex = extent_create(name, 0, 0xffffffff, 278 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 279 extent_free(sc->sc_ioex, sc->sc_iobase, 280 sc->sc_iolimit - sc->sc_iobase + 1, EX_NOWAIT); 281 } 282 } 283 284 /* Figure out the memory mapped I/O address range of the bridge. */ 285 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_MEM); 286 sc->sc_membase = (blr & 0x0000fff0) << 16; 287 sc->sc_memlimit = (blr & 0xfff00000) | 0x000fffff; 288 if (sc->sc_memlimit > sc->sc_membase) { 289 name = malloc(PPB_EXNAMLEN, M_DEVBUF, M_NOWAIT); 290 if (name) { 291 snprintf(name, PPB_EXNAMLEN, "%s pcimem", sc->sc_dev.dv_xname); 292 sc->sc_memex = extent_create(name, 0, (u_long)-1L, 293 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 294 extent_free(sc->sc_memex, sc->sc_membase, 295 sc->sc_memlimit - sc->sc_membase + 1, 296 EX_NOWAIT); 297 } 298 } 299 300 /* Figure out the prefetchable MMI/O address range of the bridge. */ 301 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFMEM); 302 sc->sc_pmembase = (blr & 0x0000fff0) << 16; 303 sc->sc_pmemlimit = (blr & 0xfff00000) | 0x000fffff; 304 #ifdef __LP64__ 305 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFBASE_HI32); 306 sc->sc_pmembase |= ((uint64_t)blr) << 32; 307 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFLIM_HI32); 308 sc->sc_pmemlimit |= ((uint64_t)blr) << 32; 309 #endif 310 if (sc->sc_pmemlimit > sc->sc_pmembase) { 311 name = malloc(PPB_EXNAMLEN, M_DEVBUF, M_NOWAIT); 312 if (name) { 313 snprintf(name, PPB_EXNAMLEN, "%s pcipmem", sc->sc_dev.dv_xname); 314 sc->sc_pmemex = extent_create(name, 0, (u_long)-1L, 315 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 316 extent_free(sc->sc_pmemex, sc->sc_pmembase, 317 sc->sc_pmemlimit - sc->sc_pmembase + 1, 318 EX_NOWAIT); 319 } 320 } 321 322 if (interface == PPB_INTERFACE_SUBTRACTIVE) { 323 if (sc->sc_ioex == NULL) 324 sc->sc_ioex = pa->pa_ioex; 325 if (sc->sc_memex == NULL) 326 sc->sc_memex = pa->pa_memex; 327 } 328 329 attach: 330 /* 331 * Attach the PCI bus that hangs off of it. 332 * 333 * XXX Don't pass-through Memory Read Multiple. Should we? 334 * XXX Consult the spec... 335 */ 336 bzero(&pba, sizeof(pba)); 337 pba.pba_busname = "pci"; 338 pba.pba_iot = pa->pa_iot; 339 pba.pba_memt = pa->pa_memt; 340 pba.pba_dmat = pa->pa_dmat; 341 pba.pba_pc = pc; 342 pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY; 343 pba.pba_busex = sc->sc_busex; 344 pba.pba_ioex = sc->sc_ioex; 345 pba.pba_memex = sc->sc_memex; 346 pba.pba_pmemex = sc->sc_pmemex; 347 pba.pba_domain = pa->pa_domain; 348 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 349 pba.pba_bridgeih = sc->sc_ih; 350 pba.pba_bridgetag = &sc->sc_tag; 351 pba.pba_intrswiz = pa->pa_intrswiz; 352 pba.pba_intrtag = pa->pa_intrtag; 353 354 sc->sc_psc = config_found(self, &pba, ppbprint); 355 } 356 357 int 358 ppbdetach(struct device *self, int flags) 359 { 360 struct ppb_softc *sc = (struct ppb_softc *)self; 361 char *name; 362 int rv; 363 364 if (sc->sc_intrhand) 365 pci_intr_disestablish(sc->sc_pc, sc->sc_intrhand); 366 367 rv = config_detach_children(self, flags); 368 369 if (sc->sc_busex) { 370 name = sc->sc_busex->ex_name; 371 extent_destroy(sc->sc_busex); 372 free(name, M_DEVBUF, PPB_EXNAMLEN); 373 } 374 375 if (sc->sc_ioex) { 376 name = sc->sc_ioex->ex_name; 377 extent_destroy(sc->sc_ioex); 378 free(name, M_DEVBUF, PPB_EXNAMLEN); 379 } 380 381 if (sc->sc_memex) { 382 name = sc->sc_memex->ex_name; 383 extent_destroy(sc->sc_memex); 384 free(name, M_DEVBUF, PPB_EXNAMLEN); 385 } 386 387 if (sc->sc_pmemex) { 388 name = sc->sc_pmemex->ex_name; 389 extent_destroy(sc->sc_pmemex); 390 free(name, M_DEVBUF, PPB_EXNAMLEN); 391 } 392 393 return (rv); 394 } 395 396 int 397 ppbactivate(struct device *self, int act) 398 { 399 struct ppb_softc *sc = (void *)self; 400 pci_chipset_tag_t pc = sc->sc_pc; 401 pcitag_t tag = sc->sc_tag; 402 pcireg_t blr, reg; 403 int off, rv = 0; 404 405 switch (act) { 406 case DVACT_SUSPEND: 407 rv = config_activate_children(self, act); 408 409 /* Save registers that may get lost. */ 410 sc->sc_csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 411 sc->sc_bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 412 sc->sc_bir = pci_conf_read(pc, tag, PPB_REG_BUSINFO); 413 sc->sc_bcr = pci_conf_read(pc, tag, PPB_REG_BRIDGECONTROL); 414 sc->sc_int = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 415 if (sc->sc_cap_off) 416 sc->sc_slcsr = pci_conf_read(pc, tag, 417 sc->sc_cap_off + PCI_PCIE_SLCSR); 418 419 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) { 420 sc->sc_msi_ma = pci_conf_read(pc, tag, 421 off + PCI_MSI_MA); 422 if (reg & PCI_MSI_MC_C64) { 423 sc->sc_msi_mau32 = pci_conf_read(pc, tag, 424 off + PCI_MSI_MAU32); 425 sc->sc_msi_md = pci_conf_read(pc, tag, 426 off + PCI_MSI_MD64); 427 } else { 428 sc->sc_msi_md = pci_conf_read(pc, tag, 429 off + PCI_MSI_MD32); 430 } 431 sc->sc_msi_mc = reg; 432 } 433 break; 434 case DVACT_RESUME: 435 if (pci_dopm) { 436 /* Restore power. */ 437 pci_set_powerstate(pc, tag, sc->sc_pmcsr_state); 438 } 439 440 /* Restore the registers saved above. */ 441 pci_conf_write(pc, tag, PCI_BHLC_REG, sc->sc_bhlcr); 442 pci_conf_write(pc, tag, PPB_REG_BUSINFO, sc->sc_bir); 443 pci_conf_write(pc, tag, PPB_REG_BRIDGECONTROL, sc->sc_bcr); 444 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, sc->sc_int); 445 if (sc->sc_cap_off) 446 pci_conf_write(pc, tag, 447 sc->sc_cap_off + PCI_PCIE_SLCSR, sc->sc_slcsr); 448 449 /* Restore I/O window. */ 450 blr = pci_conf_read(pc, tag, PPB_REG_IOSTATUS); 451 blr &= 0xffff0000; 452 blr |= sc->sc_iolimit & PPB_IO_MASK; 453 blr |= (sc->sc_iobase >> PPB_IO_SHIFT); 454 pci_conf_write(pc, tag, PPB_REG_IOSTATUS, blr); 455 blr = (sc->sc_iobase & 0xffff0000) >> 16; 456 blr |= sc->sc_iolimit & 0xffff0000; 457 pci_conf_write(pc, tag, PPB_REG_IO_HI, blr); 458 459 /* Restore memory mapped I/O window. */ 460 blr = sc->sc_memlimit & PPB_MEM_MASK; 461 blr |= (sc->sc_membase >> PPB_MEM_SHIFT); 462 pci_conf_write(pc, tag, PPB_REG_MEM, blr); 463 464 /* Restore prefetchable MMI/O window. */ 465 blr = sc->sc_pmemlimit & PPB_MEM_MASK; 466 blr |= ((sc->sc_pmembase & PPB_MEM_MASK) >> PPB_MEM_SHIFT); 467 pci_conf_write(pc, tag, PPB_REG_PREFMEM, blr); 468 #ifdef __LP64__ 469 pci_conf_write(pc, tag, PPB_REG_PREFBASE_HI32, 470 sc->sc_pmembase >> 32); 471 pci_conf_write(pc, tag, PPB_REG_PREFLIM_HI32, 472 sc->sc_pmemlimit >> 32); 473 #endif 474 475 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) { 476 pci_conf_write(pc, tag, off + PCI_MSI_MA, 477 sc->sc_msi_ma); 478 if (reg & PCI_MSI_MC_C64) { 479 pci_conf_write(pc, tag, off + PCI_MSI_MAU32, 480 sc->sc_msi_mau32); 481 pci_conf_write(pc, tag, off + PCI_MSI_MD64, 482 sc->sc_msi_md); 483 } else { 484 pci_conf_write(pc, tag, off + PCI_MSI_MD32, 485 sc->sc_msi_md); 486 } 487 pci_conf_write(pc, tag, off + PCI_MSI_MC, 488 sc->sc_msi_mc); 489 } 490 491 /* 492 * Restore command register last to avoid exposing 493 * uninitialised windows. 494 */ 495 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 496 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 497 (reg & 0xffff0000) | (sc->sc_csr & 0x0000ffff)); 498 499 rv = config_activate_children(self, act); 500 break; 501 case DVACT_POWERDOWN: 502 rv = config_activate_children(self, act); 503 504 if (pci_dopm) { 505 /* 506 * Place the bridge into the lowest possible 507 * power state. 508 */ 509 sc->sc_pmcsr_state = pci_get_powerstate(pc, tag); 510 pci_set_powerstate(pc, tag, 511 pci_min_powerstate(pc, tag)); 512 } 513 break; 514 default: 515 rv = config_activate_children(self, act); 516 break; 517 } 518 return (rv); 519 } 520 521 void 522 ppb_alloc_busrange(struct ppb_softc *sc, struct pci_attach_args *pa, 523 pcireg_t *busdata) 524 { 525 pci_chipset_tag_t pc = sc->sc_pc; 526 u_long busnum, busrange; 527 528 for (busrange = 16; busrange > 0; busrange >>= 1) { 529 if (extent_alloc(pa->pa_busex, busrange, 1, 0, 0, 530 EX_NOWAIT, &busnum)) 531 continue; 532 *busdata |= pa->pa_bus; 533 *busdata |= (busnum << 8); 534 *busdata |= ((busnum + busrange - 1) << 16); 535 pci_conf_write(pc, pa->pa_tag, PPB_REG_BUSINFO, *busdata); 536 return; 537 } 538 } 539 540 void 541 ppb_alloc_resources(struct ppb_softc *sc, struct pci_attach_args *pa) 542 { 543 pci_chipset_tag_t pc = sc->sc_pc; 544 pcireg_t id, busdata, blr, bhlcr, type, csr; 545 pcireg_t addr, mask; 546 pcitag_t tag; 547 int bus, dev; 548 int reg, reg_start, reg_end, reg_rom; 549 int io_count = 0; 550 int mem_count = 0; 551 bus_addr_t start, end; 552 u_long base, size; 553 554 if (pa->pa_memex == NULL) 555 return; 556 557 busdata = pci_conf_read(pc, sc->sc_tag, PPB_REG_BUSINFO); 558 bus = PPB_BUSINFO_SECONDARY(busdata); 559 if (bus == 0) 560 return; 561 562 /* 563 * Count number of devices. If there are no devices behind 564 * this bridge, there's no point in allocating any address 565 * space. 566 */ 567 for (dev = 0; dev < pci_bus_maxdevs(pc, bus); dev++) { 568 tag = pci_make_tag(pc, bus, dev, 0); 569 id = pci_conf_read(pc, tag, PCI_ID_REG); 570 571 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID || 572 PCI_VENDOR(id) == 0) 573 continue; 574 575 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 576 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 577 case 0: 578 reg_start = PCI_MAPREG_START; 579 reg_end = PCI_MAPREG_END; 580 reg_rom = PCI_ROM_REG; 581 break; 582 case 1: /* PCI-PCI bridge */ 583 reg_start = PCI_MAPREG_START; 584 reg_end = PCI_MAPREG_PPB_END; 585 reg_rom = 0; /* 0x38 */ 586 io_count++; 587 mem_count++; 588 break; 589 case 2: /* PCI-Cardbus bridge */ 590 reg_start = PCI_MAPREG_START; 591 reg_end = PCI_MAPREG_PCB_END; 592 reg_rom = 0; 593 io_count++; 594 mem_count++; 595 break; 596 default: 597 return; 598 } 599 600 for (reg = reg_start; reg < reg_end; reg += 4) { 601 if (pci_mapreg_probe(pc, tag, reg, &type) == 0) 602 continue; 603 604 if (type == PCI_MAPREG_TYPE_IO) 605 io_count++; 606 else 607 mem_count++; 608 } 609 610 if (reg_rom != 0) { 611 addr = pci_conf_read(pc, tag, reg_rom); 612 pci_conf_write(pc, tag, reg_rom, ~PCI_ROM_ENABLE); 613 mask = pci_conf_read(pc, tag, reg_rom); 614 pci_conf_write(pc, tag, reg_rom, addr); 615 if (PCI_ROM_SIZE(mask)) 616 mem_count++; 617 } 618 } 619 620 csr = pci_conf_read(pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 621 622 /* 623 * Get the bridge in a consistent state. If memory mapped I/O 624 * is disabled, disabled the associated windows as well. 625 */ 626 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 627 pci_conf_write(pc, sc->sc_tag, PPB_REG_MEM, 0x0000ffff); 628 pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFMEM, 0x0000ffff); 629 pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFBASE_HI32, 0); 630 pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFLIM_HI32, 0); 631 } 632 633 /* Allocate I/O address space if necessary. */ 634 if (io_count > 0 && pa->pa_ioex) { 635 blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_IOSTATUS); 636 sc->sc_iobase = (blr << PPB_IO_SHIFT) & PPB_IO_MASK; 637 sc->sc_iolimit = (blr & PPB_IO_MASK) | 0x00000fff; 638 blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_IO_HI); 639 sc->sc_iobase |= (blr & 0x0000ffff) << 16; 640 sc->sc_iolimit |= (blr & 0xffff0000); 641 if (sc->sc_iolimit < sc->sc_iobase || sc->sc_iobase == 0) { 642 start = max(PCI_IO_START, pa->pa_ioex->ex_start); 643 end = min(PCI_IO_END, pa->pa_ioex->ex_end); 644 for (size = 0x2000; size >= PPB_IO_MIN; size >>= 1) 645 if (extent_alloc_subregion(pa->pa_ioex, start, 646 end, size, size, 0, 0, 0, &base) == 0) 647 break; 648 if (size >= PPB_IO_MIN) { 649 sc->sc_iobase = base; 650 sc->sc_iolimit = base + size - 1; 651 blr = pci_conf_read(pc, sc->sc_tag, 652 PPB_REG_IOSTATUS); 653 blr &= 0xffff0000; 654 blr |= sc->sc_iolimit & PPB_IO_MASK; 655 blr |= (sc->sc_iobase >> PPB_IO_SHIFT); 656 pci_conf_write(pc, sc->sc_tag, 657 PPB_REG_IOSTATUS, blr); 658 blr = (sc->sc_iobase & 0xffff0000) >> 16; 659 blr |= sc->sc_iolimit & 0xffff0000; 660 pci_conf_write(pc, sc->sc_tag, 661 PPB_REG_IO_HI, blr); 662 663 csr |= PCI_COMMAND_IO_ENABLE; 664 } 665 } 666 } 667 668 /* Allocate memory mapped I/O address space if necessary. */ 669 if (mem_count > 0 && pa->pa_memex) { 670 blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_MEM); 671 sc->sc_membase = (blr << PPB_MEM_SHIFT) & PPB_MEM_MASK; 672 sc->sc_memlimit = (blr & PPB_MEM_MASK) | 0x000fffff; 673 if (sc->sc_memlimit < sc->sc_membase || sc->sc_membase == 0) { 674 start = max(PCI_MEM_START, pa->pa_memex->ex_start); 675 end = min(PCI_MEM_END, pa->pa_memex->ex_end); 676 for (size = 0x2000000; size >= PPB_MEM_MIN; size >>= 1) 677 if (extent_alloc_subregion(pa->pa_memex, start, 678 end, size, size, 0, 0, 0, &base) == 0) 679 break; 680 if (size >= PPB_MEM_MIN) { 681 sc->sc_membase = base; 682 sc->sc_memlimit = base + size - 1; 683 blr = sc->sc_memlimit & PPB_MEM_MASK; 684 blr |= (sc->sc_membase >> PPB_MEM_SHIFT); 685 pci_conf_write(pc, sc->sc_tag, 686 PPB_REG_MEM, blr); 687 688 csr |= PCI_COMMAND_MEM_ENABLE; 689 } 690 } 691 } 692 693 /* Enable bus master. */ 694 csr |= PCI_COMMAND_MASTER_ENABLE; 695 696 pci_conf_write(pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, csr); 697 } 698 699 int 700 ppb_intr(void *arg) 701 { 702 struct ppb_softc *sc = arg; 703 pcireg_t reg; 704 705 /* 706 * XXX ignore hotplug events while in autoconf. On some 707 * machines with onboard re(4), we get a bogus hotplug remove 708 * event when we reset that device. Ignoring that event makes 709 * sure we will not try to forcibly detach re(4) when it isn't 710 * ready to deal with that. 711 */ 712 if (cold) 713 return (0); 714 715 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 716 sc->sc_cap_off + PCI_PCIE_SLCSR); 717 if (reg & PCI_PCIE_SLCSR_PDC) { 718 if (reg & PCI_PCIE_SLCSR_PDS) 719 task_add(systq, &sc->sc_insert_task); 720 else 721 task_add(systq, &sc->sc_remove_task); 722 723 /* Clear interrupts. */ 724 pci_conf_write(sc->sc_pc, sc->sc_tag, 725 sc->sc_cap_off + PCI_PCIE_SLCSR, reg); 726 return (1); 727 } 728 729 return (0); 730 } 731 732 #ifdef PCI_MACHDEP_ENUMERATE_BUS 733 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 734 #else 735 extern int pci_enumerate_bus(struct pci_softc *, 736 int (*)(struct pci_attach_args *), struct pci_attach_args *); 737 #endif 738 739 void 740 ppb_hotplug_insert(void *xsc) 741 { 742 struct ppb_softc *sc = xsc; 743 struct pci_softc *psc = (struct pci_softc *)sc->sc_psc; 744 745 if (!LIST_EMPTY(&psc->sc_devs)) 746 return; 747 748 /* XXX Powerup the card. */ 749 750 /* XXX Turn on LEDs. */ 751 752 /* Wait a second for things to settle. */ 753 timeout_add_sec(&sc->sc_to, 1); 754 } 755 756 void 757 ppb_hotplug_insert_finish(void *arg) 758 { 759 struct ppb_softc *sc = arg; 760 761 task_add(systq, &sc->sc_rescan_task); 762 } 763 764 int 765 ppb_hotplug_fixup(struct pci_attach_args *pa) 766 { 767 pcireg_t bhlcr; 768 769 bhlcr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 770 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 771 case 0: 772 return ppb_hotplug_fixup_type0(pa->pa_pc, 773 pa->pa_tag, *pa->pa_bridgetag); 774 case 1: 775 return ppb_hotplug_fixup_type1(pa->pa_pc, 776 pa->pa_tag, *pa->pa_bridgetag); 777 default: 778 return (0); 779 } 780 } 781 782 int 783 ppb_hotplug_fixup_type0(pci_chipset_tag_t pc, pcitag_t tag, pcitag_t bridgetag) 784 { 785 pcireg_t intr; 786 int line; 787 788 /* 789 * Fill in the interrupt line for platforms that need it. 790 * 791 * XXX We assume that the interrupt line matches the line used 792 * by the PCI Express bridge. This may not be true. 793 */ 794 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 795 if (PCI_INTERRUPT_PIN(intr) != PCI_INTERRUPT_PIN_NONE && 796 PCI_INTERRUPT_LINE(intr) == 0) { 797 /* Get the interrupt line from our parent. */ 798 intr = pci_conf_read(pc, bridgetag, PCI_INTERRUPT_REG); 799 line = PCI_INTERRUPT_LINE(intr); 800 801 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 802 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 803 intr |= line << PCI_INTERRUPT_LINE_SHIFT; 804 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 805 } 806 807 return (0); 808 } 809 810 int 811 ppb_hotplug_fixup_type1(pci_chipset_tag_t pc, pcitag_t tag, pcitag_t bridgetag) 812 { 813 pcireg_t bhlcr, bir, csr, val; 814 int bus, dev, reg; 815 816 bir = pci_conf_read(pc, bridgetag, PPB_REG_BUSINFO); 817 if (PPB_BUSINFO_SUBORDINATE(bir) <= PPB_BUSINFO_SECONDARY(bir)) 818 return (0); 819 820 bus = PPB_BUSINFO_SECONDARY(bir); 821 bir = pci_conf_read(pc, tag, PPB_REG_BUSINFO); 822 bir &= (0xff << 24); 823 bir |= bus++; 824 bir |= (bus << 8); 825 bir |= (bus << 16); 826 pci_conf_write(pc, tag, PPB_REG_BUSINFO, bir); 827 828 for (reg = PPB_REG_IOSTATUS; reg < PPB_REG_BRIDGECONTROL; reg += 4) { 829 val = pci_conf_read(pc, bridgetag, reg); 830 pci_conf_write(pc, tag, reg, val); 831 } 832 833 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 834 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 835 csr |= PCI_COMMAND_MASTER_ENABLE; 836 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 837 csr |= PCI_COMMAND_SERR_ENABLE; 838 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 839 840 for (dev = 0; dev < pci_bus_maxdevs(pc, bus); dev++) { 841 tag = pci_make_tag(pc, bus, dev, 0); 842 843 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 844 if (PCI_HDRTYPE_TYPE(bhlcr) != 0) 845 continue; 846 847 ppb_hotplug_fixup_type0(pc, tag, bridgetag); 848 } 849 850 return (0); 851 } 852 853 void 854 ppb_hotplug_rescan(void *xsc) 855 { 856 struct ppb_softc *sc = xsc; 857 struct pci_softc *psc = (struct pci_softc *)sc->sc_psc; 858 859 if (psc) { 860 /* Assign resources. */ 861 pci_enumerate_bus(psc, ppb_hotplug_fixup, NULL); 862 863 /* Attach devices. */ 864 pci_enumerate_bus(psc, NULL, NULL); 865 } 866 } 867 868 void 869 ppb_hotplug_remove(void *xsc) 870 { 871 struct ppb_softc *sc = xsc; 872 struct pci_softc *psc = (struct pci_softc *)sc->sc_psc; 873 874 if (psc) { 875 pci_detach_devices(psc, DETACH_FORCE); 876 877 /* 878 * XXX Allocate the entire window with EX_CONFLICTOK 879 * such that we can easily free it. 880 */ 881 if (sc->sc_ioex != NULL) { 882 extent_alloc_region(sc->sc_ioex, sc->sc_iobase, 883 sc->sc_iolimit - sc->sc_iobase + 1, 884 EX_NOWAIT | EX_CONFLICTOK); 885 extent_free(sc->sc_ioex, sc->sc_iobase, 886 sc->sc_iolimit - sc->sc_iobase + 1, EX_NOWAIT); 887 } 888 889 if (sc->sc_memex != NULL) { 890 extent_alloc_region(sc->sc_memex, sc->sc_membase, 891 sc->sc_memlimit - sc->sc_membase + 1, 892 EX_NOWAIT | EX_CONFLICTOK); 893 extent_free(sc->sc_memex, sc->sc_membase, 894 sc->sc_memlimit - sc->sc_membase + 1, EX_NOWAIT); 895 } 896 897 if (sc->sc_pmemex != NULL) { 898 extent_alloc_region(sc->sc_pmemex, sc->sc_pmembase, 899 sc->sc_pmemlimit - sc->sc_pmembase + 1, 900 EX_NOWAIT | EX_CONFLICTOK); 901 extent_free(sc->sc_pmemex, sc->sc_pmembase, 902 sc->sc_pmemlimit - sc->sc_pmembase + 1, EX_NOWAIT); 903 } 904 } 905 } 906 907 int 908 ppbprint(void *aux, const char *pnp) 909 { 910 struct pcibus_attach_args *pba = aux; 911 912 /* only PCIs can attach to PPBs; easy. */ 913 if (pnp) 914 printf("pci at %s", pnp); 915 printf(" bus %d", pba->pba_bus); 916 return (UNCONF); 917 } 918