1 /* $OpenBSD: ppb.c,v 1.53 2011/10/31 21:44:54 mikeb Exp $ */ 2 /* $NetBSD: ppb.c,v 1.16 1997/06/06 23:48:05 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Christopher G. Demetriou 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/device.h> 38 #include <sys/timeout.h> 39 #include <sys/workq.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcidevs.h> 44 #include <dev/pci/ppbreg.h> 45 46 #ifndef PCI_IO_START 47 #define PCI_IO_START 0 48 #endif 49 50 #ifndef PCI_IO_END 51 #define PCI_IO_END 0xffffffff 52 #endif 53 54 #ifndef PCI_MEM_START 55 #define PCI_MEM_START 0 56 #endif 57 58 #ifndef PCI_MEM_END 59 #define PCI_MEM_END 0xffffffff 60 #endif 61 62 struct ppb_softc { 63 struct device sc_dev; /* generic device glue */ 64 pci_chipset_tag_t sc_pc; /* our PCI chipset... */ 65 pcitag_t sc_tag; /* ...and tag. */ 66 pci_intr_handle_t sc_ih[4]; 67 void *sc_intrhand; 68 struct extent *sc_ioex; 69 struct extent *sc_memex; 70 struct extent *sc_pmemex; 71 struct device *sc_psc; 72 int sc_cap_off; 73 struct timeout sc_to; 74 75 bus_addr_t sc_iobase, sc_iolimit; 76 bus_addr_t sc_membase, sc_memlimit; 77 bus_addr_t sc_pmembase, sc_pmemlimit; 78 79 pcireg_t sc_csr; 80 pcireg_t sc_bhlcr; 81 pcireg_t sc_bir; 82 pcireg_t sc_bcr; 83 pcireg_t sc_int; 84 pcireg_t sc_slcsr; 85 pcireg_t sc_msi_mc; 86 pcireg_t sc_msi_ma; 87 pcireg_t sc_msi_mau32; 88 pcireg_t sc_msi_md; 89 int sc_pmcsr_state; 90 }; 91 92 int ppbmatch(struct device *, void *, void *); 93 void ppbattach(struct device *, struct device *, void *); 94 int ppbdetach(struct device *self, int flags); 95 int ppbactivate(struct device *self, int act); 96 97 struct cfattach ppb_ca = { 98 sizeof(struct ppb_softc), ppbmatch, ppbattach, ppbdetach, ppbactivate 99 }; 100 101 struct cfdriver ppb_cd = { 102 NULL, "ppb", DV_DULL 103 }; 104 105 void ppb_alloc_resources(struct ppb_softc *, struct pci_attach_args *); 106 int ppb_intr(void *); 107 void ppb_hotplug_insert(void *, void *); 108 void ppb_hotplug_insert_finish(void *); 109 int ppb_hotplug_fixup(struct pci_attach_args *); 110 int ppb_hotplug_fixup_type0(pci_chipset_tag_t, pcitag_t, pcitag_t); 111 int ppb_hotplug_fixup_type1(pci_chipset_tag_t, pcitag_t, pcitag_t); 112 void ppb_hotplug_rescan(void *, void *); 113 void ppb_hotplug_remove(void *, void *); 114 int ppbprint(void *, const char *pnp); 115 116 int 117 ppbmatch(struct device *parent, void *match, void *aux) 118 { 119 struct pci_attach_args *pa = aux; 120 121 /* 122 * This device is mislabeled. It is not a PCI bridge. 123 */ 124 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH && 125 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT82C586_PWR) 126 return (0); 127 /* 128 * Check the ID register to see that it's a PCI bridge. 129 * If it is, we assume that we can deal with it; it _should_ 130 * work in a standardized way... 131 */ 132 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 133 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_PCI) 134 return (1); 135 136 return (0); 137 } 138 139 void 140 ppbattach(struct device *parent, struct device *self, void *aux) 141 { 142 struct ppb_softc *sc = (struct ppb_softc *)self; 143 struct pci_attach_args *pa = aux; 144 pci_chipset_tag_t pc = pa->pa_pc; 145 struct pcibus_attach_args pba; 146 pci_intr_handle_t ih; 147 pcireg_t busdata, reg, blr; 148 char *name; 149 int pin; 150 151 sc->sc_pc = pc; 152 sc->sc_tag = pa->pa_tag; 153 154 busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO); 155 156 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 157 printf(": not configured by system firmware\n"); 158 return; 159 } 160 161 #if 0 162 /* 163 * XXX can't do this, because we're not given our bus number 164 * (we shouldn't need it), and because we've no way to 165 * decompose our tag. 166 */ 167 /* sanity check. */ 168 if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata)) 169 panic("ppbattach: bus in tag (%d) != bus in reg (%d)", 170 pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata)); 171 #endif 172 173 /* Check for PCI Express capabilities and setup hotplug support. */ 174 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 175 &sc->sc_cap_off, ®) && (reg & PCI_PCIE_XCAP_SI)) { 176 #ifdef __i386__ 177 if (pci_intr_map(pa, &ih) == 0) 178 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_BIO, 179 ppb_intr, sc, self->dv_xname); 180 #else 181 if (pci_intr_map_msi(pa, &ih) == 0 || 182 pci_intr_map(pa, &ih) == 0) 183 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_BIO, 184 ppb_intr, sc, self->dv_xname); 185 #endif 186 187 if (sc->sc_intrhand) { 188 printf(": %s", pci_intr_string(pc, ih)); 189 190 /* Enable hotplug interrupt. */ 191 reg = pci_conf_read(pc, pa->pa_tag, 192 sc->sc_cap_off + PCI_PCIE_SLCSR); 193 reg |= (PCI_PCIE_SLCSR_HPE | PCI_PCIE_SLCSR_PDE); 194 pci_conf_write(pc, pa->pa_tag, 195 sc->sc_cap_off + PCI_PCIE_SLCSR, reg); 196 197 timeout_set(&sc->sc_to, ppb_hotplug_insert_finish, sc); 198 } 199 } 200 201 printf("\n"); 202 203 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL || 204 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82801BA_HPB && 205 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82801BAM_HPB)) 206 ppb_alloc_resources(sc, pa); 207 208 for (pin = PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_D; pin++) { 209 pa->pa_intrpin = pa->pa_rawintrpin = pin; 210 pa->pa_intrline = 0; 211 pci_intr_map(pa, &sc->sc_ih[pin - PCI_INTERRUPT_PIN_A]); 212 } 213 214 /* 215 * The UltraSPARC-IIi APB doesn't implement the standard 216 * address range registers. 217 */ 218 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 219 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_SIMBA) 220 goto attach; 221 222 /* Figure out the I/O address range of the bridge. */ 223 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_IOSTATUS); 224 sc->sc_iobase = (blr & 0x000000f0) << 8; 225 sc->sc_iolimit = (blr & 0x000f000) | 0x00000fff; 226 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_IO_HI); 227 sc->sc_iobase |= (blr & 0x0000ffff) << 16; 228 sc->sc_iolimit |= (blr & 0xffff0000); 229 if (sc->sc_iolimit > sc->sc_iobase) { 230 name = malloc(32, M_DEVBUF, M_NOWAIT); 231 if (name) { 232 snprintf(name, 32, "%s pciio", sc->sc_dev.dv_xname); 233 sc->sc_ioex = extent_create(name, 0, 0xffffffff, 234 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 235 extent_free(sc->sc_ioex, sc->sc_iobase, 236 sc->sc_iolimit - sc->sc_iobase + 1, EX_NOWAIT); 237 } 238 } 239 240 /* Figure out the memory mapped I/O address range of the bridge. */ 241 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_MEM); 242 sc->sc_membase = (blr & 0x0000fff0) << 16; 243 sc->sc_memlimit = (blr & 0xfff00000) | 0x000fffff; 244 if (sc->sc_memlimit > sc->sc_membase) { 245 name = malloc(32, M_DEVBUF, M_NOWAIT); 246 if (name) { 247 snprintf(name, 32, "%s pcimem", sc->sc_dev.dv_xname); 248 sc->sc_memex = extent_create(name, 0, 0xffffffff, 249 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 250 extent_free(sc->sc_memex, sc->sc_membase, 251 sc->sc_memlimit - sc->sc_membase + 1, 252 EX_NOWAIT); 253 } 254 } 255 256 /* Figure out the prefetchable MMI/O address range of the bridge. */ 257 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFMEM); 258 sc->sc_pmembase = (blr & 0x0000fff0) << 16; 259 sc->sc_pmemlimit = (blr & 0xfff00000) | 0x000fffff; 260 #ifdef __LP64__ /* XXX because extents use long... */ 261 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFBASE_HI32); 262 sc->sc_pmembase |= ((uint64_t)blr) << 32; 263 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFLIM_HI32); 264 sc->sc_pmemlimit |= ((uint64_t)blr) << 32; 265 #endif 266 if (sc->sc_pmemlimit > sc->sc_pmembase) { 267 name = malloc(32, M_DEVBUF, M_NOWAIT); 268 if (name) { 269 snprintf(name, 32, "%s pcipmem", sc->sc_dev.dv_xname); 270 sc->sc_pmemex = extent_create(name, 0, (u_long)-1L, 271 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 272 extent_free(sc->sc_pmemex, sc->sc_pmembase, 273 sc->sc_pmemlimit - sc->sc_pmembase + 1, 274 EX_NOWAIT); 275 } 276 } 277 278 /* 279 * The Intel 82801BAM Hub-to-PCI can decode subtractively. 280 * XXX We probably should handle subtractive decode bridges 281 * in general. 282 */ 283 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 284 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BA_HPB || 285 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BAM_HPB)) { 286 if (sc->sc_ioex == NULL) 287 sc->sc_ioex = pa->pa_ioex; 288 if (sc->sc_memex == NULL) 289 sc->sc_memex = pa->pa_memex; 290 } 291 292 attach: 293 /* 294 * Attach the PCI bus that hangs off of it. 295 * 296 * XXX Don't pass-through Memory Read Multiple. Should we? 297 * XXX Consult the spec... 298 */ 299 bzero(&pba, sizeof(pba)); 300 pba.pba_busname = "pci"; 301 pba.pba_iot = pa->pa_iot; 302 pba.pba_memt = pa->pa_memt; 303 pba.pba_dmat = pa->pa_dmat; 304 pba.pba_pc = pc; 305 pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY; 306 pba.pba_ioex = sc->sc_ioex; 307 pba.pba_memex = sc->sc_memex; 308 pba.pba_pmemex = sc->sc_pmemex; 309 pba.pba_domain = pa->pa_domain; 310 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 311 pba.pba_bridgeih = sc->sc_ih; 312 pba.pba_bridgetag = &sc->sc_tag; 313 pba.pba_intrswiz = pa->pa_intrswiz; 314 pba.pba_intrtag = pa->pa_intrtag; 315 316 sc->sc_psc = config_found(self, &pba, ppbprint); 317 } 318 319 int 320 ppbdetach(struct device *self, int flags) 321 { 322 struct ppb_softc *sc = (struct ppb_softc *)self; 323 char *name; 324 int rv; 325 326 if (sc->sc_intrhand) 327 pci_intr_disestablish(sc->sc_pc, sc->sc_intrhand); 328 329 rv = config_detach_children(self, flags); 330 331 if (sc->sc_ioex) { 332 name = sc->sc_ioex->ex_name; 333 extent_destroy(sc->sc_ioex); 334 free(name, M_DEVBUF); 335 } 336 337 if (sc->sc_memex) { 338 name = sc->sc_memex->ex_name; 339 extent_destroy(sc->sc_memex); 340 free(name, M_DEVBUF); 341 } 342 343 if (sc->sc_pmemex) { 344 name = sc->sc_pmemex->ex_name; 345 extent_destroy(sc->sc_pmemex); 346 free(name, M_DEVBUF); 347 } 348 349 return (rv); 350 } 351 352 int 353 ppbactivate(struct device *self, int act) 354 { 355 struct ppb_softc *sc = (void *)self; 356 pci_chipset_tag_t pc = sc->sc_pc; 357 pcitag_t tag = sc->sc_tag; 358 pcireg_t blr, reg; 359 int off, rv = 0; 360 361 switch (act) { 362 case DVACT_QUIESCE: 363 rv = config_activate_children(self, act); 364 break; 365 case DVACT_SUSPEND: 366 rv = config_activate_children(self, act); 367 368 /* Save registers that may get lost. */ 369 sc->sc_csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 370 sc->sc_bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 371 sc->sc_bir = pci_conf_read(pc, tag, PPB_REG_BUSINFO); 372 sc->sc_bcr = pci_conf_read(pc, tag, PPB_REG_BRIDGECONTROL); 373 sc->sc_int = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 374 if (sc->sc_cap_off) 375 sc->sc_slcsr = pci_conf_read(pc, tag, 376 sc->sc_cap_off + PCI_PCIE_SLCSR); 377 378 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) { 379 sc->sc_msi_ma = pci_conf_read(pc, tag, 380 off + PCI_MSI_MA); 381 if (reg & PCI_MSI_MC_C64) { 382 sc->sc_msi_mau32 = pci_conf_read(pc, tag, 383 off + PCI_MSI_MAU32); 384 sc->sc_msi_md = pci_conf_read(pc, tag, 385 off + PCI_MSI_MD64); 386 } else { 387 sc->sc_msi_md = pci_conf_read(pc, tag, 388 off + PCI_MSI_MD32); 389 } 390 sc->sc_msi_mc = reg; 391 } 392 393 if (pci_dopm) { 394 /* Place the bridge into D3. */ 395 sc->sc_pmcsr_state = pci_get_powerstate(pc, tag); 396 pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D3); 397 } 398 break; 399 case DVACT_RESUME: 400 if (pci_dopm) { 401 /* Restore power. */ 402 pci_set_powerstate(pc, tag, sc->sc_pmcsr_state); 403 } 404 405 /* Restore the registers saved above. */ 406 pci_conf_write(pc, tag, PCI_BHLC_REG, sc->sc_bhlcr); 407 pci_conf_write(pc, tag, PPB_REG_BUSINFO, sc->sc_bir); 408 pci_conf_write(pc, tag, PPB_REG_BRIDGECONTROL, sc->sc_bcr); 409 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, sc->sc_int); 410 if (sc->sc_cap_off) 411 pci_conf_write(pc, tag, 412 sc->sc_cap_off + PCI_PCIE_SLCSR, sc->sc_slcsr); 413 414 /* Restore I/O window. */ 415 blr = pci_conf_read(pc, tag, PPB_REG_IOSTATUS); 416 blr &= 0xffff0000; 417 blr |= sc->sc_iolimit & PPB_IO_MASK; 418 blr |= (sc->sc_iobase >> PPB_IO_SHIFT); 419 pci_conf_write(pc, tag, PPB_REG_IOSTATUS, blr); 420 blr = (sc->sc_iobase & 0xffff0000) >> 16; 421 blr |= sc->sc_iolimit & 0xffff0000; 422 pci_conf_write(pc, tag, PPB_REG_IO_HI, blr); 423 424 /* Restore memory mapped I/O window. */ 425 blr = sc->sc_memlimit & PPB_MEM_MASK; 426 blr |= (sc->sc_membase >> PPB_MEM_SHIFT); 427 pci_conf_write(pc, tag, PPB_REG_MEM, blr); 428 429 /* Restore prefetchable MMI/O window. */ 430 blr = sc->sc_pmemlimit & PPB_MEM_MASK; 431 blr |= (sc->sc_pmembase >> PPB_MEM_SHIFT); 432 pci_conf_write(pc, tag, PPB_REG_PREFMEM, blr); 433 #ifdef __LP64__ 434 pci_conf_write(pc, tag, PPB_REG_PREFBASE_HI32, 435 sc->sc_pmembase >> 32); 436 pci_conf_write(pc, tag, PPB_REG_PREFLIM_HI32, 437 sc->sc_pmemlimit >> 32); 438 #endif 439 440 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) { 441 pci_conf_write(pc, tag, off + PCI_MSI_MA, 442 sc->sc_msi_ma); 443 if (reg & PCI_MSI_MC_C64) { 444 pci_conf_write(pc, tag, off + PCI_MSI_MAU32, 445 sc->sc_msi_mau32); 446 pci_conf_write(pc, tag, off + PCI_MSI_MD64, 447 sc->sc_msi_md); 448 } else { 449 pci_conf_write(pc, tag, off + PCI_MSI_MD32, 450 sc->sc_msi_md); 451 } 452 pci_conf_write(pc, tag, off + PCI_MSI_MC, 453 sc->sc_msi_mc); 454 } 455 456 /* 457 * Restore command register last to avoid exposing 458 * uninitialised windows. 459 */ 460 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 461 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 462 (reg & 0xffff0000) | (sc->sc_csr & 0x0000ffff)); 463 464 rv = config_activate_children(self, act); 465 break; 466 } 467 return (rv); 468 } 469 470 void 471 ppb_alloc_resources(struct ppb_softc *sc, struct pci_attach_args *pa) 472 { 473 pci_chipset_tag_t pc = sc->sc_pc; 474 pcireg_t id, busdata, blr, bhlcr, type, csr; 475 pcireg_t addr, mask; 476 pcitag_t tag; 477 int bus, dev; 478 int reg, reg_start, reg_end, reg_rom; 479 int io_count = 0; 480 int mem_count = 0; 481 bus_addr_t start, end; 482 u_long base, size; 483 484 if (pa->pa_memex == NULL) 485 return; 486 487 busdata = pci_conf_read(pc, sc->sc_tag, PPB_REG_BUSINFO); 488 bus = PPB_BUSINFO_SECONDARY(busdata); 489 if (bus == 0) 490 return; 491 492 /* 493 * Count number of devices. If there are no devices behind 494 * this bridge, there's no point in allocating any address 495 * space. 496 */ 497 for (dev = 0; dev < pci_bus_maxdevs(pc, bus); dev++) { 498 tag = pci_make_tag(pc, bus, dev, 0); 499 id = pci_conf_read(pc, tag, PCI_ID_REG); 500 501 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID || 502 PCI_VENDOR(id) == 0) 503 continue; 504 505 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 506 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 507 case 0: 508 reg_start = PCI_MAPREG_START; 509 reg_end = PCI_MAPREG_END; 510 reg_rom = PCI_ROM_REG; 511 break; 512 case 1: /* PCI-PCI bridge */ 513 reg_start = PCI_MAPREG_START; 514 reg_end = PCI_MAPREG_PPB_END; 515 reg_rom = 0; /* 0x38 */ 516 break; 517 case 2: /* PCI-Cardbus bridge */ 518 reg_start = PCI_MAPREG_START; 519 reg_end = PCI_MAPREG_PCB_END; 520 reg_rom = 0; 521 break; 522 default: 523 return; 524 } 525 526 for (reg = reg_start; reg < reg_end; reg += 4) { 527 if (pci_mapreg_probe(pc, tag, reg, &type) == 0) 528 continue; 529 530 if (type == PCI_MAPREG_TYPE_IO) 531 io_count++; 532 else 533 mem_count++; 534 } 535 536 if (reg_rom != 0) { 537 addr = pci_conf_read(pc, tag, reg_rom); 538 pci_conf_write(pc, tag, reg_rom, ~PCI_ROM_ENABLE); 539 mask = pci_conf_read(pc, tag, reg_rom); 540 pci_conf_write(pc, tag, reg_rom, addr); 541 if (PCI_ROM_SIZE(mask)) 542 mem_count++; 543 } 544 } 545 546 csr = pci_conf_read(pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 547 548 /* 549 * Get the bridge in a consistent state. If memory mapped I/O 550 * is disabled, disabled the associated windows as well. 551 */ 552 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 553 pci_conf_write(pc, sc->sc_tag, PPB_REG_MEM, 0x0000ffff); 554 pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFMEM, 0x0000ffff); 555 pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFBASE_HI32, 0); 556 pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFLIM_HI32, 0); 557 } 558 559 /* Allocate I/O address space if necessary. */ 560 if (io_count > 0 && pa->pa_ioex) { 561 blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_IOSTATUS); 562 sc->sc_iobase = (blr << PPB_IO_SHIFT) & PPB_IO_MASK; 563 sc->sc_iolimit = (blr & PPB_IO_MASK) | 0x00000fff; 564 blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_IO_HI); 565 sc->sc_iobase |= (blr & 0x0000ffff) << 16; 566 sc->sc_iolimit |= (blr & 0xffff0000); 567 if (sc->sc_iolimit < sc->sc_iobase || sc->sc_iobase == 0) { 568 start = max(PCI_IO_START, pa->pa_ioex->ex_start); 569 end = min(PCI_IO_END, pa->pa_ioex->ex_end); 570 for (size = 0x2000; size >= PPB_IO_MIN; size >>= 1) 571 if (extent_alloc_subregion(pa->pa_ioex, start, 572 end, size, size, 0, 0, 0, &base) == 0) 573 break; 574 if (size >= PPB_IO_MIN) { 575 sc->sc_iobase = base; 576 sc->sc_iolimit = base + size - 1; 577 blr = pci_conf_read(pc, sc->sc_tag, 578 PPB_REG_IOSTATUS); 579 blr &= 0xffff0000; 580 blr |= sc->sc_iolimit & PPB_IO_MASK; 581 blr |= (sc->sc_iobase >> PPB_IO_SHIFT); 582 pci_conf_write(pc, sc->sc_tag, 583 PPB_REG_IOSTATUS, blr); 584 blr = (sc->sc_iobase & 0xffff0000) >> 16; 585 blr |= sc->sc_iolimit & 0xffff0000; 586 pci_conf_write(pc, sc->sc_tag, 587 PPB_REG_IO_HI, blr); 588 589 csr |= PCI_COMMAND_IO_ENABLE; 590 } 591 } 592 } 593 594 /* Allocate memory mapped I/O address space if necessary. */ 595 if (mem_count > 0 && pa->pa_memex) { 596 blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_MEM); 597 sc->sc_membase = (blr << PPB_MEM_SHIFT) & PPB_MEM_MASK; 598 sc->sc_memlimit = (blr & PPB_MEM_MASK) | 0x000fffff; 599 if (sc->sc_memlimit < sc->sc_membase || sc->sc_membase == 0) { 600 start = max(PCI_MEM_START, pa->pa_memex->ex_start); 601 end = min(PCI_MEM_END, pa->pa_memex->ex_end); 602 for (size = 0x2000000; size >= PPB_MEM_MIN; size >>= 1) 603 if (extent_alloc_subregion(pa->pa_memex, start, 604 end, size, size, 0, 0, 0, &base) == 0) 605 break; 606 if (size >= PPB_MEM_MIN) { 607 sc->sc_membase = base; 608 sc->sc_memlimit = base + size - 1; 609 blr = sc->sc_memlimit & PPB_MEM_MASK; 610 blr |= (sc->sc_membase >> PPB_MEM_SHIFT); 611 pci_conf_write(pc, sc->sc_tag, 612 PPB_REG_MEM, blr); 613 614 csr |= PCI_COMMAND_MEM_ENABLE; 615 } 616 } 617 } 618 619 pci_conf_write(pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, csr); 620 } 621 622 int 623 ppb_intr(void *arg) 624 { 625 struct ppb_softc *sc = arg; 626 pcireg_t reg; 627 628 /* 629 * XXX ignore hotplug events while in autoconf. On some 630 * machines with onboard re(4), we get a bogus hotplug remove 631 * event when we reset that device. Ignoring that event makes 632 * sure we will not try to forcibly detach re(4) when it isn't 633 * ready to deal with that. 634 */ 635 if (cold) 636 return (0); 637 638 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 639 sc->sc_cap_off + PCI_PCIE_SLCSR); 640 if (reg & PCI_PCIE_SLCSR_PDC) { 641 if (reg & PCI_PCIE_SLCSR_PDS) 642 workq_add_task(NULL, 0, ppb_hotplug_insert, sc, NULL); 643 else 644 workq_add_task(NULL, 0, ppb_hotplug_remove, sc, NULL); 645 646 /* Clear interrupts. */ 647 pci_conf_write(sc->sc_pc, sc->sc_tag, 648 sc->sc_cap_off + PCI_PCIE_SLCSR, reg); 649 return (1); 650 } 651 652 return (0); 653 } 654 655 #ifdef PCI_MACHDEP_ENUMERATE_BUS 656 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 657 #else 658 extern int pci_enumerate_bus(struct pci_softc *, 659 int (*)(struct pci_attach_args *), struct pci_attach_args *); 660 #endif 661 662 void 663 ppb_hotplug_insert(void *arg1, void *arg2) 664 { 665 struct ppb_softc *sc = arg1; 666 struct pci_softc *psc = (struct pci_softc *)sc->sc_psc; 667 668 if (!LIST_EMPTY(&psc->sc_devs)) 669 return; 670 671 /* XXX Powerup the card. */ 672 673 /* XXX Turn on LEDs. */ 674 675 /* Wait a second for things to settle. */ 676 timeout_add_sec(&sc->sc_to, 1); 677 } 678 679 void 680 ppb_hotplug_insert_finish(void *arg) 681 { 682 workq_add_task(NULL, 0, ppb_hotplug_rescan, arg, NULL); 683 } 684 685 int 686 ppb_hotplug_fixup(struct pci_attach_args *pa) 687 { 688 pcireg_t bhlcr; 689 690 bhlcr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 691 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 692 case 0: 693 return ppb_hotplug_fixup_type0(pa->pa_pc, 694 pa->pa_tag, *pa->pa_bridgetag); 695 case 1: 696 return ppb_hotplug_fixup_type1(pa->pa_pc, 697 pa->pa_tag, *pa->pa_bridgetag); 698 default: 699 return (0); 700 } 701 } 702 703 int 704 ppb_hotplug_fixup_type0(pci_chipset_tag_t pc, pcitag_t tag, pcitag_t bridgetag) 705 { 706 pcireg_t intr; 707 int line; 708 709 /* 710 * Fill in the interrupt line for platforms that need it. 711 * 712 * XXX We assume that the interrupt line matches the line used 713 * by the PCI Express bridge. This may not be true. 714 */ 715 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 716 if (PCI_INTERRUPT_PIN(intr) != PCI_INTERRUPT_PIN_NONE && 717 PCI_INTERRUPT_LINE(intr) == 0) { 718 /* Get the interrupt line from our parent. */ 719 intr = pci_conf_read(pc, bridgetag, PCI_INTERRUPT_REG); 720 line = PCI_INTERRUPT_LINE(intr); 721 722 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 723 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 724 intr |= line << PCI_INTERRUPT_LINE_SHIFT; 725 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 726 } 727 728 return (0); 729 } 730 731 int 732 ppb_hotplug_fixup_type1(pci_chipset_tag_t pc, pcitag_t tag, pcitag_t bridgetag) 733 { 734 pcireg_t bhlcr, bir, csr, val; 735 int bus, dev, reg; 736 737 bir = pci_conf_read(pc, bridgetag, PPB_REG_BUSINFO); 738 if (PPB_BUSINFO_SUBORDINATE(bir) <= PPB_BUSINFO_SECONDARY(bir)) 739 return (0); 740 741 bus = PPB_BUSINFO_SECONDARY(bir); 742 bir = pci_conf_read(pc, tag, PPB_REG_BUSINFO); 743 bir &= (0xff << 24); 744 bir |= bus++; 745 bir |= (bus << 8); 746 bir |= (bus << 16); 747 pci_conf_write(pc, tag, PPB_REG_BUSINFO, bir); 748 749 for (reg = PPB_REG_IOSTATUS; reg < PPB_REG_BRIDGECONTROL; reg += 4) { 750 val = pci_conf_read(pc, bridgetag, reg); 751 pci_conf_write(pc, tag, reg, val); 752 } 753 754 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 755 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 756 csr |= PCI_COMMAND_MASTER_ENABLE; 757 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 758 csr |= PCI_COMMAND_SERR_ENABLE; 759 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 760 761 for (dev = 0; dev < pci_bus_maxdevs(pc, bus); dev++) { 762 tag = pci_make_tag(pc, bus, dev, 0); 763 764 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 765 if (PCI_HDRTYPE_TYPE(bhlcr) != 0) 766 continue; 767 768 ppb_hotplug_fixup_type0(pc, tag, bridgetag); 769 } 770 771 return (0); 772 } 773 774 void 775 ppb_hotplug_rescan(void *arg1, void *arg2) 776 { 777 struct ppb_softc *sc = arg1; 778 struct pci_softc *psc = (struct pci_softc *)sc->sc_psc; 779 780 if (psc) { 781 /* Assign resources. */ 782 pci_enumerate_bus(psc, ppb_hotplug_fixup, NULL); 783 784 /* Attach devices. */ 785 pci_enumerate_bus(psc, NULL, NULL); 786 } 787 } 788 789 void 790 ppb_hotplug_remove(void *arg1, void *arg2) 791 { 792 struct ppb_softc *sc = arg1; 793 struct pci_softc *psc = (struct pci_softc *)sc->sc_psc; 794 795 if (psc) { 796 pci_detach_devices(psc, DETACH_FORCE); 797 798 /* 799 * XXX Allocate the entire window with EX_CONFLICTOK 800 * such that we can easily free it. 801 */ 802 if (sc->sc_ioex != NULL) { 803 extent_alloc_region(sc->sc_ioex, sc->sc_iobase, 804 sc->sc_iolimit - sc->sc_iobase + 1, 805 EX_NOWAIT | EX_CONFLICTOK); 806 extent_free(sc->sc_ioex, sc->sc_iobase, 807 sc->sc_iolimit - sc->sc_iobase + 1, EX_NOWAIT); 808 } 809 810 if (sc->sc_memex != NULL) { 811 extent_alloc_region(sc->sc_memex, sc->sc_membase, 812 sc->sc_memlimit - sc->sc_membase + 1, 813 EX_NOWAIT | EX_CONFLICTOK); 814 extent_free(sc->sc_memex, sc->sc_membase, 815 sc->sc_memlimit - sc->sc_membase + 1, EX_NOWAIT); 816 } 817 818 if (sc->sc_pmemex != NULL) { 819 extent_alloc_region(sc->sc_pmemex, sc->sc_pmembase, 820 sc->sc_pmemlimit - sc->sc_pmembase + 1, 821 EX_NOWAIT | EX_CONFLICTOK); 822 extent_free(sc->sc_pmemex, sc->sc_pmembase, 823 sc->sc_pmemlimit - sc->sc_pmembase + 1, EX_NOWAIT); 824 } 825 } 826 } 827 828 int 829 ppbprint(void *aux, const char *pnp) 830 { 831 struct pcibus_attach_args *pba = aux; 832 833 /* only PCIs can attach to PPBs; easy. */ 834 if (pnp) 835 printf("pci at %s", pnp); 836 printf(" bus %d", pba->pba_bus); 837 return (UNCONF); 838 } 839