1 /* $OpenBSD: piixpm.c,v 1.36 2011/05/28 14:56:32 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel PIIX and compatible Power Management controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcidevs.h> 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 #include <dev/pci/piixreg.h> 36 37 #include <dev/i2c/i2cvar.h> 38 39 #ifdef PIIXPM_DEBUG 40 #define DPRINTF(x) printf x 41 #else 42 #define DPRINTF(x) 43 #endif 44 45 #define PIIXPM_DELAY 200 46 #define PIIXPM_TIMEOUT 1 47 48 struct piixpm_softc { 49 struct device sc_dev; 50 51 bus_space_tag_t sc_iot; 52 bus_space_handle_t sc_ioh; 53 void * sc_ih; 54 int sc_poll; 55 56 struct i2c_controller sc_i2c_tag; 57 struct rwlock sc_i2c_lock; 58 struct { 59 i2c_op_t op; 60 void * buf; 61 size_t len; 62 int flags; 63 volatile int error; 64 } sc_i2c_xfer; 65 }; 66 67 int piixpm_match(struct device *, void *, void *); 68 void piixpm_attach(struct device *, struct device *, void *); 69 70 int piixpm_i2c_acquire_bus(void *, int); 71 void piixpm_i2c_release_bus(void *, int); 72 int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 73 void *, size_t, int); 74 75 int piixpm_intr(void *); 76 77 struct cfattach piixpm_ca = { 78 sizeof(struct piixpm_softc), 79 piixpm_match, 80 piixpm_attach 81 }; 82 83 struct cfdriver piixpm_cd = { 84 NULL, "piixpm", DV_DULL 85 }; 86 87 const struct pci_matchid piixpm_ids[] = { 88 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB200_SMB }, 89 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB300_SMB }, 90 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB400_SMB }, 91 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SBX00_SMB }, 92 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_PM }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_PM }, 95 96 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_CSB5 }, 97 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_CSB6 }, 98 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_HT_1000 }, 99 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_HT_1100 }, 100 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_OSB4 }, 101 102 { PCI_VENDOR_SMSC, PCI_PRODUCT_SMSC_VICTORY66_PM } 103 }; 104 105 int 106 piixpm_match(struct device *parent, void *match, void *aux) 107 { 108 return (pci_matchbyid(aux, piixpm_ids, 109 sizeof(piixpm_ids) / sizeof(piixpm_ids[0]))); 110 } 111 112 void 113 piixpm_attach(struct device *parent, struct device *self, void *aux) 114 { 115 struct piixpm_softc *sc = (struct piixpm_softc *)self; 116 struct pci_attach_args *pa = aux; 117 bus_space_handle_t ioh; 118 u_int16_t smb0en; 119 bus_addr_t base; 120 pcireg_t conf; 121 pci_intr_handle_t ih; 122 const char *intrstr = NULL; 123 struct i2cbus_attach_args iba; 124 125 sc->sc_iot = pa->pa_iot; 126 127 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 128 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SBX00_SMB && 129 PCI_REVISION(pa->pa_class) >= 0x40) { 130 /* 131 * On the AMD SB800, the SMBus I/O registers are well 132 * hidden. We need to look at the "SMBus0En" Power 133 * Management register to find out where they live. 134 * We use indirect IO access through the index/data 135 * pair at 0xcd6/0xcd7 to access "SMBus0En". Since 136 * the index/data pair may be needed by other drivers, 137 * we only map them for the duration that we actually 138 * need them. 139 */ 140 if (bus_space_map(sc->sc_iot, SB800_PMREG_BASE, 141 SB800_PMREG_SIZE, 0, &ioh) != 0) { 142 printf(": can't map i/o space\n"); 143 return; 144 } 145 146 /* Read "SmBus0En" */ 147 bus_space_write_1(sc->sc_iot, ioh, 0, SB800_PMREG_SMB0EN); 148 smb0en = bus_space_read_1(sc->sc_iot, ioh, 1); 149 bus_space_write_1(sc->sc_iot, ioh, 0, SB800_PMREG_SMB0EN + 1); 150 smb0en |= (bus_space_read_1(sc->sc_iot, ioh, 1) << 8); 151 152 bus_space_unmap(sc->sc_iot, ioh, SB800_PMREG_SIZE); 153 154 if ((smb0en & SB800_SMB0EN_EN) == 0) { 155 printf(": SMBus disabled\n"); 156 return; 157 } 158 159 /* Map I/O space */ 160 base = smb0en & SB800_SMB0EN_BASE_MASK; 161 if (base == 0 || bus_space_map(sc->sc_iot, base, 162 SB800_SMB_SIZE, 0, &sc->sc_ioh)) { 163 printf(": can't map i/o space"); 164 return; 165 } 166 167 /* Read configuration */ 168 conf = bus_space_read_1(sc->sc_iot, sc->sc_ioh, SB800_SMB_HOSTC); 169 if (conf & SB800_SMB_HOSTC_SMI) 170 conf = PIIX_SMB_HOSTC_SMI; 171 else 172 conf = PIIX_SMB_HOSTC_IRQ; 173 } else { 174 /* Read configuration */ 175 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 176 DPRINTF((": conf 0x%08x", conf)); 177 178 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 179 printf(": SMBus disabled\n"); 180 return; 181 } 182 183 /* Map I/O space */ 184 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 185 PIIX_SMB_BASE_MASK; 186 if (base == 0 || bus_space_map(sc->sc_iot, base, 187 PIIX_SMB_SIZE, 0, &sc->sc_ioh)) { 188 printf(": can't map i/o space\n"); 189 return; 190 } 191 } 192 193 sc->sc_poll = 1; 194 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 195 /* No PCI IRQ */ 196 printf(": SMI"); 197 } else { 198 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 199 /* Install interrupt handler */ 200 if (pci_intr_map(pa, &ih) == 0) { 201 intrstr = pci_intr_string(pa->pa_pc, ih); 202 sc->sc_ih = pci_intr_establish(pa->pa_pc, 203 ih, IPL_BIO, piixpm_intr, sc, 204 sc->sc_dev.dv_xname); 205 if (sc->sc_ih != NULL) { 206 printf(": %s", intrstr); 207 sc->sc_poll = 0; 208 } 209 } 210 } 211 if (sc->sc_poll) 212 printf(": polling"); 213 } 214 215 printf("\n"); 216 217 /* Attach I2C bus */ 218 rw_init(&sc->sc_i2c_lock, "iiclk"); 219 sc->sc_i2c_tag.ic_cookie = sc; 220 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 221 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 222 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 223 224 bzero(&iba, sizeof(iba)); 225 iba.iba_name = "iic"; 226 iba.iba_tag = &sc->sc_i2c_tag; 227 config_found(self, &iba, iicbus_print); 228 229 return; 230 } 231 232 int 233 piixpm_i2c_acquire_bus(void *cookie, int flags) 234 { 235 struct piixpm_softc *sc = cookie; 236 237 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 238 return (0); 239 240 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 241 } 242 243 void 244 piixpm_i2c_release_bus(void *cookie, int flags) 245 { 246 struct piixpm_softc *sc = cookie; 247 248 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 249 return; 250 251 rw_exit(&sc->sc_i2c_lock); 252 } 253 254 int 255 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 256 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 257 { 258 struct piixpm_softc *sc = cookie; 259 u_int8_t *b; 260 u_int8_t ctl, st; 261 int retries; 262 263 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 264 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 265 len, flags)); 266 267 /* Wait for bus to be idle */ 268 for (retries = 100; retries > 0; retries--) { 269 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 270 if (!(st & PIIX_SMB_HS_BUSY)) 271 break; 272 DELAY(PIIXPM_DELAY); 273 } 274 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 275 PIIX_SMB_HS_BITS)); 276 if (st & PIIX_SMB_HS_BUSY) 277 return (1); 278 279 if (cold || sc->sc_poll) 280 flags |= I2C_F_POLL; 281 282 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 283 return (1); 284 285 /* Setup transfer */ 286 sc->sc_i2c_xfer.op = op; 287 sc->sc_i2c_xfer.buf = buf; 288 sc->sc_i2c_xfer.len = len; 289 sc->sc_i2c_xfer.flags = flags; 290 sc->sc_i2c_xfer.error = 0; 291 292 /* Set slave address and transfer direction */ 293 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_TXSLVA, 294 PIIX_SMB_TXSLVA_ADDR(addr) | 295 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 296 297 b = (void *)cmdbuf; 298 if (cmdlen > 0) 299 /* Set command byte */ 300 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HCMD, b[0]); 301 302 if (I2C_OP_WRITE_P(op)) { 303 /* Write data */ 304 b = buf; 305 if (len > 0) 306 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 307 PIIX_SMB_HD0, b[0]); 308 if (len > 1) 309 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 310 PIIX_SMB_HD1, b[1]); 311 } 312 313 /* Set SMBus command */ 314 if (len == 0) 315 ctl = PIIX_SMB_HC_CMD_BYTE; 316 else if (len == 1) 317 ctl = PIIX_SMB_HC_CMD_BDATA; 318 else if (len == 2) 319 ctl = PIIX_SMB_HC_CMD_WDATA; 320 321 if ((flags & I2C_F_POLL) == 0) 322 ctl |= PIIX_SMB_HC_INTREN; 323 324 /* Start transaction */ 325 ctl |= PIIX_SMB_HC_START; 326 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HC, ctl); 327 328 if (flags & I2C_F_POLL) { 329 /* Poll for completion */ 330 DELAY(PIIXPM_DELAY); 331 for (retries = 1000; retries > 0; retries--) { 332 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 333 PIIX_SMB_HS); 334 if ((st & PIIX_SMB_HS_BUSY) == 0) 335 break; 336 DELAY(PIIXPM_DELAY); 337 } 338 if (st & PIIX_SMB_HS_BUSY) 339 goto timeout; 340 piixpm_intr(sc); 341 } else { 342 /* Wait for interrupt */ 343 if (tsleep(sc, PRIBIO, "piixpm", PIIXPM_TIMEOUT * hz)) 344 goto timeout; 345 } 346 347 if (sc->sc_i2c_xfer.error) 348 return (1); 349 350 return (0); 351 352 timeout: 353 /* 354 * Transfer timeout. Kill the transaction and clear status bits. 355 */ 356 printf("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 357 "flags 0x%02x: timeout, status 0x%b\n", 358 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags, 359 st, PIIX_SMB_HS_BITS); 360 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HC, 361 PIIX_SMB_HC_KILL); 362 DELAY(PIIXPM_DELAY); 363 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 364 if ((st & PIIX_SMB_HS_FAILED) == 0) 365 printf("%s: abort failed, status 0x%b\n", 366 sc->sc_dev.dv_xname, st, PIIX_SMB_HS_BITS); 367 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS, st); 368 return (1); 369 } 370 371 int 372 piixpm_intr(void *arg) 373 { 374 struct piixpm_softc *sc = arg; 375 u_int8_t st; 376 u_int8_t *b; 377 size_t len; 378 379 /* Read status */ 380 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 381 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 382 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 383 PIIX_SMB_HS_FAILED)) == 0) 384 /* Interrupt was not for us */ 385 return (0); 386 387 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 388 PIIX_SMB_HS_BITS)); 389 390 /* Clear status bits */ 391 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS, st); 392 393 /* Check for errors */ 394 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 395 PIIX_SMB_HS_FAILED)) { 396 sc->sc_i2c_xfer.error = 1; 397 goto done; 398 } 399 400 if (st & PIIX_SMB_HS_INTR) { 401 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 402 goto done; 403 404 /* Read data */ 405 b = sc->sc_i2c_xfer.buf; 406 len = sc->sc_i2c_xfer.len; 407 if (len > 0) 408 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 409 PIIX_SMB_HD0); 410 if (len > 1) 411 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 412 PIIX_SMB_HD1); 413 } 414 415 done: 416 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 417 wakeup(sc); 418 return (1); 419 } 420