1 /* $OpenBSD: piixpm.c,v 1.33 2009/11/05 09:37:05 sthen Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel PIIX and compatible Power Management controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 #include <sys/proc.h> 29 30 #include <machine/bus.h> 31 32 #include <dev/pci/pcidevs.h> 33 #include <dev/pci/pcireg.h> 34 #include <dev/pci/pcivar.h> 35 36 #include <dev/pci/piixreg.h> 37 38 #include <dev/i2c/i2cvar.h> 39 40 #ifdef PIIXPM_DEBUG 41 #define DPRINTF(x) printf x 42 #else 43 #define DPRINTF(x) 44 #endif 45 46 #define PIIXPM_DELAY 200 47 #define PIIXPM_TIMEOUT 1 48 49 struct piixpm_softc { 50 struct device sc_dev; 51 52 bus_space_tag_t sc_iot; 53 bus_space_handle_t sc_ioh; 54 void * sc_ih; 55 int sc_poll; 56 57 struct i2c_controller sc_i2c_tag; 58 struct rwlock sc_i2c_lock; 59 struct { 60 i2c_op_t op; 61 void * buf; 62 size_t len; 63 int flags; 64 volatile int error; 65 } sc_i2c_xfer; 66 }; 67 68 int piixpm_match(struct device *, void *, void *); 69 void piixpm_attach(struct device *, struct device *, void *); 70 71 int piixpm_i2c_acquire_bus(void *, int); 72 void piixpm_i2c_release_bus(void *, int); 73 int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 74 void *, size_t, int); 75 76 int piixpm_intr(void *); 77 78 struct cfattach piixpm_ca = { 79 sizeof(struct piixpm_softc), 80 piixpm_match, 81 piixpm_attach 82 }; 83 84 struct cfdriver piixpm_cd = { 85 NULL, "piixpm", DV_DULL 86 }; 87 88 const struct pci_matchid piixpm_ids[] = { 89 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB200_SMB }, 90 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB300_SMB }, 91 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB400_SMB }, 92 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SBX00_SMB }, 93 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_PM }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_PM }, 96 97 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_CSB5 }, 98 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_CSB6 }, 99 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_HT_1000 }, 100 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_HT_1100 }, 101 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_OSB4 }, 102 103 { PCI_VENDOR_SMSC, PCI_PRODUCT_SMSC_VICTORY66_PM } 104 }; 105 106 int 107 piixpm_match(struct device *parent, void *match, void *aux) 108 { 109 return (pci_matchbyid(aux, piixpm_ids, 110 sizeof(piixpm_ids) / sizeof(piixpm_ids[0]))); 111 } 112 113 void 114 piixpm_attach(struct device *parent, struct device *self, void *aux) 115 { 116 struct piixpm_softc *sc = (struct piixpm_softc *)self; 117 struct pci_attach_args *pa = aux; 118 struct i2cbus_attach_args iba; 119 pcireg_t base, conf; 120 pci_intr_handle_t ih; 121 const char *intrstr = NULL; 122 123 /* Read configuration */ 124 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 125 DPRINTF((": conf 0x%08x", conf)); 126 127 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 128 printf(": SMBus disabled\n"); 129 return; 130 } 131 132 /* Map I/O space */ 133 sc->sc_iot = pa->pa_iot; 134 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 135 if (PCI_MAPREG_IO_ADDR(base) == 0 || 136 bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(base), 137 PIIX_SMB_SIZE, 0, &sc->sc_ioh)) { 138 printf(": can't map i/o space\n"); 139 return; 140 } 141 142 sc->sc_poll = 1; 143 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 144 /* No PCI IRQ */ 145 printf(": SMI"); 146 } else { 147 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 148 /* Install interrupt handler */ 149 if (pci_intr_map(pa, &ih) == 0) { 150 intrstr = pci_intr_string(pa->pa_pc, ih); 151 sc->sc_ih = pci_intr_establish(pa->pa_pc, 152 ih, IPL_BIO, piixpm_intr, sc, 153 sc->sc_dev.dv_xname); 154 if (sc->sc_ih != NULL) { 155 printf(": %s", intrstr); 156 sc->sc_poll = 0; 157 } 158 } 159 } 160 if (sc->sc_poll) 161 printf(": polling"); 162 } 163 164 printf("\n"); 165 166 /* Attach I2C bus */ 167 rw_init(&sc->sc_i2c_lock, "iiclk"); 168 sc->sc_i2c_tag.ic_cookie = sc; 169 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 170 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 171 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 172 173 bzero(&iba, sizeof(iba)); 174 iba.iba_name = "iic"; 175 iba.iba_tag = &sc->sc_i2c_tag; 176 config_found(self, &iba, iicbus_print); 177 178 return; 179 } 180 181 int 182 piixpm_i2c_acquire_bus(void *cookie, int flags) 183 { 184 struct piixpm_softc *sc = cookie; 185 186 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 187 return (0); 188 189 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 190 } 191 192 void 193 piixpm_i2c_release_bus(void *cookie, int flags) 194 { 195 struct piixpm_softc *sc = cookie; 196 197 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 198 return; 199 200 rw_exit(&sc->sc_i2c_lock); 201 } 202 203 int 204 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 205 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 206 { 207 struct piixpm_softc *sc = cookie; 208 u_int8_t *b; 209 u_int8_t ctl, st; 210 int retries; 211 212 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 213 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 214 len, flags)); 215 216 /* Wait for bus to be idle */ 217 for (retries = 100; retries > 0; retries--) { 218 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 219 if (!(st & PIIX_SMB_HS_BUSY)) 220 break; 221 DELAY(PIIXPM_DELAY); 222 } 223 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 224 PIIX_SMB_HS_BITS)); 225 if (st & PIIX_SMB_HS_BUSY) 226 return (1); 227 228 if (cold || sc->sc_poll) 229 flags |= I2C_F_POLL; 230 231 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 232 return (1); 233 234 /* Setup transfer */ 235 sc->sc_i2c_xfer.op = op; 236 sc->sc_i2c_xfer.buf = buf; 237 sc->sc_i2c_xfer.len = len; 238 sc->sc_i2c_xfer.flags = flags; 239 sc->sc_i2c_xfer.error = 0; 240 241 /* Set slave address and transfer direction */ 242 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_TXSLVA, 243 PIIX_SMB_TXSLVA_ADDR(addr) | 244 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 245 246 b = (void *)cmdbuf; 247 if (cmdlen > 0) 248 /* Set command byte */ 249 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HCMD, b[0]); 250 251 if (I2C_OP_WRITE_P(op)) { 252 /* Write data */ 253 b = buf; 254 if (len > 0) 255 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 256 PIIX_SMB_HD0, b[0]); 257 if (len > 1) 258 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 259 PIIX_SMB_HD1, b[1]); 260 } 261 262 /* Set SMBus command */ 263 if (len == 0) 264 ctl = PIIX_SMB_HC_CMD_BYTE; 265 else if (len == 1) 266 ctl = PIIX_SMB_HC_CMD_BDATA; 267 else if (len == 2) 268 ctl = PIIX_SMB_HC_CMD_WDATA; 269 270 if ((flags & I2C_F_POLL) == 0) 271 ctl |= PIIX_SMB_HC_INTREN; 272 273 /* Start transaction */ 274 ctl |= PIIX_SMB_HC_START; 275 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HC, ctl); 276 277 if (flags & I2C_F_POLL) { 278 /* Poll for completion */ 279 DELAY(PIIXPM_DELAY); 280 for (retries = 1000; retries > 0; retries--) { 281 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 282 PIIX_SMB_HS); 283 if ((st & PIIX_SMB_HS_BUSY) == 0) 284 break; 285 DELAY(PIIXPM_DELAY); 286 } 287 if (st & PIIX_SMB_HS_BUSY) 288 goto timeout; 289 piixpm_intr(sc); 290 } else { 291 /* Wait for interrupt */ 292 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 293 goto timeout; 294 } 295 296 if (sc->sc_i2c_xfer.error) 297 return (1); 298 299 return (0); 300 301 timeout: 302 /* 303 * Transfer timeout. Kill the transaction and clear status bits. 304 */ 305 printf("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 306 "flags 0x%02x: timeout, status 0x%b\n", 307 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags, 308 st, PIIX_SMB_HS_BITS); 309 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HC, 310 PIIX_SMB_HC_KILL); 311 DELAY(PIIXPM_DELAY); 312 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 313 if ((st & PIIX_SMB_HS_FAILED) == 0) 314 printf("%s: abort failed, status 0x%b\n", 315 sc->sc_dev.dv_xname, st, PIIX_SMB_HS_BITS); 316 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS, st); 317 return (1); 318 } 319 320 int 321 piixpm_intr(void *arg) 322 { 323 struct piixpm_softc *sc = arg; 324 u_int8_t st; 325 u_int8_t *b; 326 size_t len; 327 328 /* Read status */ 329 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 330 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 331 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 332 PIIX_SMB_HS_FAILED)) == 0) 333 /* Interrupt was not for us */ 334 return (0); 335 336 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 337 PIIX_SMB_HS_BITS)); 338 339 /* Clear status bits */ 340 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS, st); 341 342 /* Check for errors */ 343 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 344 PIIX_SMB_HS_FAILED)) { 345 sc->sc_i2c_xfer.error = 1; 346 goto done; 347 } 348 349 if (st & PIIX_SMB_HS_INTR) { 350 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 351 goto done; 352 353 /* Read data */ 354 b = sc->sc_i2c_xfer.buf; 355 len = sc->sc_i2c_xfer.len; 356 if (len > 0) 357 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 358 PIIX_SMB_HD0); 359 if (len > 1) 360 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 361 PIIX_SMB_HD1); 362 } 363 364 done: 365 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 366 wakeup(sc); 367 return (1); 368 } 369